june 21 , 201 3 | final | v1. 0 9 1 digital multi - p hase buck controller i r3536a ir3538 a features ? 6 - phase & 8 - phase dual output pwm controller ? phases are flexibly assigned between loops 1 & 2 ? intel? vr12, amd? 3.4mhz svi/pvi & memory modes ? overclocking & gaming mode with vmax setting ? switching frequency from 200khz to 1.2mhz per phase ? ir effi ciency shaping features including variable gate drive and dynamic phase control ? programmable 1 - phase or 2 - phase for light loads and active diode emulation for very light loads ? ir adaptive transient algorithm (ata) on both loops minimizes output bulk capaci tors and system cost ? auto - phase detection with auto - compensation ? per - loop fault protection: ovp, uvp, ocp, otp, cfp ? i2c/smbus/pmbus system interface for telemetry of temperature, voltage, current & power for both loops ? non - volatile memory (nvm) for cust om configuration ? compatible with ir atl and 3.3v t ri - state drivers ? +3.3v supply voltage; - 20oc to 85oc ambient operation ? pb - free, rohs, 7x7 48 - pin & 8x8 56 - pin qfn , msl2 package applications ? intel ? vr12 & amd? svi & pvi based systems ? ddr memory with vtt trac king ? overclocked & gaming platforms pin diagram figure 1: ir3536a package top view description the ir3536a and ir3538a are dual - loop digital multi - phase buck controllers. the ir3536a drive up to 6 phases and the ir3538a drives up to 8 phases. the ir35 36a and ir3538a are fully intel? vr12 and amd? svi/pvi comp liant on both loops and provide a vtt tracking function for ddr memory. the ir3536a and ir3538a include the ir efficiency shaping technology to deliver exceptional efficiency at minimum cost acros s the entire load range. ir variable gate drive optimizes the mosfet gate drive voltage based on real - time load current. ir dynamic phase control adds/drops phases based upon load current. the ir3536a and ir3538a can be configured to enter 1 - phase opera tion and active diode emulation mode automatically or by command. irs unique adaptive transient algorithm (ata), based on proprietary non - linear digital pwm algorithms, minimizes output bulk capacitors. the i2c/pmbus interface can communicate with up to 16 ir3536a and ir3538a based vr loops. device configuration and fault parameters are easily defined using the ir intuitive power designer ( dpdc ) gui and stored in on - chip nvm. the ir3536a and ir3538a provides extensive ovp, uvp, ocp and otp fault protecti on and includes thermistor based temperature sensing with vr_hot signal. nvm storage saves pins and enables a small package size. the ir3536a and ir3538a also include numerous features like register diagnostics for fast design cycles and platform different iation, truly simplifying vrd design and enabling fastest time - to - market with its set - and - forget methodology . figure 2 : ir3538a package top view
june 21 , 201 3 | final | v1. 0 9 2 digital multi - p hase buck controller i r3536a ir3538 a ordering information ir353 ? a m ? ? ? ? ? ? ? ? ? figure 3: ir3536a package top view, enlarged package packing qty part number programming qfn tr= 3000 ty=2600 ir3536 a mtr pbf ir3536a mt ypbf default qfn tr=3000 ty=2600 ir3538 a mtr pbf ir3538a mt ypbf default qfn tr= 3000 ir3536 a m xxyytr p 1 customer configuratio n qfn tr= 3000 ir3538 a m xxyytr p 1 customer configuratio n notes: 1. customer specific configuration file, where xx = customer id and yy = configuration file (codes assigned by ir marketing) . figure 4: ir3538a package top view, enlarged p/pbf C lead free tr C tape & reel / ty - tray yy C configuration file id xx C customer id package type (qfn) part C : ir3536 a 8 : ir3538 a
june 21 , 201 3 | final | v1. 0 9 3 digital multi - p hase buck controller i r3536a ir3538 a functional block dia gram figure 5 : ir3536a / ir3538a functional block diagram ir3538a ir3538a ir3538/ ir3536/ ir3538/ chl8326 chl8328 i s e n 1 i r t n 1 i s e n x i r t n x i s e n y i r t n y i s e n z i r t n z t s e n v i n s e n v o l t a g e a d c v s e n v r t n c o n t r o l a n d m o n i t o r i n g v o u t 1 _ e r r o r v o u t 2 _ e r r o r p w m 1 p w m 2 p w m 3 p w m 4 p w m 5 r e f e r e n c e , o s c i l l a t o r , s t a t e c o n t r o l , i n t e r f a c e s , r e g i s t e r s a n d n v m s v _ c l k 1 / s v c _ v i d [ 3 ] 2 a d c c l o c k s m u x c l o c k s p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 v 3 _ 3 i o u t v i n t e m p f a u l t b u s s y s t e m c l o c k i o u t v i n t e m p v o u t f a u l t b u s s y s t e m c l o c k v i d _ 1 v i d _ 2 c u r r e n t a d c i t o t _ 1 i t o t _ 2 i p 1 i p x i p y i p 1 i p 6 i p 7 i p 8 m o d e c o n t r o l i p z v a r _ g a t e l d o v c c 1 . 8 v v 1 8 a s v _ d i o 1 / s v d _ v i d [ 2 ] 2 s m b _ a l e r t v r _ h o t # 1 / v r h o t _ i c r i t # 2 v r _ r e a d y 1 / p w r g d 2 v r _ r e a d y _ l 2 1 / p w r o k 2 p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 r r e s r c s p r s c m a f e _ 1 v i d _ 1 s m b _ d i o s m b _ c l k s v _ a d d r 1 / v i d [ 1 ] 2 c f p 1 / v f i x e n _ p s i 2 p m _ a d d r 1 / p m _ a d d r _ v i d [ 0 ] 2 p s i 1 / v i d [ 5 ] 2 e n p w m 6 p w m 7 p w m 8 o n l y f o r c h l 8 3 2 8 p w m g e n e r a t o r . . . . . . . . . . . . . . . . . . . . . . . . o n l y f o r c h l 8 3 2 8 c h l 8 3 2 6 c h l 8 3 2 8 x 3 4 y 4 5 z 6 8 s v _ a l e r t # 1 / v i d [ 4 ] 2 g p o _ a g p o _ b o n l y f o r c h l 8 3 2 8 1 i n t e l / m p o l m o d e 2 a m d m o d e t s e n 2 v s e n _ l 2 v r t n _ l 2 r c s p _ l 2 r s c m _ l 2 a f e _ 2 v i d _ 2 i t o t _ 2 m o n i t o r a d c
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