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1 typical application network features description smartmesh ip network manager 2.4ghz 802.15.4e wireless manager ltc5800- ipr features n complete radio transceiver, embedded processor, and networking software for forming a self-healing mesh network n smartmesh ? networks incorporate: n time synchronized network-wide scheduling n per-transmission frequency-hopping n redundant spatially diverse topologies n network-wide reliability and power optimization n nist certified security n smartmesh networks deliver: n >99.999% network reliability achieved in the most challenging rf environments n sub 50a routing nodes n compliant to 6lowpan internet protocol (ip) and ieee 802.15.4e standards n provides network management functions and security capabilities n manages networks of up to 32 nodes (LTC5800-IPRa) or up to 100 nodes (LTC5800-IPRb) n sub 1ma average current consumption enables batter y-powered network management n pcb module versions available ( lt p ?5901/2-ipr) with rf modular certifications n 72-lead 10mm 10mm qfn package l, lt , lt c , lt m , linear technology, the linear logo, dust, dust networks, smartmesh and eterna are registered trademarks and lt p , the dust networks logo smartmesh ip and manager- on-chip are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7375594, 7420980, 7529217, 7791419, 7881239, 7898322, 8222965. * eterna is dust networks low power radio soc architecture. smartmesh ip? wireless sensor networks are self manag- ing, low power internet protocol ( ip) networks built from wireless nodes called motes. the lt c ? 5800-ipr is the ip manager- on- chip? in the eterna ? * family of ieee 802.15.4e system-on-chip ( soc) solutions, featuring a highly inte- grated, low power radio design by dust networks ? as well as an arm cortex-m 3 32- bit microprocessor running dusts embedded smartmesh ip networking software. based on the ietf 6 lowpan and ieee-802.15.4e stan - dards, the LTC5800-IPR soc runs smartmesh ip network management software to monitor and manage network performance and provide a data ingress/egress point via a uart interface. the smartmesh ip software provided with the LTC5800-IPR is fully tested and validated, and is readily configured via a software application programming interface. with dusts time-synchronized smartmesh ip networks, all motes in the network may route, source or terminate data, while providing many years of battery- powered operation. smartmesh ip motes deliver a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform. 5800ipr ta01 20mhz controller sensor in+ in? spi ltc2379-18 32khz ltc5800-ipm uart antenna 20mhz 32khz LTC5800-IPR uart antenna host application 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
2 table of contents network features .......................................... 1 LTC5800-IPR features .................................... 1 t ypical application ........................................ 1 description .................................................. 1 smartmesh network overview .......................... 3 absolute maximum ratings .............................. 4 order information .......................................... 4 recommended operating conditions ................... 4 pin configuration .......................................... 4 dc characteristics ......................................... 5 radio specifications ...................................... 5 radio receiver characteristics .......................... 6 radio t ransmitter characteristics ....................... 6 digital i/o characteristics ................................ 7 t emperature sensor characteristics .................... 7 system characteristics ................................... 7 uar t ac characteristics .................................. 8 time n ac characteristics ................................ 9 radio_inhibit ac characteristics ..................... 9 flash ac characteristics ................................. 10 flash spi slave ac characteristics .................... 10 external bus ac characteristics ........................ 11 t ypical performance characteristics .................. 13 pin functions .............................................. 18 operation ................................................... 23 power supply .......................................................... 23 s upply monitoring and reset ................................. 24 p recision timing ..................................................... 24 ap plication time synchronization .......................... 24 ti me references ..................................................... 24 ra dio ...................................................................... 25 u arts .................................................................... 25 c li uart ................................................................ 27 a utonomous mac ................................................... 27 s ecurity .................................................................. 28 t emperature sensor ............................................... 28 r adio inhibit ........................................................... 28 f lash programming ................................................ 28 f lash data retention ............................................... 28 ne tworking ............................................................. 29 s tate diagram ......................................................... 30 applications information ................................ 33 re gulatory and standards compliance .................. 33 so ldering information ............................................. 33 related documentation .................................. 34 package description ..................................... 35 t ypical application ....................................... 36 related parts .............................................. 36 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
3 smartmesh network overview a smartmesh network consists of a self- forming multi- hop, mesh of nodes, known as motes, which collect and relay data, and a network manager that monitors and manages network performance and security, and exchanges data with a host application. smartmesh networks communicate using a time slotted channel hopping ?( tsch) link layer, pioneered by dust networks. in a tsch network, all motes in the network are synchronized to within less than a millisecond. time in the network is organized into time slots, which enable collision- free packet exchange and per- transmission channel-hopping. in a smartmesh network, every device has one or more parents ( e.g., mote 3 has motes 1 and ?2 as parents) that provide redundant paths to overcome communications interruption due to interference, physical obstruction or multi-path fading. if a packet transmission fails on one path, the next retransmission may try on a different path and different rf channel. a network begins to form when the network manager instructs its on- board access point ( ap) radio to begin sending? advertisements packets that contain information that enables a device to synchronize to the network and request to join. this message exchange is part of the? secu - rity? handshake that establishes encrypted communications between the manager or application, and mote. once motes have joined the network, they maintain synchronization through time corrections when a packet is acknowledged. the network manager uses health reports to continually optimize the network to maintain >99.999% data reliability even in the most challenging rf environments. the use of tsch allows smartmesh devices to sleep in- between scheduled communications and draw very little power in this state. motes are only active in time slots where they are scheduled to transmit or receive, typically resulting in a duty cycle of <1%. the optimization soft - ware in the network manager coordinates this schedule automatically. when combined with the eterna low power radio, every mote in a smartmesh networkeven busy routing onescan run on batteries for years. by default, all motes in a network are capable of routing traffic from other motes, which simplifies installation by avoiding the complexity of having distinct routers vs non-routing end nodes. motes may be configured as non-routing to further reduce that particular motes power consumption and to support a wide variety of network topologies. host application ap sno 01 network manager mote 2 mote 1 mote 3 an ongoing discovery process ensures that the network continually discovers new paths as the rf conditions change. in addition, each mote in the network tracks per - formance statistics ( e.g., quality of used paths, and lists of potential paths) and periodically sends that information to the network manager in packets called health reports. all nodes are routers. they can transmit and receive. this new node can join anywhere because all nodes can route. sno 02 at the heart of smartmesh motes and network managers is the eterna ieee 802.15.4 e system-on-chip ( soc), fea- turing dust networks highly integrated, low power radio design, plus an arm cortex-m 3 32- bit microprocessor running smartmesh networking software. the smartmesh networking software comes fully compiled yet is configu - rable via a rich set of application programming interfaces (apis) which allows a host application to interact with the network, e.g., to transfer information to a device, to configure data publishing rates on one or more motes, or to monitor network state or performance metrics. data publishing can be uniform or different for each device, with motes being able to publish infrequently or faster than once per second as needed. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
4 pin configuration absolute maximum ratings supply voltage on vsupply .................................. 3 .76 v input voltage on ai _ 0/1/2/3 inputs ........................ 1.8 0 v voltage on any digital i/o pin .. C0. 3 v to vsupply + 0.3 v input rf level ...................................................... 10 db m storage temperature range ( note 3) ..... C5 5 c to 125 c junction temperature ( note 3) ............................. 12 5 c operating temperature range ................. C 40 c to 85 c caution: this part is sensitive to electrostatic discharge (esd). it is very important that proper esd precautions be observed when handling the LTC5800-IPR. (note 1) pin functions shown in italics are currently not supported in software. top view wr package 72-lead plastic qfn radio_inhibit 1 cap_pa_1p 2 cap_pa_1m 3 cap_pa_2m 4 cap_pa_2p 5 cap_pa_3p 6 cap_pa_3m 7 cap_pa_4m 8 cap_pa_4p 9 vddpa 10 lna_en 11 radio_tx 12 radio_txn 13 antenna 14 ai_0 15 ai_1 16 ai_3 17 ai_2 18 osc_32k_xout 19 osc_32k_xin 20 vbgap 21 resetn 22 tdi 23 tdo 24 tms 25 tck 26 dp4 27 osc_20m_xin 28 osc_20m_xout 29 vdda 30 vcore 31 vosc 32 eb_data_7 33 eb_data_6 34 eb_data_4 35 eb_data_0 36 54 vpp 53 eb_io_oen 52 eb_io_wen 51 reserved / uartc1_rx 50 reserved / uartc1_tx 49 eb_io_cson 48 eb_data_5 47 eb_data_2 46 eb_data_3 45 ipcs_ssn 44 ipcs_sck 43 eb_addr_0 42 ipcs_mosi 41 eb_addr_1 40 ipcs_miso 39 eb_io_le2 38 uartco_rx / eb_data_1 37 uartco_tx / eb_io_le0 exposed pad (gnd) 72 timen 71 uart_tx 70 uart_tx_ctsn 69 uart_tx_rtsn 68 uart_rx 67 uart_rx_ctsn 66 uart_rx_rtsn 65 vsupply 64 cap_prime_1p 63 cap_prime_1m 62 cap_prime_2m 61 cap_prime_2p 60 cap_prime_3p 59 cap_prime_3m 58 cap_prime_4m 57 cap_prime_4p 56 vprime 55 flash_p_enn / eb_io_le1 t jmax = 125c, jc top = 0.2c/w, jcbottom = 0.6c/w exposed pad is gnd, must be soldered to pcb order information recommended operating conditions lead free finish part marking package description specified temperature range ltc5800iwr-ipra#pbf ltc5800wr-ipra 72-lead (10mm 10mm 0.85mm) plastic qfn C40c to 85c ltc5800iwr-iprb#pbf ltc5800wr-iprb 72-lead (10mm 10mm 0.85mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. for a description of the dash options see the ip manager options section. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. symbol parameter conditions min typ max units vsupply supply voltage including noise and load regulation l 2.1 3.76 v supply noise requires recommended rlc filter, 50hz to 2mhz l 250 mv operating relative humidity non-condensing l 10 90 % rh temperature ramp rate while operating in network l C8 8 c/min 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
5 dc characteristics radio specifications the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. operation/state conditions min typ max units power-on reset during power-on reset, maximum 750s + vsupply rise time from 1v to 1.9v 12 ma doze ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference active 1.2 a deep sleep ram on, arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768khz reference inactive 0.8 a in-circuit programming resetn and flash_p_enn asserted, ipcs_sck at 8mhz 20 ma peak operating current 8dbm 0dbm system operating at 14.7mhz, radio t ransmitting, during flash write. maximum duration 4.33ms 30 26 ma ma active arm cortex m3, ram and flash operating, radio and all other peripherals off. clock frequency of cpu and peripherals set to 7.3728mhz, v core = 1.2v 1.3 ma flash write single bank flash write 3.7 ma flash erase single bank page or mass erase 2.5 ma radio tx 0dbm 8dbm current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 5.4 9.7 ma ma radio rx current with autonomous mac managing radio operation, cpu inactive. clock frequency of cpu and peripherals set to 7.3728mhz. 4.5 ma parameter conditions min typ max units frequency band l 2.4000 2.4835 ghz number of channels l 15 channel separation l 5 mhz channel center frequency where k = 11 to 25, as defined by ieee.802.4.15 l 2405 + 5 ?(k C 11) mhz modulation ieee 802.15.4 direct sequence spread spectrum (dsss) raw data rate l 250 kbps antenna pin esd protection hbm per jedec jesd22-a114f 1000 v range (note 4) indoor outdoor free space 25 c, 50% rh, 2dbi omni-directional antenna, antenna 2m above ground 100 300 1200 m m m 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
6 radio receiver characteristics radio transmitter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. parameter conditions min typ max units receiver sensitivity packet error rate (per) = 1% (note 5) C93 dbm receiver sensitivity per = 50% C95 dbm saturation maximum input level the receiver will properly receive packets 0 dbm adjacent channel rejection (high side) desired signal at C82dbm, adjacent modulated channel 5mhz above the desired signal, per = 1% (note 5) 22 dbc adjacent channel rejection (low side) desired signal at C82dbm, adjacent modulated channel 5mhz below the desired signal, per = 1% (note 5) 19 dbc alternate channel rejection (high side) desired signal at C82dbm, alternate modulated channel 10mhz above the desired signal, per = 1% (note 5) 40 dbc alternate channel rejection (low side) desired signal at C82dbm, alternate modulated channel 10mhz below the desired signal, per = 1% (note 5) 36 dbc second alternate channel rejection desired signal at C82dbm, second alternate modulated channel either 15mhz above or below, per = 1% (note 5) 42 dbc co-channel rejection desired signal at C82dbm, undesired signal is an 802.15.4 modulated signal at the same frequency, per = 1% C6 dbc lo feed through C55 dbm frequency error tolerance (note 6) 50 ppm symbol error tolerance 50 ppm received signal strength indicator (rssi) input range C90 to C10 dbm rssi accuracy 6 db rssi resolution 1 db parameter conditions min typ max units output power high calibrated setting low calibrated setting delivered to a 50 load 8 0 dbm dbm spurious emissions 30mhz to 1000 mhz 1ghz to 12.75ghz 2.4ghz ism upper band edge (peak) 2.4ghz ism upper band edge (average) 2.4ghz ism lower band edge conducted measurement with a 50 single-ended load, 8dbm output power. all measurements made with max hold. rf implementation per eterna reference design rbw = 120khz, vbw = 100hz rbw = 1mhz, vbw = 3mhz rbw = 1mhz, vbw = 3mhz rbw = 1mhz, vbw = 10hz rbw = 100khz, vbw = 100khz LTC5800-IPR ltc 5800-ipr
7 digital i/o characteristics temperature sensor characteristics system characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. symbol parameter conditions (note 7) min typ max units v il low level input voltage l C0.3 0.6 v v ih high level input voltage (note 8) l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 1, i ol(max) = 1.2ma l 0.4 v v oh high level output voltage type 1, i oh(max) = C0.8ma l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 2, low drive, i ol(max) = 2.2ma l 0.4 v v oh high level output voltage type 2, low drive, i oh(max) = C1.6ma l vsupply C 0.3 vsupply + 0.3 v v ol low level output voltage type 2, high drive, i ol(max) = 4.5ma l 0.4 v v oh high level output voltage type 2, high drive, i oh(max) = C3.2ma l vsupply C 0.3 vsupply + 0.3 v input leakage current input driven to vsupply or gnd 50 na pull-up/pull-down resistance 50 k parameter conditions min typ max units offset temperature offset error at 25c 0.25 c slope error 0.033 c/c symbol parameter conditions min typ max units doze to active state transition 5 s doze to radio tx or rx 1.2 ms q cca charge to sample rf channel rssi charge consumed starting from doze state and completing an rssi measurement 4 c q max largest atomic charge operation flash erase, 21ms max duration l 200 c resetn pulse width l 125 s 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
8 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. (note 13) uart ac characteristics symbol parameter conditions min typ max units permitted rx baud rate error both application programming interface (api) and command line interface (cli) uarts l C2 2 % generated tx baud rate error both api and cli uarts l C1 1 % t rx_rts to rx_cts assertion of uart_rx_rtsn to assertion of uart_rx_ctsn, or negation of uart_ rx_rtsn to negation of uart_rx_ctsn l 0 2 ms t cts_r to rx assertion of uart_rx_ctsn to start of byte l 0 20 ms t eop to rx_ rts end of packet (end of the last stop bit) to negation of uart_rx_rtsn l 0 22 ms t beg_tx_rts to tx_cts assertion of uart_tx_rtsn to assertion of uart_tx_ctsn l 0 22 ms t end_tx_rts to tx_cts negation of uart_tx_rtsn to negation of uart_tx_ctsn mode 2 only 22 ms t end_tx_cts to tx_ rts negation of uart_tx_ctsn to negation of uart_tx_rtsn mode 4 only 2 bit period t tx_cts to tx assertion of uart_tx_ctsn to start of byte l 0 2 bit period t eop to tx_ rts end of packet (end of the last stop bit) to negation of uart_tx_rtsn l 0 1 bit period t rx_interbyte receive inter-byte delay l 100 ms t tx to tx_cts start of byte to negation of uart_tx_ctsn l 0 ns 5800irp f01 uart_rx_rtsn uart_rx_ctsn t rx_rts to rx_cts uart_rx uart_tx_rtsn uart_tx_ctsn uart_tx t eop to rx_rts t rx_rts to rx_cts t rx_cts to rx t rx_interbyte byte 0 byte 1 byte 0 byte 1 t rx_rts to rx_cts t end_tx_cts to tx_rts t tx_rts to tx t tx to tx_cts t eop to tx_rts t end_tx_rts to tx_cts figure 1. api uart timing 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
9 time n ac characteristics symbol parameter conditions min typ max units t strobe timen signal strobe width l 125 s t response delay from rising edge of timen to the start of time packet on api uart l 0 100 ms t time_hold delay from end of time packet on api uart to falling edge of subsequent timen l 0 ns timestamp resolution (note 9) l 1 s network-wide time accuracy (note 10) l 5 s 5800ipr f02 timen uart_tx t strobe t time_hold t response time indication payload figure 2. timestamp timing the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t radio_off delay from rising edge of radio_inhibit to radio disabled l 20 ms t radio_inhibit_strobe maximum radio_inhibit strobe width l 2 s 5800ipr f03 radio_inhibit radio state t radio_off t radio_inhibit_strobe active/off active/off off figure 3. radio_inhibit timing radio_ inhibit ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. (note 13) 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
10 flash ac characteristics flash spi slave ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. (note 13) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t write time to write a 32-bit word (note 11) l 21 s t page_erase time to erase a 2kb page (note 11) l 21 ms t mass_erase time to erase 256kb flash bank (note 11) l 21 ms data retention 25c 85c 105c 100 20 8 y ears y ears years symbol parameter conditions min typ max units t fp_en_to_reset setup from assertion of flash_p_enn to assertion of resetn l 0 ns t fp_enter delay from the assertion resetn to the first falling edge of ipcs_ssn l 125 s t fp_exit delay from the completion of the last flash spi slave transaction to the negation of resetn and flash_p_enn (note 12) l 10 s t sss ipcs_ssn setup to the leading edge of ipcs_sck l 15 ns t ssh ipcs_ssn hold from trailing edge of ipcs_sck l 15 ns t ck ipcs_sck period l 50 ns t dis ipcs_mosi data setup l 15 ns t dih ipcs_mosi data hold l 5 ns t dov ipcs_miso data valid l 3 ns t off ipcs_miso data tr i -state l 0 30 ns 5800irp f04 ipcs_sck ipcs_mosi ipcs_ssn resetn flash_p_enn t fp_en_to_reset t fp_enter t sss t ck t dis t dih t ssh t fp_exit figure 4. flash programming interface timing 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
11 figure 5. external bus read timing figure 6. external bus write timing external bus ac characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and vsupply = 3.6v unless otherwise noted. (note 13) symbol parameter conditions min typ max units t lepw eb_io_le0, eb_io_le1, eb_io_le2 pulse width l 100 ns t ah eb_data_[7:0] address hold from the rising edge of eb_io_le0, eb_io_le1, and eb_io_le2 eb_data_[7:0] during address phase l 90 ns t av_to_dl eb_addr_[1:0] address valid until eb_data_[7:0] data latched l 90 ns t csn_to_oen eb_cs0n asserted until eb_oen asserted l 150 ns t csn_off eb_cs0n negated between external bus transfers l 100 ns t su_to_csn eb_addr_[1:0], eb_io_wen setup to eb_csn asserted l 50 ns t h_from_csn eb_addr_[1:0], eb_io_wen hold from eb_csn negated l 50 ns t lepw eb_io_le0 eb_io_le1 eb_io_le2 eb_data_[7:0] eb_addr_[1:0] eb_io_csn eb_io_oen t lepw t lepw t ah t av_to_dl t csn_off 5800ipr f05 t csn_to_oen t ah t ah x xx 11 10 01 00 x a[25:18] a[17:10] a[9:2] d[31:24] d[23:16] d[7:0] d[15:8] eb_io_le0 t lepw eb_io_le1 eb_io_le2 eb_data_[7:0] eb_addr_[1:0] eb_io_wen eb_io_cs0n t lepw t lepw t ah x xx 11 10 00 00 01 a[25:18] a[17:10] a[9:2] d[31:24] d[23:16] d[7:0] d[15:8] x t ah t ah t su_to_csn t csn 5800ipr f06 t csn_off t h_from_csn 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
12 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to eterna. however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 3: extended storage at high temperature is discouraged, as this negatively affects the data retention of eternas calibration data. see the flash data retention section for details. note 4: actual rf range is subject to a number of installation-specific variables including, but not restricted to ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and near-presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. as a result, range varies. note 5: as specified by ieee std. 802.15.4-2006: wireless medium access control (mac) and physical layer (phy) specifications for low- rate wireless personal area networks (lr-wpans) http://www.standards.ieee.org/findstds/standard/802.15.4-2011.html note 6: ieee std. 802.15.4-2006 requires transmitters to maintain a frequency tolerance of better than 40 ppm. note 7: per pin i/o types are provided in the pin functions section. note 8: vih maximum voltage input must respect the vsuppl y maximum voltage specification. note 9: see the smartmesh ip manager api guide for the time indication notification definition. note 10: network time accuracy is a statistical measure and varies over the temperature range, reporting rate and the location of the device relative to the manager in the network. see the typical performance characteristics section for a more detailed description. note 11: code execution from flash banks being written or erased is suspended until completion of the flash operation. note 12: following erase or write transfers, the ipcs spi slave status register, 0xd7 must be polled to determine the completion time of the erase or write operation prior to negating either flash_p_enn or resetn. note 13: guaranteed by design, not production tested. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
13 typical performance characteristics in mesh networks data can propagate from the manager to the nodes, downstream, or from the motes to the man- ager, upstream , via a sequence of transmissions from one device to the next. as shown in figure 8, data originating from mote p1 may propagate to the manager directly or through p2. as mote p1 may directly communicate with the manager, mote p1 is referred to as a 1- hop mote. data originating from mote d1, must propagate through at least one other mote, p2 or p1, and as a result is referred to as a 2- hop mote. the fewest number of hops from a mote to the manager determines the hop depth. as described in application time synchronization , eterna provides two mechanisms for applications to maintain a time base across a network. the synchronization perfor - mance plots that follow were generated using the more precise timen input. publishing rate is the rate a mote ap- plication sends upstream data. synchronization improves as the publishing rate increases. baseline synchronization performance is provided for a network operating with a publishing rate of zero. actual performance for applica - tions in network will improve as publishing rates increase. all synchronization testing was performed with the 1- hop mote inside a temperature chamber. timing errors due to temperature changes and temperature differences both between the manager and this mote and between this mote and its descendents therefore propagated down through the network. the synchronization of the 3- hop and 5-hop motes to the manager was thus affected by the temperature ramps even though they were at room temperature. for 2c/minute testing the temperature chamber was cycled between C40 c and 85 c at this rate for 24 hours. for 8c/minute testing, the temperature chamber was rapidly cycled between 85 c and 45 c for 8 hours, followed by rapid cycling between C5 c and 45 c for 8 hours, and lastly, rapid cycling between C40 c and 15 c for 8 hours. packet rate (packets/s) 0 0 supply current (ma) 0.4 0.8 1.2 5 10 15 20 5800ipr f07a 25 1.6 2.0 0.2 0.6 1.0 1.4 1.8 30 reporting interval (sec) 0 0 median latency (sec) 0.5 1.0 1.5 2.0 2.5 5 10 15 20 5800ipr f07b 25 30 5 hops 4 hops 3 hops 2 hops 1 hop figure 7 manager 1 hop 2 hop 3 hop 5800ipr f08 p1 p2 p3 d1 d2 figure 8. example network graph 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
14 synchronization error (s) ?40 normalized frequency of occurrence (%) 4 5 6 20 30 ?10 0 10 5800ipr g09 3 2 ?30 ?20 40 1 0 7 = 1.0 = 7.4 n = 88179 synchronization error (s) ?40 normalized frequency of occurrence (%) 8 10 12 20 30 ?10 0 10 5800ipr g08 6 4 ?30 ?20 40 2 0 14 = 1.1 = 3.8 n = 88179 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 2 4 6 8 ?20 0 20 40 5800ipr g07 10 12 ?30 ?10 10 30 = 3.6 = 5.0 n = 88144 typical performance characteristics timen synchronization error 0 packets/s publishing rate, 1 hop, room temperature timen synchronization error 0 packets/s publishing rate, 1 hop, 2c/min timen synchronization error 0 packets/s publishing rate, 1 hop, 8c/min timen synchronization error 0 packets/s publishing rate, 3 hops, room t emperature timen synchronization error 0 packets/s publishing rate, 3 hops, 2c/min timen synchronization error 0 packets/s publishing rate, 3 hops, 8c/min timen synchronization error 0 packets/s publishing rate, 5 hops, room t emperature timen synchronization error 0 packets/s publishing rate, 5 hops, 2c/min timen synchronization error 0 packets/s publishing rate, 5 hops, 8c/min synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g01 50 60 ?30 ?10 10 30 = 0.0 = 0.9 n = 89700 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 5 10 15 20 ?20 0 20 40 5800ipr g02 25 30 ?30 ?10 10 30 = ?0.2 = 1.7 n = 89699 synchronization error (s) ?40 normalized frequency of occurrence (%) 8 10 12 20 30 ?10 0 10 5800ipr g03 6 4 ?30 ?20 40 2 0 14 = ?0.2 = 3.6 n = 89698 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 5 10 15 20 ?30 ?20 ?10 0 5800ipr g04 10 20 30 40 = 1.5 = 3.3 n = 93812 synchronization error (s) ?40 normalized frequecy of occurrence (%) 8 10 12 20 30 ?10 0 10 5800ipr g05 6 4 ?30 ?20 40 2 0 14 = 0.9 = 3.9 n = 93846 synchronization error (s) ?40 normalized frequency of occurrence (%) 4 5 6 20 30 ?10 0 10 5800ipr g06 3 2 ?30 ?20 40 1 0 7 = 1.0 = 7.7 n = 93845 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
15 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g16 50 60 ?30 ?10 10 30 = 0.2 = 1.4 n = 33932 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g17 50 60 ?30 ?10 10 30 = 0.0 = 1.3 n = 33930 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g18 50 ?30 ?10 10 30 = ?1.0 = 1.3 n = 33929 typical performance characteristics timen synchronization error 1 packet/s publishing rate, 1 hop, room temperature timen synchronization error 1 packet/s publishing rate, 1 hop, 2c/min timen synchronization error 1 packet/s publishing rate, 1 hop, 8c/min timen synchronization error 1 packet/s publishing rate, 3 hops, room t emperature timen synchronization error 1 packet/s publishing rate, 3 hops, 2c/min timen synchronization error 1 packet/s publishing rate, 3 hops, 8c/min timen synchronization error 1 packet/s publishing rate, 5 hops, room t emperature timen synchronization error 1 packet/s publishing rate, 5 hops, 2c/min timen synchronization error 1 packet/s publishing rate, 5 hops, 8c/min synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g10 50 60 ?30 ?10 10 30 = 0.0 = 1.2 n = 22753 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g11 50 60 ?30 ?10 10 30 = ?0.2 = 1.2 n = 17008 synchronization error (s) ?40 0 normalized frequency of occurrence (%) 10 20 30 40 ?20 0 20 40 5800ipr g12 50 ?30 ?10 10 30 = ?0.2 = 1.2 n = 17007 synchronization error (s) ?40 normalized frequency of occurrence (%) 20 25 30 20 30 ?10 0 10 5800ipr g13 15 10 ?30 ?20 40 5 0 35 = 0.5 = 1.9 n = 85860 synchronization error (s) ?40 normalized frequency of occurrence (%) 25 30 35 40 5800ipr g14 20 15 10 0 ?20 0 20 ?30 ?10 10 30 5 45 40 = 0.1 = 1.5 n = 85858 synchronization error (s) ?40 normalized frequency of occurrence (%) 20 25 30 20 30 ?10 0 10 5800ipr g15 15 10 ?30 ?20 40 5 0 35 = 0.1 = 1.5 n = 85855 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
16 typical performance characteristics as described in the smartmesh network overview , devices in network spend the vast majority of their time inactive in their lowest power state ( doze). on a synchronous schedule a mote will wake to communicate with another mote. regularly occurring sequences which wake, perform a significant function and return to sleep are considered atomic. these operations are considered atomic as the sequence of events can not be separated into smaller events while performing a useful function. for example, transmission of a packet over the radio is an atomic op - eration. atomic operations may be characterized in either charge or energy. in a time slot where a mote successfully sends a packet, an atomic transmit includes setup prior to sending the message, sending the message, receiving the acknowledgment and the post processing needed as a result of the message being sent. similarly in a time slot when a mote successfully receives a packet, an atomic receive includes setup prior to listening, listening until the start of the packet transition, receiving the packet, sending the acknowledgement and post processing required due to the arrival of the packet. to ensure reliability each mote in the network is provided multiple time slots for each packet it nominally will send and forward. the time slots are assigned to communicate upstream, towards the manager, with at least two different motes. when combined with frequency hopping this pro - vides t emporal, spatial a nd spectral redundancy. given this approach a mote will often listen for a message that it will never receive since the time slot is not being used by the transmitting mote. it has already successfully transmitted the packet. since typically 3 time slots are scheduled for every 1 packet to be sent or forwarded, motes will perform more of these atomic idle listens than atomic transmit or atomic receive sequences. examples of transmit, receive and idle listen atomic operations are shown in figure 9. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
17 typical performance characteristics atomic operationmaximum length transmit with acknowledge, 7.5ms time slot (54.5c total charge at 3.6v) atomic operationmaximum length receive with acknowledge, 7.5ms time slot (32.6c total charge at 3.6v) atomic operationidle listen, 7.5ms time slot (6.4c total charge at 3.6v) figure 9 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
18 pin functions pin functions in italics are currently not supported in software. the following table organizes the pins by functional groups. for those i/o with multiple functions the alternate functions are shown on the second and third line in their respective row. the no column provides the pin number. the second column lists the function. the type column lists the i/o type. the i/o column lists the direction of the signal relative to eterna. the pull column shows which signals have a fixed passive pull-up or pull-down. the description column provides a brief signal description. no power supply type i/o pull description p gnd power C C ground connection, p = qfn paddle 2 cap_pa_1p power C C pa dc/dc converter capacitor 1 plus terminal 3 cap_pa_1m power C C pa dc/dc converter capacitor 1 minus terminal 4 cap_pa_2m power C C pa dc/dc converter capacitor 2 minus terminal 5 cap_pa_2p power C C pa dc/dc converter capacitor 2 plus terminal 6 cap_pa_3p power C C pa dc/dc converter capacitor 3 plus terminal 7 cap_pa_3m power C C pa dc/dc converter capacitor 3 minus terminal 8 cap_pa_4m power C C pa dc/dc converter capacitor 4 minus terminal 9 cap_pa_4p power C C pa dc/dc converter capacitor 4 plus terminal 10 vddpa power C C internal power amplifier power supply, bypass 30 vdda power C C regulated analog supply, bypass 31 vcore power C C regulated core supply, bypass 32 vosc power C C regulated oscillator supply, bypass 56 vprime power C C internal primary power supply, bypass 57 cap_prime_4p power C C primary dc/dc converter capacitor 4 plus terminal 58 cap_prime_4m power C C primary dc/dc converter capacitor 4 minus terminal 59 cap_prime_3m power C C primary dc/dc converter capacitor 3 minus terminal 60 cap_prime_3p power C C primary dc/dc converter capacitor 3 plus terminal 61 cap_prime_2p power C C primary dc/dc converter capacitor 2 plus terminal 62 cap_prime_2m power C C primary dc/dc converter capacitor 2 minus terminal 63 cap _prime_1m power C C primary dc/dc converter capacitor 1 minus terminal 64 cap_prime_1p power C C primary dc/dc converter capacitor 1 plus terminal 65 vsupply power C C power supply input to eterna no radio type i/o pull description 1 radio_inhibit gpio15 1 (note 14) i i/o C C radio inhibit general purpose digital i/o 11 lna_en gpio17 1 o i/o C external lna enable general purpose digital i/o 12 radio_tx gpio18 1 o i/o C C radio tx active (external pa enable/switch control) general purpose digital i/o 13 radio_txn gpio19 1 o i/o C C radio tx active (external pa enable/switch control), active low general purpose digital i/o 14 antenna C C C single-ended antenna port, 50 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
19 pin functions pin functions in italics are currently not supported in software. no crystals type i/o pull description 19 osc_32k_xout crystal 0 C 32khz crystal xout 20 osc_32k_xin crystal i C 32khz crystal xin 28 osc_20m_xin crystal i C 20mhz crystal xin 29 osc_20m_xout crystal 0 C 20mhz crystal xout no reset type i/o pull description 22 resetn 1 0 up reset input, active low no jtag type i/o pull description 23 tdi 1 i up jtag test data in 24 tdo 1 o C jtag test data out 25 tms 1 i up jtag test mode select 26 tck 1 i down jtag test clock no special purpose type i/o pull description 72 timen 1 (note 14) i C time capture request, active low no cli and external memory type i/o pull description 33 eb_data_7 1 i/o C external bus data bit 7 34 eb_data_6 1 i/o C external bus data bit 6 35 eb_data_4 1 i/o C external bus data bit 4 36 eb_data_0 1 i/o C external bus data bit 0 37 uartc0_tx eb_io_le0 2 o o C cli uar t 0 transmit external bus i/o latch enable 0 for external address bits a[9:2] 38 uartc0_rx eb_data_1 1 i i/o C cli uar t 0 receive external bus data bit 1 39 eb_io_le2 1 o C external bus i/o latch enable 2 for external address bits a[25:18] 41 eb_addr_1 2 o C external bus address bit 1 43 eb_addr_0 2 o C external bus address bit 0 46 eb_data_3 1 i/o C external bus data bit 3 47 eb_data_2 1 i/o C external bus data bit 2 48 eb_data_5 1 i/o C external bus data bit 5 49 eb_io_cs0n 2 o C external bus chip select 0 50 uartc1_tx 2 o C cli uart 1 transmit 51 uartc1_rx 1 i C cli uart 1 receive 52 eb_io_wen 2 o C external bus write enable strobe 53 eb_io_oen 2 o C external bus output enable strobe 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
20 pin functions pin functions in italics are currently not supported in software. no ipcs spi/flash programming (note 15) type i/o pull description 40 ipcs_miso 2 o C spi flash emulation (miso) master in slave out port 42 ipcs_mosi 1 i C spi flash emulation (mosi) master out slave in port 44 ipcs_sck 1 i C spi flash emulation (sck) serial clock port 45 ipcs_ssn 1 i C spi flash emulation slave select, active low 55 flash_p_enn eb_io_le1 1 i o up up flash program enable, active low external bus i/o latch enable 1 no api uart type i/o pull description 66 uart_rx_rtsn 1 (note 14) i C uart receive ( rts ) request to send, active low 67 uart_rx_ctsn 1 o C uart receive (cts) clear to send, active low 68 uart_rx 1 (note 14) i C uart receive 69 uart_tx_rtsn 1 o C uart transmit ( rts ) request to send, active low 70 uart_tx_ctsn 1 (note 14) i C uart transmit (cts) clear to send, active low 71 uart_tx 2 o C uart transmit note 14: these inputs are always enabled and must be driven or pulled to a valid state to avoid leakage. note 15: embedded programming over the ipcs spi bus is only avaliable when resetn is asserted. vsupply: system and i/o power supply. provides power to the chip including the on-chip dc/dc converters. the digital-interface i/o voltages are also set by this voltage. bypass with 2.2 f and 0.1 f to ensure the dc/dc convert - ers operate properly. vddp a: pa -converter bypass pin. a 0.47 f capacitor should be connected from vddpa to ground with as short a trace as feasible. do not connect anything else to this pin. vdda: analog-regulator bypass pin. a 0.1 f capacitor should be connected from vdda to ground with as short a trace as feasible. do not connect anything else to this pin. vcore: core-regulator bypass pin. a 56 nf capacitor should be connected from vcore to ground with as short a trace as feasible. do not connect anything else to this pin. vosc: oscillator-regulator bypass pin. a 56 nf capacitor should be connected from vosc to ground with as short a trace as feasible. do not connect anything else to this pin. vprime: primary-converter bypass pin. a 0.22 f capaci - tor should be connected from vprime to ground with as short a trace as feasible. do not connect anything else to this pin. vbgap: bandgap reference output. used for testing and calibration. do not connect anything to this pin. cap_pa_1p, cap_pa_1m through cap_pa_4p, cap_ pa _4m: dedicated power amplifier dc/ dc converter capacitor pins. these pins are used when the radio is transmitting to efficiently convert vsupply to the proper voltage for the power amplifier. a 56 nf capacitor should be connected between each p and m pair. trace length should be as short as feasible. cap_ prime_1p , cap _ prime _ 1 m through cap_prime_4p, cap _prime_4m: primary dc/dc con- verter capacitor pins . these pins are used when the device is awake to efficiently convert vsupply to the proper voltage for the three on-chip low dropout regulators. a 56nf capacitor should be connected between each p and m pair. trace length should be as short as feasible. antenna: multiplexed receiver input and transmitter output pin. the impedance presented to the antenna pin should be 50, single-ended with respect to paddle ground. to ensure regulatory compliance of the final product please see the eterna integration guide for filtering requirements. the antenna pin should not have a dc path to ground; ac blocking must be included if a dc-grounded antenna is used. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
21 pin functions osc_32k_xout: output pin for the 32 khz oscillator. connect to 32 khz quartz crystal. the osc_32k_xout and osc_32k_xin traces must be well-shielded from other signals, both on the same pcb layer and lower pcb layers, as shown in figure 10. osc_32k_xin: input for the 32 khz oscillator. connect to 32khz quartz crystal. the osc_32 k_ xout and osc_32k_xin traces must be well-shielded from other signals, both on the same pcb layer and lower pcb layers, as shown in figure 10. osc_20 m_ xout: output for the 20mhz oscillator. connect only to a supported 20 mhz quartz crystal. the osc_20 m_ xout and osc_20 m_ xin traces must be well-shielded from other signals, both on the same pcb layer and lower pcb layers, as shown in figure 10. see the eterna integration guide for supported crystals. osc_20m_xin: input for the 20 mhz oscillator. connect only to a supported 20 mhz quartz crystal. the osc_20m_ xout and osc_20m_xin traces must be well-shielded from other signals, both on the same pcb layer and lower pcb layers, as shown in figure 10. resetn: the asynchronous reset signal is internally pulled up. resetting eterna will result in the arm cortex m3 rebooting and loss of network connectivity. use of this signal for resetting eterna is not recommended, except during power-on and in-circuit programming. radio_ inhibit: radio_ inhibit provide a mechanism for an external device to temporarily disable radio operation. failure to observe the timing requirements defined in the radio_inhibit ac characteristics table may result in unreliable network operation. in designs where the radio_inhibit function is not needed the input must either be tied, pulled or actively driven low to avoid excess leakage. tms, tck, tdi, tdo: jtag port supporting software debug and boundary scan. an ieee std 1149.1b-1994 compliant boundary scan definition language ( bdsl) file for the wr qfn72 package can be found here. sleepn: the sleepn function is not currently supported in software. the sleepn input must either be tied, pulled or actively driven high to avoid excess leakage. uart _ rx, uart _ rx _ rtsn, uart _ rx _ ctsn, uart _ tx , uart _ tx _ rtsn, uart _ tx _ ctsn : the api uart interface includes bidirectional wake-up and flow control. unused input signals must be driven or pulled to their inactive state . timen: strobing the timen input is the most accurate method to acquire the network time maintained by eterna. eterna latches the network timestamp with sub-microsec - ond resolution on the rising edge of the timen signal and produces a packet on the api serial port containing the timing information. figure 10. pcb top metal layer shielding of crystal signals 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
22 pin functions uartc0_rx, uartc0_tx, uartc1_rx, uartc1_tx: the cli uart provides a mechanism for monitoring, configuration and control of eterna during operation. on the LTC5800-IPR cli uart 0 is used when eterna is not configured to support external ram and cli uart 1 is used when eterna is configured to support external ram. for a complete description of the supported commands see the smartmesh ip manager cli guide. eb_ data_0 through eb_ data_7, eb _ addr_0, eb _ addr_1, eb_io_le1 through eb_io_le2, eb_io_cs0n, eb_io_wen, eb_io_enn: the external bus provides a multiplexed address data bus enabling the cortex-m3 direct access of external byte wide ram. the additional ram is used by network management software enabling the support of a larger network of motes with higher packet throughput. to support the addressing needed, each latch signal, eb_io_le0, eb_io_le1, and eb_io_le2 will strobe to latch 8- bits of address from the eb_data[7:0] bus. eb_io_le0, eb_io_le1, and eb_io_le2 correspond to address bits [9:2], [17:10] and [25:18] respectively. eb_addr_0 and eb_addr_1 correspond to the lower two bits of address. for systems with 256 kb or less eb_ io_ le2 can be ignored. eb _ io_ cs 0n , eb _ io_ wen and eb_io_oen provide chip select, write enable and output enable control of the external ram. flash _p_ enn, ipcs _ ssn, ipcs _ sck, ipcs _ miso, ipcs_ssn: the in-circuit programming control system ( ipcs) bus enables in- circuit programming of eterna s flash memory. ipcs_sck is a clock and should be terminated appropriately for the driving source to prevent overshoot and ringing. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
23 operation the ltc5800 is the worlds most energy-efficient ieee 802.15.4 compliant platform, enabling battery and en- ergy har vested applications. with a powerful 32- bit arm cortex-m3, best-in-class radio, flash, ram and purpose- built peripherals, eterna provides a flexible, scalable and robust networking solution for applications demanding minimal energy consumption and data reliability in even the most challenging rf environments. shown in figure 11, eterna integrates purpose- built peripherals that excel in both low operating-energy con - sumption and the ability to rapidly and precisely cycle between operating and low-power states. items in the gray shaded region labeled analog core correspond to the analog/rf components. power supply eterna is powered from a single pin, vsupply, which powers the i/o cells and is also used to generate internal supplies. eterna s two on- chip dc/ dc converters minimize energy consumption while the device is awake. to con - serve power the dc/dc converters are disabled when the device is in low power state. the integrated power supply conditioning architecture, including the two integrated dc/ dc converters and three integrated low dropout regula - tors, provides excellent rejection of supply noise. eternas operating supply voltage range is high enough to support direct connection to lithium-thionyl chloride ( li-socl 2 ) sources and wide enough to support battery operation over a broad temperature range. 4-bit dac vga bpf ppf agc lpf adc dac 10-bit adc pll rssi lna pa 20mhz 32khz 32khz, 20mhz ptat 5800ipr f09 bat load limiter voltage reference analog core digital core core regulator clock regulator analog regulator pa dc/dc converter primary dc/dc converter relaxation oscillator por timers sched sram 72kb flash 512kb flash controller aes auto mac 802.15.4 mod 802.15.4 framing dma ipcs spi slave cli uart (2 pin) api uart (6 pin) adc ctrl 802.15.4 demod pmu/ clock control code system figure 11. eterna block diagram 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
24 operation supply monitoring and reset eterna integrates a power-on-reset ( por) circuit. as the resetn input pin is nominally configured with an internal pull-up resistor, no connection is required. for a graceful shutdown, the software and the networking layers should be cleanly halted via api commands prior to assertion of the resetn pin. see the smartmesh ip manager api guide for details on the disconnect and reset commands. eterna includes a soft brown-out monitor that fully protects the flash from corruption in the event that power is removed while writing to flash. the integrated flash supervisory functionality, in conjunction with a fault tolerant file system, yields a robust nonvolatile storage solution. precision timing eternas unique low power dedicated timing hardware and timing algorithms provide a significant improvement over competing 802.15.4 product offerings. this functionality provides timing precision two to three orders of magnitude better than any other low power solution available at the time of publication. improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception thereby lowering even further the power consumed by smartmesh networks. eternas patented timing hardware and timing algorithms provide superior performance over rapid temperature changes , further differentiating eternas reliability when compared with other wireless products. in addition, precise timing enables networks to reduce spectral dead time, increasing total network throughput. application time synchronization in addition to coordinating time slots across the network, which is transparent to the user, eternas timing manage - ment is used to support two mechanisms to share network time. having an accurate, shared, network-wide time base enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. eterna will send a time packet through its serial interface when one of the following occurs: n eterna receives an api request to read time n the timen signal is asserted the use of timen has the advantage of being more accu- rate. the value of the time stamp is captured in hardware relative to the rising edge of timen. if an api request is used, due to packet processing, the value of the time stamp may be captured several milliseconds after receipt of the packet. see the timen ac characteristics table for the timen functions definition and specifications. time references eterna includes three clock sources: an internal relaxation oscillator, a low power oscillator designed for a 32.768khz cr ystal, and the radio reference oscillator designed for a 20mhz crystal. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
25 operation relaxation oscillator the relaxation oscillator is the primary clock source for eterna, providing the clock for the cpu, memory subsys - tems, and all peripherals. the internal relaxation oscillator is dynamically calibrated to 7.3728 mhz. the internal re- laxation oscillator typically starts up in a few s, providing an expedient, low energy method for duty cycling between active and low power states. quick start-up from the doze state, defined in the state diagram section, allows eterna to wake up and receive data over the uart and spi interfaces by simply detecting activity on the appropriate signals. 32.768khz crystal oscillator once eterna is powered up and the 32.768 khz crystal source has begun oscillating, the 32.768 khz crystal re - mains operational while in the active state, and is used as the timing basis when in doze state. see the state diagram section, for a description of eternas operational states. 20mhz crystal oscillator the 20 mhz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by eterna as needed. eterna requires specific characterized 20mhz crystal references. see the the eterna integra - tion guide for a complete list of the currently supported 20mhz crystals. radio eterna includes the lowest power commer cially available 2.4ghz ieee 802.15.4 e radio by a substantial margin. (please refer to radio specifications section for power consumption numbers.) eternas integrated power ampli - fier is calibrated and temperature compensated to con- sistently provide power at a limit suitable for worldwide radio certifications. additionally, eterna uniquely includes a hardware-based autonomous mac that handles precise sequencing of peripherals, including the transmitter, the receiver, and advanced encryption standard ( aes) pe - ripherals. the hardware-based autonomous media access controller ( mac) minimizes cpu activity, thereby further decreasing power consumption. uarts the principal network interface is through the application programming interface ( api) uart. a command-line in - terface ( cli) uart is also provided for support of test and debug functions. both uarts sense activity continuously, consuming virtually no power until data is transferred over the port and then automatically returning to their lowest power state after the conclusion of a transfer. the defini - tion for packet encoding on the api uart interface can be found in the smartmesh ip manager api guide and the cli command definitions can be found in the smartmesh ip manager cli guide. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
26 operation api uart protocols the api uart supports multiple protocols with the goal of supporting a wide range of companion multipoint control units ( mcus) while reducing power consumption of the system. as a general rule, higher serial data rates translate into lower energy consumption for both endpoints. the receive half of the api uart protocol includes two additional signals in addition to uart_rx: uart_rx_ rtsn and uart_rx_ctsn. the transmit half of the api uart protocol includes two additional signals in addition to uart_tx: uart_tx_rtsn and uart_tx_ctsn. the two supported protocols are referred to as uart mode ?2 and uart mode 4. mode setting is controlled via the fuse table . in the figures accompanying the protocol descriptions, signals driven by the companion processor are drawn in black and signals driven by eterna are drawn in blue. uart mode 2 uart mode 2 provides the most energy-efficient method for operating eternas api uart. uart mode 2 requires the use of all six uart signals, but does not require adherence to the minimum inter-packet delay as defined in section uart ac characteristics. uart mode 2 incorporates edge-sensitive flow control, at either 9600 or 115200 baud. packets are hdlc encoded with one stop bit and no parity bit. the flow control signals for eternas api receive path are shown in figure 12, uart mode 2 receive flow control. transfers are initiated by the companion processor asserting uart_ rx_ rtsn. eterna then responds by enabling the uart and asserting uart _ rx _ ctsn. after detecting the assertion of uart_ rx _ ctsn the companion processor sends the entire packet. following the transmission of the final byte in the packet, the companion processor negates uart_ rx_ rtsn and waits until the negation of uart_rx_ctsn before asserting uart_rx_rtsn again. the flow control signals for eternas api transmit path are shown in figure 13, uart mode 2 transmit flow control. transfers are initiated by eterna asserting uart_ tx_ rtsn. the companion processor responds by asserting uart_ tx_ctsn when ready to receive data. after detecting the falling edge of uart_tx_ctsn eterna sends the entire packet. following the transmission of the final byte in the packet eterna negates uart_tx_rtsn and waits until the negation of uart_tx_ctsn before asserting uart_tx_rtsn again. the companion processor may negate uart_tx_ctsn any time after the first byte is transmitted provided the timeout from uart_tx_rtsn to uart_tx_ctsn is met. 5800irp f12 uart_rx byte 0 byte 1 uart_rx_ctsn uart_rx_rtsn 5800irp f13 uart_tx byte 0 byte 1 uart_tx_ctsn uart_tx_rtsn figure 12. uart mode 2 receive flow control figure 13. uart mode 2 transmit flow control 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
27 figure 14. uart mode 4 transmit flow control 5800irp f14 uart_tx byte 0 byte 1 uart_tx_ctsn uart_tx_rtsn operation uart mode 4 uart mode 4 incorporates level-sensitive flow control on the tx channel and requires no flow control on the rx channel, supporting both 9600 and 115200 baud. the use of level-sensitive flow control signals enables higher data rates with the option of using a reduced set of the flow control signals; however, the companion processor must negate uart_tx_ctsn prior to the end of the packet and wait at least t rx_rts to rx_cts between transmit packets see the uart ac characteristics table for complete timing specifications. packets are hdlc encoded with one stop bit and no parity bit. the use of the rx flow control signals ( uart_ rx_ rtsn and uart_ rx_ ctsn) for mode ? 4 are optional provided the use is limited to the industrial temperature range (C40 c to 85 c); otherwise, the flow control is manditory. the flow control signals for the tx channel are shown in figure 14, uart mode 4 transmit flow control. transfers are initiated by eterna asserting uart _ tx_ rtsn. the uart _ tx_ ctsn signal may be actively driven by the companion processor when ready to receive a packet or uart_tx_ctsn may be tied low if the companion processor is always ready to receive a packet. after detecting a logic 0 on uart_ tx_ ctsn eterna sends the entire packet. following the transmission of the final byte in the packet eterna negates uart_tx_rtsn and waits for a minimum period defined in the uart ac characteristics table before asserting uart_tx_rtsn again. for details on the timing of the uart protocol, see section uart ac characteristics . cli uart the command line interface ( cli) uart port is a 2-wire protocol ( tx and rx) that operates at a fixed 9600 baud rate with one stop bit and no parity. the cli uart inter - face is intended to support command line instructions and response activity. autonomous mac eterna was designed as a system solution to provide a reliable, ultralow power, and secure network. a reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too complex to completely support through hardware acceleration alone. as described in the precision timing section, proper time management is essential for optimizing a solution that is both low power and reliable. to address these requirements eterna includes the autonomous mac, which incorporates a coprocessor for controlling all of the time-critical radio operations. the autonomous mac provides two benefits: first, preventing variable software latency from affecting network timing and second, greatly reducing system power consumption by allowing the cpu 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
28 operation to remain inactive during the majority of the radio activity. the autonomous mac provides software-independent timing control of the radio and radio-related functions, resulting in superior reliability and exceptionally low power . security network security is an often overlooked component of a complete network solution. proper implementation of se - curity protocols is significant in terms of both engineering effort and market value in an oem product. eterna system solutions provide a fips-197 validated encryption scheme that includes authentication and encryption at the mac and network layers with separate keys for each mote. this not only yields end-to-end security, but if a mote is somehow compromised, communication from other motes is still secure. a mechanism for secure key exchange allows keys to be kept fresh. to prevent physical attacks, eterna includes hardware support for electronically locking de - vices, thereby preventing access to eterna s flash and ram memory and thus the keys and code stored therein. this lock-out feature also provides a means to securely unlock a device should support of a product require access. for details see the board specific configuration guide. temperature sensor eterna includes a calibrated temperature sensor on chip. the temperature readings are available locally through eternas serial api, in addition to being available via the network manager. the performance characteristics of the temperature sensor can be found in the temperature sensor characteristics table. radio inhibit the radio_inhibit input enables an external controller to temporarily disable the radio software drivers (for example, to take a sensor reading that is susceptible to radio interference). when radio_inhibit is asserted the software radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. if the current timeslot is active when radio_inhibit is asserted the radio will be disabled after the present operation completes. for details on the timing associated with radio_inhibit, see the radio_inhibit ac characteristics table. flash programming this product is provided without software programmed into the device. oems will need to program software images during development and manufacturing. eterna s software images are loaded via the in-circuit programming control system ( ipcs) spi interface. sequencing of resetn and flash_p_enn, as described in the flash spi slave a/c characteristics table, places eterna in a state emulating a serial flash to support in-circuit programming. hardware and software for supporting development and produc - tion programming of devices is described in the eterna serial programmer guide. the serial protocol, spi, and timing parameters are described in the flash spi slave a/c characteristics table. flash d ata retention eterna contains internal flash ( non-volatile memory) to store calibration results, unique id, configuration settings and software images. flash retention is specified over the operating temperature range. see electrical characteristics and absolute maximum ratings sections. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
29 operation non destructive storage above the operating temperature range of C55 c to 105 c is possible; however, this may result in a degradation of retention characteristics. the degradation in flash retention for temperatures >105c can be approximated by calculating the dimensionless acceleration factor using the following equation. af = e ea k ? ? ? ? ? ? ? 1 t use + 273 C 1 t stress + 273 ? ? ? ? ? ? ? ? ? ? ? ? where: af = acceleration factor ea = activation energy = 0.6ev k = 8.625 ? 10 C5 ev/k t use = is the specified temperature retention in c t stress = actual storage temperature in c example: calculate the effect on retention when storing at a temperature of 125c. t stress = 125c t use = 85c af = 7.1 so the overall retention of the flash would be degraded by a factor of 7.1, reducing data retention from 20 years at 85c to 2.8 years at 125c. networking the LTC5800-IPR network manager provides the ingress/ egress point at the wired to wireless mesh network boundary via the api uart interface. the complexity of the mesh network management is handled entirely within the embedded software, which also provides dynamic network optimization, deterministic power management, intelligent routing, and configurable bandwidth allocation while achieving carrier class data reliability and low power operation. dynamic network optimization dynamic network optimization allows eterna to address the changing rf requirements in harsh environments result - ing in a network that is continuously self-monitoring and self-adjusting. the manager performs dynamic network optimization based upon periodic reports on network health and link quality that it receives from the network motes. the manager uses this information to provide performance statistics to the application layer and proactively solve connectivity problems in the network. dynamic network optimization not only maintains network health, but also allows eterna to deliver deterministic power management. one of the key advantages of smartmesh networking so - lutions is the network manager is aware of and tracking the success or failure of every packet transaction, so not only can the network be optimized, but the solution can be rigorously tested to produce a system solution with better than 99.999% reliability. deterministic power management deterministic power management balances traffic in the network by diverting traffic around heavily loaded motes (for example, motes with high reporting rates). in do - ing so, it reduces power consumption for these motes and balances power consumption across the network. deterministic power management provides predictable maintenance schedules to prevent down time and lower the cost of network ownership. when combined with field devices using eternas industry-leading low power radio technology, deterministic power management enables over a decade of battery life for network motes. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
30 operation intelligent routing intelligent routing provides each packet with an optimal path through the network. the shortest distance between two points is a straight line, but in rf the quickest path is not always the one with the fewest hops. intelligent routing finds optimal paths by considering the link quality (one path may lose more packets than another) and the retry schedule, in addition to the number of hops. the result is reduced network power consumption, elimination of in-network collisions, and unmatched network scalability and reliability. configurable bandwidth allocation smartmesh networks provide configurations that enable users to make bandwidth and latency versus power trade- offs both network wide and on a per device basis. this flexibility enables solutions that tailored to the application requirements, such as request/response, fast file trans - fer, and alerting. relevant configuration parameters are described in the smartmesh ip users guide . the design trade- offs between network performance and current consumption are supported via the smartmesh power and performance estimator . ip manager options the ip manager is offered in two different dash code options, the ltc5800- ipra and ltc5800- iprb. the LTC5800-IPRa option supports managing networks of 32 motes or fewer and the ltc5800- iprb option supports managing networks of up to 100 motes with the use of ex- ternal sram , as described in the eterna integration guide . external sram may be used with either the ltc5800- ipra or LTC5800-IPRb to increase the packet throughput of the ip manager from 24 packets per second without sram to 36 packets per second with sram. ltc5800 - ipra manag - ers that have external sram can be upgraded to support managing networks of up to 100 motes by purchasing a software licensing key as described in the smartmesh ip users guide. state diagram in order to provide capabilities and flexibility in addition to ultra low power, eterna operates in various states, as shown in figure 15, and described in this section. state transitions shown in red are not recommended. fuse table eternas fuse table is a 2 kb page in flash that contains two data structures. one structure supports hardware configuration immediately following power-on reset or the assertion of resetn. the second structure supports configuration of software board support parameters. fuse tables are generated via the fuse table application de - scribed in the board specific configuration guide . hardware configuration of i/o immediately following power-on reset provides a method to minimize leakage due to floating nets prior to software configuration. i/o leakage can contribute hundreds of microamperes of leakage per input, potentially stressing current limited supplies. examples of software board support parameters include setting of uart modes, clock sources and trim values. fuse tables are loaded into flash using the same software and in-circuit programmer used to load software images as described in the eterna serial programmer guide. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
31 operation start-up start-up occurs as a result of either crossing the power-on reset threshold or asserting resetn. after the completion of power-on reset or the falling edge of an internally synchronized resetn, eterna loads its fuse table which, as described in the previous section, includes configuring i/o direction. in this state, eterna checks the state of the flash_p_enn and resetn pins and enters the serial flash emulation mode if both signals are asserted. if the flash_p_enn pin is not asserted but resetn is asserted, eterna automatically reduces its energy consumption to a minimum until resetn is released. once resetn is de-asserted, eterna goes through a boot sequence, and then enters the active state. serial flash emulation when both resetn and flash_p_enn are asserted, eterna disables normal operation and enters a mode to emulate the operation of a serial flash. in this mode, its flash can be programmed. operation once eterna has completed start-up eterna transitions to the operational group of states ( active/cpu active, active/ cpu inactive, and doze). there, eterna cycles between the various states, automatically selecting the lowest pos - sible power state while fulfilling the demands of network operation. active state in the active state, eternas relaxation oscillator is running and peripherals are enabled as needed. the arm cortex -m3 cycles between cpu-active and cpu-inactive ( referred to in the arm cortex-m3 literature as sleep now mode). eternas extensive use of dma and intelligent peripherals that independently move eterna between active state and doze state minimizes the time the cpu is active, signifi - cantly reducing eternas energy consumption. doze state the doze state consumes orders of magnitude less cur - rent than the active state and is entered when all of the peripherals and the cpu are inactive. in the doze state eternas full state is retained, timing is maintained, and eterna is configured to detect, wake, and rapidly respond to activity on i/os ( such as uart signals and the timen pin). in the doze state the 32.768 khz oscillator and as - sociated timers are active. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
32 figure 15. eterna state diagram serial flash emulation load fuse settings resetn low and flash_p_enn high resetn high and flash_p_enn high reset deassert resetn cpu and peripherals inactive hw or pmu event boot start-up operation inactive doze deep sleep low power sleep command 5800ipr f15 assert resetn assert resetn assert resetn cpu active cpu inactive power-on reset resetn low and flash_p_enn low set resetn high and flash_p_enn high for 125s, then set resetn low vsupply > por active operation 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
33 applications information regulatory and standards compliance radio certification eterna is suitable for systems targeting compliance with worldwide radio frequency regulations: etsi en 300 328 and en 300 440 class 2 ( europe), fcc cfr47 part 15 (us), and arib std-t 66 ( japan). application program - ming interfaces ( apis) supporting regulatory testing are provided on both the api and cli uart interfaces. the eterna certification user guide provides: n reference information required for certification n test plans for common regulatory test cases n example cli api calls n sample manual language and example label compliance to restriction of hazardous substances (rohs) restriction of hazardous substances ( rohs) is a directive that places maximum concentration limits on the use of cadmium ( cd), lead ( pb), hexavalent chromium (cr +6 ), mercury ( hg), polybrominated biphenyl ( pbb), and poly- brominated diphenyl ethers ( pbde). linear technology is committed to meeting the requirements of the european community directive 2002/95/ec. this product has been specifically designed to utilize rohs-compliant materials and to eliminate or reduce the use of restricted materials to comply with 2002/95/ec. the rohs-compliant design features include: n rohs-compliant solder for solder joints n rohs-compliant base metal alloys n rohs-compliant precious metal plating n rohs-compliant cable assemblies and connector choices n lead-free qfn package n halogen-free mold compound n rohs-compliant and 245 c re-flow compatible note: customers may elect to use certain types of lead- free solder alloys in accordance with the european com - munity directive 2002/95/ ec. depending on the type of solder paste chosen, a corresponding process change to optimize reflow temperatures may be required. soldering information eterna is suitable for both eutectic pbsn and rohs-6 reflow . the maximum reflow soldering temperature is 260 o c. a more detailed description of layout recommendations, as - sembly procedures and design considerations is included in the eterna integration guide. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
34 related documentation title location description smartmesh ip users guide http://www.linear.com/docs/41880 theory of operation for smartmesh ip networks and motes smartmesh ip manager api guide http://www.linear.com/docs/41883 definitions of the applications interface commands available over the api uart smartmesh ip manager cli guide http://www.linear.com/docs/41882 definitions of the command line interface commands available over the cli uart eterna integration guide http://www.linear.com/docs/41874 recommended practices for designing with the ltc5800 eterna serial programmer guide http://www.linear.com/docs/41876 users guide for the eterna serial programmer used for in circuit programming of the ltc5800 board specific configuration guide http://www.linear.com/docs/41875 users guide for the eterna board specific configuration application, used to configure the board specific parameters eterna certification user guide http://www.linear.com/docs/42918 the essential documentation necessary to complete radio certifications, including examples for common test cases smartmesh ip tools guide http://www.linear.com/docs/42453 the users guide for all ip related tools, and specifically the definition for the on-chip application protocol (oap) 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
35 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 0.15 c seating plane 0.10 c 0.10 c 0.15 c 9.75 bsc 9.75 bsc 10.00 bsc b b 10.00 bsc 0.5 0.1 72 55 36 19 54 37 18 1 c detail a pin 1 r0.300 typ 6.00 0.15 6.00 0.15 detail b 0.50 bsc 0.65 ref 0?14 (4) detail a 0.02 max 1.0mm 0.20 ref 0.50 0.60 max 0.25 0.05 b bac0.10 m detail b wr72 0213 rev a c0.0.5 m 0.60 max wr package 72-lead qfn (10mm 10mm) (reference ltc dwg # 05-08-1930 rev a) 8.50 ref (4 sides) 0.50 bsc 6.00 0.15 6.00 0.15 8.90 0.05 10.50 0.05 0.25 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered note: 1. drawing conforms to jedec package outline mo-220 2. dimension ?b? applies to metalized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has optional radius on the other end of the terminal, the dimension b should not be measured in that radius area 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. drawing not to scale 0.8 0.05 ltcxxxxxx tray pin 1 bevel package in tray loading orientation component pin ?a1? information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr
36 related parts typical application power over ethernet network manager 14 mii antenna mii tx + txp txm rxp rxm txp txm timen uart 1pf 0.1f 100v smaj58a tvs 3.3v 5800ipr ta02 rj45 smsc 8710a (10/100 phy) tx ? rx + rx ? spare + spare ? 12 13 10 1 3 2 11 coilcraft ethi-230ld 9 4 6 5 1 2 3 6 4 5 7 8 atmel sam4e LTC5800-IPR 1pf 100pf 3.3nh ltc4265 poe pd interface controller lt8300 isolated flyback converter part number description comments lt p 5901-ipra ip wireless mesh 32 mote manager pcb module with chip antenna includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, japan, australia and new zealand lt p 5902-ipra ip wireless mesh 32 mote manager pcb module with mmcx antenna connector includes modular radio certification in the united states, canada, europe, south korea, japan, taiwan, india, australia and new zealand lt p 5901-iprb ip wireless mesh 100 mote manager pcb module with chip antenna includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand lt p 5902-iprb ip wireless mesh 100 mote manager pcb module with mmcx antenna connector includes modular radio certification in the united states, canada, europe, south korea, japan, taiwan, india, australia and new zealand lt p 5901-iprc ip wireless mesh 32 mote manager pcb module with chip antenna, external ram support for up to 36 packets per second includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand lt p 5902-iprc ip wireless mesh 32 mote manager pcb module with mmcx antenna connector, external ram support for up to 36 packets per second includes modular radio certification in the united states, canada, europe, south korea, japan, taiwan, india, australia and new zealand ltc 5800-ipma ip wireless mote ultralow power mote, 72-lead 10mm 10mm qfn lt p 5901-ipma ip wireless mesh mote pcb module with chip antenna includes modular radio certification in the united states, canada, europe, japan, south korea, taiwan, india, australia and new zealand lt p 5902-ipma ip wireless mesh mote pcb module with mmcx antenna connector includes modular radio certification in the united states, canada, europe,south korea, japan, taiwan, india, australia and new zealand ltc2379-18 18-bit,1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc ltc3388-1/ ltc3388-3 20v high efficiency nanopower step-down regulator 860na i q in sleep, 2.7v to 20v input, v out : 1.2v to 5.0v, enable and standby pins linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC5800-IPR ? linear technology corporation 2014 lt 0414 ? printed in usa 5800iprf for more information www.linear.com/LTC5800-IPR ltc 5800-ipr

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