View ATA6617C-14_8085506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

9132i-auto-06/14 general features single-package high performance, low power avr ? 8-bit microcontroller with lin transceiver, 5v regulator (85ma current capability) and watchdog very low current consumption in sleep mode 8kbytes/16kbytes flash memory for application program (atmel ? ata6616c/ata6617c) supply voltage up to 40v operating voltage: 5v to 27v temperature range: t case ?40c to +125c qfn38, 5mm 7mm package description atmel ata6616c/ata6617c is a system-in-package (sip) product, which is particularly suited for complete lin-bus node applications. it consists of two ics in one package sup- porting highly integrated solutions for in-vehi cle lin networks. the first chip is the lin- system-basis-chip (lin-sbc) ata 6624, which has an integrated lin transceiver, a 5v reg- ulator (85ma) and a window watchdog. the second chip is an automotive microcontroller from atmel?s series of avr 8-bit microcon troller with advanced risc architecture, the atmel attiny87 with 8-kbytes and the atme l attiny167 with 16-kbytes flash memory. all pins of the lin system basis chip as well as all pins of the avr microcontroller are bonded out to provide customers the same flex ibility for their applications as they have when using discrete parts. in section 1. ?atmel ata6616c/ata6617c lin system in package solution (sip)? on page 3 you will find the pin configuration for the complete sip. in section 3. ?lin system-basis- chip block? on page 7 the lin sbc is described, and in section 4. ?atmel attiny87/attiny167 microcontroller block for atmel ata6616c/ata6617c? on page 26 the avr is described in detail. ata6616c/ata6617c 8k/16k flash microcontrolle r with lin transceiver, 5v regulator and watchdog datasheet
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 2 figure 1. application diagram mcu atmel attiny 87/167 atmel ata6616c/ata6617c lin-sbc atmel ata6624 lin-bus
3 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 1. atmel ata6616c/ata6 617c lin system in pa ckage solution (sip) 1.1 pinning atmel ata6616c/ata6617c figure 1-1. pinning qfn38 table 1-1. pin description pin symbol function 1 pb2 port b 2 i/o line (pci nt10/oc1av/usck/scl) 2 pb1 port b 1 i/o line (pcint9/oc1bu/do) 3 pb0 port b 0 i/o line (pcint8/oc1au/di/sda) 4 pa0 port a 0 i/o line (pcint0/adc0/rxd/rxlin) 5 pa1 port a 1 i/o line (pcint1/adc1/txd/txlin) 6 pa2 port a 2 i/o line (pcint2/adc2/oc0a/do/miso) 7 rxd (1) receive data output 8 inh (1) battery-related output for control ling an external voltage regulator 9 txd (1) transmit data input; active low output (strong pull down) after a local wake-up request 10 nres (1) output undervoltage and watchdog reset (open drain) 11 wd_osc (1) external resistor for adjustable watchdog timing 12 tm (1) for factory testing only (tie to ground) 13 mode (1) for debug mode: low watchdog is on; high watchdog is off 14 kl_15 (1) ignition detection (edge sensitive) 15 pvcc (1) 5v regulator sense input pin 16 vcc (1) 5v regulator output/driver pin 17 vs (1) battery supply 18 en (1) enables the device into normal mode 19 ntrig (1) low level watchdog trigger input from microcontroller 20 wake (1) high voltage input for local wake-up request; if not needed connect to vs 21 gnd (1) system ground lin-sbc note: 1. this identifies the pins of the lin sbc atmel ? ata6624 atmel ata6616c/ata6617c 78 56 1112 910 34 12 25 24 27 26 21 20 23 22 29 28 31 14 13 15 17 16 19 18 37 38 36 34 35 32 33 30 en mode kl15 vcc vs ntrig pb5 gnd pb3 gnd gnd pb4 vcc pb7 pb6 pa7 pa6 pa5 pa4 agnd avcc pa3 lin pb1 pb2 pb0 pa0 pa1 pa2 rxd inh txd tm nres wd_osc wake gnd pvcc
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 4 22 lin (1) lin bus line input/output 23 pa3 port a 3 i/o line (pcint3/adc3/isrc/int0) 24 mcuavcc microcontroller analog supply voltage (referred to as avcc pin in section 4. on page 26 ) 25 agnd analog ground 26 pa4 port a 4 i/o line (pcint 4/adc4/icp1/di/sda/mosi) 27 pa5 port a 5 i/o line (pcint5/adc5/t1/usck/scl) 28 pa6 port a 6 i/o line (pcint6/adc6/ain0/ss) 29 pa7 port a 7 i/o line (pcint7/adc7/ain1) 30 pb7 port b 7 i/o line (pcint 15/adc10/oc1bx / reset) 31 pb6 port b 6 i/o line (pcint14/adc9/oc1ax/int0) 32 pb5 port b 5 i/o line (pcint 13/adc8/oc1bw/xtal2/clko) 33 pb4 port b 4 i/o line (pci nt12/oc1aw/xtal1/clki) 34 mcuvcc microcontroller supply voltage (referred to as vcc pin in section 4. on page 26 ) 35 gnd system ground 36 gnd ground (optional) 37 gnd ground (optional) 38 pb3 port b 3 i/o line (pcint11/oc1bv) 39 backside heat slug is connected to gnd table 1-1. pin description (continued) pin symbol function note: 1. this identifies the pins of the lin sbc atmel ? ata6624
5 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 2. absolute maximum ratings table 2-1. maximum ratings of the sip stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 2 kv cdm esd stm 5.3.1 1 kv machine model esd aec-q100-rev.f (003) 150 v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, lin, kl_15 (47k /100nf) to gnd - pin wake (33 k serial resistor) to gnd 6 5 kv kv esd hbm following stm5.1 with 1.5k 100pf - pin vs, lin, kl_15, wake to gnd 6 kv storage temperature t s ?55 +150 c operating temperature (1) t case ?40 +125 c thermal resistance junction to heat slug r thjc 5 k/w thermal resistance junctiion to ambient r thja 25 k/w thermal shutdown of vcc regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c note: 1. t case means the temperature of the heat slug (backside). it is mandatory that this backside temperature is 125c in the application. table 2-2. maximum ratings of the lin-sbc stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms; t a =25c output current i vcc 85ma v s +40 v pulse time 2min; t a =25c output current i vcc 85ma v s 27 v wake (with 33k serial resistor) kl_15 (with 47k /100nf) dc voltage transient voltage due to iso7637 (coupling 1nf) ?1 ?150 +40 +100 v v inh - dc voltage ?0.3 v s + 0.3 v
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 6 lin - dc voltage ?27 +40 v logic pins (rxd, txd, en, nres, ntrig, wd_osc, mode, tm) ?0.3 +5.5 v output current nres i nres +2 ma pvcc dc voltage vcc dc voltage ?0.3 ?0.3 +5.5 +6.5 v v table 2-2. maximum ratings of the lin-sbc (continued) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit table 2-3. maximum ratings of the microcontroller stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit voltage on any pin except reset with respect to ground ?0.5 mcuvcc + 0.5 v voltage on reset with respect to gnd ?0.5 13.0 v voltage on mcuvcc with respect to gnd ?0.5 6.0 v dc current per i/o pin 40.0 ma dc current mcuvcc and gnd pins 200.0 ma injection current at mcuvcc = 0v to 5v (2) 5.0 ma notes: 1. maximum current per port = 30ma 2. functional corruption may occur
7 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 3. lin system-basis-chip block 3.1 features master and slave operation possible supply voltage up to 40v operating voltage v s = 5v to 27v typically 10a supply current during sleep mode typically 57a supply current in silent mode linear low-drop voltage regulator, 85ma current capability: normal, fail-safe, and silent mode v cc = 5.0v 2% in sleep mode v cc is switched off vcc undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output nres negative trigger input for watchdog boosting the voltage regulator possibl e with an external npn transistor lin physical layer according to lin 2.0, 2.1 specific ation and saej2602-2 wake-up capability via lin-bus, wake pin, or kl_15 pin inh output to control an external voltage regulat or or to switch off the master pull-up resistor txd time-out timer bus pin is overtemperature and short-ci rcuit protected versus gnd and battery adjustable watchdog time via external resistor advanced emc and esd performance fulfills the oem ?hardware requirements for lin in automotive applications rev.1.0? interference and damage protection according to iso7637 3.2 description the lin-sbc is a fully integrated lin transceiver, which comp lies with the lin 2.0, 2.1 and saej2602-2 specifications. it has a low-drop voltage regulator with a 5v /85ma output and a window watchdog. the vo ltage regulator is able to source up to 85ma, but if necessary the output can be boosted by an external npn transistor. the lin-sbc is designed to handle the low-speed data commun ication in vehicles, e.g., in convenience electronics. improved slope control at the lin-driver ensures secure data communication up to 20kbaud. sleep mode and silent mode guarantee very low current consumption.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 8 figure 3-1. block diagram adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer edge detection debounce time internal testing unit control unit slew rate control wake-up bus timer mode select undervoltage reset normal/silent/ fail-safe mode 5v rf filter watchdog out rxd gnd ntrig pvcc pvcc pvcc tm mode en txd kl_15 wake receiver - + normal mode normal and fail-safe mode lin wd_osc nres pvcc vcc vs inh
9 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 3.3 functional description 3.3.1 physical layer compatibility since the lin physical layer is independent from higher lin laye rs (e.g., the lin protocol layer), all nodes with a lin physica l layer according to revision 2.x can be mixed with lin physical layer nodes, which are according to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3), withou t any restrictions. 3.3.2 supply pin (vs) the lin operating voltage is v s = 5v to 27v. an undervoltage detection is implemented to disable data transmission if v s falls below vs th < 4v in order to avoid false bus messages. after swit ching on vs, the ic starts in fail-safe mode, and the voltage regulator is switched on (i.e., output capability). the supply current is typically 10a in sleep mode and 57a in silent mode. 3.3.3 ground pin (gnd) the ic does not affect the lin bus in th e event of gnd disconnection. it is able to handle a ground shift up to 11.5% of vs. the mandatory system ground is pin 5. 3.3.4 voltage regulator output pin (vcc) the internal 5v voltage regulator is capabl e of driving loads up to 85ma. it is able to supply the microcontroller and other ic s on the pcb and is protected again st overload by means of current limitation and overtemperature shut-down. furthermore, the output voltage is monitored and will cause a reset signal at the nres output pin if it drops below a defined threshold v thun . to boost the maximum load current, an external npn transis tor with its base connected to the vcc pin and its emitter connected to pvcc can be used. 3.3.5 voltage regulator sense pin (pvcc) the pvcc is the sense input pin of the volt age regulator. for normal applications (i.e., when only using the internal output transistor), this pin is connected to t he vcc pin. if an external boosting transist or is used, the pvcc pin must be connected to the output of this transistor, i.e., its emitter terminal. 3.3.6 bus pin (lin) a low-side driver with internal current lim itation and thermal shutdown and an internal pull-up resistor compliant with the lin 2.x specification are implement ed. the allowed voltage range is between ?27v and +40v. reverse currents from the lin bus to vs are suppressed, even in the event of gnd shifts or battery disconnection. lin receiver thresholds are compatible with the lin protocol specification. the fa ll time from recessive to dominant bus st ate and the rise time from dominant to recessive bus state are slope controlled. 3.3.7 input/output pin (txd) in normal mode the txd pin is the microcont roller interface used to control the stat e of the lin output. txd must be pulled to ground in order to have a low lin bus. if txd is high or unconn ected (internal pull-up resistor), the lin output transistor is turned off, and the bus is in recessive state. during fail-saf e mode, this pin is used as output. it is current-limited to < 8ma . and is latched to low if the last wa ke-up event was from pin wake or kl_15. 3.3.8 txd dominant time-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in dominant state. if txd is forc ed to low for longer than t dom > 6ms, the lin-bus driver is s witched to recessive state. to reactivate the lin-bus driver , switch txd to high (> 10s).
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 10 3.3.9 output pin (rxd) the output pin reports the state of the lin bus to the microc ontroller. lin high (recessive state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rx d. the output has an internal pull-up resistor with typically 5k to vcc. the ac characteristics can be defined with an external load capacitor of 20pf. the output is short-circuit pr otected. rxd is switched off in unpowered mode (i.e., v s = 0v). 3.3.10 enable input pin (en) the enable input pin controls the operation mode of the device. if en is high, the ci rcuit is in normal mode with transmission paths from txd to lin and from lin to rxd both active. the vcc voltage regulator op erates with 5v/85ma output capability. if en is switched to low while txd is still high, the device is forced to silent mode. no data tr ansmission is then possible, a nd the current consumptio n is reduced to i vs typ. 57a. the vcc regulator has its full functionality. if en is switched to low while txd is low, the device is fo rced to sleep mode. no data transmission is possible, and the voltage regulator is switched off. 3.3.11 wake input pin (wake) the wake input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. it is usually connected to an external switch in the application to generate a local wake-up. a pull-up current source, typically 10a, is implemented. if a local wake-up is not needed for the applicati on, connect the wake pin directly to the vs pin. 3.3.12 mode input pin (mode) connect the mode pin directly or via an external resistor to gnd for normal watc hdog operation. to debug the software of the connected microcontroller, connect the mode pin to vcc and the watchdog is switched off. 3.3.13 tm input pin the tm pin is used for final production measurements at atmel. in normal application, it must always be connected to gnd. 3.3.14 kl_15 pin the kl_15 pin is a high-voltage input used to wake up the device from sleep or silent mode. it is an edge-sensitive pin (low- to-high transition). it is usually connected to ignition to gen erate a local wake-up in the application when the ignition is switched on. although kl_15 pin is at high voltage (v batt ), it is possible to switch the ic into sleep or silent mode. connect the kl_15 pin directly to gnd if you do not need it. a debounce timer with a typical tdb kl_15 of 160s is implemented. the input voltage threshold can be adjusted by varyin g the external resistor due to the input current i kl_15 . to protect this pin against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nf are recommended. with this rc combination you can increase the wake-up time tw kl_15 and, therefore, the sensitivit y against transients on the ignition kl_15. the wake-up time can also be increased by using external capacitors with higher values. 3.3.15 inh output pin the inh output pin is used to switch on an external voltage regulator durin g normal or fail-safe mode. the inh pin is switched off in sleep or silent mode. it is possible to switch off the external 1k master resistor via the inh pin for master node applications. the inh pin is switch ed off during vcc undervoltage reset. 3.3.16 reset output pin (nres) the reset output pin, an open-drain output, switches to low during v cc undervoltage or a watchdog failure. 3.3.17 wd_osc output pin the wd_osc output pin provides a typical voltage of 1.2v, wh ich supplies an external resistor with values between 34k and 120k to adjust the watchdog oscillator time.
11 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 3.3.18 ntrig input pin the ntrig input pin is the trigger input for the window watchdog . a pull-up resistor is implemented. a negative edge triggers the watchdog. the trigger signal (low) must exceed a minimum time t trigmin to generate a watchdog trigger. 3.3.19 wake-up events from sleep or silent mode lin-bus wake pin en pin kl_15 3.4 modes of operation figure 3-2. modes of operation table 3-1. modes of operation mode of operation transceiver vcc watchdog wd_osc inh rxd lin fail-safe off 5v on 1.23v on high, except after wake up recessive normal on 5v on 1.23v on lin depending txd depending silent off 5v off 0v off high recessive sleep off 0v off 0v off 0v recessive unpowered mode v batt = 0v a: v s > 5v b: v s < 4v c: bus wake-up event d: wake up from wake or kl_15 pin sleep mode vcc: switched off communication: off watchdog: off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d + e e c + d b local wake-up event go to sleep command e: nres switches to low silent mode vcc: 5v with undervoltage monitoring communication: off watchdog : off normal mode vcc: 5v with undervoltage monitoring communication: on watchdog: on fail-safe mode vcc : 5v with undervoltage monitoring communication : off watchdog: on
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 12 3.4.1 normal mode this is the normal transmitting and receiving mode of the lin interface in acoordance with the lin specification lin 2.x. the voltage regulator is active and can source up to 85ma. th e undervoltage detection is ac tivated. the watchdog needs a trigger signal from ntrig to avoid resets at nres. if nres is switched to low, the ic cha nges its state to fail-safe mode. 3.4.2 silent mode a falling edge at en when txd is high switches the ic into s ilent mode. the txd signal has to be logic high during the mode select window (see figure 3-3 ). the transmission path is disabled in silent mode. the overall supply current from v batt is a combination of the i vssi = 57a plus the vcc regul ator output current i vcc . the internal slave termination between the lin pin and the vs pi n is disabled in silent mode. only a weak pull-up current (typically 10a) between the lin pin and the vs pin is present. silent mode can be activated independently from the actual level on the lin, wake, or kl_15 pins. if an undervoltage conditi on occurs, nres is switched to low, and the ic changes its state to fail-safe mode. a voltage lower than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and switches on the internal slave termination be tween the lin pin and the vs pin. figure 3-3. switch to silent mode a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and followed by a rising edge at the lin pin (see figure 3-4 on page 13 ) results in a remote wake-up request. the device switches from silent mode to fail-safe mode. the remote wake-up request is in dicated by a low level at the rxd pin to interrupt the microcontroller (see figure 3-4 on page 13 ). en high can be used to switch directly to normal mode. delay time silent mode t d _silent = maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en normal mode silent mode
13 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 3-4. lin wake-up from silent mode 3.4.3 sleep mode a falling edge at en when txd is low switches the ic into sl eep mode. the txd signal has to be logic low during the mode select window ( figure 3-5 on page 14 ). in order to avoid any influence to the li n-pin during switching into sleep mode it is possible to switch the en up to 3.2s earlier to low than the tx d. therefore, the best and ea siest way are two falling edges at txd and en at the same time.the transmission pat h is disabled in sleep mode. the supply current i vssleep from v batt is typically 10a. the vcc regulator and the inh output are switched off. nres and rxd are low. the internal slave termination between the lin pin and vs pin is disabled, only a weak pull-up current (typ ically 10a) between the lin pin and the vs pin is present. sleep mode can be activated independently from the current level on the lin, wake, or kl_15 pin. a voltage lower than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and switches on the internal slave termination between the lin pin and the v s pin. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and followed by a rising edge at pin lin results in a remote wake-up request. the device switches from sleep mode to fail-safe mode. the vcc regulator is activated, and the remote wake-up request is indicated by a low level at the rxd pin to interrupt the microcontroller (see figure 3-6 on page 15 ). watchdog off start watchdog lead time t d watchdog undervoltage detection active silent mode 5v fail safe mode 5v normal mode low fail-safe mode normal mode en high node in silent mode high high nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 14 figure 3-5. switch to sleep mode 3.4.4 fail-safe mode the device automatically swit ches to fail-safe mode at system power up and the voltage regulator is switched on (see figure 3-7 on page 17 ).the nres output switches to low for t res = 4ms and gives a reset to the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a power down of v batt (v s < 4v) during silent or sleep mode switches t he ic into fail-safe mode. a low level at nres switches into fail-safe mode directly. during fail-safe mode t he txd pin is an output and signals the last wake-up source. 3.4.5 unpowered mode if you connect battery voltage to the application circuit, the vo ltage at the vs pin increases according to the block capacitor (see figure 3-7 on page 17 ). after vs is higher than the vs undervoltage threshold vs th , the ic mode changes from unpowered mode to fail-safe mode. the vcc out put voltage reaches its nominal value after t vcc . this time, t vcc , depends on the vcc capacitor and the load. the nres is low for the reset time delay t reset . during this time, t reset , no mode change is possible. delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en sleep mode normal mode mode select window
15 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 3-6. lin wake-up from sleep mode 3.5 wake-up scenarios from silent or sleep mode 3.5.1 remote wake-up via dominant bus state a voltage lower than the lin pre_wake detection v linl at the lin pin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level v busdom maintained for a certain time period (> t bus ) and followed by a rising edge at pin lin result in a remote wake-up request. the device switches from silent or sleep mode to fail-safe mode. the vcc voltage regulator is/remains activated, the inh pin is switched to high, and the remote wake-up request is indicated by a low level at the rxd pin to generate an interrupt for the mi crocontroller. a low level at the lin pin in the normal mode starts the bus wake-up filt ering time, and if the ic is switched to silent or sleep mode, it will receive a wake-up after a positive edge at the lin pin. 3.5.2 local wake-up via pin wake a falling edge at the wake pin fo llowed by a low level maintained for a certain time period (> t wake ) results in a local wake- up request. the device switches to fail-safe mode. the local wa ke-up request is indicated by a low level at the rxd pin to generate an interrupt in the microc ontroller and a strong pull down at txd. when the wake pin is lo w, it is possible to switch to silent or sleep mode via pin en. in this case, the wake- up signal has to be switched to high > 10s before the negative edge at wake starts a new local wake-up request. regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time watchdog nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd watchdog off start watchdog lead time t d
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 16 3.5.3 local wake-up via pin kl_15 a positive edge at pin kl_15 followed by a high voltage level for a certain time period (> t kl_15 ) results in a local wake-up request. the device switches into the fail-safe mode. the ex tra long wake-up time ensures that no transients at kl_15 create a wake-up. the local wake-up request is indicated by a low level at the rxd pin to generate an interrupt for the microcontroller and a strong pull down at txd. during high-level voltage at pin kl_15, it is possible to switch to silent or sleep mode via pin en. in this case, the wake-up signal has to be switched to low > 250s before the positive edge at kl_15 starts a new local wake-up request. with exte rnal rc combination, the time is even longer. 3.5.4 wake-up source recognition the device can distinguish between a local wake-up request (w ake or kl_15 pins) and a remote wake-up request (via lin bus). the wake-up source can be read on the txd pin in fail-safe mode. a high level indicates a remote wake-up request (weak pull up at the txd pin); a low level indicates a local wake-up request (strong pull down at the txd pin). the wake-up request flag (signalled on the rxd pin) as well as the wake-up source flag (signalled on the txd pin) is immediately reset if the microcontroller sets the en pin to high (see figure 3-3 on page 12 and figure 3-4 on page 13 ) and the ic is in normal mode. the last wake-up source flag is stored and signalled in fail-safe mode at the txd pin. 3.5.5 fail-safe features during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff , and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high bec ause lin is high. during lin overtemperature switch-off, the vcc regulator works independently. during a short-circuit from lin to gnd the ic can be s witched into sleep or silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. the reverse current is very low < 2 a at the lin pin during loss of v batt . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vcc, the output limits the output current to i vcc_lin . due to undervoltage, nres switches to low and sends a reset to the microcontroller. the ic switc hes into fail-safe mode. if the chip temperature exceeds the value t vccoff , the vcc output switches off. the chip c ools down and after a hysteresis of t hys , switches the output on again. because of the fail-safe mode, the vcc voltage will s witch on again even though en is switched off from the microcontroller. the microcontroller ca n start with its normal operation. en pin provides a pull-down resistor to force the tr ansceiver into recessive mode if en is disconnected. rxd pin is set floating if v batt is disconnected. txd pin provides a pull-up resistor to force the tr ansceiver into recessive mode if txd is disconnected. if txd is short-circuited to g nd, it is possible to switch to sleep mode via enable after t dom > 20ms. if the wd_osc pin has a short-circuit to gnd and the nt rig signal has a period time > 27ms, the watchdog runs with an internal oscillator and guarantees a reset after the second ntrig signal at the latest. if the resistor at wo_osc pin is disc onnected, the watchdog runs with an inte rnal oscillator and guarantees a reset after the second ntrig signal at the latest.
17 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 3.5.6 voltage regulator the voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. it is recommended to us e an electrolythic capacitor with c 1.8f and a ceramic capacitor with c = 100nf. the values of these capacitors can be vari ed by the customer, depending on the application. the main power dissipation of the ic is created from the vcc output current i vcc , which is needed for the application. in figure 3-8 on page 17 the safe operating area of the atmel ? ata6616c/ata6617c is shown. figure 3-7. vcc voltage regulator: ramp-up and undervoltage detection figure 3-8. power dissipation: safe operating ar ea vcc output current versus supply voltage v s at different ambient temperatures for programming purposes of the microcontroller it is potentially nece ssary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. this will not affect the system basis chip. nres 5v t t t vs vcc 5v v thun t res_f t reset t vcc 5.5v 12v 4 5 6 7 8 9 10111213141516171819 90 80 70 60 50 40 30 20 10 0 i vcc (ma) v s (v) t amb = 100c t amb = 105c t amb = 110c t amb = 115c
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 18 3.6 watchdog the watchdog anticipates a trigger signal from the microcon troller at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time t trigmin > 200ns. if a triggering signal is not received, a reset signal will be generated at output nres. after a watchdog reset, the ic starts with th e lead time. the timing basis of the watchdog is provided by the internal oscillator. its time period, t osc , is adjustable via the external resistor r wd_osc (34k to 120k ). during silent or sleep mode the watchdog is switched off to reduce current consumption. the minimum time for the first watchdog pulse is required afte r the undervoltage reset at nres disappears. it is defined as lead time t d . after wake up from sleep or silent mode, the lead time t d starts with the negativ e edge of the rxd output. 3.6.1 typical timing sequence with r wd_osc = 51k the trigger signal t wd is adjustable between 20ms and 64ms using the external resistor r wd_osc . for example, with an ex ternal resistor of r wd_osc = 51k 1%, the typical parameters of the watchdog are as follows: t osc = 0.405 r wd_osc ? 0.0004 (r wd_osc ) 2 (r wd_osc in k ; t osc in s) t osc = 19.6s due to 51k t d = 7895 19.6s = 155ms t 1 = 1053 19.6s = 20.6ms t 2 = 1105 19.6s = 21.6ms t nres = constant = 4 ms after ramping up the battery voltage, the 5v regulator is switched on. the reset output nr es stays low for the time t reset (typically 4ms), then it switc hes to high, and the watchdog waits for the trigge r sequence from the microcontroller. the lead time, t d , follows the reset and is t d = 155ms. in this time, the first watchdog pulse from the microcontroller is required. if the trigger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 4ms will reset the mi crocontroller after t d = 155ms. the times t 1 and t 2 have a fixed relationship between each other. a triggering signal from the microc ontroller is anticipated within the time frame of t 2 = 21.6ms. to avoid false triggering from glitches, the tr igger pulse must be longer than t trig,min > 200ns. this slope serves to restart the watchdog sequence. if the triggering signal fails in this open window t 2 , the nres output will be drawn to ground. a triggering signal during the closed window t 1 immediately switches nres to low. figure 3-9. timing sequence with r wd_osc = 51k t nres = 4ms undervoltage reset watchdog reset t reset = 4ms t trig > 200ns t 1 = 20.6ms t 2 = 21ms t 2 t 1 t wd t d = 155ms vcc ntrig nres
19 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 3.6.2 worst case calculation with r wd_osc = 51 k the internal oscillator has a tole rance of 20%. this means that t 1 and t 2 can vary by 20%. the worst case calculation for the watchdog period t wd is calculated below. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.5ms, t 1,max = 1.2 t 1 = 24.8ms t 2,min = 0.8 t 2 = 17.3ms, t 2,max = 1.2 t 2 = 26ms t wdmax = t 1min + t 2min = 16.5ms + 17.3ms = 33.8ms t wdmin = t 1max = 24.8ms t wd = 29.3ms 4.5ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to correctly supply the trigger inputs. table 3-2. typical watchdog timings r wd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 13.3 105 14.0 14.7 19.9 4 51 19.61 154.8 20.64 21.67 29.32 4 91 33.54 264.80 35.32 37.06 50.14 4 120 42.84 338.22 45.11 47.34 64.05 4 3.7 electrical characteristics 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 5 27 v a 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v (t j = 25c) vs i vssleep 3 10 14 a b sleep mode v lin > v s ? 0.5v v s < 14v (t j = 125c) vs i vssleep 5 11 16 a a 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vcc vs i vssi 47 57 67 a b bus recessive v s < 14v (t j = 125c) without load at vcc vs i vssi 56 66 76 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus dominant v s < 14v v cc load current 50ma vs i vsdom 50 53 ma a 1.6 supply current in fail- safe mode bus recessive v s < 14v without load at vcc vs i vsfail 250 550 a a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 20 1.7 v s undervoltage threshold vs v sth 3.7 4.4 5 v a 1.8 vs undervoltage threshold hysteresis vs v sth_hys 0.2 v a 2 rxd output pin 2.1 low-level output sink current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low-level output voltage i rxd = 1ma rxd v rxdl 0.4 v a 2.3 internal resistor to v cc rxd r rxd 3 5 7 k a 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high-level leakage current v txd =vcc txd i txd ?3 +3 a a 3.5 low-level output sink current at local wake-up request fail-safe mode v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 2 2.5 8 ma a 4 en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v v a 4.3 pull-down resistor v en = v cc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 ntrig watchdog input pin 5.1 low-level voltage input ntrig v ntrigl ?0.3 +0.8 v a 5.2 high-level voltage input ntrig v ntrigh 2 v cc + 0.3v v a 5.3 pull-up resistor v ntrig = 0v ntrig r ntrig 125 250 400 k a 5.4 high-level leakage current v ntrig = v cc ntrig i ntrig ?3 +3 a a 6 mode input pin 6.1 low-level voltage input mode v model ?0.3 +0.8 v a 6.2 high-level voltage input mode v modeh 2 v cc + 0.3v v a 6.3 leakage current v mode = v cc or v mode = 0v mode i mode ?3 +3 a a 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
21 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 7 inh output pin 7.1 high-level voltage i inh = ?15ma init v inhh v s ? 0.75 v s v a 7.2 switch-on resistance between vs and inh init r inh 30 50 a 7.3 leakage current sleep mode v inh = 0v/27v, v s = 27v init i inhl ?3 +3 a a 8 lin bus driver: bus load conditions: load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; r rxd = 5k ; c rxd = 20pf; load 3 (medium): 6.8nf, 660 characterized on samples; 10.6 and 10.7 s pecifies the timing parameters for proper operation at 20kb it/s, 10.8 and 10.9 at 10.4kbit/s. 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s v a 8.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 8.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 8.6 pull-up resistor to v s the serial diode is mandatory lin r lin 20 30 60 k a 8.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 8.8 lin current limitation v bus = v batt_max lin i bus_lim 40 120 200 ma a 8.9 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_do m ?1 ?0.35 ma a 8.10 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 10 20 a a 8.11 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network. gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 22 8.12 leakage current at a disconnected battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 9.2 receiver dominant state v en = 5v lin v busdom 0.4 v s v a 9.3 receiver recessive state v en = 5v lin v busrec 0.6 v s v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 v s 0.175 v s v a 9.5 pre_wake detection lin high-level input voltage lin v linh v s ? 2v v s + 0.3v v a 9.6 pre_wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 10 internal timers 10.1 dominant time for wake- up via lin bus v lin = 0v lin t bus 30 90 150 s a 10.2 time delay for mode change from fail-safe into normal mode via en pin v en = 5v en t norm 5 15 20 s a 10.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v en t sleep 2 7 12 s a 10.4 txd dominant time-out time v txd = 0v txd t dom 6 13 20 ms a 10.5 time delay for mode change from silent mode into normal mode via en v en = 5v en t s_n 5 15 40 s a 10.6 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 10.7 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
23 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 10.8 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 10.9 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 10.10 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 11 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions c rxd = 20pf 11.1 propagation delay of receiver ( figure 3-10 on page 25 ) v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 11.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 12 nres open drain output pin 12.1 low-level output voltage v s 5.5v i nres = 1ma nres v nresl 0.14 v a 12.2 low-level output low 10k to 5v v cc = 0v nres v nresll 0.14 v a 12.3 undervoltage reset time v s 5.5v c nres = 20pf nres t reset 2 4 6 ms a 12.4 reset debounce time for falling edge v s 5.5v c nres = 20pf nres t res_f 1.5 10 s a 13 watchdog oscillator 13.1 voltage at wd_osc in normal mode i wd_osc = ?200a v vs 4v wd_ osc v wd_osc 1.13 1.23 1.33 v a 13.2 possible values of resistor wd_ osc r osc 34 120 k a 13.3 oscillator period r osc = 34k t osc 10.65 13.3 15.97 s a 13.4 oscillator period r osc = 51k t osc 15.68 19.6 23.52 s a 13.5 oscillator period r osc = 91k t osc 26.83 33.5 40.24 s a 13.6 oscillator period r osc = 120k t osc 34.2 42.8 51.4 s a 14 watchdog timing relative to t osc 14.1 watchdog lead time after reset t d 7895 cycles a 14.2 watchdog closed window t 1 1053 cycles a 14.3 watchdog open window t 2 1105 cycles a 14.4 watchdog reset time nres nres t nres 3.2 4 4.8 ms a 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 24 15 kl_15 pin 15.1 high-level input voltage r v = 47 k positive edge initializes a wake-up kl_15 v kl_15h 4 v s + 0.3v v a 15.2 low-level input voltage r v = 47 k kl_15 v kl_15l ?1 +2 v a 15.3 kl_15 pull-down current v s < 27v v kl_15 = 27v kl_15 i kl_15 50 65 a a 15.4 internal debounce time without external capacitor kl_15 tdb kl_15 80 160 250 s a 15.5 kl_15 wake-up time r v = 47k , c = 100nf kl_15 tw kl_15 0.4 2 4.5 ms c 16 wake pin 16.1 high-level input voltage wake v wakeh v s ? 1v v s + 0.3v v a 16.2 low-level input voltage initializes a wake-up signal wake v wakel ?1 v s ? 3.3v v a 16.3 wake pull-up current v s < 27v v wake = 0v wake i wake ?30 ?10 a a 16.4 high-level leakage current v s = 27v v wake = 27v wake i wakel ?5 +5 a a 16.5 time of low pulse for wake-up via wake pin v wake = 0v wake i wakel 30 70 150 s a 17 vcc voltage regulator, pvcc = vcc 17.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc vcc nor 4.9 5.1 v a 6v < v s < 18v (0ma to 85ma) vcc vcc nor 4.9 5.1 v c 17.2 output voltage vcc at low vs 4v < v s < 5.5v vcc vcc low v s ? v d 5.1 v a 17.3 regulator drop voltage v s > 4v i vcc = ?20ma vs, vcc v d1 250 mv a 17.4 regulator drop voltage v s > 4v i vcc = ?50ma vs, vcc v d2 400 600 mv a 17.5 regulator drop voltage v s > 3.3v i vcc = ?15ma vs, vcc v d3 200 mv a 17.6 line regulation 5.5v < v s < 18v vcc vcc line 0.1 0.2 % a 17.7 load regulation 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 17.8 power supply ripple rejection 10hz to 100khz c vcc = 10f v s = 14v, i vcc = ?15ma vcc 50 db d 17.9 output current limitation v s > 5.5v vcc i vcclim ?240 ?130 ?85 ma a 17.10 external load capacity 0.2 < esr < 5 at 100khz for phase margin 60 vcc c load 1.8 10 f d esr < 0.2 at 100khz for phase margin 30 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
25 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 3-10. definition of bus timing characteristics 17.11 vcc undervoltage threshold referred to vcc v s > 5.5v vcc v thunn 4.2 4.8 v a 17.12 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vcc vhys thun 250 mv a 17.13 ramp-up time v s > 5.5v to v cc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 130 300 s a 3.7 electrical characteristics (continued) 5v < v s < 27v, ?40c < t case < 125c, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 26 4. atmel attiny87/attiny167 microcontrol ler block for atmel ata6616c/ata6617c 4.1 features high performance, low power avr ? 8-bit microcontroller advanced risc architecture 123 powerful instructions ? mo st single clock cycle execution 32 8 general purpose working registers fully static operation non-volatile program and data memories 8kbytes/16kbytes of in-system progra mmable (isp) program memory flash endurance: 10,000 write/erase cycles 512 bytes in-system programmable eeprom endurance: 100,000 write/erase cycles 512 bytes internal sram programming lock for self-programming flash program and eeprom data security low size lin/uart software in-system programmable peripheral features lin 2.1 and 1.3 controller or 8-bit uart 8-bit asynchronous timer/counter0: 10-bit clock prescaler 1 output compare or 8-bit pwm channel 16-bit synchronous timer/counter1: 10-bit clock prescaler external event counter 2 output compares units or 16-bit pwm c hannels each driving up to 4 output pins master/slave spi serial interface, universal serial interface (usi) with start condition detector (ma ster/slave spi, twi,...) 10-bit adc: 11 single ended channels 8 differential adc channel pairs with programmable gain (8x or 20x) on-chip analog comparator with selectable voltage reference 100a 10% current source (lin node identification) on-chip temperature sensor programmable watchdog timer with separate on-chip oscillator special microcontroller features dynamic clock switching (external/internal rc/wa tchdog clock) for power control, emc reduction debugwire on-chip debug (ocd) system hardware in-system progra mmable (isp) via spi port external and internal interrupt sources interrupt and wake-up on pin change low power idle, adc noise reduction, and power-down modes enhanced power-on reset circuit programmable brown-out detection circuit internal calibrated rc oscillator 8mhz 4mhz to 16mhz and 32khz crystal/ceramic resonator oscillators
27 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 i/o and packages 16 programmable i/o lines 20-pin soic, 32-pad qfn and 20-pin tssop operating voltage: 2.7v to 5.5v for atmel ? attiny87/attiny167 speed grade: 0mhz to 8mhz at 2.7v to 5.5v (autom otive temperature rang e: ?40c to +125c) 0mhz to 16mhz at 4.5v to 5.5v (autom otive temperature range: ?40c to +125c) 4.2 description 4.2.1 comparison between atmel attiny87 and atmel attiny167 atmel attiny87 and atmel attiny167 are hardware and software co mpatible. they differ only in memory sizes as shown in table 4-1 . 4.2.2 part description the atmel attiny87/167 is a low-power cmos 8-bit microcontroller based on the avr ? enhanced risc architecture. by executing powerful instruct ions in a single clock cycle, the atmel attiny87/167 achieves throughput s approaching 1mips per mhz allowing the system desi gner to optimize powe r consumption versus processing speed. the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulti ng architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmel attiny87/167 provid es the following features: 8k/16kbyte of in-system programmable flash, 512bytes eeprom, 512bytes sram, 16 general purpose i/o lines, 32 general purpos e working registers, one 8-bi t timer/counter with compare modes, one 8-bit high speed timer/counter, universal serial inte rface, a lin controller, intern al and external interrupts, a 11-channel, 10-bit adc, a programmable watchdog timer with internal oscillator, and three software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode sa ves the register contents, disabling all chip functions until the next interrupt or hardware reset. the adc noise reduct ion mode stops the cpu and all i/o modules except adc, to minimize switching noise during adc conversions. the device is manufactured using atmel high density non-vo latile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-s ystem through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core . the boot program can use any interface to download the application program in the flash memory. by combining an 8-bit risc cpu with in -system self-programmable flash on a monol ithic chip, the atmel attiny87/167 is a powerful microcontroller that provides a highly flexible and co st effective solution to many embedded control applications. the atmel attiny87/167 avr is supported with a full suite of program and system dev elopment tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. table 4-1. memory size summary device flash eeprom sram interrupt vector size attiny167 16kbytes 512bytes 512bytes 2-instruction-words / vector attiny87 8kbytes 512bytes 512bytes 2-instruction-words / vector
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 28 4.2.3 automotive quality grade the atmel ? attiny87/167 have been developed and manufactured acco rding to the most stringe nt requirements of the international standard iso-ts-16949. this data sheet contains limit values ex tracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the atmel attiny87/167 have been verified during regular product qualificatio n as per aec-q100 grade 1. as indicated in the ordering information paragraph, this docu ment refers only to grade 1 products, for grade 0 products refer to appendix a. 4.2.4 disclaimer typical values contained in this data sheet are bas ed on simulations and characterization of other avr ? microcontrollers manufactured on the same process technology. min. and max va lues will be available after the device is characterized. table 4-2. temperature grade identification for automotive products temperature temperature identifier comments ?40c/+125c z grade 1 ?40c/+150c d grade 0
29 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.2.5 block diagram figure 4-1. block diagram 4.2.6 resources a comprehensive set of development to ols, application notes and datasheet s are available for download on http://www.atmel.com/avr . 4.2.7 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part sp ecific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt h andling in c is compiler depende nt. please conf irm with the c compiler documentation for more details. power supervision por/bod and reset oscillator circuits/ clock generation watchdog timer watchdog oscillator program logic debugwire avr cpu eeprom data bus flash gnd vcc a/d conv. internal voltage references timer/ counter-1 timer/ counter-0 analog comparator spi and usi 11 2 port b (8) port a (8) lin/uart sram avcc aref reset xtal[1; 2] pb[0 to 7] pa[0 to 7]
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 30 4.3 avr cpu core 4.3.1 overview this section discusses the avr ? core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to acce ss memories, perform calculations, control peripherals, and handle interrupts. figure 4-2. block diagram of the avr architecture status and control interrupt unit 32 x 8 general purpose registers alu data bus 8-bit data sram watchdog timer instruction register instruction decoder analog comparator eeprom i/o lines i/o module n control lines direct addressing indirect addressing i/o module 2 i/o module 1 a.d.c. program counter flash program memory
31 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 in order to maximize perfor mance and parallelism, the avr ? uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memo ry are executed with a single level pipelining. while one instruction is being executed, the next in struction is pre-fetched from the program memory. this co ncept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working regi sters with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu operation, two operands are output from the register file, the operat ion is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers c an also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16 -bit x-, y-, and z-register, de scribed later in this section. the alu supports arithmetic and logic operat ions between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional ju mp and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address prog ram counter (pc) is stored on the stack. the stack is effectively allocated in the general data sr am, and consequently the stack size is onl y limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read /write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate interrupt vector in th e interrupt vector table. the interrupts have priority in accord ance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. 4.3.2 alu ? arithmetic logic unit the high-performance avr alu operates in direct connection wi th all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general pu rpose registers or between a register and an immediate are executed. the alu operations are divided into three main ca tegories ? arithmetic, logica l, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 4.3.3 status register the status register contains information about the result of the most rec ently executed arithmetic instruction. this information can be used for altering program flow in order to per form conditional operations. note that the status register is updated after all alu operations, as specifi ed in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, re sulting in faster and more compact code. the status register is not automati cally stored when entering an interrupt r outine and restored when returning from an interrupt. this must be handled by software.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 32 4.3.3.1 sreg ? avr status register the avr ? status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bi t is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subs equent interrupts. the i-bit can also be se t and cleared by the application with the sei and cli instructions, as describ ed in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) us e the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by th e bst instruction, and a bit in t can be copied into a bit in a register in the register f ile by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is usef ul in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative fl ag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s comple ment arithmetic. see the ?ins truction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?ins truction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or l ogic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logi c operation. see the ?instruction set description? for detailed information. bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
33 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.3.4 general purpose register file the register file is optimized for the avr ? enhanced risc instruction set. in order to achieve the required performance and flexibility, the following in put/output schemes are supported by the register file: one 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input one 16-bit output operand an d one 16-bit result input figure 4-3 shows the structure of the 32 general purpose working registers in the cpu. figure 4-3. avr cpu general purpose working registers most of the instructions operating on the regi ster file have direct access to all regi sters, and most of them are single cycle instructions. as shown in figure 4-3 , each register is also assigned a data memory addr ess, mapping them directly into the first 32 locations of the user data space. although not being physically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x- , y- and z-pointer registers can be set to index any register i n the file. 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 34 4.3.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three i ndirect address registers x, y, and z are defined as described in figure 4-4 . figure 4-4. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instru ction set reference for details). 4.3.5 stack pointer the stack is mainly used for storing te mporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register alwa ys points to the top of the st ack. note that the stack is implemented as growing from higher memory locations to lower memory locations. this implie s that a stack push command decreases the stack pointer. the stack pointer points to t he data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine call s are executed or interrupts are enabled. the stack pointer must be set to point above 0x60. the stack po inter is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremen ted by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr ? stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some impl ementations of the avr architec ture is so small that only spl is needed. in this case, the sph register will not be present 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e)
35 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.3.5.1 sph and spl ? stack pointer register 4.3.6 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr ? cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 4-5 shows the parallel instruction fetches and instruction exec utions enabled by the harvar d architecture and the fast access register file concept. this is the basic pipelining co ncept to obtain up to 1mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-5. the parallel instructio n fetches and instruction executions figure 4-6 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 4-6. single cycle alu operation bit 151413121110 9 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value isram end (see table 4-3 on page 38 ) clk cpu 1st instruction fetch 1st instruction execute 2nd instruction fetch t1 t2 t3 t4 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch clk cpu t1 register operands fetch result write back alu operation execute total execution time t2 t3 t4
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 36 4.3.7 reset and interrupt handling the avr ? provides several different interrupt sources. these in terrupts and the separate reset vector each have a separate program vector in the program memory sp ace. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in t he status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the re set and interrupt vect ors. the complete list of vectors is shown in section 4.8 ?interrupts? on page 76 . the list also determines the prio rity levels of the different interrupts. the lower the addres s the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. 4.3.7.1 interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cl eared and all interrupts are disabled. the user software can write logic one to the i-bit to enable nested interrupts. all enab led interrupts can then interrupt the current interrupt routi ne. the i-bit is automatically set when a return fr om interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interr upt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bi t position(s) to be cleared. if an interrupt condition occurs while the corres ponding interrupt enable bit is cleared, the interr upt flag will be set and remembered until the inte rrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set an d remembered until the global interrupt enable bit is se t, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interr upt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears befo re the interrupt is enabled, the interrupt will not be triggere d. when the avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status regi ster is not automatically stored when entering an in terrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the inte rrupts will be immediately disabled. no interrupt will be execute d after the cli instruction, even if it occu rs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence.
37 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 when using the sei instruction to enable interrupts, the in struction following sei will be executed before any pending interrupts, as shown in this example. 4.3.7.2 interrupt response time the interrupt execution response for all the enabled avr ? interrupts is four clock cycles mi nimum. after four clock cycles the program vector address for the actual interr upt handling routine is exec uted. during this four cl ock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs du ring execution of a multi-cycle in struction, this inst ruction is completed before the interrup t is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt hand ling routine takes four clock cycl es. during these four clock cycl es, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 38 4.4 avr memories this section describes the diff erent memories in the atmel ? attiny87/167. the avr ? architecture has two main memory spaces, the data memory and the program memory space. in addition, the atmel attiny87/167 features an eeprom memory for data storage. all three memory spaces are linear and regular. 4.4.1 in-system re-programmable flash program memory the atmel attiny87/167 contains on-chip in-system reprogrammable flash memory fo r program storage (see ?flash size? in table 4-3 ). since all avr instructions are 16 or 32 bits wide, the flash is organized as 16 bits wide. atmel attiny87/167 does not have separate boot loader and applic ation program sections, and the spm inst ruction can be executed from the entire flash. see selfprgen description in section 4.21.2.1 ?store program memory control and status register ? spmcsr? on page 217 for more details. the flash memory has an endurance of at least 10,000 write/erase cycles in automotive range. the atme l attiny87/167 program counter (pc) address the program memory locations. section 4.22 ?memory programming? on page 222 contains a detailed description on flash data serial downloading using the spi pins. constant tables can be allocated within the entire progra m memory address space (see t he lpm ? load program memory instruction description). timing diagrams for instruction fetc h and execution are presented in section 4.3.6 ?instruction execution timing? on page 35 . table 4-3. memory mapping. memory mnemonic attiny87 attiny167 flash size flash size 8kbytes 16kbytes start address - 0x0000 end address flash end 0x1fff (1) 0x0fff (1) 0x3fff (1) 0x1fff (1) 32 registers size - 32 bytes start address - 0x0000 end address - 0x001f i/o registers size - 64 bytes start address - 0x0020 end address - 0x005f ext i/o registers size - 160 bytes start address - 0x0060 end address - 0x00ff internal sram size isram size 512 bytes start address isram start 0x0100 end address isram end 0x02ff eeprom size e2 size 512 bytes start address - 0x0000 end address e2 end 0x01ff notes: 1. byte address. 2. word (16-bit) address.
39 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-7. program memory map 4.4.2 sram data memory figure 4-8 shows how the atmel ? attiny87/167 sram memory is organized. the atmel attiny87/167 is a complex microcontroller with mo re peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out inst ructions. for the extended i/o space in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next locations address the internal data sram (see ?isram size? in table 4-3 on page 38 ). the five different addressing modes for the data memory cover: direct, indirect with displacement, indirect, indirect with pre-decrement, and indirect with post-increment. in the regist er file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locati ons from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o registers and the internal data sram in the atmel attiny87/167 are all accessible through all these addressing modes. the register file is described in section 4.3.4 ?general purpose register file? on page 33 . figure 4-8. data memory map 0x0000 flash end program memory 32 registers data memory 0x0000 - 0x001f 0x0020 - 0x005f 0x0060 - 0x00ff isram start isram end 64 i/o registers 160 ext i/o registers internal sram (isram size)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 40 4.4.2.1 data memory access times this section describes the general access timing concepts for internal memory access. the in ternal data sram access is performed in two clk cpu cycles as described in figure 4-9 . figure 4-9. on-chip data sram access cycles 4.4.3 eeprom data memory the atmel ? attiny87/167 co ntains eeprom memory (see ?e2 size? in table 4-3 on page 38 ). it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles in automotive range. the access bet ween the eeprom and the cpu is described in the following, specifying the eeprom address registers, the eeprom data register and the eeprom control register. section 4.22 ?memory programming? on page 222 contains a detailed description on eeprom programming in spi or parallel programming mode. 4.4.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access times for the eeprom are given in table 4-4 on page 44 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instructions that write the eeprom, some precautions must be taken. in heavily filt ered power supplies, vcc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a volt age lower than specified as minimum for the clock frequency used. see section 4.4.3.6 ?preventing eeprom corruption? on page 42 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes , a specific write procedure must be followed. refer to section 4.4.3.2 ?atomic byte programming? on page 40 and section 4.4.3.3 ?split byte programming? on page 40 for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instru ction is executed. when the eeprom is written, the cpu is ha lted for two clock cycles before the next instruction is executed. 4.4.3.2 atomic byte programming using atomic byte programming is the simplest mode. when wr iting a byte to the eeprom, th e user must write the address into the eearl register and data into eedr register. if th e eepmn bits are zero, writing eepe (within four cycles after eempe is written) will trigger the erase/ write operation. both the erase and wr ite cycle are done in one operation and the total programming time is given in tabl e 1. the eepe bit remains set until the erase and write operations are completed. while the device is busy with programming, it is not possible to do any other eeprom operations. 4.4.3.3 split byte programming it is possible to split the eras e and write cycle in two different operations. th is may be useful if the system requires short access time for some limited period of time (typically if the pow er supply voltage falls). in or der to take advantage of this method, it is required that the location s to be written have been erased before th e write operation. but since the erase and write operations are split, it is possible to do the erase opera tions when the system allows doing time-critical operations (typically a fter power-up). clk cpu t1 data data rd wr address valid compute address next instruction write read memory access instruction a ddress t2 t3
41 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.4.3.4 erase to erase a byte, the address must be writ ten to eear. if the eepmn bits are 0b01, writing the eepe ( within four cycles after eempe is written) will trigger the erase op eration only (programming time is gi ven in table 1). the eepe bit remains set until the erase operation comple tes. while the device is bu sy programming, it is not possi ble to do any other eeprom operations. 4.4.3.5 write to write a location, the user must writ e the address into eear and the data into eedr. if the eepmn bits are 0b10, writing the eepe (within four cycles after eempe is written) will trigge r the write operation only (p rogramming time is given in table 1-1 ). the eepe bit remains set until the write operation complete s. if the location to be written has not been erased before write, the data that is stored must be considered as lost. while t he device is busy with programming, it is not possible to do any other eeprom operations. the calibrated oscillator is used to time the eeprom accesses. make sure the oscillator frequency is within the requirements described in section 4.5.5.1 ?osccal ? oscillato r calibration register? on page 58 . the following code examples show one assembly and one c func tion for erase, write, or atom ic write of the eeprom. the examples assume that interrupts are controlled (e.g., by disa bling interrupts globally) so that no interrupts will occur during execution of these functions. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set programming mode ldi r16, (0< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 42 the next code examples show assembly and c functions fo r reading the eeprom. the examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. 4.4.3.6 preventing eeprom corruption during periods of low vcc, the eeprom da ta can be corrupted because the supply voltage is too low for the cpu and the eeprom to operate properly. these issues are the same as for board level systems using eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regu lar write sequence to the eeprom requires a minimum vo ltage to operate correct ly. secondly, the cpu itself can ex ecute instructions incorrectly, if the supply voltage is too low. eeprom data corruption can easily be avoided by fo llowing this design recommendation: keep the avr ? reset active (low) during periods of insufficient powe r supply voltage. this can be done by enabling the internal brown-out detector (bod). if the detection level of the in ternal bod does not match the needed detection level, an external low vcc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. assembly code example eeprom_read: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_read ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; start eeprom read by writing eere sbi eecr,eere ; read data from data register in r16,eedr ret c code example unsigned char eeprom_read( unsigned char ucaddress) { /* wait for completion of previous write */ while(eecr & (1< 43 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.4.4 i/o memory the i/o space definition of the atmel ? attiny87/167 is shown in section 4.26 ?register summary? on page 256 . all atmel attiny87/167 i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address r ange 0x00 - 0x1f are directly bit-accessibl e using the sbi and cbi instructions. in these registers, the value of single bits c an be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific comma nds in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel attiny87/167 is a complex microcont roller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. for compatibility with future devices, reserved bits should be wr itten to zero if accessed. re served i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note t hat, unlike most other avr, the cbi and sbi instructions will only operate on the spec ified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 4.4.4.1 general purpose i/o registers the atmel attiny87/167 contains three general purpose i/o registers. these registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. the general purpose i/o registers within the address range 0x00 - 0x1f are directly bit-acce ssible using the sbi, cbi, sbis, and sbic instructions. 4.4.5 register description 4.4.5.1 eearh and eearl ? eeprom address register ? bit 7:1 ? reserved bits these bits are reserved for future use and will always read as 0 in atmel attiny87/167. ? bits 8:0 ? eear8:0: eeprom address the eeprom address registers ? eearh and eearl ? specifies the high eeprom address in the eeprom space (see ?e2 size? in table 4-3 on page 38 ). the eeprom data bytes are addressed line arly between 0 and ?e2 size?. the initial value of eear is undefined. a proper value mu st be written before the eeprom may be accessed. bit 76543210 -------eear8 eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl bit 76543210 read/writerrrrrrrr/w read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000000x initial valuexxxxxxxx
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 44 4.4.5.2 eedr ? eeprom data register ? bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation the eedr regi ster contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read o peration, the eedr contains the data read out from the eeprom at the address given by eear. 4.4.5.3 eecr ? eeprom control register ? bit 7,6 ? res: reserved bits these bits are reserved for future use and will always read as 0 in atmel attiny87/167. after reading, mask out these bits. for compatibility with future avr ? devices, always write these bits to zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bits setting defines which pr ogramming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new val ue) or to split the erase and write operations in two different o perations. the programming times for the different modes are shown in table 4-4 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i-bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant in terrupt when non-volatile memory is ready for programming. ? bit 2 ? eempe: eeprom master program enable the eempe bit determines whet her writing eepe to one will have effect or not. when eempe is set, setting eepe within four clock cycles will program the eeprom at the selected address. if eempe is zero, setting eepe will have no effect. when eempe has been writte n to one by software, hardware clears the bit to zero after four clock cycles. bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 table 4-4. eeprom mode bits eepm1 eepm0 typical programming time operation 0 0 3.4ms erase and write in one operation (atomic operation) 0 1 1.8ms erase only 1 0 1.8ms write only 1 1 ? reserved for future use
45 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 1 ? eepe: eeprom program enable the eeprom program enable signal eepe is the programming enable signal to the eeprom. wh en eepe is written, the eeprom will be programmed according to the eepmn bits setting. the eempe bit must be written to one before a logical one is written to eepe, other wise no eeprom write takes plac e. when the write access time has elapsed, t he eepe bit is cleared by hardware. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal ? eere ? is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to one to trigger the eeprom read. the eeprom read access takes one instruction, and the reques ted data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. 4.4.5.4 general purpose i/o register 2 ? gpior2 4.4.5.5 general purpose i/o register 1 ? gpior1 4.4.5.6 general purpose i/o register 0 ? gpior0 4.5 system clock and clock options the atmel ? attiny87/167 provides a large number of clock sources. they can be divided into two categories: internal and external. some external clock sources can be shared with t he asynchronous timer. after re set, the clock source is determined by the cksel fuses. once t he device is running, software clock swit ching is possible to any other clock sources. hardware controls are provided for clock switching managem ent but some specific procedu res must be observed. clock switching should be performed with caution as some settings c ould result in the device having an incorrect configuration. bit 76543210 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 gpior2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gpior10 gpior1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 gpior0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 46 4.5.1 clock systems and their distribution figure 4-10 presents the principal clock systems in the avr ? and their distributi on. all of the clocks may not need to be active at any given time. in or der to reduce power consumptio n, the clocks to modules not be ing used can be halted by using different sleep modes or by using featur es of the dynamic clock switch circuit (see section 4.6 ?power management and sleep modes? on page 62 and section 4.5.3 ?dynamic clock switch? on page 52 ). the clock systems are detailed below. figure 4-10. clock distribution 4.5.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with the avr core operation. exampl es of such modules are the general purpose register file, the status register and the data memory hol ding the stack pointer. halting the cpu clock inhibits the core from performing ge neral operations and calculations. 4.5.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like synchronous timer/counter. the i/o clock is also used by the external interrupt module, but note that some external in terrupts are detected by asynch ronous logic, allowing such interrupts to be detected even if the i/o clock is halted. 4.5.1.3 flash clock ? clk flash the flash clock controls operation of the flash interface. the flash clock is usually active simultaneously with the cpu clock. asynchronous timer/counter0 flash and eeprom calibrated rc oscillator low-frequency crystal oscillator crystal oscillator watchdog oscillator prescaler ckout fuse multiplexer pb4/xtal1/clki pb5/xtal2/clko general i/o avr clock control unit adc external clock cpu core source clock watchdog clock ram reset logic watchdog timer clk i/o clk asy clk cpu clk adc clk flash clock switch
47 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.5.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/count er to be clocked directly from an external clock or an external low frequency crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 4.5.1.5 adc clock ? clk adc the adc is provided with a dedicated clock do main. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this give s more accurate adc conversion results. 4.5.2 clock sources the device has the following cl ock source options, selectable by flash fuse bits (default) or by the clkselr register (dynamic clock switch circuit) as shown below. the clock from the selected source is input to the avr ? clock generator, and routed to the appropriate modules. the various choices for each clocking option are given in the following sections. when the cpu wakes up from power-down or power-save, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring st able oscillator operation before instruction execution starts. when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. the watchdog oscillator is used for timing this real-time part of the start-up sequence. the number of wdt oscillator cycles used for ea ch time-out is shown in table 4-6 . 4.5.2.1 default clock source at reset, the cksel and sut fuse settings are copied into the clkselr register. the device will then use the clock source and the start-up timings defined by th e clkselr bits (csel3..0 and csut1:0). the device is shipped with cksel fuses = 0010 b , sut fuses = 10 b , and ckdiv8 fuse programmed. the default clock source setting is therefore the internal rc oscillator running at 8mhz with the longest start- up time and an initial system clock divided by 8. this default setting ens ures that all users can make their desired clock source setti ng using an in-system or high-voltage programmer. this set-up must be taken into account when using isp tools. table 4-5. device clocking options select (1) versus pb4 and pb5 functionality device clocking option cksel3..0 (2) csel3..0 (3) pb4 pb5 external clock 0000 b clki clko - i/o calibrated internal rc oscillator 8.0mhz 0010 b i/o clko - i/o watchdog oscillator 128khz 0011 b i/o clko - i/o external low-frequency oscillator 01xx b xtal1 xtal2 external crystal/ceramic resonator (0.4 - 0.9mhz) 100x b xtal1 xtal2 external crystal/ceramic resonator (0.9 - 3.0mhz) 101x b xtal1 xtal2 external crystal/ceramic resonator (3.0 - 8.0mhz) 110x b xtal1 xtal2 external crystal/ceramic resonator (8.0 - 16.0mhz) 111x b xtal1 xtal2 notes: 1. for all fuses ?1? means unpr ogrammed while ?0? means programmed 2. flash fuse bits 3. clkselr register bits table 4-6. number of watc hdog oscillator cycles typ. time-out (vcc = 5.0v) typ. time-out (vcc = 5.0v) number of cycles 4.1ms 4.3ms 512 65ms 69ms 8k (8,192)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 48 4.5.2.2 calibrated internal rc oscillator by default, the internal rc oscillator provides an approxim ate 8.0mhz clock. the frequency is nominal at 5v and 25c. though voltage and temperature dependent, this cl ock can be accurately calibrated by the user. see table 4-81 on page 239 and section 4.25.7 ?internal osc illator speed? on page 254 for more details. if selected, it can operate wit hout external components. at reset, hardware loads the pre-programmed calibration value into the osccal register and thereby automatica lly configuring the rc oscill ator. at 5v and 25 c, this calibration gives a frequency of 8mhz 1%. the tolerance of the internal rc oscillator remains be tter than 10% within the whole automotive temperature and voltage ranges (4.5v to 5.5v, ?40c to +125c). the accuracy of this calibration is shown as factory calibration in table 4-81 on page 239 . by adjusting the osccal register in software, see section 4.5.5.1 ?osccal ? oscillator calibration register? on page 58 , it is possible to get a higher calibration accuracy than by usin g the factory calibration. the accuracy of this calibration is shown as user calibration in table 4-81 on page 239 . the watchdog oscillator will still be used for the watchdog time r and for the reset time-out even when this oscillator is used as the device clock. for more information on the pre-programmed calibration value, see the section section 4.22.4 ?calibration byte? on page 224 . when this oscillator is selected, start-up times are dete rmined by the sut fuses or by csut field as shown in table 4-8 . table 4-7. internal calibrated rc oscillator operating modes (1) frequency range (2) (mhz) cksel3..0 (3)(4) csel3..0 (5) 7.6 - 8.4 0010 notes: 1. if 8mhz frequency exceeds the specification of the device (depends on vcc), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8 2. the frequency ranges are guideline values 3. the device is shipped with this cksel = ?0010? 4. flash fuse bits. 5. clkselr register bits table 4-8. start-up times for the internal calibrated rc oscillator clock selection sut1..0 (1) csut1..0 (2) start-up time from power-down/save additional delay from reset (vcc = 5.0v) recommended usage 00 (3) 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1ms fast rising power 10 (4) 6 ck 14ck + 65ms slowly rising power 11 reserved notes: 1. flash fuse bits 2. clkselr register bits 3. this setting is only available if rstdisbl fuse is not set 4. the device is shipped with this option selected
49 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.5.2.3 128khz internal oscillator the 128khz internal oscillator is a low power oscillator pr oviding a clock of 128khz. the frequency is nominal at 5v and 25c. this clock may be selected as the system clock by programming c ksel fuses or csel field as shown in table 4-5 on page 47 . when this clock source is selected, start-up times are determined by the sut fuses or by csut field as shown in table 4-9 . 4.5.2.4 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inve rting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 4-11 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and res onators. the optimal value of the capacitors depends on the crystal or resonator in use, t he amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 4-10 . for ceramic resonators , the capacitor values given by the manufacturer should be used. figure 4-11. crystal oscillator connections table 4-9. start-up times for th e 128khz internal oscillator sut1..0 (1) csut1..0 (2) start-up time from power-down/save additional delay from reset (vcc = 5.0v) recommended usage 00 (3) 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1ms fast rising power 10 6 ck 14ck + 65ms slowly rising power 11 reserved notes: 1. flash fuse bits 2. clkselr register bits 3. this setting is only available if rstdisbl fuse is not set c2 xtal2 xtal1 gnd c1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 50 the oscillator can operate in three diff erent modes, each optimized for a specif ic frequency range. the operating mode is selected by cksel3..1 fuses or by csel3..1 field as shown in table 4-10 . the cksel0 fuse together with the sut1..0 fu ses or csel0 together with cs ut1..0 field select the start-up times as shown in table 4-11 . table 4-10. crystal oscillator operating modes cksel3..1 (1) csel3..1 (2) frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (3) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 notes: 1. flash fuse bits 2. clkselr register bits 3. this option should not be used with crystals, only with ceramic resonators table 4-11. start-up times for the cr ystal oscillator clock selection cksel0 (1) csel0 (2) sut1..0 (1) csut1..0 (2) start-up time from power-down/save additional delay from reset (vcc = 5.0v) recommended usage 0 00 258 ck (3) 14ck + 4.1ms ceramic resonator, fast rising power 0 01 258 ck (3) 14ck + 65ms ceramic resonator, slowly rising power 0 10 (5) 1k (1024) ck (4) 14ck ceramic resonator, bod enabled 0 11 1k (1024)ck (4) 14ck + 4.1ms ceramic resonator, fast rising power 1 00 1k (1024)ck (4) 14ck + 65ms ceramic resonator, slowly rising power 1 01 (5) 16k (16384) ck 14ck crystal oscillator, bod enabled 1 10 16k (16384) ck 14ck + 4.1ms crystal oscillator, fast rising power 1 11 16k (16384) ck 14ck + 65ms crystal oscillator, slowly rising power notes: 1. flash fuse bits. 2. clkselr register bits. 3. these options should only be used when not operatin g close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 4. these options are intended for use with ceramic res onators and will ensure frequency stability at start-up. they can also be used with crystals when not operat ing close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 5. this setting is only available if rstdisbl fuse is not set.
51 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.5.2.5 low-frequency crystal oscillator to use a 32.768khz watch crystal as the clock source for the dev ice, the low-frequency crystal osc illator must be selected by setting cksel fuses or c sel field as shown in table 4-5 on page 47 . the crystal should be connected as shown in figure 4-12 . refer to the 32.768khz crystal oscillator application not e for details on oscillator operation and how to choose appropriate values for c1 and c2. the 32.768khz watch crystal oscillator can be used by the asynchronous timer if the (high-frequency) crystal oscillator is not running or if the external clock is not enabled (see section 4.5.3.3 ?enable/dis able clock source? on page 54 ). the asynchronous timer is then able to start itself this low-frequency crystal oscillator. figure 4-12. low-frequency crystal oscillator connections when this oscillator is selected, start-up times are dete rmined by the sut fuses or by csut field as shown in table 4-12 . table 4-12. start-up times for the low freq uency crystal oscillator clock selection sut1..0 (1) csut1..0 (2) start-up time from power-down/save additional delay from reset (vcc = 5.0v) recommended usage 00 1k (1024) ck (3) 4.1ms fast rising power or bod enabled 01 1k (1024) ck (3) 65ms slowly rising power 10 32k (32768) ck 65ms stable frequency at start-up 11 reserved notes: 1. flash fuse bits 2. clkselr register bits 3. these options should only be used if frequency stability at start-up is not important for the application c1 = 12 to 22pf c2 = 12 to 22pf 12 to 22pf capacitors may be necessary if parasitic impedance (pads, wires and pcb) is very low. xtal2 32.768khz xtal1 gnd
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 52 4.5.2.6 external clock to drive the device from this external clock source, clki should be driven as shown in figure 4-13 . to run the device on an external clock, the cksel fuses or csel field must be programmed as shown in table 4-5 on page 47 . figure 4-13. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses or csut field as shown in table 4-13 this external clock can be used by the asynchronous timer if the high or low frequency crystal oscillator is not running (see section 4.5.3.3 ?enable/disable clock source? on page 54 ). the asynchronous timer is then able to enable this input. note that the system clock prescaler can be used to implemen t run-time changes of the internal clock frequency while still ensuring stable operation. refer to section 4.5.4 ?system clock prescaler? on page 58 for details. 4.5.2.7 clock output buffer if not using a crystal oscillator, the dev ice can output the system clock on the cl ko pin. to enable the output, the ckout fuse or cout bit of clkselr register has to be programmed. this option is useful when the device clock is needed to drive other circuits on the system. note th at the clock will not be output during reset and the normal operation of i/o pin wil l be overridden when the fuses are programmed. if the sy stem clock prescaler is used, it is the divided system clock that is output. 4.5.3 dynamic clock switch 4.5.3.1 features the atmel ? attiny87/167 provides a powerful dynamic clock switch circuit that allows users to turn on and off clocks of the device on the fly. the built-in de-glitching circuitry allows clocks to be enabled or disa bled asynchronously. this enables efficient power management schemes to be implemented easily and quickly. in a safety application, the dynamic clock switch circuit allows continuous monitoring of the external clock permitting a fallback schem e in case of clock failure. the control of the dynamic clock switch circuit must be supervis ed by software. this operation is facilitated by the following features: safe commands , to avoid unintentional commands, a special write procedure must be followed to change the clkcsr register bits ( section 4.5.5.2 ?clkpr ? clock prescaler register? on page 59 ) table 4-13. start-up times for th e external clock selection sut1..0 (1) csut1..0 (2) start-up time from power-down/save additional delay from reset (vcc = 5.0v) recommended usage 00 6ck 14ck (+ 4.1ms (3) ) bod enabled 01 6ck 14ck + 4.1ms fast rising power 10 6ck 14ck + 65ms slowly rising power 11 reserved notes: 1. flash fuse bits 2. clkselr register bits 3. additional delay (+ 4ms) available if rstdisbl fuse is set (xtal2) (clko) clki (xtal1) gnd external clock signal ~
53 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 exclusive action , the actions are controlled by a decoding table (commands) written to the clkcsr register. this ensures that only one command operation can be launched at any time. the main actions of the decoding table are: ?disable clock source?, ?enable clock source?, ?request clock availability?, ?clock source switching?, ?recover system clock source?, ?enable watchdog in automatic reload mode?. command status return. the ? request clock availability ? command returns status via the clkrdy bit in the clkcsr register. the ? recover system clock source ? command returns a code of the current clock source in the clkselr register. this informati on is used in the supervisory so ftware routines as shown in section 4.5.3.7 on page 54 . 4.5.3.2 clkselr register fuses substitution at reset, bits of the low fuse byte are copied into the clksel r register. the content of this register can subsequently be user modified to overwrite the default values from the low fuse byte. cksel3..0, sut1..0 and ckout fuses correspond respectively to csel3..0, csut1:0 and ~(cout ) bits of the clkselr register as shown in figure 4-14 on page 53 . source selection the available codes of clock source are given in table 4-5 on page 47 . figure 4-14. fuses substitution and clock source selection the clkselr register contains the csel, csut and cout values which will be used by the ?enable/disable clock source?, ?request for clock availability? or ?clock source switching? commands. source recovering the ? recover system clock source ? command updates the cksel field of clkselr register (see section 4.5.3.6 ?system clock source recovering? on page 54 ). internal data bus default r/w reg. fuse: fuse low byte register: clkselr selected configuration clock switch current configuration reset clksel [3..0] sut [1..0] ckout csel [3..0] csut [1..0] cout sel decoder sclkrq (*) sclkrq (*) :command of clock control and status register cksel[3..0] en-0 ckout en-1 en-2 en-n sel-0 sel-1 sel-2 sel-n sel encoder sut[1..0]
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 54 4.5.3.3 enable/disable clock source the ? enable clock source ? command selects and enables a clock source configured by the se ttings in the clkselr register. csel3..0 will select the clock so urce and csut1:0 will select the start-up time (just as cksel and sut fuse bits do). to be sure that a clock source is operating, the ? request for clock availability? command must be executed after the ? enable clock source ? command. this will indicate via the clkrdy bit in the clkcsr register that a valid clock source is available and operational. the ? disable clock source ? command disables the clock so urce indicated by the settings of cl kselr register (only csel3..0). if the clock source indicated is currently the one that is used to drive the syst em clock, the command is not executed. because the selected configuration is latched at clock source level, it is possible to enable many clock sources at a given time (ex: the internal rc oscillator for system clock + an oscilla tor with external crystal). the user (code) is responsible of this management. 4.5.3.4 cout command the ? ckout ? command allows to drive the clko pin. refer to section 4.5.2.7 ?clock output buffer? on page 52 for using. 4.5.3.5 clock availability ?request for clock availability? command enables a hardware o scillation cycle counter driven by the selected source clock, csel3..0. the count limit value is determined by the settings of csut1..0. the clock is declared ready (clkrdy = 1) when the count limit value is reached. the clk rdy flag is reset when the count starts. once set, this flag remains unchanged until a new count is commanded. to perform this checking, the cksel and csut fields s hould not be changed while the operation is running. note that once the new cl ock source is selected (? enable clock source ? command), the count procedure is automatically started. the user (code) should wait for the setting of the clkrdy flag in clkscr register before using a newly selected clock. at any time, the user (code) can ask for the availability of a clock source. the user (code) can request it by writing the ?request for clock availability? command in the clkscr register. a full polling of the status of clock sources can thus be done. 4.5.3.6 system clock source recovering the ? recover system clock source ? command returns the current clock source used to driv e the system clock as per table 4-5 on page 47 . the cksel field of clkselr register is then updated wi th this returned value. there is no information on the sut used or status on ckout. 4.5.3.7 clock switching to drive the system clock, the user can sw itch from the current clock source to an y other of the following ones (one of them being the current clock source): 1. calibrated internal rc oscillator 8.0mhz, 2. internal watchdog oscillator 128khz, 3. external clock, 4. external low-frequency oscillator, 5. external crystal/ceramic resonator. the clock switching is performed by a sequence of commands. fi rst, the user (code) must ma ke sure that the new clock source is operating. then the ? clock source switching ? command can be issued. once this command has been successfully completed using the ? recover system clock source ? command, the user (code) may stop the previous clock source. it is strongly recommended to run this sequence only once the interru pts have been disabled. the user (code) is responsible for the correct implementation of the clock switching sequence.
55 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 here is a ?light? c-code that describes such a sequence of commands. warning: in the atmel ? attiny87/167, only one among the three external clock sources can be enabled at a given time. moreover, the enables of the external clock and of the ex ternal low-frequency oscillat or are shared with the asynchronous timer. c code example void clockswiching (unsigned char clk _ number, unsigned char sut) { #define clock _ recover 0x05 #define clock _ enable 0x02 #define clock _ switch 0x04 #define clock _ disable 0x01 unsigned char previous _ clk, temp; // disable interrupts temp = sreg; asm (?cli?); // save the current system clock source clkcsr = 1 << clkcce; clkcsr = clock _ recover; previous _ clk = clkselr & 0x0f; // enable the new clock source clkselr = ((sut << 4) & 0x30) | (clk _ number & 0x0f); clkcsr = 1 << clkcce; clkcsr = clock _ enable; // wait for clock validity while ((clkcsr & (1 << clkrdy)) == 0); // switch clock source clkcsr = 1 << clkcce; clkcsr = clock _ switch; // wait for effective switching while (1) { clkcsr = 1 << clkcce; clkcsr = clock _ recover; if ((clkselr & 0x0f) == (clk _ number & 0x0f)) break; } // shut down unneeded clock source if (previous_clk != (clk_number & 0x0f)) { clkselr = previous _ clk; clkcsr = 1 << clkcce; clkcsr = clock _ disable; } // re-enable interrupts sreg = temp; }
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 56 4.5.3.8 clock monitoring a safe system needs to monito r its clock sources. two do mains need to be monitored: clock sources for peripherals, clocks sources for system clock generation. in the first domain, the user (code) can easil y check the validity of the clock(s) (see section 4.5.3.4 ?cout command? on page 54 ). in the second domain, the lack of a clock results in t he code not running. thus, the presence of the system clock needs to be monitored by hardware. using the on-chip watchdog allows this monitoring. normally, th e watchdog reloading is performed only if the code reaches some specific software labels, reaching t hese labels proves that the system clock is running. otherwise the watchdog reset is enabled. this behavior can be considered as a clock monitoring. if the standard watchdog functiona lity is not desired, the atmel ? attiny87/167 watchdog permits the system clock to be monitored without having to resort to the complexity of a full software watchdog han dler. the solution proposed in the atmel attiny87/167 is to automate the watchdog reloading wit h only one command, at the beginning of the session. so, to monitor the system clock, the user will have two options: 1. using the standard watchdog features (software reload), 2. or using the automatic reloading (hardware reload). the two options are exclusive. warning: these two options make sense only if the clock source at reset is an internal source. the fuse settings determine this operation. figure 4-15. watchdog timer with automatic reloading the ? enable watchdog in automatic reload mode ? command has priority over the stand ard watchdog enabling. in this mode, only the reset function of the watchdog is enabled (no more wa tchdog interrupt). the wdp3..0 bits of the wdtcsr register always determine the watchdog timer prescaling. as the watchdog will not be active before executing the ? enable watchdog in automatic reload mode ? command, it is recommended to activate this command before switching to an external clock source (see following notes). notes: 1. only the reset (watchdog reset included) disables this function. the watchdog system reset flag (wdrf bit of mcusr register) can be used to monitor the reset cause. 2. only clock frequencies (4 watchdog clock frequency) can be monitored. internal bus register: wdtcsr watchdog checker reload watchdog clock automatic reolading mode system clk enable 01 wd interrupt wd reset wdp [3..0] wde wdif wdie
57 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 here is a ?light? c-code of a clock switch ing function using automatic clock monitoring. c code example void clockswiching (unsigned char clk _ number, unsigned char sut) { #define clock _ recover 0x05 #define clock _ enable 0x02 #define clock _ switch 0x04 #define clock _ disable 0x01 #define wd _ arl _ enable 0x06 #define wd _ 2048cycles 0x07 unsigned char previous _ clk, temp; // disable interrupts temp = sreg; asm (?cli?); // save the current system clock source clkcsr = 1 << clkcce; clkcsr = clock _ recover; previous _ clk = clkselr & 0x0f; // enable the new clock source clkselr = ((sut << 4) & 0x30) | (clk _ number & 0x0f); clkcsr = 1 << clkcce; clkcsr = clock _ enable; // wait for clock validity while ((clkcsr & (1 << clkrdy)) == 0); // switch clock source clkcsr = 1 << clkcce; clkcsr = clock _ switch; // wait for effective switching while (1) { clkcsr = 1 << clkcce; clkcsr = clock _ recover; if ((clkselr & 0x0f) == (clk _ number & 0x0f)) break; } // shut down unneeded clock source if (previous_clk != (clk_number & 0x0f)) { clkselr = previous _ clk; clkcsr = 1 << clkcce; clkcsr = clock _ disable; } // re-enable interrupts sreg = temp; } // enable the watchdog in automatic reload mode wdtcsr = (1 << wdce) | (1 << wde); wdtcsr = (1 << wde) | wd _ 2048cycles; clkcsr = 1 << clkcce; clkcsr = wd _ arl _ enable;
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 58 4.5.4 system clock prescaler 4.5.4.1 features the atmel ? attiny87/167 system clock can be divided by setting the clock prescaler register ? clkpr. this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 4-14 on page 60 . 4.5.4.2 switching time when switching between prescaler settings, the system clock pr escaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency correspondi ng to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the fr equency of the undivided clock, which may be faster than the cpu?s clock frequency. hence, it is not possible to determine the state of the prescaler ? ev en if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values are writte n, it takes between t1 + t2 and t1 + 2 t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clo ck period, and t2 is the period corresponding to the new prescaler setting. 4.5.5 register description 4.5.5.1 osccal ? oscillator calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillat or to remove process variations from the oscillator frequency. the factory- calibrated value is automatically written to this register during chip reset, giving an oscil lator frequency of 8.0mhz at 25c. the applic ation software can write this register to change the oscillator frequency. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1mhz within 2 % accuracy. calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and fl ash write accesses, and these write times will be affected accordingly. if the eeprom or flash are written, do not calibrate to more than 8.8mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of operat ion for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. incrementing cal6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1mhz. bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value
59 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.5.5.2 clkpr ? clock prescaler register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable cha nge of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when the clkps bits are written. rewriting the cl kpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 6:4 ? res: reserved bits these bits are reserved bits in the atmel ? attiny87/167 and will always read as zero. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected cl ock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the applic ation requirements. as the divide r divides the master clock inpu t to the mcu, the speed of all synchronous peripherals is reduc ed when a division factor is used. the division factors are given in table 4-14 . to avoid unintentional c hanges of clock frequency, a spec ial write procedure must be fo llowed to chan ge the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write th e desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescale r setting in order not to disturb the procedure. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the cl kps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?001 1?, giving a division factor of eight at start up. this feature should be used if the selected clock source has a higher fr equency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits r egardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 60 4.5.5.3 clkcsr ? clock control and status register ? bit 7 ? clkcce: clock control change enable the clkcce bit must be written to logic one to enable change of the clkcsr bits. the clkcce bit is only updated when the other bits in clkcsr are simultaneously written to zero. clkcce is cleared by hard ware four cycles after it is written or when the clkcsr bits are written. rewriting the clkcce bit wi thin this time-out period does neither extend the time-out period, nor clear the clkcce bit. ? bits 6:5 ? res: reserved bits these bits are reserved bits in the atmel ? attiny87/167 and will always read as zero. ? bits 4 ? clkrdy: clock ready flag this flag is the output of the ? clock availability ? logic. this flag is cleared by the ? request for clock availability ? command or ? enable clock source ? command being entered. it is set when ? clock availability ? logic confirms that the (selected) clock is r unning and is stable. the delay from the request and the flag setting is not fixed, it depends on the clock start-up time, the clock frequency and, of course, if the clock is a live. the user?s code has to differentiate between ? no_clock_signal ? and ? clock_signal_not_yet_available ? condition. ? bits 3:0 ? clkc3:0: clock control bits 3 - 0 these bits define the command to provide to the ? clock switch? module. the special write procedure must be followed to change the clkc3..0 bits ( see ?bit 7 ? clkcce: clock control change enable? on page 60. ). 1. write the clock control change enable (clkcce) bit to one and all other bits in clkcsr to zero. 2. within 4 cycles, write the des ired value to clkcsr regist er while clearing clkcce bit. interrupts should be disabled when setting clkcsr register in order not to disturb the procedure. table 4-14. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved bit 7 65 4 3210 clkcce ? ? clkrdy clkc3 clkc2 clkc1 clkc0 clkcsr read/write r/w r r r r/w r/w r/w r/w initial value0 00 0 0000
61 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.5.5.4 clkselr - clock selection register ? bit 7? res: reserved bit this bit is reserved bit in the atmel ? attiny87/167 and will always read as zero. ? bit 6 ? cout: clock out the cout bit is initialized with ~(ckout) fuse bit. the cout bit is only used in case of ? ckout ? command. refer to section 4.5.2.7 ?clock output buffer? on page 52 for using. in case of ? recover system clock source ? command, cout it is not affect ed (no recovering of this setting). ? bits 5:4 ? csut1:0: clock start-up time csut bits are initialized with the values of sut fuse bits. in case of ? enable/disable clock source ? command, csut field provides the code of the clock start-up time. refer to subdivisions of section 4.5.2 ?clock sources? on page 47 for code of clock start-up times. in case of ? recover system clock source ? command, csut field is not affected (no recovering of sut code). ? bits 3:0 ? csel3:0: clock source select csel bits are initialized with t he values of cksel fuse bits. in case of ? enable/disable clock source ?, ? request for clock availability ? or ? clock source switch ? command, csel field provides the code of the clock source. refer to table 4-5 on page 47 and subdivisions of section 4.5.2 ?clock sources? on page 47 for clock source codes. in case of ? recover system clock source ? command, csel field contains the code of the clock source used to drive the clock control unit as described in figure 4-10 on page 46 . table 4-15. clock command list clock command clkc3..0 no command 0000 b disable clock source 0001 b enable clock source 0010 b request for clock availability 0011 b clock source switch 0100 b recover system clock source code 0101 b enable watchdog in automatic reload mode 0110 b ckout command 0111 b no command 1 xxx b bit 7 6 543210 - cout csut1 csut0 csel3 csel2 csel1 csel0 clkselr read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 ~ (ckout) fuse sut1..0 fuses cksel3..0 fuses
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 62 4.6 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr ? provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. when enabled, the brown-out detector (bod) actively monitors the power supply voltage during the sleep periods. to further save power, it is possible to disable the bod in some sleep modes. see section 4.6.2 ?bod disable? on page 62 for more details. 4.6.1 sleep modes figure 4-10 on page 46 presents the different clock systems in the atmel ? attiny87/167, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 4-16 shows the different sleep modes, their wake up sources and bod disable ability. to enter any of the four sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm1, and sm0 bits in th e smcr register select which sleep mode (idle, adc noise reduction, power-down, or power-save) will be activated by the sleep instruction. see table 4-17 on page 65 for a summary. if an enabled interru pt occurs while the mcu is in a sleep mode, the mcu wakes up. the mc u is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execut ion from the instruction following sleep. the contents of the register file and sr am are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 4.6.2 bod disable when the brown-out detector (bod ) is enabled by bodlevel fuses, table 4-69 on page 223 , the bod is actively monitoring the power supply voltage during a sleep period. to save power, it is possible to disable the bod by software for some of the sleep modes, see table 4-16 . the sleep mode power consumption will then be at the same level as when bod is globally disabled by fuses. if bod is disabled in softwar e, the bod function is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is automatically en abled again. this ensures safe operation in case the vcc level has dropped during the sleep period. when the bod has been disabled, the wake-up time from sleep mode will be approximately 60s to ensure that the bod is working correctly before the mcu continues executing code. bod disable is controlled by bods bit (bod sleep) in the contro l register mcucr, see section 4.6.9.2 ?mcucr ? mcu control register? on page 65 . setting it to one turns off the bod in relevant sleep modes, while a zero in this bit keeps bod active. default setting keeps bod active, i.e. bods is cleared to zero. writing to the bods bit is controlled by a timed sequence and an enable bit, see section 4.6.9.2 ?mcucr ? mcu control register? on page 65 . table 4-16. active clock domains and wake-up sources in the different sleep modes sleep mode active clock domains oscillators wake-up sources software bod disable clk cpu clk flash clk io clk adc clk asy main clock source enabled timer0 osc. enable int1, int0 and pin change spm/eeprom ready adc wdt usi start condition timer0 other i/o idle x x x x x x x x x x x x adc noise reduction x x x x x (1) x x x x x power-down x (1) x x x power-save x x x (1) x x x x notes: 1. for int1 and int0, only level interrupt
63 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.6.3 idle mode when the sm1..0 bits are written to 00, the sleep instruction ma kes the mcu enter idle m ode, stopping the cpu but allowing the spi, analog comparator, adc, usi start condition, asynchronous time r/counter, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the spi interrupts. if wake-up from the analog comparator interrup t is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will re duce power consumption in idle mode. if the adc is enabled, a conversion starts au tomatically when this mode is entered. 4.6.4 adc noise reduction mode when the sm1..0 bits are written to 01, the sleep instru ction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, the usi start condition, the asynchronous timer/counter and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when th is mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watch dog system reset, a watch dog interrupt, a brown-out reset, a usi start condition interrupt, an asynchronous timer/counter inte rrupt, an spm/eeprom ready interr upt, an external level interr upt on int0 or int1 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 4.6.5 power-down mode when the sm1..0 bits are written to 10, the sleep instruct ion makes the mcu ent er power-down mode. in this mode, the external oscillator is stopped, while the external interrupts, the usi start condition, and t he watchdog continue operating (if enabled). only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out rese t, the usi st art condition interrupt, an external level interrupt on int0 or int1, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowin g operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to section 4.9 ?external interrupts? on page 79 for details. when waking up from power-down mode, there is a delay fr om the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that def ine the reset time-out period, as described in section 4.5.2 ?clock sources? on page 47 . 4.6.6 power-save mode when the sm1..0 bits are written to 11, the sleep instruction ma kes the mcu enter power-sav e mode. this mode is identical to power-down, with one exception: if timer/counter0 is clocked asynchronou sly, i.e., the as0 bit in assr is set, ti mer/counter0 will run during sleep. the device can wake up from either timer overflow or output compare event from timer/ counter0 if the corresponding timer/counter0 interrupt enable bits are set in timsk0, and the global interrupt enable bit in sreg is set. if the asynchronous timer is not clocked asynchronously, power-down mode is recommended instead of power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in power- save mode if as0 is 0. this sleep mode ba sically halts all clocks except clk asy , allowing operation only of asynchronous modules, including timer/counter0 if clocked asynchronously. 4.6.7 power reduction register the power reduction register (prr), see section 4.6.9.3 ?prr ? power reduction register? on page 66 , provides a method to stop the clock to individual peripherals to reduce power co nsumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled befor e stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and active mode to significantly reduce the overal l power consumption. in all other sleep modes, the clock is already stopped.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 64 4.6.8 minimizing power consumption there are several possibilities to consider when tr ying to minimize the power consumption in an avr ? controlled system. in general, sleep modes should be used as much as possible, a nd the sleep mode should be selected so that as few as possible of the device?s functions are op erating. all functions not needed should be disabled. in particular, the following modules may need special considerat ion when trying to achieve the lowest possible power consumption. 4.6.8.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to section 4.18 ?adc ? analog to digital converter? on page 191 for details on adc operation. 4.6.8.2 analog comparator when entering idle mode, the analog com parator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comp arator is automatically disabled. however, if the analog comparator is set up to us e the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage refer ence will be enabled, independent of sleep mode. refer to section 4.19 ?anacomp - analog comparator? on page 209 for details on how to conf igure the analog comparator. 4.6.8.3 brown-out detector if the brown-out detector is not needed by the application, this module should be tur ned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to section 4.7.1.5 ?brown-out detection? on page 69 for details on how to configure the brown-out detector. 4.6.8.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the ana log comparator or the adc. if these modules are disabled as described in the sections above, the internal volt age reference will be disabled and it will not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to section 4.7.2 ?internal voltage reference? on page 70 for details on the start-up time. output the internal voltage reference is not needed in the deeper sleep modes. this module should be turned off to reduce significantly to the total cu rrent consumption. refer to section 4.17.3.1 ?amiscr ? analog miscellaneous control register? on page 190 for details on how to disable the internal voltage reference output. 4.6.8.5 internal current source the internal current source is not needed in the deeper sleep modes. this module should be turned off to reduce significantly to the total cu rrent consumption. refer to section 4.17.3.1 ?amiscr ? analog miscellaneous control register? on page 190 for details on how to disable the internal current source. 4.6.8.6 watchdog timer if the watchdog timer is not needed in the ap plication, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. in the deeper sleep modes, this will contribute significantly to the total cu rrent consumption. refer to section 4.7.3 ?watchdog timer? on page 71 for details on how to configure the watchdog timer. 4.6.8.7 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabl ed. this ensures that no power is consum ed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-u p conditions, and it will then be enabled. refer to the section section 4.10.2.6 ?digital input enable and sleep modes? on page 88 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to vcc/2, the input buffer will use exces sive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to vcc/2 on an in put pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to section 4.18.12.6 ?didr1 ? digital i nput disable register 1? on page 207 and section 4.18.12.5 ?didr0 ? digital input disable register 0? on page 207 for details.
65 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.6.8.8 on-chip debug system if the on-chip debug system is enabled by the dwen fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. in the deeper sleep modes, this will contribute signif icantly to the total current consumption. 4.6.9 register description 4.6.9.1 smcr ? sleep mode control register the sleep mode control register contai ns control bits for power management. ? bits 7..3 res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bits 2..1 ? sm1..0: sleep mode select bits 1, and 0 these bits select between the four available sleep modes as shown in table 4-17 . ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the progra mmer?s purpose, it is recomm ended to write the sleep enable (se) bit to one just before the executio n of the sleep instruction and to cl ear it immediatel y after waking up. 4.6.9.2 mcucr ? mcu control register ? bit 6 ? bods: bod sleep the bods bit must be written to logic one in order to turn off bod during sleep, see table 4-16 on page 62 . writing to the bods bit is controlled by a timed sequence and an enable bit, bodse in mcucr. to disable bod in relevant sleep modes, both bods and bodse must first be set to one. then, to set the bods bit, bods must be set to one and bodse must be set to zero within four clock cycles. the bods bit is active three clock cycles after it is set. a sleep instruction must be executed wh ile bods is active in order t o turn off the bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? bodse: bod sleep enable bodse enables setting of bods control bit, as explained in bods bit description. bod disable is controlled by a timed sequence. bit 76543210 ?????sm1sm0sesmcr read/write rrrrrr/wr/wr/w initial value00000000 table 4-17. sleep mode select sm1 sm0 sleep mode 0 0 idle 0 1 adc noise reduction 1 0 power-down 1 1 power-save bit 7 6 5 4 3 2 1 0 ? bods bodse pud ? ? ? ? mcucr read/write r r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 66 4.6.9.3 prr ? power reduction register ? bit 7 - res: reserved bit this bit is reserved in atmel ? attiny87/167 and will always read as zero. ? bit 6 - res: reserved bit this bit is reserved in atmel attiny87/167 and will always read as zero. ? bit5 - prlin: power reduct ion lin / uart controller writing a logic one to this bit shuts down the lin by stopping t he clock to the module. when waking up the lin again, the lin should be re initialized to ensure proper operation. ? bit 4 - prspi: power reduction serial peripheral interface if using debugwire on-chip debug system, this bit should not be written to one. writing a logic one to this bit shuts down the serial peripheral interface by stopping the clock to the module. when waking up the spi again, the spi should be re in itialized to ensure proper operation. ? bit 3 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts do wn the timer/counter1 module . when the timer/counter1 is enabled, operation will continue like before the shutdown. ? bit 2 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/co unter0 module in synchronous mode (as0 is 0). when the timer/counter0 is enabled, operation will continue like before the shutdown. ? bit 1 - prusi: power reduction usi writing a logic one to this bit shuts down the usi by stoppi ng the clock to the module. when waking up the usi again, the usi should be re-initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts down the adc. the a dc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. 4.7 system control and reset 4.7.1 reset 4.7.1.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be an rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vect ors are not used, and regular pr ogram code can be placed at these locations. the circuit diagram in figure 4-16 shows the reset circuit. tables in section 4.23.3 ?reset characteristics? on page 239 defines the electrical parameters of the reset circuitry. the i/o ports of the avr ? are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invo ked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time- out period of the delay counter is defined by the user through the sut and cksel fuses. the different se lections for t he delay period are presented in section 4.5.2 ?clock sources? on page 47 . bit 76543210 ? ? prlin prspi prtim1 prtim0 prusi pradc prr read/write r r r/w r/w r/w r/w r/w r/w initial value00000000
67 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.7.1.2 reset sources the atmel ? attiny87/167 has four sources of reset: power-on reset: the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). external reset: the mcu is reset wh en a low level is present on the reset pin for longer than the minimum pulse length. watchdog system reset: the mcu is reset when the watc hdog timer period expires and the watchdog system reset mode is enabled. brown-out reset: the mcu is reset when the supply vo ltage vcc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. figure 4-16. reset circuit power-on reset circuit brown-out reset circuit mcu status register (mcusr) reset circuit pull-up resistor bodlevel [2..0] s q r data bus ck sut [1..0] cksel [3..0] rstdisbl counter reset internal reset timeout spike filter reset vcc delay counters watchdog timer watchdog oscillator clock generator porf borf wdrf extrf
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 68 4.7.1.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 4-84 on page 240 . the por is activated whenever vcc is below the detection level. the por circuit can be used to trigger the start- up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the del ay counter, which de termines how long the device is kept in reset after vcc rise. the reset signal is activated again, without any delay, when vcc decreases below the detection level. figure 4-17. mcu start-up, reset tied to vcc figure 4-18. mcu start-up, reset extended externally 4.7.1.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 4-83 on page 239 ) will generate a reset, even if the clock is not ru nning. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. the external reset can be disabled by the rstdisbl fuse, see table 4-70 on page 223 . figure 4-19. external reset during operation v cc internal reset time-out t tout v pormax v pormin v pot v ccrr v cc internal reset reset time-out v por v rst t tout v ccrr t tout reset v cc internal reset time-out v rst
69 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.7.1.5 brown-out detection atmel ? attiny87/167 has an on-chip brown-out detection (bod) circ uit for monitoring the vcc level during operation by comparing it to a fixed trigger level. the trigger leve l for the bod can be selected by the bodlevel fuses ( table 4-85 on page 240 ). the trigger level has a hysteresis to ensure spike free brown-out detection. the hyster esis on the detection level should be interpreted as v bot + =v bot +v hyst / 2 and v bot ? =v bot ?v hyst /2. when the bod is enabled, and vcc decreases to a value below the trigger level (v bot ? in figure 4-20 ), the brown-out reset is immediately activated. when vcc increases above the trigger level (v bot + in figure 4-20 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in vcc if the voltage stays below the trigger level for longer than t bod given in table 4-86 on page 240 . figure 4-20. brown-out reset during operation 4.7.1.6 watchdog system reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to section 4.7.3 ?watchdog timer? on page 71 for details on operation of the watchdog timer. figure 4-21. watchdog system reset during operation v bot- v bot+ t tout v cc reset internal reset time-out 1 ck cycle v cc reset internal reset reset time-out wd time-out t tout
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 70 4.7.1.7 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 7..4 ? res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bit 3 ? wdrf: watchdog system reset flag this bit is set if a watchdog system reset occurs. the bit is re set by a power-on reset, or by writing a logic zero to the flag . ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occu rs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 4.7.2 internal voltage reference atmel attiny87/167 features an internal bandgap reference. th is reference is used for brow n-out detection, and it can be used as an input to the anal og comparator or the adc. 4.7.2.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence th e way it should be used. the start-up time is given in table 4-87 on page 240 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the bodlevel [2:0] fuses). 2. when the bandgap reference is connected to the analog comparator (by setting the acirs bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, af ter setting the acirs bit or enabling the adc, the user must always allow the reference to start up before the output fr om the analog comparator or adc is used. to reduce power consumption in power- down mode or in power-save, the user can avoid the three condit ions above to ensure that the reference is turned off before entering in these power reduction modes. bit 76543210 ????wdrfborfextrfporfmcusr read/write rrrrr/wr/wr/wr/w initial value0000 see bit description
71 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.7.3 watchdog timer atmel ? attiny87/167 has an enhanced watchdog timer (wdt). the main features are: clocked from separate on-chip oscillator 4 operating modes interrupt system reset interrupt and system reset clock monitoring selectable time-out period from 16ms to 8s possible hardware fuse watchdog always on (wdton) for fail-safe mode 4.7.3.1 watchdog timer behavior the watchdog timer (wdt) is a timer counting cycl es of a separate on-chip 128khz oscillator. figure 4-22. watchdog timer the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the counter, an interru pt or system reset will be issued. in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one exampl e is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang- up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an interrupt and th en switch to syste m reset mode. this mode will for instance allow a safe shutdown by savi ng critical parameters before a system reset. the watchdog always on (w dton) fuse, if programmed, will force the watch dog timer to system rese t mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locke d to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the wa tchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of t he previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. osc/64k osc/16k osc/2k osc/4k osc/8k osc/32k osc/128k osc/256k osc/512k osc/1024k watchdog prescaler wdp0 wde watchdog reset clock monitoring wdif wdie wdp1 wdp2 wdp3 mcu reset interrupt ~ 128khz oscillator
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 72 the following code example shows one assembly and one c function for turning off the watchdog timer. the example assumes that interrupts are controlled (e.g. by disabling in terrupts globally) so that no interrupts will occur during the execution of these functions. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 73 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the following code example shows one assembly and one c function for changing the time -out value of the watchdog timer. 4.7.3.2 clock monitoring the watchdog timer can be used to detect a loss of syst em clock. this confi guration is driven by t he dynamic clock switch circuit. please refer to section 4.5.3.8 ?clock monitoring? on page 56 for more information. assembly code example (1) wdt_prescaler_change: ; turn off global interrupt cli ; reset watchdog timer wdr ; start timed sequence lds r16, wdtcr ori r16, (1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 74 4.7.3.3 watchdog timer control register - wdtcr ? bit 7 - wdif: watc hdog interrupt flag this bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. wdif is cleared by hardware when executing the corre sponding interrupt handling vector. alternat ively, wdif is cleared by writing a logic one to the flag. when the i-bit in sreg and wdie are set, the watchdog time-o ut interrupt is executed. ? bit 6 - wdie: watchdog interrupt enable when this bit is written to one and the i-bit in the status r egister is set, the watchdog interrupt is enabled. if wde is clear ed in combination with this setting, the watchdog timer is in in terrupt mode, and the corresponding interrupt is executed if time- out in the watchdog timer occurs. if wde is set, the watchdog timer is in interrupt and system reset mode. the first time-out in the watchdog timer will set wdif. executing the corresponding interrupt vector will clea r wdie and wdif automatically by hardware (the watchdog goes to system reset mode). this is useful for keeping the wa tchdog timer security while us ing the interrupt. to stay in interrupt and system reset mode, wdie must be set after ea ch interrupt. this should however not be done within the interrupt service routine itself , as this might compromise th e safety-function of the watch dog system reset mode. if the interrupt is not executed before the next time-out, a system reset will be applied. if the watchdog timer is used as clock monitor (c.f. section ? ?bits 3:0 ? clkc3:0: clock control bits 3 - 0? on page 60 ), the system reset mode is enabled and the in terrupt mode is autom atically disabled. ? bit 4 - wdce: watchdog change enable this bit is used in timed sequences for changing wde and pre scaler bits. to clear the wde bit, and/or change the prescaler bits, wdce must be set. once written to one, hardware will cl ear wdce after four clock cycles. ? bit 3 - wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensu res multiple resets during conditions caus ing failure, and a safe start-up after the failure. ? bit 5, 2..0 - wdp3..0: watchdog timer prescaler 3, 2, 1 and 0 the wdp3..0 bits determine the watchdog timer prescaling wh en the watchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 4-19 on page 75 . bit 76543210 wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 wdtcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 x 0 0 0 table 4-18. watchdog timer configuration clock monitor wdton wde wdie mode action on time-out x 0 0 0 stopped none on y (1) y (1) y (1) system reset mode reset off 0 0 1 interrupt mode interrupt 0 1 0 system reset mode reset 0 1 1 interrupt and system reset mode interrupt, then go to system reset mode 1 x x system reset mode reset note: 1. at least one of these three enables (wdton, wde and wdie) equal to 1
75 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 table 4-19. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at vcc = 5.0v 0 0 0 0 2k (2048) cycles 16ms 0 0 0 1 4k (4096) cycles 32ms 0 0 1 0 8k (8192) cycles 64ms 0 0 1 1 16k (16384) cycles 0.125s 0 1 0 0 32k (32768) cycles 0.25s 0 1 0 1 64k (65536) cycles 0.5s 0 1 1 0 128k (131072) cycles 1.0s 0 1 1 1 256k (262144) cycles 2.0s 1 0 0 0 512k (524288) cycles 4.0s 1 0 0 1 1024k (1048576) cycles 8.0s 1 0 1 0 reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 76 4.8 interrupts this section describes the specifics of t he interrupt handling as performed in atmel ? attiny87/167. for a general explanation of the avr ? interrupt handling, refer to section 4.3.7 ?reset and inte rrupt handling? on page 36 . 4.8.1 innterrupt vectors in atmel attiny87/167 table 4-20. reset and interrupt vectors in atmel attiny87/167 vector nb. program address source interrupt definition attiny87 attiny167 1 0x0000 0x0000 reset external pin, power-on reset, brown-out reset and watchdog system reset 2 0x0001 0x0002 int0 external interrupt request 0 3 0x0002 0x0004 int1 external interrupt request 1 4 0x0003 0x0006 pcint0 pin change interrupt request 0 5 0x0004 0x0008 pcint1 pin change interrupt request 1 6 0x0005 0x000a wdt watchdog time-out interrupt 7 0x0006 0x000c timer1 capt timer/counter1 capture event 8 0x0007 0x000e timer1 compa timer/counter1 compare match a 9 0x0008 0x0010 timer1 compb timer/coutner1 compare match b 10 0x0009 0x0012 timer1 ovf timer/counter1 overflow 11 0x000a 0x0014 timer0 compa timer/counter0 compare match a 12 0x000b 0x0016 timer0 ovf timer/counter0 overflow 13 0x000c 0x0018 lin tc lin/uart transfer complete 14 0x000d 0x001a lin err lin/uart error 15 0x000e 0x001c spi, stc spi serial tran sfer complete 16 0x000f 0x001e adc adc conversion complete 17 0x0010 0x0020 ee ready eeprom ready 18 0x0011 0x0022 analog comp analog comparator 19 0x0012 0x0024 usi start usi start condition detection 20 0x0013 0x0026 usi ovf usi counter overflow
77 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.8.2 program setup in attiny87 the most typical and general program setup for the reset and in terrupt vector addresses in at tiny87 is (2-byte step - using ?rjmp? instruction): address (1) label code comments 0x0000 rjmp reset ; reset handler 0x0001 rjmp int0addr ; irq0 handler 0x0002 rjmp int1addr ; irq1 handler 0x0003 rjmp pcint0addr ; pcint0 handler 0x0004 rjmp pcint1addr ; pcint1 handler 0x0005 rjmp wdtaddr ; watchdog timer handler 0x0006 rjmp icp1addr ; timer1 capture handler 0x0007 rjmp oc1aaddr ; timer1 compare a handler 0x0008 rjmp oc1baddr ; timer1 compare b handler 0x0009 rjmp ovf1addr ; timer1 overflow handler 0x000a rjmp oc0aaddr ; timer0 compare a handler 0x000b rjmp ovf0addr ; timer0 overflow handler 0x000c rjmp lintcaddr ; lin transfer complete handler 0x000d rjmp linerraddr ; lin error handler 0x000e rjmp spiaddr ; spi transfer complete handler 0x000f rjmp adccaddr ; adc conversion complete handler 0x0010 rjmp erdyaddr ; eeprom ready handler 0x0011 rjmp aciaddr ; analog comparator handler 0x0012 rjmp usistartaddr ; usi start condition handler 0x0013 rjmp usiovfaddr ; usi overflow handler 0x0014 reset: ldi r16, high(ramend); main program start 0x0015 out sph,r16 ; set stack pointer to top of ram 0x0016 ldi r16, low(ramend) 0x0017 out spl,r16 0x0018 sei ; enable interrupts 0x0019 xxx ... ... ... ... note: 16-bit address
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 78 4.8.3 program setup in attiny167 the most typical and general program setup for the reset and interrupt vector addresses in attiny167 is (4-byte step - using ?jmp? instruction): address (1) label code comments 0x0000 jmp reset ; reset handler 0x0002 jmp int0addr ; irq0 handler 0x0004 jmp int1addr ; irq1 handler 0x0006 jmp pcint0addr ; pcint0 handler 0x0008 jmp pcint1addr ; pcint1 handler 0x000a jmp wdtaddr ; watchdog timer handler 0x000c jmp icp1addr ; timer1 capture handler 0x000e jmp oc1aaddr ; timer1 compare a handler 0x0010 jmp oc1baddr ; timer1 compare b handler 0x0012 jmp ovf1addr ; timer1 overflow handler 0x0014 jmp oc0aaddr ; timer0 compare a handler 0x0016 jmp ovf0addr ; timer0 overflow handler 0x0018 jmp lintcaddr ; lin transfer complete handler 0x001a jmp linerraddr ; lin error handler 0x001c jmp spiaddr ; spi transfer complete handler 0x001e jmp adccaddr ; adc conversion complete handler 0x0020 jmp erdyaddr ; eeprom ready handler 0x0022 jmp aciaddr ; analog comparator handler 0x0024 jmp usistartaddr ; usi start condition handler 0x0026 jmp usiovfaddr ; usi overflow handler 0x0028 reset: ldi r16, high(ramend); main program start 0x0029 out sph,r16 ; set stack pointer to top of ram 0x002a ldi r16, low(ramend) 0x002b out spl,r16 0x002c sei ; enable interrupts 0x002d xxx ... ... ... ... note: 1. 16-bit address
79 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.9 external interrupts 4.9.1 overview the external interrupts are triggered by the int1..0 pins or any of the pcint15..0 pins. observe that, if enabled, the interrupts will trigger even if the int1..0 or pcint15..0 pins are configured as outputs. th is feature provides a way of generating a software interrupt. the pin change interrupt pcint1 will trigger if any enabled pcint15..8 pin toggles. the pin change interrupt pcint0 will trigger if any enabled pcint7..0 pin toggles. the pcmsk1 and pcmsk0 registers control which pins contribute to the pin change interrupts. pin change interrupts on pcint15..0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the int1..0 interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specific ation for the external interrupt control regist er a ? eicra. when the int1..0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is he ld low. the recognition of fa lling or rising edge interrupts on int1..0 requires the presence of an i/o clock, described in section 4.5.1 ?clock systems and their distribution? on page 46 . low level interrupts and the edge interrupt on int1..0 are detect ed asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down or power-save, the required level must be held long enough for the mcu to complete the wake-up to trigger t he level interrupt. if the level disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. the start-up time is defined by the sut and cksel fuses as described in section 4.5.1 ?clock systems and their distribution? on page 46 . 4.9.2 pin change interrupt timing an example of timing of a pin change interrupt is shown in figure 4-23 . figure 4-23. timing of pin change interrupts clk pin_lat pin_sync pcint[i] pin pcint_in[i] pcint_sync pcint_set/flag pcif n pin_lat pin_sync pcint_sync clk 0 7 clk pcint_set/flag pcint [i] bit (of pcmsk n ) pcint[i] pin pcif n (interrupt flag) pcint_in[i] dq le dq dq dq dq
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 80 4.9.3 external interrupts register description 4.9.3.1 external interrupt control register a ? eicra the external interrupt control register a cont ains control bits for interrupt sense control. ? bit 7..4 ? res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corre sponding interrupt mask are set. the level and edges on the external int1 pin that activate the interrupt are defined in table 4-21 . the value on the int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last l onger than one clock period will generate an interrupt. shorter pulses are no t guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the current ly executing instruction to generate an interrupt. ? bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corre sponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 4-21 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last l onger than one clock period will generate an interrupt. shorter pulses are no t guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the current ly executing instruction to generate an interrupt. 4.9.3.2 external interrupt mask register ? eimsk ? bit 7, 2 ? res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bit 1 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), the ex ternal pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in t he external interrupt control r egister a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int1 pin or level sensed. activity on the pin will cau se an interrupt request even if int1 is configured as an output. th e corresponding interrupt of external interrupt request 1 is executed from the int1 interrupt vector. bit 76543210 ? ? ? ? isc11 isc10 isc01 isc00 eicra read/write r r r r r/w r/w r/w r/w initial value00000000 table 4-21. interrupt sense control iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request. 1 0 the falling edge of intn generates an interrupt request. 1 1 the rising edge of intn generates an interrupt request. bit 76543210 ??????int1int0eimsk read/write rrrrrrr/wr/w initial value00000000
81 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), the ex ternal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in t he external interrupt control r egister a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int0 pin or level sensed. activity on the pin will cau se an interrupt request even if int0 is configured as an output. th e corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. 4.9.3.3 external interrupt flag register ? eifr ? bit 7, 2 ? res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bit 1 ? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an inte rrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always c leared when int1 is configured as a level interrupt. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an inte rrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always c leared when int0 is configured as a level interrupt. 4.9.3.4 pin change interrupt control register ? pcicr ? bit 7, 2 ? res: reserved bits these bits are unused bits in the atmel attiny87/167, and will always read as zero. ? bit 1 - pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status r egister (sreg) is set (one), pi n change interrupt 1 is enabled. any change on any enabled pcint15..8 pin will cause an interr upt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint 15..8 pins are enabled individually by the pcmsk1 register. ? bit 0 - pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), pin change interrupt 0 is enabled. an y change on any enabled pcint7..0 pin will cause an interrupt. t he corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7..0 pi ns are enabled individually by the pcmsk0 register. bit 76543210 ??????intf1intf0eifr read/write rrrrrrr/wr/w initial value00000000 bit 76543210 ??????pcie1pcie0pcicr read/write rrrrrrr/wr/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 82 4.9.3.5 pin change interrupt flag register ? pcifr ? bit 7, 2 ? res: reserved bits these bits are unused bits in the atmel ? attiny87/167, and will always read as zero. ? bit 1 - pcif1: pin change interrupt flag 1 when a logic change on any pcint15..8 pin triggers an interrupt request, pcif1 becomes set (one ). if the i-bit in sreg and the pcie1 bit in pcicr are set (one), the mcu will jump to t he corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. ? bit 0 - pcif0: pin change interrupt flag 0 when a logic change on any pcint7..0 pin triggers an inte rrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are set (one), the mcu will jump to t he corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. 4.9.3.6 pin change mask register 1 ? pcmsk1 ? bit 7..0 ? pcint15..8: pin change enable mask 15..8 each pcint15..8-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint15..8 is set and the pcie1 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint15..8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 4.9.3.7 pin change mask register 0 ? pcmsk0 ? bit 7..0 ? pcint7..0: pi n change enable mask 7..0 each pcint7..0 bit selects whether pin change interrupt is enabl ed on the corresponding i/o pin. if pcint7..0 is set and the pcie0 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 ??????pcif1pcif0pcifr read/write rrrrrrr/wr/w initial value00000000 bit 76543210 pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
83 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10 i/o-ports 4.10.1 introduction all avr ? ports have true read-modify- write functionality when used as general digita l i/o ports. this means that the direction of one port pin can be changed without uni ntentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/ disabling of pull-up resistors (if configured as input). each output buffer has symmetrical dr ive characteristics with both high sink and source capability. the pin driver is strong enough to drive le d displays directly. all port pins have individually selectable pull-up resistors wi th a supply-voltage invariant resistance. all i/o pins have pr otection diodes to both vcc and ground as indicated in figure 4-24 . refer to section 4.23 ?electrical characteristics? on page 237 for a complete list of parameters. figure 4-24. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the numbering letter for the port, and a lower case ?n? represents the bit number. howeve r, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in section 4.10.4 ?register description for i/o ports? on page 101 . three i/o memory address locations are allocated for each po rt, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pi nx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. howeve r, writing a logic one to a bit in the pinx register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-up disable ? pud bit in mcucr or pudx in portcr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is described in section 4.10.2 ?ports as general digital i/o? on page 84 . most port pins are multiplexed with alternate functi ons for the peripheral features on the device. how each alternate function interferes with the port pin is described in section 4.10.3 ?alternate po rt functions? on page 89 . refer to the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin r pu pxn logic see figure general digital i/o for details
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 84 4.10.2 ports as general digital i/o the ports are bi-directional i/o port s with optional internal pull-ups. figure 4-25 shows a functional description of one i/o- port pin, here generically called pxn. figure 4-25. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. d 0 1 q wrx rrx wpx pxn clr reset synchronizer data bus portxn q q l d q q d q pinxn reset rpx wdx: write ddrx wrx: wpx: rpx: rrx: read portx register read portx pin write portx register rdx: write portx read ddrx pud: pullup disable clk i/o : sleep: i/o clock sleep control rdx clk i/o pud wdx sleep d q clr ddxn q
85 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10.2.1 configuring the pin each port pin consists of three register bi ts: ddxn, portxn, and pinxn. as shown in section 4.10.4 ?register description for i/o ports? on page 101 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects th e direction of this pin. if ddxn is writte n logic one, pxn is configured as an outp ut pin. if ddxn is written logic zero, px n is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pul l- up resistor off, portxn has to be written logic zero or th e pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 4.10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, in dependent on the value of ddrxn. note that the sbi assembler instruction can be used to toggle one single bit in a port. 4.10.2.3 break-before-make switching in the break-before-make mode when switching the ddrxn bit from input to output an immediat e tri-state period lasting one system clock cycle is introduced as indicated in figure 4-26 . for example, if the system cl ock is 4mhz and the ddrxn is written to make an output, the immediate tr i-state period of 250ns is introduced, before the value of portxn is seen on the port pin. to avoid glitches it is recommended that t he maximum ddrxn toggle frequency is two system clock cycles. the break-before-make is a port-wise mode and it is activated by the port-wise bbmx enable bits. for further information about the bbmx bits, see section 4.10.3.2 ?port control register ? portcr? on page 91 . when switching the ddrxn bit from output to input there is no immedi ate tri-state period introduced. figure 4-26. break before make, sw itching between input and output system clock r16 r17 portx instructios 0x02 0x02 0x01 0x01 tri-state tri-state tri-state 0x01 0x55 nop out ddrx, r16 out ddrx, r17 immediate tri-state cycle immediate tri-state cycle ddrx px0 px1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 86 4.10.2.4 switching between input and output when switching between tri-state ({ddxn, portxn} = 0, 0) a nd output high ({ddxn, portxn} = 1, 1), an intermediate state with either pull-up enabled {ddxn, portxn} = 0, 1) or output low ({ddxn, portxn} = 1, 0) must occur. normally, the pull-up enabled state is fully acceptable, as a hi gh-impedant environment will not notice the difference between a strong high driver and a pull-up. if this is not the case, th e pud bit in the mcucr register or the p udx bit in portcr register can be set to disable all pull-ups in the port. switching between input with pull-up and out put low generates the same problem. th e user must use ei ther the tri-state ({ddxn, portxn} = 0, 0) or the output high state ({ddxn, portxn} = 1, 1) as an intermediate step. table 4-22 summarizes the control signals for the pin value. 4.10.2.5 reading the pin value independent of the setting of data direct ion bit ddxn, the port pin can be read thro ugh the pinxn register bit. as shown in figure 4-25 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 4-27 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 4-27. synchronization when reading an externally applied pin value consider the clock period starting shortl y after the first fallin g edge of the system cl ock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicate d by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn regist er at the succeeding positive clock edge. as indicated by the two arrows tpd,max and tpd,min, a sing le signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 4-28 on page 87 . the out instruction sets the ?sync latch? signal at the positi ve edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. table 4-22. port pin configurations ddxn portxn pud (in mcucr) (1) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) note: 1. or port-wise pudx bit in portcr register. system clk instructios sync latch pinxn r17 xxx xxx 0x00 0xff in r17, pinx t pd, max t pd, min
87 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-28. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read ba ck the value recently assigned to some of the pins. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 88 4.10.2.6 digital input en able and sleep modes as shown in figure 4-25 , the digital input signal can be clamped to grou nd at the input of the sc hmitt trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down or power-save mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to vcc/2. sleep is overridden for port pins enabled as external interrupt pins. if the external interrupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in section 4.10.3 ?alternate port functions? on page 89 . if a logic high level (?one?) is present on an asynchronous extern al interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pi n? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sle ep mode, as the clamping in these sleep mode produces the requested logic change. 4.10.2.7unconnected pins if some pins are unused, it is recommend ed to ensure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described ab ove, floating inputs should be avoided to reduce current consumption in all other modes where the digital in puts are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the inte rnal pull-up. in this case, the pull-up wi ll be disabled during reset. if low power consumption during reset is important, it is re commended to use an external pull-up or pull-down. connecting unused pins directly to vcc or gnd is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
89 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 4-29 shows how the port pin control signals from the simplified figure 4-25 can be overridden by alternate functions. the overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the avr ? microcontroller family. figure 4-29. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. d 0 1 q wrx rrx wpx ptoexn pxn clr reset synchronizer data bus portxn q 0 1 q l d set clr clr q q d q pinxn 0 1 reset rpx pxn pull-up override enable pxn pull-up override value pud: pull-up disable puoexn: pxn port value override value pvovxn: pxn port value override enable pvoexn: pxn data direction override enable pxn data direction override value ddoexn: ddovxn: sleep control sleep: pxn, port toggle override enable ptoexn: pxn digital input enable override value dieovxn: pxn digital input enable override enable dieoexn: i/o clock rdx: rpx: write pinx wrx: analog input/output pin n on portx digital input pin n on portx rrx: read portx register wpx: write portx aioxn: dixn: read portx pin wdx: read ddrx write ddrx puovxn: rdx clk i/o dixn aioxn clk: i/o dieovxn dieoexn pvoexn ddoexn pvovxn 0 1 puoexn puovxn 0 1 ddovxn sleep pud wdx d q clr ddxn q
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 90 table 4-23 summarizes the function of the overridi ng signals. the pin and port indexes from figure 4-29 are not shown in the succeeding tables. the overriding signals are generated inte rnally in the modules having the alternate function. the following subsections shortly describe the alternate functi ons for each port, and relate the overriding signals to the alternate function. refer to the alternat e function description for further details. 4.10.3.1 mcu control register ? mcucr ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o po rts are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0, 1). see section 4.10.2.1 ?configur ing the pin? on page 85 for more details about this feature. table 4-23. generic description of overri ding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, (pud or pdux)} = 0, 1, 0. puov pull-up override value if puoe is set, the pull-up is enabled /disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, pud and pudx register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driv er is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. bit 7 6 5 4 3 2 1 0 ? bods bodse pud ? ? ? ? mcucr read/write r r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0
91 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10.3.2 port control register ? portcr ? bits 5, 4 ? bbmx: break-before-make mode enable when these bits are written to one, the port-wise break-before-make mode is activa ted. the intermediate tri-state cycle is then inserted when writing ddrxn to make an output. for further information, see section 4.10.2.3 ?break-before-make switching? on page 85 . ? bits 1, 0 ? pudx: port-wise pull-up disable when these bits are written to one, the port-wise pull-ups in the defined i/o ports are disabl ed even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0, 1). the port-wise pull-up disable bits are ored with the global pull-up disable bit (p ud) from the mcucr register. see section 4.10.2.1 ?configuring the pin? on page 85 for more details about this feature. bit 7 6 5 4 3 2 1 0 - - bbmb bbma - - pudb puda portcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 92 4.10.3.3 alternate functions of port a the port a pins with alternate functions are shown in table 4-24 . table 4-24. port a pins alternate functions port pin alternate function pa7 pcint7 (pin change interrupt 7) adc7 (adc input channel 7) ain1 (analog comparator positive input) xref (internal voltage reference output) aref (external voltage reference input) pa6 pcint6 (pin change interrupt 6) adc6 (adc input channel 6) ain0 (analog comparator negative input) ss (spi slave select input) pa5 pcint5 (pin change interrupt 5) adc5 (adc input channel 5) t1 (timer/counter1 clock input) usck (three-wire mode usi alternate clock input) scl (two-wire mode usi alternate clock input) sck (spi master clock) pa4 pcint4 (pin change interrupt 4) adc4 (adc input channel 4) icp1 (timer/counter1 input capture trigger) di (three-wire mode usi alternate data input) sda (two-wire mode usi alternate data input/output) mosi (spi master output/slave input) pa3 pcint3 (pin change interrupt 3) adc3 (adc input channel 3) isrc (current source pin) int1 (external interrupt1 input) pa2 pcint2 (pin change interrupt 2) adc2 (adc input channel 2) oc0a (output compare and pwm output a for timer/counter0) do (three-wire mode usi alternate data output) miso (spi master input/slave output) pa1 pcint1 (pin change interrupt 1) adc1 (adc input channel 1) txd (uart transmit pin) txlin (lin transmit pin) pa0 pcint0 (pin change interrupt 0) adc0 (adc input channel 0) rxd (uart receive pin) rxlin (lin receive pin)
93 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the alternate pin configuration is as follows: ? pcint7/adc7/ain1/xref/aref ? port a, bit7 pcint7: pin change interrupt, source 7. adc7: analog to digital converter, channel 7. ain1: analog comparator positive input. this pin is directly connected to the positive input of the analog comparator. xref: internal voltage reference output. the internal voltage re ference 2.56v or 1.1v is out put when xrefen is set and if either 2.56v or 1.1v is used as refer ence for adc conversion. when xref output is enabled, the pin port pull-up and digital output driver are turned off. aref: external voltage reference input for adc. the pin port pull-up and digital output driver are disabled when the pin is used as an external voltage reference input for adc or as when the pin is only used to connect a bypass capacitor for the voltage reference of the adc. ? pcint6/adc6/ain0/ss ? port a, bit6 pcint6: pin change interrupt, source 6. adc6: analog to digital converter, channel 6. ain0: analog comparator negative input. this pin is directly connected to the negative input of the analog comparator. ss : spi slave select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of dda6. as a slave, the spi is activated when this pin is driven low. when th e spi is enabled as a master, the data direction of this pin is controlled by dda6. when the pin is forced to be an input, the pull-up can still be controlled by the porta6 bit. ? pcint5/adc5/t1/usck/scl/sck ? port a, bit5 pcint5: pin change interrupt, source 5. adc5: analog to digital converter, channel 5. t1: timer/counter1 clock input. usck: three-wire mode usi clock input. scl: two-wire mode usi clock input. sck: spi master clock output, slave clock input pin. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of dda5. when th e spi is enabled as a master, the data di rection of this pin is controlled by dda5. when the pin is forced to be an input, th e pull-up can still be controlled by the porta5 bit. ? pcint4/adc4/icp1/di/sda/mosi ? port a, bit 4 pcint4: pin change interrupt, source 4. adc4: analog to digital converter, channel 4. icp1: timer/counter1 input ca pture trigger. the pa3 pin can act as an input capture pin for timer/counter1. di: three-wire mode usi data input. usi three-wire mode do es not override normal port functions, so pin must be configure as an input for di function. sda: two-wire mode serial interf ace (usi) data input / output. mosi: spi master output / slave input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of dda3. when the spi is enabled as a master, t he data direction of this pin is controlled by dda3. when the pin is forced by the spi to be an input, th e pull-up can still be controlled by the porta3 bit. ? pcint3/adc3/isrc/int1 ? port a, bit 3 pcint3: pin change interrupt, source 3. adc3: analog to digital converter, channel 3. iscr: current source output pin. while current is sourced by the current source module, the user can use the analog to digital converter channel 4 (adc4) to measure the pin voltage. int1: external interrupt, source 1. the pa4 pi n can serve as an external interrupt source.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 94 ? pcint2/adc2/oc0a/do/miso ? port a, bit 2 pcint2: pin change interrupt, source 2. adc2: analog to digital converter, channel 2. oc0a: output compare match a or output pwm a for timer/count er0. the pin has to be configured as an output (dda2 set (one)) to serve these functions. do: three-wire mode usi data output. thr ee-wire mode data output overrides porta2 and it is driven to the port when the data direction bit dda2 is set. porta2 still enables the pu ll-up, if the direction is input and porta2 is set (one). miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of dda2. when the spi is enabled as a salve, the data direction of this pin is controlled by dda2. when the pin is forced to be an input, the pull-up can still be controlled by porta2. ? pcint1/adc1/txd/txlin ? port a, bit 1 pcint1: pin change interrupt, source 1. adc1: analog to digital converter, channel 1. txd: uart transmit pin. when the uart transmitter is enabled, this pin is configured as an output regardless the value of dda1. porta1 still enables the pull-up, if the direction is input and porta2 is set (one). txlin: lin transmit pin. when the lin is enabled, this pin is configured as an output regardless the value of dda1. porta1 still enables the pull-up, if the dire ction is input and porta2 is set (one). ? pcint0/adc0/rxd/rxlin ? port a, bit 0 pcint0: pin change interrupt, source 0. adc0: analog to digital converter, channel 0. rxd: uart receive pin. when the uart rece iver is enabled, this pin is configured as an input regardless of the value of dda0. when the pin is forced to be an input, a logical one in porta0 will turn on the internal pull-up. rxlin: lin receive pin. when the lin is enabled, this pin is configured as an input regardless of the value of dda0. when the pin is forced to be an input, a logical one in porta0 will turn on the internal pull-up.
95 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 table 4-25 and table 4-26 relate the alternate functions of port a to the overriding signals shown in figure 4-29 on page 89 . table 4-25. overriding signals for alternate functions in pa7..pa4 signal name pa7/pcint7/ adc7/ain1 /xref/aref pa6/pcint6/ adc6/ain0/ss pa5/pcint5/adc5/ t1/usck/scl/sck pa4/pcint4/adc4/ icp1/di/sda/mosi puoe 0 spe & mstr spe & mstr spe & mstr puov 0 porta6 & pud porta5 & pud porta4 & pud ddoe 0 spe & mstr (spe & mstr ) | (usi_2_wire & usipos) (spe & mstr ) | (usi_2_wire & usipos) ddov 0 0 (usi_scl_hold | porta5 ) & ddra6 { (spe & mstr ) ? (0) : (usi_shiftout | porta4 ) & ddra4) } pvoe 0 0 (spe & mstr) | (usi_2_wire & usipos & ddra5) (spe & mstr) | (usi_2_wire & usipos & ddra4) pvov 0 0 { (spe & mstr) ? (sck_output) : ~ (usi_2_wire & usipos & ddra5) } { (spe & mstr) ? (mosi_output) : ~ (usi_2_wire & usipos & ddra4) } ptoe 0 0 usi_ptoe & usipos 0 dieoe adc7d | (pcie0 & pcmsk07) adc6d | (pcie0 & pcmsk06) adc5d | (usisie & usipos) | (pcie0 & pcmsk05) adc4d | (usisie & usipos) | (pcie0 & pcmsk04) dieov pcie0 & pcmsk07 pcie0 & pcmsk06 (usisie & usipos) | (pcie0 & pcmsk05) (usisie & usipos) | (pcie0 & pcmsk04) di pcint7 pcint6 -/- ss pcint5 -/- t1 -/- usck -/- scl -/- sck pcint4 -/- icp1 -/- di -/- sda -/- mosi aio adc7 -/- ain1 -/- xref -/- aref adc6 -/- ain0 adc5 adc4
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 96 table 4-26. overriding signals for alternate functions in pa3..pa0 signal name pa3/pcint3/adc3/ isrc/int1 pa2/pcint2/adc2/ oc0a/do/miso pa1/pcint1/adc1/ txd/txlin pa0/pcint0/adc0/ rxd/rxlin puoe 0 spe & mstr lin_tx_enable lin_rx_enable puov porta3 & pud porta2 & pud { (lin_tx_enable) ? (0) : (porta1 & pud ) } porta0 & pud ddoe 0 spe & mstr lin_tx_enable lin_rx_enable ddov 0 0 lin_tx_enable 0 pvoe 0 (spe & mstr) | (usi_2_wire & usi_3_wire & usipos) | oc0a lin_tx_enable 0 pvov 0 { (spe & mstr) ? (miso_output) : ( ( usi_2_wire & usi_3_wire & usipos ) ? (usi_shiftout) : (oc0a) ) } { (lin_tx_enable) ? (lin_tx) : (0) } 0 ptoe 0 0 0 0 dieoe adc3d | int1_enable | (pcie0 & pcmsk03) adc2d | (pcie0 & pcmsk02) adc1d | (pcie0 & pcmsk01) adc0d | (pcie0 & pcmsk00) dieov int1_enable | (pcie0 & pcmsk03) pcie0 & pcmsk02 pcie0 & pcmsk01 pcie0 & pcmsk00 di pcint3 -/- int1 pcint2 -/- miso pcint1 pcint0 aio adc3 -/- isrc adc2 adc1 adc0
97 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10.3.4 alternate functions of port b the port b pins with alternate functions are shown in table 4-27 . table 4-27. port b pins alternate functions port pin alternate functions pb7 pcint15 (pin change interrupt 15) adc10 (adc input channel 10) oc1bx (output compare and pwm ou tput b-x for timer/counter1) reset (reset input pin) dw ( debugwire i/o) pb6 pcint14 (pin change interrupt 14) adc9 (adc input channel 9) oc1ax (output compare and pwm ou tput a-x for timer/counter1) int0 (external interrupt0 input) pb5 pcint13 (pin change interrupt 13) adc8 (adc input channel 8) oc1bw (output compare and pwm output b-w for timer/counter1) xtal2 (chip clock oscillator pin 2) clko (system clock output) pb4 pcint12 (pin change interrupt 12) oc1aw (output compare and pwm output a-w for timer/counter1) xtal1 (chip clock oscillator pin 1) clki (external clock input) pb3 pcint11 (pin change interrupt 11) oc1bv (output compare and pwm ou tput b-v for timer/counter1) pb2 pcint10 (pin change interrupt 10) oc1av (output compare and pwm output a-v for timer/counter1) usck (three-wire mode usi default clock input) scl (two-wire mode usi default clock input) pb1 pcint9 (pin change interrupt 9) oc1bu (output compare and pwm output b-u for timer/counter1) do (three-wire mode usi default data output) pb0 pcint8 (pin change interrupt 8) oc1au (output compare and pwm output a-u for timer/counter1) di (three-wire mode usi default data input) sda (two-wire mode usi default data input / output)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 98 the alternate pin configuration is as follows: ? pcint15/adc10/oc1bx/reset /dw ? port b, bit 7 pcint15: pin change interrupt, source 15. adc10: analog to digital converter, channel 10. oc1bx: output compare and pwm output b-x for timer/counter1. the pb7 pin has to be configured as an output (ddb7 set (one)) to serve this function. the oc1bx pin is also the output pin for the pwm mode timer function (c.f. oc1bx bit of tccr1d register). reset : reset input pin. when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to rely on power-on reset and brown-out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connect ed to the pin, and the pin can not be used as an i/o pin. if pb7 is used as a reset pin, ddb7, portb7 and pinb7 will all read 0. dw: when the debugwire enable (dwen) fuse is programme d and lock bits are unprogrammed, the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. ? pcint14/adc9/oc1ax/int0 ? port b, bit 6 pcint14: pin change interrupt, source 14. adc9: analog to digital converter, channel 9. oc1ax: output compare and pwm output a-x for timer/counter1. the pb6 pin has to be configured as an output (ddb6 set (one)) to serve this function. the oc1ax pin is also the output pin for the pwm mode timer function (c.f. oc1ax bit of tccr1d register). int0: external interrupt0 input. the pb6 pin can serve as an external interrupt source. ? pcint13/adc8/oc1bw/xtal2/ clko ? port b, bit 5 pcint13: pin change interrupt, source 13. adc8: analog to digital converter, channel 8. oc1bw: output compare and pwm output b-w for timer/counte r1. the pb5 pin has to be conf igured as an output (ddb5 set (one)) to serve this function. the oc1bw pin is also t he output pin for the pwm mode timer function (c.f. oc1bw bit of tccr1d register). xtal2: chip clock oscillator pin 2. used as clock pin for cr ystal oscillator or low-frequency crystal oscillator. when used as a clock pin, the pin can not be used as an i/o pin. clko: divided system clock output. the di vided system clock can be output on the pb5 pin. the divided system clock will be output if the ckout fuse is programmed, regardless of the portb5 and ddb5 settings. it will also be output during reset. ? pcint12/oc1aw/xtal1/clki ? port b, bit 4 pcint12: pin change interrupt, source 12. oc1aw: output compare and pwm output a-w for timer/counte r1. the pb4 pin has to be conf igured as an output (ddb4 set (one)) to serve this function. the oc1aw pin is also t he output pin for the pwm mode timer function (c.f. oc1aw bit of tccr1d register). xtal1: chip clock oscillator pin 1. used for all chip clock so urces except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. clki: external clock input. when used as a cloc k pin, the pin can not be used as an i/o pin. note: if pb4 is used as a clock pin (xtal1 or clki), ddb4, portb4 and pinb4 will all read 0.
99 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? pcint11/oc1bv ? port b, bit 3 pcint11: pin change interrupt, source 11. oc1bv: output compare and pwm output b-v for timer/counter1. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc1bv pin is also the output pin for the pwm mode timer function (c.f. oc1bv bit of tccr1d register). ? pcint10/oc1av/usck/scl ? port b, bit 2 pcint10: pin change interrupt, source 10. oc1av: output compare and pwm output a-v for timer/counter1. the pb2 pin has to be configured as an output (ddb2 set (one)) to serve this function. the oc1av pin is also the output pin for the pwm mode timer function (c.f. oc1av bit of tccr1d register). usck: three-wire mode usi clock input. scl: two-wire mode usi clock input. ? pcint9/oc1bu/do ? port b, bit 1 pcint9: pin change interrupt, source 9. oc1bu: output compare and pwm output b-u for timer/coun ter1. the pb1 pin has to be configured as an output (ddb1 set (one)) to serve this function. the oc1bu pin is also the output pin for the pwm mode timer function (c.f. oc1bu bit of tccr1d register). do: three-wire mode usi data output. three- wire mode data output overrides portb1 and it is driven to the port when the data direction bit ddb1 is set. portb1 still enables the pull-up, if the direction is input and portb1 is set (one). ? pcint8/oc1au/di/sda ? port b, bit 0 ipcint8: pin change interrupt, source 8. oc1au: output compare and pwm output a-u for timer/coun ter1. the pb0 pin has to be configured as an output (ddb0 set (one)) to serve this function. the oc1au pin is also the output pin for the pwm mode timer function (c.f. oc1au bit of tccr1d register). di: three-wire mode usi data input. usi three-wire mode do es not override normal port functions, so pin must be configure as an input for di function. sda: two-wire mode serial inte rface (usi) data input/output.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 100 table 4-28 and table 4-29 relate the alternate functions of port b to the overriding signals shown in figure 4-29 on page 89 . table 4-28. overriding signals for alternate functions in pb7..pb4 signal name pb7/pcint15/adc10/ oc1bx/reset /dw pb6/pcint14/adc9/ oc1ax/int0 pb5/pcint13/adc8/ oc1bw/xtal2/clko pb4/pcint12/ oc1aw/xtal1/clki puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc1b_enable & oc1bx oc1a_enable & oc1ax oc1b_enable & oc1bw oc1a_enable & oc1aw pvov oc1b oc1a oc1b oc1a ptoe 0 0 0 0 dieoe adc10d | (pcie1 & pcmsk15) adc9d | int0_enable | (pcie1 & pcmsk14) adc8d | (pcie1 & pcmsk13) (pcie1 & pcmsk13) dieov pcie1 & pcmsk15 int0_enable | (pcie1 & pcmsk14) pcie1 & pcmsk13 1 di pcint15 pcint14 -/- int1 pcint13 pcint12 aio reset -/- adc10 -/- adc9 -/- isrc adc8 -/- xtal2 xtal1 -/- clki table 4-29. overriding signals for alternate functions in pb3..pb0 signal name pb3/pcint11/ oc1bv pb2/pcint10/ oc1av/usck/scl pb1/pcint9/ oc1bu/do pb0/ipcint8/ oc1au/di/sda puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 (usi_2_wire & usipos ) 0 (usi_2_wire & usipos ) ddov 0 (usi_scl_hold | portb2 ) & ddrb2 0 (usi_shiftout | portb0 ) & ddrb0) pvoe oc1b_enable & oc1bv (usi_2_wire & usipos & ddrb2) | (oc1a_enable & oc1av) (usi_2_wire & usi_3_wire & usipos ) | (oc1b_enable & oc1bu) (usi_2_wire & usipos & ddrb0) | (oc1a_enable & oc1au) pvov oc1b { (usi_2_wire & usipos & ddrb2) ? (0) : (oc1a) } { (usi_2_wire & usi_3_wire & usipos ) ? (usi_shiftout) : (oc1b) } { (usi_2_wire & usipos & ddrb0) ? (0) : (oc1a) } ptoe 0 usi_ptoe & usipos 0 0 dieoe pcie1 & pcmsk11 (usisie & usipos ) | (pcie1 & pcmsk10) pcie1 & pcmsk9 (usisie & usipos ) | (pcie1 & pcmsk8) dieov 1 (usisie & usipos ) | (pcie1 & pcmsk10) 1 (usisie & usipos ) | (pcie1 & pcmsk8) di pcint11 pcint10 -/- usck -/- scl pcint9 pcint8 -/- di -/- sda aio 0 0 0 0
101 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.10.4 register description for i/o ports 4.10.4.1 port a data register ? porta 4.10.4.2 port a data di rection register ? ddra 4.10.4.3 port a input pins register ? pina 4.10.4.4 port b data register ? portb 4.10.4.5 port b data di rection register ? ddrb 4.10.4.6 port b input pins register ? pinb bit 76543210 porta7 porta6 porta5 porta4 port a3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) initial value n/a n/a n/a n/a n/a n/a n/a n/a
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 102 4.11 8-bit timer/counter0 and asynchronous operation timer/counter0 is a general purpose, single channel, 8-bit timer/cunter module. the main features are: 4.11.1 features single channel counter clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) frequency generator 10-bit clock prescaler overflow and compare match interrupt sources (tov0 and ocf0a) allows clocking from external crystal (i.e. 32khz watch crystal) independent of the i/o clock 4.11.2 overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. however, when using the register or bit defines in a program, the precise form must be us ed, i.e., tcnt0 for accessing timer/counter0 counter value and so on. a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a value and so on. a simplified block diagram of the 8-bit timer/counter is shown in figure 4-30 . cpu accessible i/o regist ers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the section 4.11.11 ?8-bit timer/counter register description? on page 113 . figure 4-30. 8-bit timer/counter0 block diagram top = 0 = 0xff bottom status flags synchronized status flags asynchronous mode select (asn) synchronization unit xtal2 xtal1 ocnx tcntn timer/counter count clear direction ocrnx assrn tccrnx = data bus control logic prescaler waveform generation oscillator clk tn clk i/o clk i/o clk asy tovn (int. req.) ocnx (int. req.)
103 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the timer/counter (tcnt0) and output compar e register (ocr0a) are 8-bit registers. interrupt request (shorten as int.req.) signals are all visible in the timer interr upt flag register (tifr0). all interrupts are individually masked with the timer int errupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or asynchronously clocked from the xtal1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block contro ls which clock source the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare register (ocr0a) is compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (oc0a). section 4.11.5 ?output compare unit? on page 104 for details. the compare match event will also set the compare flag (ocf0a) which can be used to generate an output compare interrupt request. 4.11.2.1 definitions the following definitions are used extensively throughout the section: 4.11.3 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter contro l register (tccr0).the clock source clk t0 is by default equal to the mcu clock, clk i/o . when the as0 bit in the assr register is written to logic one, the clock source is taken from the ti mer/counter oscillator connected to xtal1 and xtal2 or directly from xtal1. for details on asynchronous operation, see section 4.11.11.5 ?asynchronous status register ? assr? on page 116 . for details on clock sources and prescaler, see section 4.11.10 ?timer/counter0 prescaler? on page 112 . 4.11.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 4-31 shows a block diagram of the counter and its surrounding environment. figure 4-31. counter unit block diagram bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum w hen it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignm ent is dependent on the mode of operation. to p bottom tovn (int. req.) data bus control logic tcntn clk tn clk tns clear count direction clk i/o prescaler oscillator xtal2 xtal1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 104 signal description (internal signals): count increment or decrement tcnt0 by 1. direction selects between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t 0 timer/counter0 clock. top signalizes that tcnt0 has reached maximum value. bottom signalizes that tcnt0 has r eached minimum value (zero). depending on the mode of operation used, t he counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source , selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has pr iority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc0a. for more details about advanced counting sequences and waveform generation, see section 4.11.7 ?modes of operation? on page 106 . the timer/counter overflow flag (tov0) is set according to t he mode of operation selected by the wgm01:0 bits. tov0 can be used for generating a cpu interrupt. 4.11.5 output compare unit the 8-bit comparator continuously compares tcnt0 with th e output compare register (ocr0a). whenever tcnt0 equals ocr0a, the comparator signals a match. a match will set the ou tput compare flag (ocf0a) at the next timer clock cycle. if enabled (ocie0a = 1), the outpu t compare flag generates an output compare interrupt. the ocf0a flag is automatically cleared when the interrupt is executed. alternatively, the ocf0 a flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an out put according to operating mode set by the wgm01:0 bits and compare output mode (com0a1:0) bits. the max and bo ttom signals are used by the waveform generator for handling the special cases of the ex treme values in some modes of operation (see section 4.11.7 ?modes of operation? on page 106 ). figure 4-32 shows a block diagram of the output compare unit. figure 4-32. output comp are unit, block diagram the ocr0a register is double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the doubl e buffering is disabled. the double buffering synchronizes the update of the ocr0a compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0a register access may seem co mplex, but this is not case. when th e double buffering is enabled, the cpu has access to the ocr0a buffer register, and if double buffer ing is disabled the cpu will access the ocr0a directly. ocfnx (int. req.) = (8-bit comparator) ocrnx waveform generator tcntn ocnx to p bottom focn wgmn1:0 comnx1:0 data bus
105 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.11.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0a) bit. forc ing compare match will not set the ocf0a flag or reload/clear the timer, but the oc0a pin will be updated as if a real compare match had occurred (the co m0a1:0 bits settings define w hether the oc0a pin is set, cleared or toggled). 4.11.5.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any co mpare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0a to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 4.11.5.3 using the ou tput compare unit since writing tcnt0 in any mode of ope ration will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compar e channel, independently of w hether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0 a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write th e tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0a should be performed bef ore setting the data direction register for the port pin to output. the easiest way of setting the oc0a value is to use the force output co mpare (foc0a) strobe bit in no rmal mode. the oc0a register keeps its value even when changing between waveform generation modes. be aware that the com0a1:0 bits are not double buffered together with the comp are value. changing the com0a1:0 bits will take effect immediately. 4.11.6 compare match output unit the compare output mode (com0a1:0) bits have two functi ons. the waveform generator uses the com0a1:0 bits for defining the output compar e (oc0a) state at the next compare match. also, the com0a1:0 bits control the oc0a pin output source. figure 4-33 shows a simplified schematic of the logic affected by the com0a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only th e parts of the general i/o port control registers (ddr and port) that are affected by the com0a1:0 bits ar e shown. when referring to the oc0a state, the reference is for the internal oc0a register, not the oc0a pin. figure 4-33. compare match output logic data bus 0 1 q d comnx1 comnx0 focnx ocnx waveform generator q d port q d ddr ocnx pin clk i/o
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 106 4.11.6.1 compare output function the general i/o port function is overridden by the output co mpare (oc0a) from the waveform generator if either of the com0a1:0 bits are set. however, the oc0a pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for th e oc0a pin (ddr_oc0a) must be set as output before the oc0a value is visible on the pin. the port override func tion is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0a state before the output is enabled. note that some com0a1:0 bit settings are reserved for certain modes of operation. see section 4.11.11 ?8-bit timer/counter register description? on page 113 . 4.11.6.2 compare output mode and waveform generation the waveform generator uses the com0a1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0a1:0 = 0 tells the waveform generator that no action on the oc0a register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 4-30 on page 113 . for fast pwm mode, refer to table 4-31 on page 113 , and for phase correct pwm refer to table 4-32 on page 114 . a change of the com0a1:0 bits state will have effect at t he first compare match after the bits are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the foc0a strobe bits. 4.11.7 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm01:0) and compare output mode (com0a1:0) bits . the compare output mode bits do not affect the counting sequence, while t he waveform generation mode bits do. the com0a1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0a1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see section 4.11.6 ?compare match output unit? on page 105 ). for detailed timing information refer to section 4.11.8 ?timer/counter timing diagrams? on page 110 . 4.11.7.1 normal mode the simplest mode of operation is t he normal mode (wgm01:0 = 0). in this mo de the counting direction is always up (incrementing), and no counter clear is performed. the coun ter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the ti mer/counter overflow flag (tov0) will be set in the same timer cl ock cycle as the tcnt0 becomes zero . the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 4.11.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm01:0 = 2), the ocr0 a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allo ws greater control of the comp are match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 4-34 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared.
107 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-34. ctc mode, timing diagram an interrupt can be generated each time the counter value reac hes the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is ru nning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare ma tch. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to to ggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to out put. the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero (0x00). the wave form frequency is defined by the following equation: the n variable represents the prescale fact or (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of opera tion, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 4.11.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm01:0 = 3) provides a high frequency pwm waveform generation option. the fast pwm differs from the ot her pwm option by its single-slope operation. the counter counts from bottom to max then restarts from bottom. in non- inverting compare output mode, the output compare (o c0a) is cleared on the compare match between tcnt0 and ocr0a, and set at bottom. in inverting compar e output mode, the output is set on compare match and cleared at bottom. due to the single-sl ope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that us es dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors ), and therefore reduces total system cost. in fast pwm mode, the counter is increm ented until the counter value matches the max value. the counter is then cleared at the following timer clock cycl e. the timing diagram for th e fast pwm mode is shown in figure 4-35 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. 12 tcntn (comnx1:0 = 1) ocnx (toggle) period 3 ocnx interrupt flag set 4 f ocnx f clk_i/o 2n 1 ocrnx + () ---------------------------------------------------- =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 108 figure 4-35. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the co unter reaches max. if the inte rrupt is enabled, the interrupt handler routine can be used fo r updating the compare value. in fast pwm mode, the compare unit allo ws generation of pwm waveforms on the oc 0a pin. setting the com0a1:0 bits to two will produce a non-inverted pwm and an inverted pwm out put can be generated by setting the com0a1:0 to three (see table 4-31 on page 113 ). the actual oc0a value will only be visible on the po rt pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or cl earing) the oc0a register at the compare match between ocr0a and tcnt0, and clearing (or setting) the oc0a register at the timer clock cycle the counter is cleared (changes from max to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale fact or (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr0a regist er represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow sp ike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the pol arity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform ou tput in fast pwm mode ca n be achieved by setting oc0a to toggle its logical level on each compare match (com0a1:0 = 1). the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc 0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 1234567 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period ocrnx update and tovn interrupt flag set ocrnx interrupt flag set f ocnxpwm f clk_i/o n 256 ------------------- =
109 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.11.7.4phase correct pwm mode the phase correct pwm mode (wgm01:0 = 1) provides a hi gh resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope opera tion. the counter counts repeatedly from bottom to max and then from max to bottom. in non- inverting compare output mode, the output compare (o c0a) is cleared on the compare match between tcnt0 and ocr0a while upcounting, and set on the compare match while downcounting. in inverting output compare mode , the operation is inverted. the dual-slope o peration has lower maximum operation frequency than single slope operation. however, due to the symmetr ic feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode is fixed to eight bits. in phase correct pwm mode the counter is incremented until the counter value matche s max. when the counter reaches max, it changes the count direction. the tcnt0 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 4-36 . the tcnt0 value is in the timing diagram shown as a hi stogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 4-36. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows ge neration of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0a1:0 to three (see table 4-32 on page 114 ). the actual oc0a value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) th e oc0a register at the compare match between ocr0a and tcnt0 when the counter increments, and setting (or clearing) the oc0a register at com pare match between ocr0a and tcnt0 when the counter decrements. the pwm frequency for t he output when using phase co rrect pwm can be calculated by the following equation: the n variable represents the prescale fact or (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr0a regist er represent special cases when generat ing a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for no n-inverted pwm mode. for inverted pwm the output will have the opposite logic values. 123 tcntn (comnx[1:0] = 2) (comnx[1:0] = 3) ocnx ocnx period tovn interrupt flag set ocrnx update ocnx interrupt flag set f ocnxpcpwm f clk_i/o n510 ------------------- =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 110 4.11.8 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t0 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 4-37 contains timing data for basic ti mer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 4-37. timer/counter timing diagram, no prescaling figure 4-38 shows the same timing data, but with the prescaler enabled. figure 4-38. timer/counter timi ng diagram, with prescaler (f clk_i/o /8) figure 4-39 shows the setting of ocf0a in all modes except ctc mode. figure 4-39. timer/counter timing diagram, setting of ocf0a, with prescaler (f clk_i/o /8) max - 1 clk i/o (clk i/o /1) tcntn tovn clk tn max bottom bottom + 1 max - 1 clk i/o (clk i/o /8) tcntn tovn clk tn max bottom bottom + 1 ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2
111 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-40 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 4-40. timer/counter timing diagram, clear timer on compar e match mode, with prescaler (f clk_i/o /8) 4.11.9 asynchronous operation of timer/counter0 when timer/counter0 operates asynchronously, some considerations must be taken. warning: when switching between asynchronous and synchronou s clocking of timer/counter0, the timer registers tcnt0, ocr0a, and tccr0a might be corrupted. a safe procedure for switching clock source is: a) disable the timer/counter0 interrup ts by clearing ocie0a and toie0. b) select clock source by sett ing as0 and exclk as appropriate. c) write new values to tcnt0, ocr0a, and tccr0a. d) to switch to asynchronous operation: wait for tcn0ub, ocr0ub, and tcr0ub. e) clear the timer/counter0 interrupt flags. f) enable interrupts, if needed. if an 32.768khz watch crystal is used, the cpu main clock frequency must be more than four times the oscillator or external clock frequency. when writing to one of the registers t cnt0, ocr0a, or tccr0a, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. ea ch of the three mentioned registers have their individual temporary register, which means that e.g. writing to tcnt0 does not disturb an ocr0a write in progress. to detect that a transfer to the destination register has taken pl ace, the asynchronous status register ? assr has been implemented. when entering power-save mode after hav ing written to tcnt0, ocr0a, or t ccr0a, the user must wait until the written register has been updated if timer/counter0 is us ed to wake up the device. ot herwise, the mcu will enter sleep mode before the changes are effective. this is particularly impor tant if the output compar e0 interrupt is used to wake up the device, since the output compare function is di sabled during writing to ocr0a or tcnt0. if the write cycle is not finished, and the mcu ent ers sleep mode before the ocr0ub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. if timer/counter0 is used to wake the device up from power-save mode, precaut ions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re-entering sleep mode is less than one tosc1 cycle, the in terrupt will not occur, and the device will fail to wake up. if the user is in doubt whether the time before re-ent ering power-save mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a) write a value to t ccr0a, tcnt0, or ocr0a. b) wait until the corresponding update busy flag in assr returns to zero. c) enter power-save or adc noise reduction mode. top - 1 clk i/o (clk i/o /8) tcntn (ctc) ocrnx ocfnx clk tn top bottom top bottom + 1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 112 when the asynchronous operation is selected, the oscillato r for timer/counter0 is always running, except in power- down mode. after a power-up reset or wake-up from power-down mode, the user should be awar e of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter0 after power-up or wake-up from po wer-down mode. the contents of all timer/counter0 registers must be considered lost after a wake-up from po wer-down mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the xtal1 pin. description of wake up from power-save mode when th e timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the foll owing cycle of the timer clock, that is, the timer is always advanced by at least one befor e the processor can read the counter value. after wake-up, the m cu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. reading of the tcnt0 register shortly after wake-up from power-save may give an incorrect result. since tcnt0 is clocked on the asynchronous cl ock, reading tcnt0 must be done through a re gister synchronized to the internal i/o clock domain (cpu main clock). synchronization takes place for every rising xtal1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt0 will read as the previous value (before entering sleep) until the next rising xtal1 edge. the p hase of the xtal1 clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt0 is thus as follows: a) write any value to either of the registers ocr0a or tccr0a. b) wait for the corresponding update busy flag to be cleared. c) read tcnt0. during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt fl ag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 4.11.10 timer/counter0 prescaler figure 4-41. prescaler for timer/counter0 timer/countern clock source clk tn clk tns /8 clk tns /32 clk tns /64 clk tns /128 clk tns /256 clk tns /1024 asn xtal2 xtal1 exclk psrn clk tns clk i/o 10-bit t/c prescaler 0 clear oscillator 0 1 0 1 csn0 csn1 csn2
113 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the clock source for timer/counter0 is named clk t0s . clk t0s is by default conn ected to the main system i/o clock clk io . by setting the as0 bit in assr, timer/counter0 is asynchronously cl ocked from the xtal oscillator or xtal1 pin. this enables use of timer/counter0 as a real time counter (rtc). a crystal can then be connected between the xtal1 and xt al2 pins to serve as an independent clock source for timer/counter0. a external clock can also be used using xtal1 as in put. setting as0 and exclk enables this configuration. for timer/counter0, the possible prescaled selections are: clk t0s /8, clk t0s /32, clk t0s /64, clk t0s /128, clk t0s /256, and clk t0s /1024. additionally, clk t0s as well as 0 (stop) may be selected. settin g the psr0 bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. 4.11.11 8-bit timer/counte r register description 4.11.11.1 timer/counter0 control register a ? tccr0a ? bit 7:6 ? com0a1:0: compare match output mode a these bits control the output compare pin (oc0a) behavior. if o ne or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm01:0 bit setting. table 4-30 shows the com0a1:0 bit functionality when the wgm 01:0 bits are set to a normal or ctc mode (non-pwm). table 4-31 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. bit 76 5 4 3 210 com0a 1 com0a 0? ? ? ? wgm01 wgm 00 tccr0a read/write r/w r/w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-30. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match. 1 0 clear oc0a on compare match. 1 1 set oc0a on compare match. table 4-31. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 1 0 clear oc0a on compare match. set oc0a at bottom (non-inverting mode). 1 1 set oc0a on compare match. clear oc0a at bottom (inverting mode). note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 4.11.7.3 ?fast pwm mode? on page 107 for more details.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 114 table 4-32 shows the com01:0 bit functionality when the wg m01:0 bits are set to phase correct pwm mode. ? bit 5:2 ? res: reserved bits these bits are reserved in the atmel ? attiny87/167 and will always read as zero. ? bit 6, 3 ? wgm01:0: waveform generation mode these bits control the counting sequence of the counter, the source for the maximu m (top) counter value, and what type of waveform generation to be used, see table 4-33 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, a nd two types of pulse width modulation (pwm) modes (see section 4.11.7 ?modes of operation? on page 106 ). table 4-32. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 4.11.7.4 ?phase correct pwm mode? on page 109 for more details. table 4-33. waveform generation mode bit description mode wgm01 (ctc0) wgm00 (pwm0) timer/counter mode of operation top update of ocr0a at tov0 flag set on (1)(2) 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr0a immediate max 3 1 1 fast pwm 0xff top max notes: 1. max = 0xff 2. bottom = 0x00
115 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.11.11.2 timer/counter0 control register b ? tccr0b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bi t, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to it s com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefor e it is the value present in the com0a1:0 bits that determ ines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6:3 ? res: reserved bits these bits are reserved in the atmel ? attiny87/167 and will always read as zero. ? bit 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 4-34 . 4.11.11.3 timer/counter0 register ? tcnt0 the timer/counter register gives direct a ccess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (re moves) the compare match on the followin g timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x register. bit 76 5 4 3 210 foc0a ? ? ? ? cs02 cs01 cs00 tccr0b read/write w r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-34. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk t0s (no prescaling) 0 1 0 clk t0s /8 (from prescaler) 0 1 1 clk t0s /32 (from prescaler) 1 0 0 clk t0s /64 (from prescaler) 1 0 1 clk t0s /128 (from prescaler) 1 1 0 clk t 0 s /256 (from prescaler) 1 1 1 clk t 0 s /1024 (from prescaler) bit 76543210 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 116 4.11.11.4 output compare register a ? ocr0a the output compare register a contains an 8-bit value that is continuou sly compared with the counter value (tcnt0). a match can be used to generate an output compare interr upt, or to generate a waveform output on the oc0a pin. 4.11.11.5 asynchronous status register ? assr ? bit 7 ? res: reserved bit this bit is reserved in the atmel ? attiny87/167 and will always read as zero. ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on xtal1 pin instead of an external crystal. writing to exclk should be done before asynchronous operation is selected. note that the cr ystal oscillator will only run when this bit is zero. ? bit 5 ? as0: asynch ronous timer/counter0 when as0 is written to zero, timer/coun ter0 is clocked from the i/o clock, cl ki/o and the timer/counter0 acts as a synchronous peripheral. when as0 is written to one, timer/counter0 is cl ocked from the low-frequency crystal oscillator ( section 4.5.2.5 ?low- frequency crystal oscillator? on page 51 ) or from external clock on xtal1 pin ( section 4.5.2.6 ?exter nal clock? on page 52 ) depending on exclk setting. when the value of as0 is cha nged, the contents of tcnt0, ocr0a, and tccr0a might be corrupted. as0 also acts as a flag: timer/counter0 is clocked from the low-frequency crystal or from external clock only if the calibrated internal rc oscillator or the internal watchdog osc illator is used to drive the system clock. after setting as0, if the switching is available, as0 remains to 1, else it is forced to 0. ? bit 4 ? tcn0ub: timer/counter0 update busy when timer/counter0 operates asynchronously and tcnt0 is written, this bit becomes set. when tcnt0 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt0 i s ready to be updated with a new value. ? bit 3 ? ocr0aub: output compare 0 register a update busy when timer/counter0 operates asynchronously and ocr0a is written, this bit becomes set. when ocr0a has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bi t indicates that ocr0a i s ready to be updated with a new value. ? bit 2 ? res: reserved bit this bit is reserved in the atmel attiny87/167 and will always read as zero. ? bit 1 ? tcr0aub: timer/counter0 control register a update busy when timer/counter0 operates asynchronously and tccr0a is written, this bit becomes set. when tccr0a has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr0a is ready to be updated with a new value. bit 76543210 ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 7654 321 0 ? exclk as0 tcn0ub ocr0aub ? tcr0aub tcr0bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0
117 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 0 ? tcr0bub: timer/counter0 control register b update busy when timer/counter0 operates asynchronously and tccr0b is written, this bit becomes set. when tccr0b has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr0b is ready to be updated with a new value. if a write is performed to any of the four timer/counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt0, ocr0 a, tccr0a and tccr0b are di fferent. when reading tcnt0, the actual timer value is read. when reading ocr0a, tccr0a or tccr0b the value in the temporary storage register is read. 4.11.11.6 timer/counter 0 interrupt mask register ? timsk0 ? bit 7:2 ? res: reserved bits these bits are reserved in the atmel ? attiny87/167 and will always read as zero. ? bit 1 ? ocie0a: timer/counter0 outp ut compare match a interrupt enable when the ocie0a bit is written to one and the i-bit in the stat us register is set (one), the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/coun ter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one and the i-bit in the status register is set (one ), the timer/counter0 overflow interrupt i s enabled. the corresponding interrupt is exec uted if an overflow in timer/counter0 oc curs, i.e., when the tov0 bit is set in the timer/counter0 interrupt flag register ? tifr0. 4.11.11.7 timer/counter0 interrupt flag register ? tifr0 ? bit 7:2 ? res: reserved bits these bits are reserved in the atmel attiny87/167 and will always read as zero. ? bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set (one) when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0 (timer/counter0 compare match interrupt enable), and ocf0a are set (one), the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the tov0 bit is set (one) when an overflow occurs in time r/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alte rnatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0a (timer/count er0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. in pwm mode, this bit is set when ti mer/counter0 changes counting direction at 0x00. bit 76543210 ??????ocie0atoie0timsk0 read/write r r r r r r r/w r/w initial value00000000 bit 76543210 ??????ocf0atov0tifr0 read/write r r r r r r r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 118 4.11.11.8 general timer/counter control register ? gtccr ? bit 1 ? psr0: prescaler reset timer/counter0 when this bit is one, the timer/counter0 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter0 is operating in asynchronou s mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if t he tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mode? on page 119 for a description of the timer/counter synchronization mode. 4.12 timer/counter1 prescaler 4.12.1 overview most bit references in this section are written in general form. a lower case ?n? repl aces the timer/ counter number. 4.12.1.1 internal clock source the timer/counter can be clo cked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 4.12.1.2 prescaler reset the prescaler is free running, i.e., operates independently of t he clock select logic of the timer/counter. since the prescaler is not affected by the timer/count er?s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts o ccurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when th e timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals th e prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing t he timer/counter to program exec ution. however, care must be taken if the other timer/counte r that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 4.12.1.3 external clock source an external clock source applied to the t1 pin can be used as timer/counter clock (clk t1 ). the t1 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 4-42 shows a functional equivalent block diagram of the t1 synchronization and edge detector logic. the registers are clocked at the positiv e edge of the internal system clock (clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 4-42. t1 pin sampling bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psr0 psr1 gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 tn synchronization edge detector tn_sync (to clock select logic) q le d q d q d clk i/o
119 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1 pin to the counter is updated. enabling and disabling of the clock input must be done when t1 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 120 4.13 16-bit timer/counter1 the 16-bit timer/counter unit allows a ccurate program execution timing (event management), wave generation, and signal timing measurement. th e main features are: 4.13.1 features true 16-bit design (i.e., allows 16-bit pwm) two independent output compare units four controlled output pins per output compare unit double buffered out put compare registers one input capture unit input capture noise canceler clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) variable pwm period frequency generator external event counter four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 4.13.2 overview many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 1. however, when using the register or bit defines in a program, the precise form must be us ed, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a lower case ?x? replaces the output compare unit channel, in th is case a or b. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr1a for accessing timer/counter1 output compare channel a value and so on. a lower case ?i? replaces the index of the output compare out put pin, in this case u, v, w or x. however, when using the register or bit defines in a pr ogram, the precise form must be used. a simplified block diagram of the 16-bit timer/counter is shown in figure 4-44 . cpu accessible i/o r egisters, including i/o bits and i/o pins, are shown in bold. the device-specif ic i/o register and bit locations are listed in the section 4.13.11 ?16-bit timer/counter register description? on page 141 .
121 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-44. 16-bit timer/counter1 block diagram (1) note: 1. refer to table 4-27 on page 97 , and table 4-24 on page 92 for timer/counter1 pin placement and description. control logic tcntn timer/counter count clear direction clk tn ocrna ocrnb tccrna icrn tccrnb tccrnc = edge detector (from prescaler) clock select top bottom tovn (int. req.) ocna (int. req.) tn waveform generation fixed top value data bus = = = 0 ocnau ocnav ocnaw ocnax ocnb (int. req.) waveform generation noise canceler ocnbu (from analog comparator output) ocnbv ocnbw ocnbx icfn (int. req.) edge detector icpn
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 122 4.13.2.1 registers the timer/counter (tcnt1), output compare re gisters (ocr1a/b), and input capture regi ster (icr1) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in section 4.13.3 ?accessing 16-bit registers? on page 123 . the timer/counter control registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated to int.r eq. in the figure) signals are all visible in the timer interr upt flag register (tifr1). all interrupts are individually maske d with the timer inte rrupt mask register (timsk1). tifr1 and timsk1 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. th e clock select logic block controls which clock source and edge the timer/ counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare register s (ocr1a/b) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to ge nerate a pwm or variable frequency output on the output compare pins, see section 4.13.7 ?output compare units? on page 128 . the compare match event will also set the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. the input capture register can capture the timer/counter value at a given external (edge triggered) event on either the input capture pin (icp1) or on the analog comparator pins ( section 4.19 ?anacomp - analog comparator? on page 209 ). the input capture unit includes a digital filterin g unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in so me modes of operation be defined by either the ocr1a register, the icr1 register, or by a set of fixed values . when using ocr1a as top value in a pwm mode, the ocr1a register can not be used for ge nerating a pwm output. ho wever, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as pwm output. 4.13.2.2 definitions the following definitions are used extensively throughout the section: bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its maximum when it becomes 0xffff (decimal 65,535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr 1 a or icr 1 register. the assignment is dependent of the mode of operation.
123 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.3 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr ? cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or writ e operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same te mporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into t he 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by t he cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the hi gh byte. reading the ocr1a/b 16-b it registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before th e high byte. 4.13.3.1 code examples the following code examples show how to access the 16-bi t timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly fo r accessing the ocr1a/b and icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register , and the interrupt code updates the temp orary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the in terrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff sts tcnt 1 h,r17 sts tcnt 1 l,r16 ; read tcnt 1 into r17:r16 lds r16,tcnt 1 l lds r17,tcnt 1 h ... c code examples (1) unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... note: the example code assumes that the part specific header file is included
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 124 the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example (1) tim16_readtcnt1: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt1 into r17:r16 lds r16,tcnt1l lds r17,tcnt1h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt1( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt1 into i */ i = tcnt1; /* restore global interrupt flag */ sreg = sreg; return i; } note: 1. the example code assumes that the part specific header file is included.
125 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b or icr1 registers can be done by using the same principle. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcnt1. 4.13.3.2 reusing the temporary high byte register if writing to more than one 16-bit regist er where the high byte is the same for a ll registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described pr eviously also applies in this case. assembly code example (1) tim16_writetcnt1: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt1 to r17:r16 sts tcnt1h,r17 sts tcnt1l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt1( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt1 to i */ tcnt1 = i; /* restore global interrupt flag */ sreg = sreg; } note: 1. the example code assumes that the part specific header file is included1
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 126 4.13.4 timer/counter clock sources the timer/counter can be clocked by an internal or an extern al clock source. the clock sour ce is selected by the clock select logic which is controlled by the cl ock select (cs12:0) bits located in the timer/counter control register b (tccr1b). for details on clock sources and prescaler, see section 4.12 ?timer/counter1 prescaler? on page 118 . 4.13.5 counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 4-45 shows a block diagram of the counter and its surroundings. figure 4-45. counter unit block diagram signal description (internal signals): count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory location s: counter high (tcnt1h) containing the upper eight bits of the counter, and counter low (tcnt1l) contai ning the lower eight bits. the tcnt1h register can only be indirectly accessed by the cpu. when the cpu does an access to the tcnt1h i/ o location, the cpu accesses the high byte temporary register (temp). the temporary register is updat ed with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register value when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will give unpredictab le results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, t he counter is cleared, incremented, or decremented at each timer clock (clk t1 ). the clk t1 can be generated from an external or internal clock source , selected by the clock select bits (cs12:0). when no clock source is selected (cs12:0 = 0) the timer is stopp ed. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t1 is present or not. a cpu write overrides (has prio rity over) all counter cl ear or count operations. the counting sequence is determined by the setting of th e waveform generation mode bits (wgm13:0) located in the timer/counter control regist ers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms ar e generated on the output compare out puts oc1a/b. for more details about advanced counting sequences and waveform generation, see section 4.13.9 ?modes of operation? on page 133 . the timer/counter overflow flag (tov1) is set according to t he mode of operation selected by the wgm13:0 bits. tov1 can be used for generating a cpu interrupt. bottom top tovn (int. req.) data bus (8-bit) control logic tcntnh (8-bit) tcntnh (16-bit counter) tcntnl (8-bit) temp (8-bit) clk tn clear count direction edge detector (from prescaler) clock select tn
127 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.6 input capture unit the timer/counter incorporates an input capture unit that can c apture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an ev ent, or multiple events, can be applied via the icp1 pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate freque ncy, duty-cycle, and other features of the signal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 4-46 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 4-46. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp1), alternativ ely on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a captur e will be triggered. when a capture is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf 1) is set at the same system clock as the tcnt1 value is copied into icr1 register. if enabled (i cie1 = 1), the input capture flag generates an input capture interrupt. the ic f1 flag is automatically cleared when t he interrupt is execut ed. alternatively the icf1 flag can be cleared by software by wr iting a logical one to its i/o bit location. reading the 16-bit value in the input capt ure register (icr1) is done by first read ing the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is co pied into the high byte temporary register (temp). when the cpu reads the icr1h i/o location it will access the temp register. the icr1 register can only be written when using a waveform gener ation mode that utilizes the ic r1 register for defining the counter?s top value. in these cases the waveform generation mode (wgm13:0) bits must be set before the top value can be written to the icr1 register. when wr iting the icr1 register the high byte mu st be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to section 4.13.3 ?accessing 16-b it registers? on page 123 . icfn (int. req.) icrnl (8-bit) icrnh (8-bit) icrn (16-bit register) temp (8-bit) tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) noise canceler analog comparator edge detector icncn acic aco write + - icesn icpn
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 128 4.13.6.1 input capture trigger source the main trigger source for the input capture unit is the inpu t capture pin (icp1). only timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator in put capture (acic) bit in the analog co mparator control and status register (acsr). be aware that changing trigger sour ce can trigger a capture. the input capt ure flag must therefore be cleared after the change. both the input capture pin (icp1) and t he analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin ( figure 4-42 on page 118 ). the edge detector is also identical. howe ver, when the noise canceler is enabled, additional logic is inserted before the edge detector, which in creases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icr1 to define top. an input capture can be triggered by softw are by controlling the port of the icp1 pin. 4.13.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in time r/counter control register b (tccr1b). when enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the icr1 register. the noise canc eler uses the system clock and is therefore not affected by the prescaler. 4.13.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is cr itical. if the processor has not read the ca ptured value in the icr1 register before the next event occurs, the icr1 will be overwritten with a new valu e. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high pr iority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logi cal one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 4.13.7 output compare units the 16-bit comparator continuously co mpares tcnt1 with the output compare r egister (ocr1a/b). if tcnt equals ocr1a/b the comparator signals a match. a match will set the ou tput compare flag (ocf1a/b) at the next timer clock cycle. if enabled (ocie1a/b = 1), the output compare flag gener ates an output compare interr upt. the ocf1a/b flag is automatically cleared when the in terrupt is executed. alternatively the ocf1a/b flag can be cleared by software by writing a logical one to its i/o bit loca tions. the waveform generator uses the match si gnal to generate an output according to operating mode set by the waveform generation mode (wgm13:0) bits and compare output mode (com1a/b1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see section 4.13.9 ?modes of operation? on page 133 ). a special feature of output com pare unit a allows it to define the timer/coun ter top value (i.e., coun ter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator.
129 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-47 shows a block diagram of the output compare unit. the el ements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 4-47. output comp are unit, block diagram the ocr1a/b register is double buffered when using any of the twelve pulse width modula tion (pwm) modes. for the normal and clear timer on compare (ctc) modes of operati on, the double buffering is disabled. the double buffering synchronizes the update of the ocr1a/b compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-sy mmetrical pwm pulses, thereby making the output glitch-free. the ocr1a/b register acce ss may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr1a/b buffer register, and if double buffering is disabled the cp u will access the ocr1a/b directly. the content of the ocr1 a/b (buffer or compare) register is only change d by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 re gister). therefore ocr1a/b is not read via the high byte temporary register (temp). however, it is a good practice to re ad the low byte first as when accessing other 16-bit registers. writing the ocr1a/b registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocr1a/bh) has to be written first. when the hi gh byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low byte (o cr1a/bl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr1a/b buffer or ocr1a/b compare regist er in the same system clock cycle. for more information of how to access the 16-bit registers refer to section 4.13.3 ?accessing 16-bit registers? on page 123 . ocrnxl buf. (8-bit) ocrnxh buf. (8-bit) ocrnx buffer (16-bit register) temp (8-bit) ocrnxl (8-bit) ocfnx (int. req.) ocrnxh (8-bit) ocrnx (16-bit register) = (16-bit comparator) wgmn3:0 comnx1:0 waveform generator tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) ocnxv top bottom ocnxu ocnxx ocnxw
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 130 4.13.7.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc1a/b) bit. forcing compare match will not set the ocf1a/b flag or rel oad/clear the timer, but the oc1a/bi pins will be updated as if a real compare match had occurred (the com1a/b1:0 bits settings define whether the oc1a/bi pins are set, cleared or toggled - if the respective ocnxi bit is set). 4.13.7.2 compare match blocking by tcnt1 write all cpu writes to the tcnt1 register will block any compare matc h that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr1a/b to be initialized to the same value as tcnt1 without triggering an interrupt when the timer/counter clock is enabled. 4.13.7.3 using the ou tput compare unit since writing tcnt1 in any mode of ope ration will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt1 equals the o cr1a/b value, the compare matc h will be missed, resulting in incorrect waveform generation. do not write the tcnt1 equa l to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. si milarly, do not write the tcnt1 value equal to bottom when the counter is downcounting. the setup of the oc1a/b should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1a/b value is to use the force output compare (foc1a/b) strobe bits in normal mode. the oc1a/b register keeps its value even when changing between waveform generation modes. be aware that the com1a/b1:0 bits are not double buffered together with the compare value. changing the com1a/b1:0 bits will take effect immediately.
131 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.8 compare match output unit the compare output mode (com1a/b1:0) bi ts have two functions. the waveform generator uses the com1a/b1:0 bits for defining the output compare (oc1 a/b) state at the next com pare match. secondly the com1a/b1:0 and ocnxi bits control the oc1a/bi pin output source. figure 4-49 shows a simplified schematic of the lo gic affected by the com1a/b1:0 and ocnxi bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. on ly the parts of the general i/o port control registers (ddr and po rt) that are affected by the com1a/b1:0 and ocnxi bits are shown. when referring to the oc1a/b state, the re ference is for the internal oc1a/b re gister, not the oc1a /bi pin. if a system reset occur, the oc1a/b register is reset to ?0?. figure 4-48. compare match output 1 0 portb0 oc1au (*) ddb0 pinb0 20 pb0/ oc1au 1 0 portb2 wgm10 com1a0 ocf1a ocf11 = com1a1 com1b0 com1b1 wgm11 wgm12 wgm13 oc1av (*) (*) oc1xi: tccr1d register bit ddb2 pinb2 waveform generation ocr1a 16-bit register ocr1b 16-bit register tcnt1 16-bit counter waveform generation 18 pb2/ oc1av 1 0 portb4 oc1aw (*) ddb4 pinb4 14 pb4/ oc1aw 1 0 portb6 oc1ax (*) ddb6 pinb6 12 pb6/ oc1ax foc1a top count direction clear bottom 1 0 portb1 oc1bu (*) ddb1 pinb1 19 pb1/ oc1bu 1 0 portb2 oc1bv (*) ddb3 pinb3 17 pb3/ oc1bv 1 0 portb4 oc1bw (*) ddb5 pinb5 13 pb5/ oc1bw 1 0 portb7 oc1bx (*) ddb7 pinb7 11 pb7/ oc1bx foc1b =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 132 figure 4-49. compare match output logic 4.13.8.1 compare output function the general i/o port function is overridden by the output comp are (oc1a/b) from the waveform generator if either of the com1a/b1:0 bits are set and if ocnxi respec tive bit is set in tccr1d register. howe ver, the oc1a/bi pin direction (input or output) is still controlled by t he data direction register (ddr) for the port pi n. the data direction r egister bit for the oc1a /bi pin (ddr_oc1a/bi) must be set as output before the oc1a/b value is visible on the pin. the port override function is generally independent of the waveform generation mo de, but there are some exceptions. refer to table 4-35 , table 4-36 and table 4-37 for details. the design of the output compare pin logic allows initialization of the oc1a/b state before the output is enabled. note that some com1a/b1:0 bit settings are reserv ed for certain modes of operation. see section 4.13.11 ?16-bit timer/counter register description? on page 141 . the com1a/b1:0 bits have no ef fect on the input capture unit. 4.13.8.2 compare output mode and waveform generation the waveform generator uses the com1a/b1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com1a/b1:0 = 0 tells the waveform generator that no action on the oc1a/b register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 4-35 on page 141 . for fast pwm mode refer to table 4-36 on page 141 , and for phase correct and phase and frequency correct pwm refer to table 4-37 on page 142 . a change of the com1a/b1:0 bits state wil l have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediat e effect by using the foc1a/b strobe bits. data bus 0 1 q d comnx1 ocnxi comnx0 focnx ocnx waveform generator q d port q d ddr ocnxi pin clk i/o
133 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.9 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm13:0) and compare output mode (com1a/b1:0) bi ts. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1a/b1:0 bits control whether the pwm output generated should be inverted or not (i nverted or non-inverted pwm). for non-pwm modes the com1a/b1:0 bits control whether the output should be set, cleared or toggle at a compare match (see section 4.13.8 ?compare match output unit? on page 131 ). the ocnxi bits over control the setti ng of the com1a/b1:0 bits as shown in figure 4-49 on page 132 . for detailed timing information refer to section 4.13.10 ?timer/counter timing diagrams? on page 139 . 4.13.9.1 normal mode the simplest mode of operation is t he normal mode (wgm13:0 = 0). in this mo de the counting direction is always up (incrementing), and no counter clear is performed. the counte r simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from th e bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 becomes zero. the tov1 flag in this ca se behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. howeve r, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to exte nd the resolution for the capture unit. the output compare units can be used to generate interrupts at some given ti me. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 4.13.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm13:0 = 4 or 12) , the ocr1a or icr1 register are used to manipulate the counter resolution. in ctc mode the count er is cleared to zero when the counter value (tcnt1) matches either the ocr1a (wgm13:0 = 4) or the icr1 (wgm13:0 = 12) . the ocr1a or icr1 define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 4-50 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 4-50. ctc mode, timing diagram 12 tcntn (comna1:0 = 1) ocnai (toggle) period 3 ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 4
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 134 an interrupt can be generated at each time the counter value re aches the top value by either using the ocf1a or icf1 flag according to the register used to define the top value. if th e interrupt is enabled, the inte rrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the compare match. the counter will then have to count to its maximum value (0xfff f) and wrap around starting at 0x0000 before the compare match can occur. in many cases this f eature is not desirable. an alternative wi ll then be to use the fast pwm mode using ocr1a for defining top (wgm13:0 = 15) since the ocr1a then will be double buffered. for generating a waveform output in ctc mode, the oc1a output can be set to to ggle its logical level on each compare match by setting the compare output mode bits to toggle mo de (com1a1:0 = 1). the oc1a value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_oc1a = 1) and oc1ai is set. the waveform generated will have a maximum frequency of f oc1a = f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of opera tion, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 4.13.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm13:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1a/b) is set on the compare match bet ween tcnt1 and ocr1a/b, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual- slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized ex ternal components (coils, capacitors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the count er value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 5, 6, or 7), the value in icr1 (wgm13:0 = 14), or the value in ocr1a (wgm13:0 = 15). the counter is then cleared at the following timer clock cycl e. the timing diagram for the fast pwm mode is shown in figure 4-51 . the figure shows fast pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line mar ks on the tcnt1 slopes represent compare matches between ocr1a/b and tcnt1. the oc1a/b interrupt flag will be set when a compare match occurs. f ocna f clk_i/o 2n 1 ocrna + () ----------------------------------------------------- = r fpwm log top 1 + () log 2 () --------------------------------- =
135 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-51. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the coun ter reaches top. in addition the oc1a or icf1 flag is set at the same timer clock cycle as tov1 is set when either ocr1a or icr1 is used for defining the to p value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1a/b. note that when using fixed top values the unused bits are masked to zero when any of the ocr1a/b registers are written. the procedure for updating icr1 differs from updating ocr1a wh en used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the cu rrent value of tcnt1. the result will then be that the counter will miss the compare match at the top val ue. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the comp are match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. w hen the ocr1a i/o location is written the value written will be put into the ocr1a buffer register. the ocr1a compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcnt1 ma tches top. the update is done at the same timer clock cycle as the tcnt1 is cleared and the tov1 flag is set. using the icr1 register for defining top works well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. ho wever, if the base pwm frequency is actively changed (by changing the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allo w generation of pwm waveforms on the oc1a/b pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pw m output can be generated by setting the com1a/b1:0 to three (see table 4-36 on page 141 ). the actual oc1a/b value will only be visible on the port pin if the data di rection for the port pin is set as output (ddr_oc1a/b) and oc1a/bi is set. the pwm wa veform is generated by setting (or clearing) the oc1a/b register at the compare match between ocr1a/b and tcnt1, an d clearing (or setting) the oc1a/b register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1a/b regi ster represents special cases when g enerating a pwm waveform output in the fast pwm mode. if the ocr1a/b is set equ al to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocr1a/b equal to top will result in a constant high or low output ( depending on the polarity of the output set by the com1a/b1:0 bits). 12345 tcntn (comnx1:0 = 2) ocnxi ocnxi period ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 67 8 (comnx1:0 = 3) f ocnxpwm f clk_i/o n1top + () ----------------------------------- - =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 136 a frequency (with 50% duty cycle) waveform ou tput in fast pwm mode ca n be achieved by setting oc1a to toggle its logical level on each compare match (com1a1:0 = 1). the waveform generated will have a maximum frequency of f oc 1a =f clk_i/o /2 when ocr1a is set to zero (0x0000). this feature is similar to the oc1a toggle in ctc mode, except the double buffer feature of the output compar e unit is enabled in the fast pwm mode. 4.13.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pw m mode (wgm13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the coun ter counts repeatedly from bo ttom (0x0000) to top and then from top to bottom. in non-inverting compare outpu t mode, the output compare (o c1a/b) is cleared on the compare match between tcnt1 and ocr1a/ b while upcounting, and set on the compare match while downcounting. in inverting output compare mode , the operation is inverted. the dual-slope o peration has lower maximum operation frequency than single slope operation. however, due to the symmetr ic feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 1, 2, or 3), the value in icr1 (wgm13:0 = 10), or the value in ocr1a (wgm13:0 = 11). the counter has then reached the top and changes the count direction. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 4-52 . the figure shows phase correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operatio n. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slope s represent compare matches between ocr1a/b and tcnt1. the oc1a/b interrupt flag will be set when a compare match occurs. figure 4-52. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time th e counter reaches bottom. when either ocr1a or icr1 is used for defining the top va lue, the oc1a or icf1 flag is set accord ingly at the same timer clock cycle as the ocr1a/b registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. r pcpwm log top 1 + () log 2 () --------------------------------- = 1 2 34 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnxi ocnxi period tovn interrupt flag set (interrupt on bottom) ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top)
137 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1a/b. note that when using fixed top values, the unused bits are masked to zero when any of the ocr1a/b registers are written. as the third period shown in figure 4-52 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocr1a/b register. since the ocr1 a/b update occurs at top, th e pwm period starts and ends at top. this implies that the length of the falling slope is determined by th e previous top value, while the length of the risi ng slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsy mmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there ar e practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow gener ation of pwm waveforms on the oc1a/b pins. setting the com1a/b1:0 bits to two will produce a non-inverted pwm an d an inverted pwm output can be generated by setting the com1a/b1:0 to three. the actual oc1a/b value will only be visi ble on the port pin if the data direction for the port pin is set as output (ddr_oc1a/b) and oc1a/bi is set. the pwm waveform is generated by setting (or clearing) the oc1a/b register at the compare match between ocr1a/b and tcnt1 when the counter increments, and clearing (or setting) the oc1a/b register at compare match between ocr1 a/b and tcnt1 when the counter decremen ts. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1a/b regi ster represent special cases when gener ating a pwm waveform output in the phase correct pwm mode. if the ocr1a/b is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pw m mode. for inverted pwm the output will have the opposite logic values. 4.13.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm13:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare outpu t mode, the output compare (oc1a/b) is cleared on the compare match between tcnt1 and ocr1a/b while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the ope ration is inverted. the dual-slope operation gives a lower maximum operation frequency compared to the single-slope opera tion. however, due to the sym metric feature of the dual- slope pwm modes, these modes are pref erred for motor control applications. the main difference between the phase co rrect, and the phase and frequency correct pwm mode is the time the ocr1a/b register is updated by the ocr1a/b buffer register, (see figure 4-52 on page 136 and figure 4-53 on page 138 ). the pwm resolution for the phase and frequency correct pw m mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incr emented until the counter value matches either the value in icr1 (wgm13:0 = 8), or the value in ocr1a (wgm13:0 = 9). the counter has then reached the top and changes the count direction. the tcnt1 value will be equal to top for o ne timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 4-53 . the figure shows phase and frequency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted a nd inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare ma tches between ocr1a/b and tcnt1. the oc1a/b interrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2ntop ------------------------------ - = r pfcpwm log top 1 + () log 2 () --------------------------------- =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 138 figure 4-53. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set at the sa me timer clock cycle as the ocr1 a/b registers ar e updated with the double buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1a/b. as figure 4-53 shows the output generated is, in c ontrast to the phase correct mode, symmetrical in all periods. since the ocr1a/b registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top works well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. ho wever, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare unit s allow generation of pwm waveforms on the oc1a/b pins. setting the com1a/b1:0 bits to two will produce a non-inve rted pwm and an inverted pwm output can be generated by setting the com1a/b1:0 to three (see table on page 142 ). the actual oc1a/b value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1a/b) and oc1a/bi is set. the pwm waveform is generated by setting (or clearing) the oc1a/b register at the comp are match between ocr1a/b and tcnt1 when the counter increments, and clearing (or setting) the oc1a/b regist er at compare match between ocr1a/b and tcnt1 when the counter decrements. the pwm frequency for the output when using phase and frequ ency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1a/b regi ster represents special cases when g enerating a pwm waveform output in the phase correct pwm mode. if the ocr1a/b is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non-inverted pwm mo de. for inverted pwm the output will have the opposite logic values. 1 2 34 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnxi ocnxi period ocna interrupt flag set or icfn interrupt flag set (interrupt on top) ocrnx/ top update and tovn interrupt flag set (interrupt on bottom) f ocnxpfcpwm f clk_i/o 2ntop ------------------------------ - =
139 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.10 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when inte rrupt flags are set, and when the ocr1a/b register is updated with the ocr1a/b buffer value (only for modes utilizing double buffering). figure 4-54 shows a timing diagram for the setting of ocf1a/b. figure 4-54. timer/counter timing diagram, setting of ocf1a/b, no prescaling figure 4-55 shows the same timing data, but with the prescaler enabled. figure 4-55. timer/counter timing diagram, setting of ocf1a/b, with prescaler (f clk_i/o /8) ocrnx - 1 clk i/o (clk i/o /1) tcntn ocrnx ocfnx clk tn ocrnx ocrnx value ocrnx + 1 ocrnx + 2 ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 140 figure 4-56 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocr1a/b register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renamin g applies for modes that set the tov1 flag at bottom. figure 4-56. timer/counter timing diagram, no prescaling figure 4-57 shows the same timing data, but with the prescaler enabled. figure 4-57. timer/counter timi ng diagram, with prescaler (f clk_i/o /8) top - 1 clk i/o (clk i/o /1) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn top old ocrnx value new ocrnx value bottom bottom + 1 top - 1 top top -1 top -2 top - 1 top bottom bottom + 1 top - 1 top top - 1 top - 2 clk i/o (clk i/o /8) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn old ocrnx value new ocrnx value
141 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.11 16-bit timer/counter register description 4.13.11.1 timer/counter1 control register a ? tccr1a ? bit 7:6 ? com1a1:0: compare output mode for channel a ? bit 5:4 ? com1b1:0: compare output mode for channel b the com1a1:0 and com1b1:0 control the output compare pins (oc1ai and oc1bi respectively) behavior. if one or both of the com1a1:0 bits are written to one, th e oc1ai output overrides the normal port fu nctionality of the i/o pin it is connected to. if one or both of the com1b1:0 bit are written to one, the oc1bi output overrides the normal port functionality of the i/o pin it is connected to. however, note t hat the data direction register (ddr) bit and oc1xi bit (tccr1d) corresponding to the oc1ai or oc1bi pin must be set in order to enable the output driver. when the oc1ai or oc1bi is connected to the pin, the functi on of the com1a/b1:0 bits is dependent of the wgm13:0 bits setting. table 4-35 shows the com1a/b1:0 bit functionality when the wgm13:0 bits are set to a normal or a ctc mode (non-pwm). table 4-36 shows the com1a/b1:0 bit functionality when the wgm13:0 bits are set to the fast pwm mode. bit 76543210 com 1 a1 com 1 a0 com 1 b1 com 1 b0 ? ? wgm 1 1wgm 1 0 tccr 1 a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-35. compare output mode, non-pwm oc1ai oc1bi com1a1 com1b1 com1a0 com1b0 description 0 x x normal port operation, oc1a/oc1b disconnected. 1 0 0 0 1 toggle oc1a/oc1b on compare match. 1 0 clear oc1a/oc1b on compare match (set output to low level). 1 1 set oc1a/oc1b on compare match (set output to high level). table 4-36. compare output mode, fast pwm (1) oc1ai oc1bi com1a1 com1b1 com1a0 com1b0 description 0 x x normal port operation, oc1a/oc1b disconnected. 1 0 0 1 0 1 wgm13=0: normal port operation, oc1a/oc1b disconnected. wgm13=1: toggle oc1a on compare match, oc1b reserved. 1 1 0 clear oc1a/oc1b on compare match set oc1a/oc1b at top 1 1 1 set oc1a/oc1b on compare match clear oc1a/oc1b at top note: 1. a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. in this case the com- pare match is ignored, but the set or clear is done at top. see section 4.13.9.3 ?fast pwm mode? on page 134 for more details.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 142 table 4-37 shows the com1a/b1:0 bit functionalit y when the wgm13:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. ? bit 3:2 ? reserved bits these bits are reserved for future use. ? bit 1:0 ? wgm11:0: waveform generation mode combined with the wgm13:2 bits found in the tccr1b register, t hese bits control the counting sequence of the counter, the source for maximum (top) counter value, and w hat type of waveform generation to be used, see table 4-38 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear ti mer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes (see section 4.13.9 ?modes of operation? on page 133 ). table 4-37. compare output mode, phase correct and phase and frequency correct pwm (1) oc1ai oc1bi com1a1 com1b1 com1a0 com1b0 description 0 x x normal port operation, oc1a/oc1b disconnected. 1 0 0 1 0 1 wgm13=0: normal port operation, oc1a/oc1b disconnected. wgm13=1: toggle oc1a on compare match, oc1b reserved. 1 1 0 clear oc1a/oc1b on compare match when up-counting. set oc1a/oc1b on compare match when downcounting. 1 1 1 set oc1a/oc1b on compare match when up-counting. clear oc1a/oc1b on compare match when downcounting. note: 1. a special case occurs when oc1a/oc1b equals top and com1a1/com1b1 is set. see section 4.13.9.4 ?phase correct pwm mode? on page 136 for more details. table 4-38. waveform generati on mode bit description (1) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1a/b at tov1 flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocr1a immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 8 1 0 0 0 pwm, phase and frequency correct icr1 bottom bottom 9 1 0 0 1 pwm, phase and frequency correct ocr1a bottom bottom 10 1 0 1 0 pwm, phase correct icr1 top bottom 11 1 0 1 1 pwm, phase correct ocr1a top bottom 12 1 1 0 0 ctc icr1 immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icr1 top top 15 1 1 1 1 fast pwm ocr1a top top note: 1. the ctc1 and pwm11:0 bit definition names are obsolete. use the wgm 12:0 definitions. however, the functionality and location of these bits are compatib le with previous versions of the timer.
143 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.11.2 timer/counter1 control register b ? tccr1b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capture noise cancel er. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) t hat is used to trigger a capture event. when the ices1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices1 bit is written to one, a rising (positive) ed ge will trigger the capture. when a capture is triggered according to the ices1 setting, the counter value is copied into the input capture register (icr1). the event will also set the input ca pture flag (icf1), and this can be used to cause an input capture interrupt, if thi s interrupt is enabled. when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequent ly the input capture f unction is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibilit y with future devices, this bit must be written to zero when tccr1b is written. ? bit 4:3 ? wgm13:2: waveform generation mode see tccr1a register description. ? bit 2:0 ? cs12:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 4-54 on page 139 and figure 4-55 on page 139 . if external pin modes are used for the timer/counter1, transit ions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. bit 7654 3210 icnc 1 ices 1 ?wgm 1 3wgm 1 2cs 1 2cs 1 1cs 1 0tccr 1 b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-39. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk i/o /1 (no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 144 4.13.11.3 timer/counter1 control register c ? tccr1c ? bit 7 ? foc1a: force output compare for channel a ? bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm13:0 bits specifies a non-pwm mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccr1a is written when operating in a pwm mode. when writing a logical one to the foc1a/foc1b bit, an imm ediate compare match is forced on the waveform generation unit. the oc1nx output is changed according to its com1a/b1:0 and oc1nx bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value present in the com1a/b1:0 bits that determine the effect of the forced compare. a foc1a/foc1b strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. 4.13.11.4 timer/counter1 control register d ? tccr1d ? bit 7:4 ? oc1bi: output compare pin enable for channel b the oc1bi bits enable the output compare pins of channel b as shown in figure 4-49 on page 132 . ? bit 3:0 ? oc1ai: output compare pin enable for channel a the oc1ai bits enable the output compare pins of channel a as shown in figure 4-49 on page 132 . 4.13.11.5 timer/counter1 ? tcnt1h and tcnt1l the two timer/counter i/o locations (tcnt1h and tcnt1l, combi ned tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both th e high and low bytes are read and written simultaneously when the cpu accesses thes e registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-b it registers. see section 4.13.3 ?accessing 16-bit registers? on page 123 . modifying the counter (tcnt1) while the counter is running introduces a risk of missing a compare match between tcnt1 and one of the ocr1a/b registers. writing to the tcnt1 register blocks (r emoves) the compare match on the follo wing timer clock for all compare units. bit 7654 3210 foc 1 afoc 1 b?? ????tccr 1 c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 7654 3210 oc 1 bx oc 1 bw oc 1 bv oc 1 bu oc 1 ax oc 1 aw oc 1 av oc 1 au tccr 1 d read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 tcnt 1 [15:8] tcnt 1 h tcnt 1 [7:0] tcnt 1 l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
145 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.13.11.6 output compare register a ? ocr1ah and ocr1al 4.13.11.7 output compare register b ? ocr1bh and ocr1bl the output compare registers contain a 16 -bit value that is continuously compar ed with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1a/b pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by al l the other 16-bit registers. see section 4.13.3 ?accessing 16-bit registers? on page 123 . 4.13.11.8 input capture register ? icr1h and icr1l the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/co unter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously when the cpu accesses these registers, th e access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all th e other 16-bit registers. see section 4.13.3 ?accessing 16-bit registers? on page 123 . 4.13.11.9 timer/counter1 interrupt mask register ? timsk1 ? bit 7..6 ? reserved bits these bits are reserved for future use. ? bit 5 ? icie1: input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector (see section 4.8.1 ?innterrupt vectors in atmel attiny87/167? on page 76 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4..3 ? reserved bits these bits are reserved for future use. bit 76543210 ocr 1 a[15:8] ocr 1 ah ocr 1 a[7:0] ocr 1 al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr 1 b[15:8] ocr 1 bh ocr 1 b[7:0] ocr 1 bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr 1 [15:8] icr 1 h icr 1 [7:0] icr 1 l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? icie 1 ??ocie 1 bocie 1 atoie 1 timsk 1 read/write r r r/w r r r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 146 ? bit 2 ? ocie1b: output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector (see section 4.8.1 ?innterrupt vectors in atmel attiny87/167? on page 76 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector (see section 4.8.1 ?innterrupt vectors in atmel attiny87/167? on page 76 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see section 4.8.1 ?innterrupt vectors in atmel attiny87/167? on page 76 ) is executed when the tov1 flag, located in tifr1, is set. 4.13.11.10timer/counter1 interrupt flag register ? tifr1 ? bit 7..6 ? reserved bits these bits are reserved for future use. ? bit 5 ? icf1: input capture flag this flag is set when a capture event oc curs on the icp1 pin. when the input capt ure register (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4..3 ? reserved bits these bits are reserved for future use. ? bit 2 ? ocf1b: output compare b match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the ou tput compare match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: output compare a match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the ou tput compare match a interrupt vector is executed. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter overflow flag the setting of this flag is dependent of the wgm13:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 4-38 on page 142 for the tov1 flag behavior when using another wgm13:0 bit setting. tov1 is automatically cleared when the ti mer/counter1 overflow inte rrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 ??icf 1 ??ocf 1 bocf 1 atov 1 tifr 1 read/write r r r/w r r r/w r/w r/w initial value00000000
147 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.14 spi - serial peripheral interface the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the atmel ? attiny87/167 and peripheral devices or between several avr ? devices. the atmel attiny87/167 spi includes the following features: 4.14.1 features full-duplex, three-wire synchronous data transfer master or slave operation lsb first or msb first data transfer seven programmable bit rates end of transmission interrupt flag write collision flag protection wake-up from idle mode double speed (ck/2) master spi mode figure 4-58. spi block diagram (1) note: 1. refer to table 4-24 on page 92 for spi pin placement. 8-bit shift register read data buffer spi control register spi status register mstr spi clock (master) spe spi control spi interrupt request select clock logic miso clock 8 88 s m s m m s msb lsb spie spe wcol spif spi2x spi2x spr1 mstr spe dord spr0 dord mstr cpol cpha spr1 spr0 mosi sck ss divider /2/4/8/16/32/64/128 clk i/o internal data bus pin control logic
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 148 the interconnection between master and slave cpus with spi is shown in figure 4-59 . the system consists of two shift registers, and a master clock generator. the spi master initiates t he communication cycle when pulling low the slave select ss pin of the desired slave. master and slav e prepare the data to be sent in their re spective shift regist ers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? sl ave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi in terface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shif ting one byte, the spi clock generator stops, setti ng the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift t he next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be ke pt in the buffer register for later use. when configured as a slave, the spi interface will rema in sleeping with miso tri- stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr r egister is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr befor e reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 4-59. spi master-slave interconnection the system is single buffered in the transmi t direction and double buffered in the receive directio n. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is co mpleted. when receiving data, however, a received character must be read from the spi dat a register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming si gnal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. when the spi is enabled, the data dire ction of the mosi, miso, sck, and ss pins is overridden according to table 4-40 . for more details on automatic port overrides, refer to section 4.10.3 ?alternate po rt functions? on page 89 . table 4-40. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input note: 1. see section 4.10.3.4 ?alternate func tions of port b? on page 97 for a detailed description of how to define the direction of the user defined spi pins. lsb slave msb 8 bit shift register lsb shift enable master msb ss sck ss sck mosi mosi miso miso 8 bit shift register spi clock generator
149 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by the actual dat a direction register contro lling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by t he actual data direction bits for these pi ns. e.g. if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 150 the following code examples show how to initialize the spi as a slave and how to perform a simple reception. assembly code example (1) spi_slaveinit: ; set miso output, all others input ldi r17,(1< 151 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.14.2 ss pin functionality 4.14.2.1 slave mode when the spi is configured as a slave, the slave select (ss) pin is always input. when ss is held low, the spi is activated, and miso becomes an output if configured so by the user. all other pins are inputs. when ss is driven high, all pins are inputs, and the spi is passive, which means that it will not re ceive incoming data. note that the spi logic will be reset once the ss pin is driven high. the ss pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. when the ss pin is driven high, the spi slave will immediat ely reset the send and receive logic, and drop any partially received data in the shift register. 4.14.2.2 master mode when the spi is configured as a master (mstr in spcr is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general output pin which does not affect the spi system. typically, the pin will be driving the ss pin of the spi slave. if ss is configured as an input, it must be hel d high to ensure master spi operation. if the ss pin is driven low by peripheral circuitry when the spi is conf igured as a master with the ss pin defined as an input, the spi system interprets this as another master select ing the spi as a slave and starting to send data to it. to avoid bu s contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi system becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set, and if t he spi interrupt is enabled, and the i-bit in sreg is set, the interrupt routine will be executed. thus, when interrupt-driven spi transmission is used in master mode, and there exis ts a possibility that ss is driven low, the interrupt should always check that the mstr bit is still set. if the mstr bit has been cleared by a slave select, it must be se t by the user to re-enable spi master mode. 4.14.2.3 spi control register ? spcr ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled . this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the l sb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode wh en written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be clea red, and spif in spsr will become set. the user will then have to set mstr to re-enab le spi master mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. wh en cpol is written to zero, sck is low when idle. refer to figure 4-60 on page 154 and figure 4-61 on page 154 for an example. the cpol functionality is summarized below: bit 76543210 spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 152 ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 4-60 and figure 4-61 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io frequency f clkio is shown in the following table. table 4-41. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 4-42. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 4-43. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 0 0 0 f clkio / 4 0 0 1 f clkio / 16 0 1 0 f clkio / 64 0 1 1 f clkio / 128 1 0 0 f clkio / 2 1 0 1 f clkio / 8 1 1 0 f clkio / 32 1 1 1 f clkio / 64
153 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.14.2.4 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an in terrupt is generated if spie in spcr is set and global interrupt s are enabled. if ss is an input and is driven low when the spi is in ma ster mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif se t, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is writte n during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi stat us register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the atmel ? attiny87/167 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck fr equency) will be doubled when the spi is in master mode (see table 4-43 ). this means that the minimum sck period will be two cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the atmel attiny87/167 is also used fo r program memory and eeprom downloading or uploading. see section 4.22.8 ?serial downloading? on page 233 for serial programmi ng and verification. 4.14.2.5 spi data register ? spdr ? bits 7:0 - spd7:0: spi data the spi data register is a read/ write register used for data transfer between th e register file and the spi shift register. wri ting to the register initiates data transmission. reading the regi ster causes the shift register receive buffer to be read. 4.14.3 data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 4-60 and figure 4-61 on page 154 . data bits are shifted out and latched in on opposite edges of the sck signal, ensuring sufficient time for data signals to stabilize. this is clearly seen by summarizing table 4-41 on page 152 and table 4-42 on page 152 , as done below. bit 76543210 spifwcol?????spi2xspsr read/write r r r rrrrr/w initial value00000000 bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxu ndefined table 4-44. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 154 figure 4-60. spi transfer format with cpha = 0 figure 4-61. spi transfer format with cpha = 1 lsb msb bit 1 bit 6 bit 2 bit 5 bit 3 bit 4 bit 4 bit 3 bit 5 bit 2 bit 6 bit 1 msb lsb msb first (dord = 0) lsb first (dord =1) sck (cpol = 0) mode 0 sck (cpol = 1) mode 2 ss sample i mosi/miso change 0 mosi pin change 0 miso pin lsb msb bit 1 bit 6 bit 2 bit 5 bit 3 bit 4 bit 4 bit 3 bit 5 bit 2 bit 6 bit 1 msb lsb msb first (dord = 0) lsb first (dord =1) sck (cpol = 0) mode 1 sck (cpol = 1) mode 3 ss sample i mosi/miso change 0 mosi pin change 0 miso pin
155 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.15 usi ? universal serial interface 4.15.1 features two-wire synchronous data transfer (master or slave) three-wire synchronous data transfer (master or slave) data received interrupt wake-up from idle mode in two-wire mode: wake-up from all sleep modes, including power-down mode two-wire start condition detector with interrupt capability 4.15.2 overview the universal serial interface, or usi, provides the basic hardware resources needed for serial communication. combined with a minimum of control software, the usi allows signific antly higher transfer rates and uses less code space than solutions based on software only. interrupts are included to minimize the processor load. a simplified block diagram of the usi is shown on figure 4-62 . cpu accessible i/o registers, in cluding i/o bits and i/o pins, are shown in bold. the device- specific i/o register and bi t locations are listed in the section 4.15.5 ?register descriptions? on page 161 . figure 4-62. universal serial interface, block diagram the 8-bit usi data register is directly accessible via the data bus and contains the incoming and outgoing data. the register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. the usi data register is a serial shift register and the most signific ant bit that is the output of the serial sh ift register is connected to one of two o utput pins depending of the wire mode configur ation. a transparent latch is inserted between the usi data register output and output pin, which delays the change of data output to the opposite clock edge of the data input samp ling. the serial input is always sampled from the data input (di) pin independent of the configuration. the 4-bit counter can be both read and wri tten via the data bus, and can generate an overflow interrupt. both the usi data register and the counter are clocked simultaneously by the same clock source. this allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. note that when an external clock source is selected the counter counts both clock edges. in this case the counter counts the number of edges, and not the number of bits. the clock can be selected from three different sources: the usck pin, timer/counter0 compare match or from software. q 3 2 1 0 le 2 usidr d tim0 comp usck/ scl two-wire clock control unit clock hold [1] bit0 bit7 usisif usioif usipf usidc usidb usisr 4-bit counter di/ sda do (output only) (input/ open drain)) (input/ open drain)) 3 2 1 0 1 0 usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr data bus
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 156 the two-wire clock control unit can generate an interrupt when a start condition is detected on t he two-wire bus. it can also generate wait states by holding the cloc k pin low after a start condition is de tected, or after the counter overflows. 4.15.3 functional descriptions 4.15.3.1three-wire mode the usi three-wire mode is compliant to the serial peripheral interface (spi) mode 0 and 1, but does not have the slave select (ss ) pin functionality. however, this feature can be implem ented in software if necessary. pin names used by this mode are: di, do, and usck. figure 4-63. three-wire mode op eration, simplified diagram figure 4-63 shows two usi units operating in three-wire mode, one as master and one as slave. the two usi data register are interconnected in such way that afte r eight usck clocks, the data in each re gister are interchanged. the same clock also increments the usi?s 4-bit counter. the counter overflow (i nterrupt) flag, or usioif, can therefore be used to determine when a transfer is completed. the clock is generated by the ma ster device software by toggling the usck pin via the port register or by writing a on e to the usitc bit in usicr. figure 4-64. three-wire mode, timing diagram bit7 di usck usck do portxn slave bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 di do master bit6 bit5 bit4 bit3 bit2 bit1 bit0 12 6 msb 54321lsb 345678 6 msb cycle (reference) usck usck 54321lsb a b c d e di do
157 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the three-wire mode timing is shown in figure 4-64 on page 156 at the top of the figure is a usck cycle reference. one bit is shifted into the usi data r egister (usidr) for each of these cycles. the us ck timing is shown for both external clock modes. in external clock mode 0 (usics0 = 0), di is sampled at positive edges, and do is changed (data r egister is shifted by one) at negative edges. external clock mode 1 (usics0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. the usi clock modes corresponds to the spi data mode 0 and 1. referring to the timing diagram ( figure 4-64 on page 156 ), a bus transfer involves the following steps: 1. the slave device and master device sets up its data out put and, depending on the protocol used, enables its out- put driver (mark a and b). the output is set up by writ ing the data to be transmitted to the usi data register. enabling of the output is done by setting the corresponding bit in the port data direction register. note that point a and b does not have any specific order, but both must be at least one half usck cycle before point c where the data is sampled. this must be done to ensure that the da ta setup requirement is sati sfied. the 4-bit counter is reset to zero. 2. the master generates a clock pulse by software toggli ng the usck line twice (c and d). the bit value on the slave and master?s data input (di) pin is sampled by th e usi on the first edge (c), and the data output is changed on the opposite edge (d). the 4-bi t counter will count both edges. 3. step 2. is repeated eight times for a complete register (byte) transfer. 4. after eight clock pulses (i.e., 16 clock edges) the counter wil l overflow and indicate that the transfer is completed. the data bytes transferred must now be processed before a new transfer can be initiated. the overflow interrupt will wake up the processor if it is set to idle mode. dep ending of the protocol used t he slave device can now set its output to high impedance. 4.15.3.2 spi master operation example the following code demonstrates how to use the usi module as a spi master: spitransfer: sts usidr,r16 ldi r16,(1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 158 the following code demonstrates how to use the usi mo dule as a spi master with ma ximum speed (fsck = fck/4): spitransfer_fast: sts usidr,r16 ldi r16,(1< 159 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.15.3.4 two-wire mode the usi two-wire mode is compliant to the inter ic (twi) bus protocol, but without slew rate limiting on outputs and input noise filtering. pin names used by this mode are scl and sda. figure 4-65. two-wire mode operation, simplified diagram figure 4-65 shows two usi units operating in two-wire mode, one as ma ster and one as slave. it is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. the main differences between the master and slave ope ration at this level, is the serial clock gene ration which is always done by the master, and only the slave uses the clock control unit. clock generation must be implemented in software, but the shift operation is done automatically by both devices. no te that only clocking on negative edge for shifti ng data is of practical use in this mode. the slave can insert wait states at start or e nd of transfer by forcing the scl clock low. this means that the master must always check if the scl line was actually released after it has generated a positive edge. since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. the clock is generated by the master by togg ling the usck pin via the port register. the data direction is not given by the physical layer. a prot ocol, like the one used by the tw i-bus, must be implemented to control the data flow. figure 4-66. two-wire mode, typical timing diagram bit7 sda scl hold scl slave bit6 bit5 bit4 bit3 bit2 bit1 bit0 two-wire clock control unit vcc bit7 sda scl master bit6 bit5 bit4 bit3 bit2 bit1 bit0 portxn 1 to 7 8 s address r/w ack data ack ack data 1 to 8 9 1 to 8 9 9 a b c d e f sda scl p
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 160 referring to the timing diagram ( figure 4-66 on page 159 ), a bus transfer involves the following steps: 1. the a start condition is generated by the master by fo rcing the sda low line while the scl line is high (a). sda can be forced low either by writing a zero to bit 7 of the shift register, or by setting the corresponding bit in the port register to zero. note that th e usi data register bit must be set to one for the output to be enabled. the slave device?s start detector logic ( figure 4-67 ) detects the start condition and se ts the usisif flag. the flag can generate an interrupt if necessary. 2. in addition, the start detector will hold the scl line lo w after the master has forced an negative edge on this line (b). this allows the slave to wake up from sleep or comp lete its other tasks before sett ing up the usi data register to receive the address. this is done by cleari ng the start condition flag and reset the counter. 3. the master set the first bit to be transferred and releases the scl line (c). the slave samples the data and shift it into the usi data register at the positive edge of the scl clock. 4. after eight bits are transferred containing slave address and data direction (read or wr ite), the slave counter over- flows and the scl line is forced low (d). if the slave is not the one the master has addr essed, it releases the scl line and waits for a new start condition. 5. if the slave is addressed it holds the sda line low du ring the acknowledgment cycle before holding the scl line low again (i.e., the counter register must be set to 14 be fore releasing scl at (d)). depending of the r/w bit the master or slave enables its output. if the bit is set, a ma ster read operation is in progr ess (i.e., the slave drives the sda line) the slave can hold the scl line low after the acknowledge (e). 6. multiple bytes can now be transmitted, all in same directio n, until a stop condition is gi ven by the master (f). or a new start condition is given. if the slave is not able to receive more data it does not ackn owledge the data byte it has last received. when the master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. figure 4-67. start condition detector, logic diagram 4.15.3.5 start condition detector the start condition detector is shown in figure 4-67 the sda line is delayed (in the range of 50 to 300ns) to ensure valid sampling of the scl line. the start condition de tector is only enabled in two-wire mode. the start condition detector is working asynchronously and ca n therefore wake up the processor from the power-down sleep mode. however, the protocol us ed might have restrictions on the scl hold time. therefore, when using this feature in this case the oscillator start-up time set by the cksel fuses (see section 4.5.1 ?clock systems and their distribution? on page 46 ) must also be taken into the consideration. refe r to the usisif bit descrip tion for further details. 4.15.4 alternative usi usage when the usi unit is not used fo r serial communication, it can be set up to do alternative ta sks due to its flexible design. 4.15.4.1 half-duplex asynchronous data transfer by utilizing the usi data register in th ree-wire mode, it is possible to implement a more compact and higher performance uart than by software only. 4.15.4.2 4-bit counter the 4-bit counter can be used as a stand-alo ne counter with overflow interrupt. note t hat if the counter is clocked externally, both clock edges will generate an increment. q sda scl write (usisif) d clr q d usisif clock hold clr
161 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.15.4.3 12-bit timer/counter combining the usi 4-bit counter and timer/counter0 allows them to be used as a 12-bit counter. 4.15.4.4 edge triggere d external interrupt by setting the counter to maximum value (f) it can function as an additional external interrupt. the overflow flag and interrup t enable bit are then used for the external interrupt . this feature is selected by the usics1 bit. 4.15.4.5 software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 4.15.5 register descriptions 4.15.5.1 usidr ? usi data register ? bits 7:0 ? usid7..0: usi data when accessing the usi data register (usidr) the serial regist er can be accessed directly. if a serial clock occurs at the same cycle the register is written, the re gister will contain the value written and no shift is performed. a (left) shift opera tion is performed depending of the usics1..0 bits setting. the shift operation can be cont rolled by an external clock edge, by a timer/counter0 compare matc h, or directly by software using the usiclk st robe bit. note that even when no wire mode is selected (usiwm1..0 = 0) both the external data input (di/sda) and the external clock input (usck/scl) can still be used by the usi data register. the output pin in use, do or sda depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the data register. the output latch is open (transparent) du ring the first half of a serial clock cycle when an exte rnal clock source is selected (usics1 = 1), and constantly open w hen an internal clock source is used (usics1 = 0). the output will be changed immediately when a new msb written as long as the latch is open. the latch ensures that data input is sampled and data output is changed on opposite clock edges. note that the corresponding data direction regi ster to the pin must be set to one fo r enabling data output from the usi data register. 4.15.5.2 usibr ? usi buffer register ? bits 7:0 ? usi d 7..0: usi buffer the content of the serial register is l oaded to the usi buffer register when the transfer is completed, and instead of accessing the usi data register (the serial register) the usi data buffer can be accessed when the cpu reads the received data. this gives the cpu time to handle other program tasks too as the controlling of the usi is not so timing critical. the us i flags as set same as when reading the usidr register. bit 7 6 5 4 3 2 1 0 usid7 usid6 usid5 usid4 usid3 usid2 usid1 usid0 usidr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 usib7 usib6 usib5 usib4 usib3 usib2 usib1 usib0 usibr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 162 4.15.5.3 usisr ? usi status register the status register contains interrupt flags, line status flags and the counter value. ? bit 7 ? usisif: start condition interrupt flag when two-wire mode is selected, the usisif flag is set (t o one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 11 b & usiclk = 0) or (usics = 10 b & usiclk = 0), any edge on the sck pin sets the flag. an interrupt will be generated when the fl ag is set while the usisie bit in usi cr and the global interrupt enable flag are set. the flag will only be cleared by writing a logical one to the us isif bit. clearing this bit will release the start detection ho ld of uscl in two-wire mode. a start condition interrupt will wake up the processor from all sleep modes. ? bit 6 ? usioif: counter overflow interrupt flag this flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). an interrupt will be generated when the flag is set while the usioie bit in usicr and the global in terrupt enable flag are set. the flag will only be cleared if a one is written to the usioif bit. clearing this bit will rele ase the counter overflow hold of scl in two-wire mode. a counter overflow interrupt will wake up the processor from idle sleep mode. ? bit 5 ? usipf: stop condition flag when two-wire mode is selected, the usipf flag is set (one) when a stop condition is detected. the flag is cleared by writing a one to this bit. note that this is not an interrupt flag. this signal is useful when implementing two-wire bus master arbitration. ? bit 4 ? usidc: data output collision this bit is logical one when bit 7 in the usi data register di ffers from the physical pin value. the flag is only valid when tw o- wire mode is used. this signal is useful when implementing two-wire bus master arbitration. ? bits 3:0 ? usicnt3. .0: counter value these bits reflect the current 4-bit count er value. the 4-bit counter value can di rectly be read or written by the cpu. the 4-bit counter increments by one for each clock generat ed either by the external clock edge detector, by a timer/counter0 compare matc h, or by software using usiclk or usitc strobe bits. the clock source depends of the setting of the usics1..0 bits. for external clock operation a special f eature is added that allows the cl ock to be generated by writing to the usitc strobe bit. this feature is enabled by write a one to the usic lk bit while setting an external clock source (usics1 = 1). note that even when no wire mode is selected (usiwm1..0 = 0) the external clock input (usck/scl) are can still be used by the counter. bit 7 6 5 4 3 2 1 0 usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 usisr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
163 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.15.5.4 usicr ? us i control register the control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe. ? bit 7 ? usisie: start condition interrupt enable setting this bit to one enables the start condition detector inte rrupt. if there is a pending inte rrupt when the usisie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the usisif bit description for further details. ? bit 6 ? usioie: counter overflow interrupt enable setting this bit to one enables the counter overflow interrupt. if there is a pending interrupt when the usioie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the usioif bit description on page 162 for further details. ? bit 5:4 ? usiwm1:0: wire mode these bits set the type of wire mode to be used. basically only the function of the outputs are affected by these bits. data and clock inputs are not affected by the mode selected and wil l always have the same function. the counter and usi data register can therefore be cl ocked externally, and data input sampled, ev en when outputs are disabled. the relations between usiwm1:0 and the usi operation is summarized in table 4-45 on page 164 . bit 7 6 5 4 3 2 1 0 usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr read/write r/w r/w r/w r/w r/w r/w w w initial value 0 0 0 0 0 0 0 0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 164 ? bit 3:2 ? usics1:0: clock source select these bits set the clock source for the usi data register and counter. the data output latc h ensures that the output is changed at the opposite edge of the sampling of the data in put (di/sda) when using exter nal clock source (usck/scl). when software strobe or timer/counter0 compare match clock option is selected, the out put latch is transparent and therefore the output is changed immediately. clearing the usics1:0 bits enables software strobe option. when using this option, writing a one to the usiclk bi t clocks both the usi data register and the counter. for external clock source (usics1 = 1), the usiclk bit is no longer used as a strobe, but selects between external clocking and software clocking by the usitc strobe bit. table 4-46 shows the relationship between the usics1..0 and us iclk setting and clock source used for the usi data register and the 4-bit counter. table 4-45. relations between us iwm1..0 and the usi operation usiwm1 usiwm0 description 0 0 outputs, clock hold, and start detector disabled. port pins operates as normal. 0 1 three-wire mode. uses do , di, and usck pins. the data output (do) pin overrides the corresponding bi t in the port register in this mode. however, the corresponding ddr bit still controls the da ta direction. when the port pin is set as input the pins pull-up is controlled by the port bit. the data input (di) and serial clock (usck) pins do not affect the normal port operation. when operating as master, clock pulses are software gen erated by toggling the port register, while the data direction is set to output. the usitc bit in the usicr register can be used for this purpose. 1 0 two-wire mode. uses sda (di) and scl (usck) pins (1) . the serial data (sda) and the serial clock (scl) pins are bi-directional and uses open-collector output drives. the output drivers are enabled by se tting the corresponding bit for sda and scl in the ddr register. when the output driver is enabled for the sda pin, the output driver will force the line sda low if the output of the usi data register or the corresponding bit in the port register is zero. otherwise the sda line will not be driven (i.e., it is released). w hen the scl pin output driver is enabled the scl line will be forced low if the corresponding bit in the po rt register is zero, or by the start detector. otherwise the scl line will not be driven. the scl line is held low when a start detector detects a start condition and the output is enabled. clearing the start condition flag (usisif) releas es the line. the sda and scl pin inputs is not affected by enabling this mode. pull-ups on the sda and scl port pin are disabled in two-wire mode. 1 1 two-wire mode. uses sda and scl pins. same operation as for the two-wire mode described above, except that the scl line is also held low when a counter overflow occurs, and is held low unt il the counter overflow flag (usioif) is cleared. note: 1. the di and usck pins are renamed to serial data (s da) and serial clock (scl) respectively to avoid confu- sion between the modes of operation. table 4-46. relations between the usics1..0 and usiclk setting usics1 usics0 usiclk usi data register clock source 4-bit counter clock source 0 0 0 no clock no clock 0 0 1 software clock strobe (usiclk) software clock strobe (usiclk) 0 1 x timer/counter0 compare match timer/counter0 compare match 1 0 0 external, positive edge external, both edges 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge software clock strobe (usitc) 1 1 1 external, negative edge software clock strobe (usitc)
165 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 1 ? usiclk: clock strobe writing a one to this bit location strobes the usi data register to shift one step and the counter to increment by one, provide d that the usics1..0 bits are set to zero and by doing so th e software clock strobe option is selected. the output will change immediately when the clock strobe is execut ed, i.e., in the same instruction cycle. th e value shifted into the usi data registe r is sampled the previous instruction cycle. the bit will be read as zero. when an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. setting the usiclk bit in this case will select the usitc strobe bit as clock source for the 4-bit counter (se e table 4-46 on page 164 ). ? bit 0 ? usitc: toggle clock port pin writing a one to this bit location toggles the usck/scl value eit her from 0 to 1, or from 1 to 0. the toggling is independent of the setting in the data direction register, but if the port value is to be shown on the pin the ddb2 must be set as output (to one). this feature allows easy clock generation when implementing master devices. the bit will be read as zero. when an external clock source is selected (usics1 = 1) and the usiclk bit is set to one, writ ing to the usitc strobe bit will directly clock the 4-bit counter. this allows an early detect ion of when the transfer is do ne when operating as a master device. 4.15.5.5 usipp ? usi pin position ? bits 7:1 ? res: reserved bits these bits are reserved bits in the atmel ? attiny87/167 and always reads as zero. ? bit 0 ? usipos: usi pin position setting or clearing this bit changes the usi pin position. bit 76543210 -------usiposusipp read/write r r rrrrrr/w initial value00000000 table 4-47. usi pin position usipos usi pin position 0 portb (default) di, sda pb0 - (pcint8/oc1au) do pb1 - (pcint9/oc1bu) usck, scl pb2 - (pcint10/oc1av) 1 port a (alternate) di, sda pa4 - (pcint4/adc4/icp1/mosi) do pa2 - (pcint2/adc2/oc0a/miso) usck, scl pa5 - (pcint5/adc5/t1/sck)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 166 4.16 lin/uart - local interconnect network controller or uart the lin (local interconnect network) is a serial communications protocol which efficiently supports the control of mechatronics nodes in distribute d automotive applications. the main properties of the lin bus are: single master with multiple slaves concept low cost silicon implementation bas ed on common uart/sci interface self synchronization with on-chip oscillator in slave node deterministic signal transmission with signal propagation time computable in advance low cost single-wire implementation speed up to 20kbit/s. lin provides a cost efficient bus communication where th e bandwidth and versatility of can are not required. the specification of the line dr iver/receiver needs to match the iso9141 nrz-standard. if lin is not required, the controller alternatively can be programmed as universal asynchronous serial receiver and transmitter (uart). 4.16.1 lin features hardware implementation of lin 2.1 (lin 1.3 compatibility) small, cpu efficient and independent ma ster/slave routines based on ?lin work flow concept? of lin 2.1 specification automatic lin header handling and filtering of irrelevant lin frames automatic lin re sponse handling extended lin error detection and signaling hardware frame time-out detection ?break-in-data? support capability automatic re-synchronization to ensure proper frame integrity fully flexible extended frames support capabilities 4.16.2 uart features full duplex operation (independent serial receive and transmit processes) asynchronous operation high resolution baud rate generator hardware support of 8 data bits, odd/even/no parity bit, 1 stop bit frames data over-run and framing error detection 4.16.3 lin protocol 4.16.3.1 master and slave a lin cluster consists of one master task and several slave tasks. a master node contai ns the master task as well as a slave task. all other nodes contain a slave task only. figure 4-68. lin cluster with one master node and ?n? slave nodes the master task decides when and which frame shall be tr ansferred on the bu s. the slave tasks provide the data transported by each frame. both the master task and the slave ta sk are parts of the frame handler master task slave task master node slave task slave node 1 slave task slave node n lin bus
167 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.3.2 frames a frame consists of a header (provided by the master task) and a response (provided by a slave task). the header consists of a break and sync pattern follow ed by a protected identifier. the identifier uniquely defines the purpose of the frame. the slave task appointed for pr oviding the response associated with the identifier transmits it. the response consists of a data field and a checksum field. figure 4-69. master and slave tasks behavior in lin frame the slave tasks waiting for the data associated wit h the identifier receives the response and us es the data transported after verifying the checksum. figure 4-70. structure of a lin frame 4.16.3.3 data transport two types of data may be transported in a frame; signals or diagnostic messages. signals signals are scalar values or byte arrays that are packed into the data field of a frame. a si gnal is always present at the same position in the data field for all frames with the same identifier. diagnostic messages diagnostic messages are transported in frames with two reserved identifiers. t he interpretation of the data field depends on the data field itself as well as the state of the communicating nodes. 4.16.3.4 schedule table the master task (in the master node) transmits frame headers bas ed on a schedule table. the schedule table specifies the identifiers for each header and the interval between the start of a frame and the start of the following frame. the master application may use different schedul e tables and select among them. 4.16.3.5 compatibility with lin 1.3 lin 2.1 is a super-set of lin 1.3. a lin 2.1 master node can handle clusters consisting of both lin 1.3 slaves and/or lin 2.1 slaves. the master will then avoid requesting the new lin 2.1 features from a lin 1.3 slave: enhanced checksum, re-configuration and diagnostics, automatic baud rate detection, ?response error? status monitoring. lin 2.1 slave nodes can not operate with a lin 1.3 master node (e.g. the lin1.3 master does not support the enhanced checksum). the lin 2.1 physical layer is backwards compatible with the li n1.3 physical layer. but not t he other way aroun d. the lin 2.1 physical layer sets greater requirements, i. e. a master node using the lin 2.1 physica l layer can operate in a lin 1.3 cluster. header master task slave task 1 slave task 2 response header response field field sync header frame slot response break delimiter break field protected identifier field data 0 field data n checksum field inter byte space inter frame space each byte field is transmitted as a serial byte, lsb first response space
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 168 4.16.4 lin/uart controller the lin/uart controller is divided in three main functions: tx lin header function, rx lin header function, lin response function. these functions mainly use two services: rx service, tx service. because these two services are basically uart services, the controller is also able to switch into an uart function. 4.16.4.1 lin overview the lin/uart controller is designed to match as closely as possible to the lin software application struct ure. the lin software application is developed as independent ta sks, several slave tasks and one master task (see section 4.16.3.4 on page 167 ). the atmel ? attiny87/167 conforms to this perspective. the only link between the master task and the slave task will be at the cross-over point where the interrupt routine is called once a new identi fier is available. thus, in a master nod e, housing both master and slave task, the tx lin header function will alert the slave task of an id entifier presence. in the same way, in a slave node, the rx li n header function will alert the slav e task of an identifier presence. when the slave task is warned of an identifier presence, it has first to analyze it to know what to do with the response. hardware flags identify the presence of one of the specific identifiers from 60 (0x3c) up to 63 (0x3f). for lin communication, only four interrupts need to be managed: lidok: new lin identifier available, lrxok: lin response received, ltxok: lin response transmitted, lerr: lin error(s). the wake-up management can be automated using the uart wake-up capability and a node sending a minimum of 5 low bits (0xf0) for lin 2.1 and 8 low bits (0x80) for lin 1.3. pin ch ange interrupt on lin wake-up signal can be also used to exit the device of one of its sleep modes. extended frame identifiers 62 (0x3e) and 63 (0x3f) are rese rved to allow the embedding of user-defined message formats and future lin formats. the byte transfer mode offered by the uart will ensure the upwards co mpatibility of lin slaves with accommodation of the lin protocol. 4.16.4.2 uart overview the lin/uart controller can also function as a conventional uart. by default, the uart operates as a full duplex controller. it has local loop back circuitry for test purposes. th e uart has the ability to buffe r one character for transmit a nd two for receive. the receive buffer is made of one 8-bit seri al register followed by one 8- bit independent buffer register. automatic flag management is implemented when the application puts or gets c haracters, thus reducing the software overhead. because transmit and receive services are independent , the user can save one device pin when one of the two services is not used. the uart has an enhanced baud rate ge nerator providing a maximum error of 2% whatever the clock frequency and the targeted baud rate.
169 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.4.3 lin/uart controller structure figure 4-71. lin/uart co ntroller block diagram 4.16.4.4 lin/uart command overview figure 4-72. lin/uart command dependencies prescaler clk i/o rxd txd sample /bit baud_rate get byte rx frame time-out synchronization monitoring data fifo put byte tx finite state machine fsm buffer rx header or lin abort byte transfer disable lin uart tx response idok recommended way txok rxok rx byte tx response tx byte tx header full duplex possible way automatic return
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 170 4.16.4.5 enable/disable setting the lena bit in lincr register enabl es the lin/uart controller. to disable the lin/uart controller, lena bit must be written to 0. no wait states are implemented, so, the disable command is taken into account immediately. 4.16.4.6 lin commands clearing the lcmd[2] bit in lincr register enables lin commands. as shown in table 4-48 , four functions controlled by the lcmd[1..0] bits of lincr register are available (c.f. figure 4-72 on page 169 ). rx header/lin abort function this function (or state) is mainly the withdrawal mode of the controller. when the controller has to execute a master task, this st ate is the start point before enabling a tx header command. when the controller has only to execute slave tasks, lin header detection/acquisition is enabled as background function. at the end of such an acquisition (rx header function), automaticall y the appropriate flags are set, and in lin 1.3, the lindlr register is set with t he uncoded length value. this state is also the start point before enabling the tx or the rx response command. a running function (i.e. tx header, tx or rx response) can be aborted by clearing lcmd[1..0] bits in lincr register (see section 4.16.5.11 ?break-in-data? on page 179 ). in this case, an abort flag - labo rt - in linerr register will be set to inform the other software tasks. no wait states are implemente d, so, the abort command is taken into account immediately. rx header function is responsible for: the break field detection, the hardware re-synchronization analyzing the synch field, the reception of the protected identifier field, the parity control and the update of th e lindlr register in case of lin 1.3, the starting of the frame_time_out, the checking of the lin communication integrity. table 4-48. lin/uart command list lena lcmd[2] lcmd[1] lcmd[0] command comment 0 x x x disable peripheral 1 0 0 0 rx header - lin abort lin withdrawal 1 tx header lcmd[2..0]=000 after tx 1 0 rx response lcmd[2..0]=000 after rx 1 tx response lcmd[2..0]=000 after tx 1 0 0 byte transfer no crc, no time out ltxdl=lrxdl=0 (lindlr: read only register) 1 0 rx byte 0 1 tx byte 1 1 full duplex
171 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 tx header function in accordance with the lin prot ocol, only the master task must enable this f unction. the header is sent in the appropriate timed slots at the programmed baud rate (c.f. linbrr and linbtr registers). the controller is responsible for: the transmission of the br eak field - 13 dominant bits, the transmission of the synch field - character 0x55, the transmission of the protected identifi er field. it is the full content of the linidr r egister (automatic check bits included). at the end of this transmission, t he controller automatically returns to rx header / lin abort state (i.e. lcmd[1..0] = 00) after setting the appropriate flags. this function leaves the controller in the same setting as after the rx header function. this means that, in lin 1.3, the lind lr register is set with the unco ded length value at the end of the tx header function. during this function, the controller is also responsible for: the starting of the frame_time_out, the checking of the lin communication integrity. rx and tx response functions these functions are initiated by the slav e task of a lin node. they must be used after sending an header (master task) or after receiving an header (considered as bel onging to the slave task). when the tx re sponse order is sent, the transmission begins. a rx response order can be sent up to the reception of the last serial bit of the first byte ( before the stop-bit). in lin 1.3, the header slot configures the lindlr register. in lin 2.1, the user must confi gure the lindlr register, either lrxdl[3..0] for rx response either ltxdl[3..0] for tx response . when the command starts, the controller checks the lin13 bit of the lincr register to apply the right rule for computing the checksum. checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with lin 2.1 slaves . checksum calculation over the data bytes only is called classic checksum and it is used for communic ation with lin 1.3 slaves. note that id entifiers 60 (0x3c) to 63 (0x3f) shall always use classic checksum. at the end of this reception or transmission , the controller autom atically returns to rx header / lin abort state (i.e. lcmd[1..0] = 00) after setting the appropriate flags. if an lin error occurs, the reception or th e transmission is stopped, the appropriate fl ags are set and the lin bus is left to recessive state. during these functions, the controller is responsible for: the initialization of the checksum operator, the transmission or the reception of ? n ? data with the update of the checksum calculation, the transmission or the checking of the checksum field, the checking of the frame_time_out, the checking of the lin communication integrity. while the controller is sending or receiving a response, break and synch fields can be detected and the identifier of this new header will be recorded. of course, specific errors on t he previous response will be maintained with this identifier reception. handling data of lin response a fifo data buffer is used for data of the lin response. after setting all parameters in the linsel register, repeated accesses to the lindat register perform data read or data write (c.f. section 4.16.5.15 ?data management? on page 181 ). note that lrxdl[3..0] and ltxdl[3..0] are not linked to the data access.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 172 4.16.4.7 uart commands setting the lcmd[2] bit in linenr register enables uart commands. tx byte and rx byte services are independent as shown in table 4-48 on page 170 . byte transfer: the uart is selected but both rx and tx services are disabled, rx byte: only the rx service is enable but tx service is disabled, tx byte: only the tx service is enable but rx service is disabled, full duplex: the uart is selected and both rx and tx services are enabled. this combination of services is controlled by the lcmd[1..0] bits of linenr register (c.f. figure 4-72 on page 169 ). data handling the fifo used for lin communication is disabled during uart accesses. lrxdl[3..0] and ltxdl[3..0] values of lindlr register are then irrelevant. lindat re gister is then used as data register and linsel register is not relevant. rx service once this service is enabled, the user is warned of an in-c oming character by the lrxok fl ag of linsir register. reading lindat register automatically clears the flag and makes free the second stage of the buffer. if the user considers that the in- coming character is irrelevant without reading it, he direct ly can clear the flag (see specif ic flag management described in section 4.16.6.2 on page 183 ). the intrinsic structure of the rx service offers a 2-byte buff er. the fist one is used for serial to parallel conversion, the second one receives the result of the conversion. this second buffer byte is reached reading lindat register. if the 2-byte buffer is full, a new in-coming character will overwrite the second one already recorded. an ovrerr error in linerr register will then accompany this character when read. a ferr error in linerr register will be set in case of framing error. tx service if this service is enabled, the user se nds a character by writing in lindat register. automatically the ltxok flag of linsir register is cleared. it will rise at the end of the serial transmission. if no new character has to be sent, ltxok flag can be cleared separately (see spec ific flag management described in section 4.16.6.2 ?lin status and interrupt register - linsir? on page 183 ). there is no transmit buffering. no error is detected by this service.
173 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.5 lin / uart description 4.16.5.1 reset the avr ? core reset logic signal also resets the lin/uart controller. another form of reset exists, a software reset controlled by lswres bit in lincr register. this se lf-reset bit performs a partial reset as shown in table 4-49 . 4.16.5.2 clock the i/o clock signal (clk i/o ) also clocks the lin/uart controller. it is its unique clock. 4.16.5.3 lin protocol selection lin13 bit in lincr register is used to select the lin protocol: lin13 = 0 (default): lin 2.1 protocol, lin13 = 1: lin 1.3 protocol. the controller checks the lin13 bit in computing the checksum (enhanced checksum in lin2.1 / classic checksum in lin 1.3). this bit is irrelevant for uart commands. 4.16.5.4 configuration depending on the mode (lin or uart), lconf[1..0] bits of the lincr register set the controller in the following configuration ( table 4-50 ). the lin configuration is independent of the programmed lin protocol. table 4-49. reset of lin/uart registers register name reset value lswres value comment lin control register lincr 0000 0000 b 0000 0000 b x=unknown u=unchanged lin status and interrupt register linsir 0000 0000 b 0000 0000 b lin enable interrupt register linenir 0000 0000 b xxxx 0000 b lin error register linerr 0000 0000 b 0000 0000 b lin bit timing register linbtr 0010 0000 b 0010 0000 b lin baud rate register low linbrrl 0000 0000 b uuuu uuuu b lin baud rate register high linbrrh 0000 0000 b xxxx uuuu b lin data length register lindlr 0000 0000 b 0000 0000 b lin identifier register linidr 1000 0000 b 1000 0000 b lin data buffer selection linsel 0000 0000 b xxxx 0000 b lin data lindat 0000 0000 b 0000 0000 b table 4-50. configuration table versus mode mode lconf[1..0] configuration lin 00 b lin standard configuration (default) 01 b no crc field detection or transmission 10 b frame_time_out disable 11 b listening mode uart 00 b 8-bit data, no parity and 1 stop-bit 01 b 8-bit data, even parity and 1 stop-bit 10 b 8-bit data, odd parity and 1 stop-bit 11 b listening mode, 8-bit data, no parity and 1 stop-bit
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 174 the listening mode connects the internal tx lin and the internal rx lin together. in this mode, the txlin output pin is disabled and the rxlin input pin is always enabled. the same scheme is available in uart mode. figure 4-73. listening mode 4.16.5.5 busy signal lbusy bit flag in linsir register is the image of the busy si gnal. it is set and cleared by hardware. it signals that the controller is busy with lin or uart communication. busy signal in lin mode figure 4-74. busy signal in lin mode when the busy signal is set, some registers are locked, user writing is not allowed: ?lin control register? - lincr - e xcept lcmd[2..0], lena and lswres, ?lin baud rate registers? - linbrrl and linbrrh, ?lin data length register? - lindlr, ?lin identifier register? - linidr, ?lin data register? - lindat. if the busy signal is set, the only available commands are: lcmd[1..0] = 00 b , the abort command is taken into account at the end of the byte, lena = 0 and/or lcmd[2] = 0, the kill command is taken into account immediately, lswres = 1, the reset command is taken into account immediately. note that, if another command is entered during busy signal, the new command is not validated and the lovrerr bit flag of the linerr register is set. the on -going transfer is not interrupted. busy signal in uart mode during the byte transmission, the busy signal is set. this locks some regi sters from be ing written: ?lin control register? - lincr - e xcept lcmd[2..0], lena and lswres, ?lin data register? - lindat. the busy signal is not generated during a byte reception. txlin internal tx lin internal rx lin listen 1 0 rxlin field field sync node providing the master task node providing a slave task header lin bus 1) lbusy 2) lbusy 3) lbusy frame slot response lcmd = tx header lidok lcmd = tx or rx response ltxok or lrxok break field protected identifier field data 0 field data n checksum field node providing neither the master task, neither a slave task
175 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.5.6 bit timing baud rate generator the baud rate is defined to be the transfer rate in bits per second (bps): baud: baud rate (in bps), f clk i/o : system i/o clock frequency, ldiv[11..0]: contents of linbrrh & linbrrl regist ers - (0-4095), the pre-scaler receives clk i/o as input clock. lbt[5..0]: least significant bits of - linbtr register- (0-63) is the number of samplings in a lin or uart bit (default value 32). equation for calculating baud rate: baud = fclk i/o / lbt[5..0] x (ldiv[11..0] + 1) equation for setting lindiv value: ldiv[11..0] = ( fclk i/o / lbt[5..0] x baud ) - 1 note that in reception a majority vote on three samplings is made. re-synchronization in lin mode when waiting for rx header, lbt[5..0] = 32 in linbtr regi ster. the re-synchronization begi ns when the break is detected. if the break size is not in the range (10.5 bits min., 28 bits max. ? 13 bits nominal), the break is refused. the re-synchronization is done by adjusting lbt[5..0] value to the synch field of the received header (0x55). then the protected identifier is sampled using the new value of lbt[5..0]. the re-synchr onization implemented in the controller tolerates a clock deviation of 2 0% and adjusts the baud rate in a 2% range. the new lbt[5..0] value will be used up to the end of the re sponse. then, the lbt[5..0] will be reset to 32 for the next header. the linbtr register can be used to (software) re-calibrate the clock oscillator. the re-synchronization is not performed if the lin node is enabled as a master. handling lbt[5..0] ldisr bit of linbtr register is used to: disable the re-synchronization (for inst ance in the case of lin master node), to enable the setting of lbt[5..0] (to manually adjust the baud rate especially in the case of uart mode). a minimum of 8 is required for lbt[5..0] due to the sampling operation. note that the lena bit of lincr register is important for this handling (see figure 4-75 ). figure 4-75. handling lbt[5..0] lena ? (lincr bit4) ldisr to write = 1 = 1 = 0 = 0 write in linbtr register lbt[5..0] forced to 0x20 ldisr forced to 0 enable re-synch. in lin mode lbt[5..0] = lbt[5..0] to write (lbt [5 to 0] min = 8) ldisr forced to 1 disable re-synch. in lin mode
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 176 4.16.5.7 data length section 4.16.4.6 ?lin commands? on page 170 describes how to set or how are automatically set the lrxdl[3..0] or ltxdl[3..0] fields of lindlr register bef ore receiving or transmitting a response. in the case of tx response the lrxdl[3..0] will be used by the hardware to count the number of bytes already successfully sent. in the case of rx response the ltxdl[3. .0] will be used by the hardware to count the number of bytes already successfully received. if an error occurs, this informati on is useful to the programmer to recover the lin messages. data length in lin 2.1 if ltxdl[3..0]=0 only the checksum will be sent, if lrxdl[3..0]=0 the first byte received will be interpreted as the checksum, if ltxdl[3..0] or lrxdl[3..0] >8, values will be forced to 8 after the command setting and before sending or receiving of the first byte. data length in lin 1.3 lrxdl and ltxdl fields are both hardware updated befo re setting lidok by decoding the data length code contained in the received prot ected identifier (lrxdl = ltxdl). via the above mechanism, a length of 0 or >8 is not possible. data length in rx response figure 4-76. lin2.1 - rx response - no error the user initializes lrxdl field before setting the rx response command, after setting the rx response command, ltxdl is reset by hardware, lrxdl field will remain unchanged during rx (during busy signal), ltxdl field will count the number of received bytes (during busy signal), if an error occurs, rx stops, the corre sponding error flag is set and ltxdl will give the number of received bytes without error, if no error occurs, lrxok is set after the reception of the checksum, lrxdl will be unchanged (and ltxdl = lrxdl). data-0 lcmd = rx response lcmd2 to 0 = 000 b lindlr = 0x?4 (*): lrxdl and ltxdl updated by user 4 ?0 1 2 3 4 lidok lin bus lrxdl (*) ltxdl (*) lbusy 1 st byte 2 nd byte 3 rd byte 4 th byte lrxok data-1 data-2 data-3 checksum
177 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 data length in tx response figure 4-77. lin1.3 - tx response - no error the user initializes ltxdl field before setting the tx response command, after setting the tx response command, lrxdl is reset by hardware, ltxdl will remain unchanged during tx (during busy signal), lrxdl will count the number of transmitted bytes (during busy signal), if an error occurs, tx stops, the corresponding error flag is set and lrxdl will give the number of transmitted bytes without error, if no error occurs, ltxok is set after the transmi ssion of the checksum, ltxdl will be unchanged (and lrxdl = ltxdl). data length after error figure 4-78. tx response - error note: information on response (ex: error on byte) is only avai lable at the end of the seri alization/de-serialization of the byte. data length in uart mode the uart mode forces lrxdl and ltxdl to 0 and disables the writing in lindlr register, note that after reset, lrxdl and ltxdl are also forced to 0. data-0 lcmd = tx response lcmd2..0 = 000 b (*): lrxdl and ltxdl updated by rx response or tx response task 4 401234 lidok lin bus lrxdl (*) ltxdl (*) lbusy 1 st byte 2 nd byte 3 rd byte 4 th byte ltxok data-1 data-2 data-3 checksum data-0 lcmd = tx response lcmd2..0 = 000 b 4 40 1 2 lin bus lrxdl ltxdl lbusy 1 st byte 2 nd byte 3 rd byte lerr data-1 data-2 error
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 178 4.16.5.8 xxok flags there are three xxok flags in linsir register: lidok: lin identifier ok it is set at the end of the header, eit her by the tx header function or by the rx header. in lin 1.3, before generating lidok, the controller updates the lrxdl and ltxdl fields in lindlr register. it is not driven in uart mode. lrxok: lin rx response complete it is set at the end of the response by the rx response f unction in lin mode and once a character is received in uart mode. ltxok: lin tx response complete it is set at the end of the response by the tx response function in lin m ode and once a character has been sent in uart mode. these flags can generate inte rrupts if the corresponding enable interrupt bit is set in the linenir register (see section 4.16.5.13 ?interrupts? on page 180 ). 4.16.5.9 xxerr flags lerr bit of the linsir register is an logical ?or? of all the bits of linerr register (see section 4.16.5.13 ?interrupts? on page 180 ). there are eight flags: lberr = lin bit error. a unit that is sending a bit on the bus also monitors the bus. a lin bit error will be flagged when the bit value that is monitored is different from the bit value that is sent. af ter detection of a lin bit error the transmission is aborted. lcerr = lin checksum error. a lin checksum error will be flagged if the inverted modulo-256 sum of all received data bytes (and the protected identifier in lin 2.1) added to the checksum does not result in 0xff. lperr = lin parity error (identifier). a lin parity error in the identifier field will be flagged if the value of the parity bits does not match with the identifier value. (see lp[1:0] bits in section 4.16.6.8 ?lin identifier register - linidr? on page 186 ). a lin slave application does not distinguish between corrupted parity bits and a corrupted identifier. the hardware does not undertake any correction. however, the lin slave application has to solve this as: known identifier (parity bits corrupted), or corrupted identifier to be ignored, or new identifier. lserr = lin synchronization error. a lin synchronization error will be flagged if a slave det ects the edges of the sy nch field outside the given tolerance. lferr = lin framing error. a framing error will be flagged if dominant stop bit is sampled. same function in uart mode. ltoerr = lin time out error. a time-out error will be flagged if the message fram e is not fully completed within the maximum length t frame_maximum by any slave task upon transmission of the synch and identifier fields (see section 4.16.5.10 ?frame time out? on page 179 ). loverr = lin overrun error. overrun error will be flagged if a new command (other than lin abort) is entered while ?busy signal? is present. in uart mode, an overrun error will be flagged if a received byte overwrites the byte stored in the serial input buffer. labort lin abort transfer reflects a previous lin abort command (lcmd[2..0] = 000) while ?busy signal? is present. after each lin error, the lin controller stops its previous ac tivity and returns to its withdrawal mode (lcmd[2..0] = 000 b ) as illustrated in figure 4-78 on page 177 . writing 1 in lerr of linsir register resets lerr bit and all the bits of the linerr register.
179 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.5.10 frame time out according to the lin protocol, a frame time-out error is flagged if: t frame > t frame_maximum . this feature is implemented in the lin/uart controller. figure 4-79. lin timing and frame time-out 4.16.5.11 break-in-data according to the lin protocol, the lin/ uart controller can detect the break/sy nc field sequence even if the break is partially superimposed with a byte of the response. when a break/sync field sequence happens, the transfer in progress is aborted and the processing of the new frame starts. on slave node(s), an error is generated (i.e. lberr in case of tx response or lferr in case of rx response ). information on data error is also available, refer to the section ?data length after error? on page 177 . on master node, the user (code) is responsible for this abort ing of frame. to do this, the master task has first to abort the on-going communication (clearing lcmd bits - lin abort command) and then to apply the tx header command. in this case, the abort error flag - labort - is set. on the slave node, the break detectio n is processed with the synchronization setting available when the lin/uart controller processed the (abort ed) response. but the re-synchronization restar ts as usual. due to a possible difference of timing reference between the break field and the rest of the fr ame, the time-out values can be slightly inaccurate. 4.16.5.12 checksum the last field of a frame is the checksum. in lin 2.1, the checksum contai ns the inverted eight bi t sum with carry over all data bytes and the protected identifier. this calculation is called enhanced checksum. in lin 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes. this calculation is called classic checksum. frame identifiers 60 (0x3c) to 61 (0x3 d) shall always use classic checksum. field field sync t header t header_nominal t response_nominal t frame_nominal = = = 34 x t bit 10 (number_of_data + 1) x t bit t header_ nominal + t response_nominal t header_maximum t response_maximum t frame_maximum = = = 1.4 x t header_nominal 1.4 x t response_nominal t header_ maximum + t response_maximum t frame t response break field nominal maximum before time-out protected identifier field data 0 field data n checksum field checksum 255 unsigned char data n 0 n ? ?? ?? ?? ?? protected id + ?? ?? ?? ?? unsigned char data n 0 n ? ?? ?? ?? ?? protected id + ?? ?? ?? ?? 8 ? ?? ?? ?? ?? + ? ? ? ? ? ? ? ? ? = checksum 255 unsigned char data n 0 n ? ?? ?? ?? ?? unsigned char data n 0 n ? ?? ?? ?? ?? 8 ? ?? ?? ?? ?? + ?? ?? ?? ?? ? =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 180 4.16.5.13 interrupts as shown in figure 4-80 on page 180 , the four communication flags of the linsir register are combined to drive two interrupts. each of these flags have their resp ective enable interrupt bit in linenir register. (see section 4.16.5.8 ?xxok flags? on page 178 and section 4.16.5.9 ?xxerr flags? on page 178 ). figure 4-80. lin interrupt mapping 4.16.5.14 message filtering message filtering based upon the whole iden tifier is not implemented. only a stat us for frame headers having 0x3c, 0x3d, 0x3e and 0x3f as identifier is available in the linsir register. the lin protocol says that a message with an identifier from 60 (0x3c) up to 63 (0x3f) uses a classic checksum (sum over the data bytes only). software will be responsible for switchin g correctly the lin13 bit to provide/check this expected checksum (the insertion of the id field in th e computation of the crc is set - or not - just after entering the rx or tx respon se command). labort ltoerr loverr lferr lserr lperr lcerr lberr lerr lin err lin tc lidok ltxok lrxok lenerr linenir.3 linenir.2 linenir.1 linenir.0 lenidok lentxok lenrxok linsir.3 linsir.2 linerr.7 linerr.6 linerr.5 linerr.4 linerr.3 linerr.2 linerr.1 linerr.0 linsir.1 linsir.0 table 4-51. frame status lidst[2..0] frame status 0xx b no specific identifier 100 b 60 (0x3c) identifier 101 b 61 (0x3d) identifier 110 b 62 (0x3e) identifier 111 b 63 (0x3f) identifier
181 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.5.15 data management lin fifo data buffer to preserve register allocation, the lin data buffer is s een as a fifo (with address pointer accessible). this fifo is accessed via the lindx[2..0] field of lin sel register through the lindat register. lindx[2..0], the data index, is the address pointer to the required data byte. the data byte can be read or written. the data index is automatically incremented af ter each lindat access if the lainc (active low) bit is cleared. a roll-over is implemented, after data index = 7 it is data index=0. otherwise, if lainc bit is set, the data index needs to be written (updated) before each lindat access. the first byte of a lin frame is stored at the data index=0, the second one at the data index=1, and so on. nevertheless, linsel must be initialized by the user before use. uart data register the lindat register is the data register (no buffering - no fi fo). in write access, lindat will be for data out and in read access, lindat will be for data in. in uart mode the linsel register is unused. 4.16.5.16 ocd support when a debugger break occurs, the state machine of the lin/ uart controller is stopped (included frame time-out) and further communication may be corrupted. 4.16.6 lin/uart register description table 4-52. lin/uart regi ster bits summary name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lincr lswres lin13 lconf1 lconf0 lena lcmd2 lcmd1 lcmd0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w linsir lidst2 lidst1 lidst0 lbusy lerr lidok ltxok lrxok 0 r 0 r 0 r 0 r 0 r/w one 0 r/w one 0 r/w one 0 r/w one linenir ? ? ? ? lenerr lenidok lentxok lenrxok 0 r 0 r 0 r 0 r 0 r/w 0 r/w 0 r/w 0 r/w linerr labort ltoerr loverr lferr lserr lperr lcerr lberr 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r linbtr ldisr lbt5 lbt4 lbt3 lbt2 lbt1 lbt0 0 r/w 0 r 1 r/(w) 0 r/(w) 0 r/(w) 0 r/(w) 0 r/(w) 0 r/(w) linbrrl ldiv7 ldiv6 ldiv5 ldiv4 ldiv3 ldiv2 ldiv1 ldiv0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w linbrrh ? ? ? ? ldiv11 ldiv10 ldiv9 ldiv8 0 r 0 r 0 r 0 r 0 r/w 0 r/w 0 r/w 0 r/w lindlr ltxdl3 ltxdl2 ltxdl1 ltxdl0 lrxdl3 lrxdl2 lrxdl1 lrxdl0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w linidr lp1 lp0 lid5/ldl1 lid4/ldl0 lid3 lid2 lid1 lid0 1 r 0 r 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w linsel ? ? ? ? lainc lindx2 lindx1 lindx0 0 r 0 r 0 r 0 r 0 r/w 0 r/w 0 r/w 0 r/w lindat ldata7 ldata6 ldata5 ldata4 ldata3 ldata2 ldata1 ldata0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 182 4.16.6.1 lin control register - lincr ? bit 7 - lswres: software reset 0 = no action, 1 = software reset (this bit is self-rese t at the end of the reset procedure). ? bit 6 - lin13: lin 1.3 mode 0 = lin 2.1 (default), 1 = lin 1.3. ? bit 5:4 - lconf[1:0]: configuration a. lin mode (default = 00): 00 = lin standard configuration (listen mode ?off?, crc ?on? & frame_time_out ?on?, 01 = no crc, no frame_time_out (listen mode ?off?), 10 = no frame_time_out (listen mode ?off? & crc ?on?), 11 = listening mode (crc ?o n? & frame_time_out ?on?). b. uart mode (default = 00): 00 = 8-bit, no parity (listen mode ?off?), 01 = 8-bit, even parity (listen mode ?off?), 10 = 8-bit, odd parity (listen mode ?off?), 11 = listening mode, 8-bit, no parity. ? bit 3 - lena: enable 0 = disable (both lin and uart modes), 1 = enable (both lin and uart modes). ? bit 2:0 - lcmd[2..0 ]: command and mode the command is only available if lena is set. 000 = lin rx header - lin abort, 001 = lin tx header, 010 = lin rx response, 011 = lin tx response, 100 = uart rx and tx byte disable, 11x = uart rx byte enable, 1x1 = uart tx byte enable. bit 7 6543210 lswres lin13 lconf1 lconf0 lena lcmd2 lcmd1 lcmd0 lincr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000
183 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.6.2 lin status and in terrupt register - linsir ? bits 7:5 - lidst[2:0]: identifier status 0xx = no specific identifier, 100 = identifier 60 (0x3c), 101 = identifier 61 (0x3d), 110 = identifier 62 (0x3e), 111 = identifier 63 (0x3f). ? bit 4 - lbusy: busy signal 0 = not busy, 1 = busy (receiving or transmitting). ? bit 3 - lerr: error interrupt it is a logical or of linerr register bits. this bit generat es an interrupt if its respective enable bit - lenerr - is set in linenir. 0 = no error, 1 = an error has occurred. the user clears this bit by writing 1 in order to reset th is interrupt. resetting lerr al so resets all linerr bits. in uart mode, this bit is also cleared by reading lindat. ? bit 2 - lidok: identifier interrupt this bit generates an interrupt if its respective enable bit - lenidok - is set in linenir. 0 = no identifier, 1 = slave task: identifier present, master task: tx header complete. the user clears this bit by writing 1, in order to reset this interrupt. ? bit 1 - ltxok: transmit performed interrupt this bit generates an interrupt if its respec tive enable bit - lentxok - is set in linenir. 0 = no tx, 1 = tx response complete. the user clears this bit by writing 1, in order to reset this interrupt. in uart mode, this bit is al so cleared by writing lindat. ? bit 0 - lrxok: receive performed interrupt this bit generates an interrupt if its respec tive enable bit - lenrxok - is set in linenir. 0 = no rx 1 = rx response complete. the user clears this bit by writing 1, in order to reset this interrupt. in uart mode, this bit is also cleared by reading lindat. bit 76543210 lidst2 lidst1 lidst0 lbusy lerr lidok ltxok lrxok linsir read/write rrrrr/woner/woner/woner/wone initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 184 4.16.6.3 lin enable interru pt register - linenir ? bits 7:4 - reserved bits these bits are reserved for future use. for compatibility wi th future devices, they must be written to zero when linenir is written. ? bit 3 - lenerr: enable error interrupt 0 = error interrupt masked, 1 = error interrupt enabled. ? bit 2 - lenidok: enable identifier interrupt 0 = identifier interrupt masked, 1 = identifier interrupt enabled. ? bit 1 - lentxok: enable transmit performed interrupt 0 = transmit performed interrupt masked, 1 = transmit performed interrupt enabled. ? bit 0 - lenrxok: enable receive performed interrupt 0 = receive performed interrupt masked, 1 = receive performed interrupt enabled. 4.16.6.4 lin error register - linerr ? bit 7 - labort: abort flag 0 = no warning, 1 = lin abort command occurred. this bit is cleared when lerr bit in linsir is cleared. ? bit 6 - ltoerr: frame_time_out error flag 0 = no error, 1 = frame_time_out error. this bit is cleared when lerr bit in linsir is cleared. ? bit 5 - loverr: overrun error flag 0 = no error, 1 = overrun error. this bit is cleared when lerr bit in linsir is cleared. ? bit 4 - lferr: framing error flag 0 = no error, 1 = framing error. this bit is cleared when lerr bit in linsir is cleared. bit76543210 - - - - lenerr lenidok lentxok lenrxok linenir read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 labort ltoerr loverr lferr lserr lperr lcerr lberr linerr read/write rrrrrrrr initial value00000000
185 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 3 - lserr: synchronization error flag 0 = no error, 1 = synchronization error. this bit is cleared when lerr bit in linsir is cleared. ? bit 2 - lperr: parity error flag 0 = no error, 1 = parity error. this bit is cleared when lerr bit in linsir is cleared. ? bit 1 - lcerr: checksum error flag 0 = no error, 1 = checksum error. this bit is cleared when lerr bit in linsir is cleared. ? bit 0 - lberr: bit error flag 0 = no error, 1 = bit error. this bit is cleared when lerr bit in linsir is cleared. 4.16.6.5 lin bit timing register - linbtr ? bit 7 - ldisr: disable bit timing re synchronization 0 = bit timing re-synchronization enabled (default), 1 = bit timing re-synchronization disabled. ? bits 5:0 - lbt[5:0]: lin bit timing gives the number of samples of a bit. sample-time = (1 / f clk i/o ) x (ldiv[11..0] + 1) default value: lbt[6:0]=32 ? min. value: lbt[6:0]=8 ? max. value: lbt[6:0]=63 4.16.6.6 lin baud rate register - linbrr ? bits 15:12 - reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when linbrr is written. ? bits 11:0 - ldiv[11:0]: scaling of clk i/o frequency the ldiv value is used to scale the entering clk i/o frequency to achieve appropriate lin or uart baud rate. bit 7654321 0 ldisr - lbt5 lbt4 lbt3 lbt2 lbt1 lbt0 linbtr read/write r/w r r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) initial value0010000 0 bit 76543210 ldiv7 ldiv6 ldiv5 ldiv4 ldiv3 ldiv2 ldiv1 ldiv0 linbrrl ----ldiv11ldiv10ldiv9ldiv8linbrrh bit 151413121110 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 186 4.16.6.7 lin data length register - lindlr ? bits 7:4 - ltxdl[3:0]: lin transmit data length in lin mode, this field gives the number of bytes to be transmitted (clamped to 8 max). in uart mode this field is unused. ? bits 3:0 - lrxdl[3:0]: lin receive data length in lin mode, this field gives the number of bytes to be received (clamped to 8 max). in uart mode this field is unused. 4.16.6.8 lin identifier register - linidr ? bits 7:6 - lp[1:0]: parity in lin mode: lp0 = lid4 ^ lid2 ^ lid1 ^ lid0 lp1 = ! ( lid1 ^ lid3 ^ lid4 ^ lid5 ) in uart mode this field is unused. ? bits 5:4 - ldl[1:0]: lin 1.3 data length in lin 1.3 mode: 00 = 2-byte response, 01 = 2-byte response, 10 = 4-byte response, 11 = 8-byte response. in uart mode this field is unused. ? bits 3:0 - lid[3:0]: lin 1.3 identifier in lin 1.3 mode: 4-bit identifier. in uart mode this field is unused. ? bits 5:0 - lid[5:0]: lin 2.1 identifier in lin 2.1 mode: 6-bit identifier (no length transported). in uart mode this field is unused. bit 76543210 ltxdl3 ltxdl2 ltxdl1 ltxdl0 lrxdl3 lrxdl2 lrxdl1 lrxdl0 lindlr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76 5 4 3210 lp1 lp0 lid5 / ldl1 lid4 / ldl0 lid3 lid2 lid1 lid0 linidr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
187 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.16.6.9 lin data buffer selection register - linsel ? bits 7:4 - reserved bits these bits are reserved for future use. for compatibility with future devices, they must be written to zero when linsel is written. ? bit 3 - lainc : auto increment of data buffer index in lin mode: 0 = auto incrementation of fifo data buffer index (default), 1 = no auto incrementation. in uart mode this field is unused. ? bits 2:0 - lindx 2:0: fifo lin data buffer index in lin mode: location (index) of the lin response data byte into the fifo data buffer. the fifo data buffer is accessed through lindat. in uart mode this field is unused. 4.16.6.10 lin data register - lindat ? bits 7:0 - ldata[7:0]: lin data in / data out in lin mode: fifo data buffer port. in uart mode: data register (no data buffer - no fifo). in write access, data out. in read access, data in. bit 76543210 ---- lainc lindx2 lindx1 lindx0 linsel read/write ----r/wr/wr/wr/w initial value---- 0000 bit 76543210 ldata7 ldata6 ldata5 ldata4 ldata3 ldata2 ldata1 ldata0 lindat read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 188 4.17 isrc - current source 4.17.1 features 100a constant current source 10% absolute accuracy the atmel ? attiny87/167 features a 100a 10% current source. up on request, the current is flowing through an external resistor. the voltage can be measured on the dedicated pin shared with the adc. using a resistor in series with a 0.5% tolerance is recommended. to protect the device against bi g values, the adc must be configured with avcc as internal reference to perform the first measurement. afterwards, another internal reference can be chosen according to the previous measured value to refine the result. when isrcen bit is set, the isrc pin sources 100 a. otherwise this pin keeps its initial function. figure 4-81. current source block diagram 4.17.2 typical applications 4.17.2.1 lin current source during the configuration of a lin node in a cluster, it may be necessary to attribute dynamically an unique physical address to every cluster node. the way to do it is not described in the lin protocol. the current source offers an excellent solution to associat e a physical address to the applicat ion supported by the lin node. a full dynamic node configuration can be us ed to set-up the lin nodes in a cluster. atmel attiny87/167 proposes to have an external resistor used in conjunction with the current source. the device measures the voltage to the boundaries of the resistanc e via the analog to digital converter. the resulting voltage defines the physical address that the communication handler will use wh en the node will participate in lin communication. in automotive applications, distributed voltages are very di sturbed. the internal current source solution of atmel attiny87/167 immunizes the address detection the against any kind of voltage variations. adc input avcc isrcen 100a adcn/ isrc external resistor
189 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 table 4-53. example of resistor values( 5%) for a 8-address system (avcc = 5v (1) ) physical address resistor value r load (ohm) typical measured voltage (v) minimum reading with a 2.56v ref typical reading with a 2.56v ref maximum reading with a 2.56v ref 0 1 000 0.1 40 1 2 200 0.22 88 2 3 300 0.33 132 3 4 700 0.47 188 4 6 800 0.68 272 5 10 000 1 400 6 15 000 1.5 600 7 22 000 2.2 880 note: 1. 5v range: max r load 30k 3v range: max r load 15k table 4-54. example of resistor values (1%) for a 16-address system (avcc = 5v (1) ) physical address resistor value r load (ohm) typical measured voltage (v) minimum reading with a 2.56v ref typical reading with a 2.56v ref maximum reading with a 2.56v ref 0 1 000 0.1 38 40 45 1 1 200 0.12 46 48 54 2 1500 0.15 57 60 68 3 1800 0.18 69 72 81 4 2200 0.22 84 88 99 5 2700 0.27 104 108 122 6 3300 0.33 127 132 149 7 4700 0.47 181 188 212 8 6 800 0.68 262 272 306 9 8 200 0.82 316 328 369 10 10 000 1.0 386 400 450 11 12 000 1.2 463 480 540 12 15 000 1.5 579 600 675 13 18 000 1.8 694 720 810 14 22 000 2.2 849 880 989 15 27 000 2.7 1023 1023 1023 note: 1. 5v range: max r load 30k 3v range: max r load 15k
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 190 4.17.2.2 current source for low cost transducer an external transducer based on a variable resi stor can be connected to the current source. this can be, for instance: a thermistor, or temperature-sensitive re sistor, used as a temperature sensor, a cds photoconductive cell, or luminosity-sensi tive resistor, used as a luminosity sensor, ... using the current source with this type of transducer eliminat es the need for additional parts otherwise required in resistor network or wheatstone bridge. 4.17.2.3 voltage reference for external devices an external resistor used in conjunction with the current source can be used as voltage reference for external devices. using a resistor in series with a lower tolerance than the current source accuracy ( 2%) is recommended. table 4-54 on page 189 gives an example of voltage references using standard values of resistors. 4.17.2.4 threshold reference for internal analog comparator an external resistor used in conjunction with the current so urce can be used as threshold reference for internal analog comparator (see section 4.19 ?anacomp - analog comparator? on page 209 ). this can be connected to ain0 (negative analog compare input pin) as well as ain1 (positive analog compare input pin). using a resistor in series with a lower tolerance than the curr ent source accuracy ( 2%) is recommended. table 4-54 gives an example of threshold references using standard values of resistors. 4.17.3 control register 4.17.3.1 amiscr ? analog misc ellaneous control register ? bit 0 ? isrcen: current source enable writing this bit to one enables the current source as shown in figure 4-81 . it is recommended to use didr register bit function when isrcen is set and to turn off the current source once the adc measurement is done. bit 76543210 - - - - - arefen xrefen isrcen amiscr read/write r r r r r r/w r/w r/w initial value00000000
191 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18 adc ? analog to digital converter 4.18.1 features 10-bit resolution 1.0lsb integral non-linearity 2lsb absolute accuracy 13 - 260s conversion time (low - high resolution) up to 15ksps at maximum resolution 11 multiplexed single ended input channels 8 differential input pairs with selectable gain temperature sensor input channel voltage from internal current source driving (isrc) optional left adjustment for adc result readout 0 - avcc adc input voltage range selectable 1.1v/2.56v adc voltage reference free running or single conversion mode adc start conversion by auto triggering on interrupt sources interrupt on adc conversion complete sleep mode noise canceler unipolar/bipolar input mode input polarity reversal mode 4.18.2 overview the atmel ? attiny87/167 features a 10-bit successive approximati on adc. the adc is connected to a 11-channel analog multiplexer which allows 16 differential voltage input combinations and 11 single- ended voltage inputs constructed from the pins pa7..pa0 or pb7..pb4. the differential input is equipped with a programmable gain stage, providing amplification steps of 8x or 20x on the diff erential input voltage before the a/ d conversion. the single-ended volt age inputs refer to 0v (agnd). the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 4-82 . internal reference voltages of nominally 1.1v or 2.56v are provided on-chip. alternatively, avcc can be used as reference voltage for single ended channels. there are al so options to output the internal 1.1v or 2.56v reference voltages or to input an external voltage reference and turn-off the internal voltage reference. these options are selected using the refs[1:0] bits of the admux control register and using arefen and xrefen bits of the amiscr control register.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 192 figure 4-82. analog to digital converter block schematic trigger select prescaler interrupt flags adc conversion complete irq start avcc adc10 agnd bandgap reference temperature sensor avcc / 4 internal 2.56/ 1.1v reference mux. decoder sample and hold comparator adc multiplexer output adc multiplexer select (admux) analog misc. (amiscr) adc control and status register a and b (adcsra/ adcrb) conversion logic adc data register (adch/ adcl) mux[4..0] xrefen arefen refs1 refs0 adlar 10-bit dac mux. x8/ x20 gain amplifier pos. input mux. neg. input mux. - + + - adsp[2..0] adts[2..0] adc[9..0] bin aden adie adif adif adate adsc adc9 adc8 adc7 adc6 aref xref adc5 adc4 isrc/ adc3 adc2 adc1 adc0 8-bit data bus
193 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.3 operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents agnd and the maximum value repres ents the voltage on avcc, the voltage reference on aref pin or an internal 1.1v/2.56v voltage reference. the voltage reference for the adc may be selected by writing to the refs[1..0] bits in admux and arefen bit in amiscr. the avcc supply, the aref pin or an internal 1.1v / 2.56v voltage reference may be selected as the adc voltage reference. the analog input channel and differential gain are selected by writing to the mux[4..0] bits in admu x register. any of the 11 adc input pins adc[10..0] can be selected as single ended inputs to the adc. the positi ve and negative inputs to the differential gain amplifier are described in table 4-59 . if differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor 8x or 20x, according to the setting of the mux[4..0] bits in admux register. this amplified value then becomes the analog input to the adc. if single ended channels are used, the gain amplifier is bypassed altogether. the on-chip temperature sensor is sele cted by writing the code defined in table 4-59 to the mux[4..0] bits in admux register when its dedicated adc c hannel is used as an adc input. a specific adc channel (defined in table 4-59 ) is used to measure the voltage to the boundaries of an external resistance flowing by a current driving by the internal current source (isrc). the adc is enabled by setting the adc enable bit, aden in adcsra register. voltage reference and input channel selections will not go into effect until aden is set. the a dc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux register. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl mus t be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means t hat if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of ad ch and adcl, the interrupt will trigger even if the result is lost. 4.18.4 starting a conversion a single conversion is started by writing a logical one to the a dc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware w hen the conversion is completed. if a different data channel is selected while a conversion is in pr ogress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra register. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb register (see description of the adts bits fo r a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a c onversion is started. this provides a method of starting conversions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger signa l during conversion, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disa bled or the global interrupt enable bit in sreg register is cl eared. a conversion can thus be triggered without causing an interr upt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 194 figure 4-83. adc au to trigger logic using the adc interrupt flag as a trigger source makes the a dc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, constant ly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra register. in this mode the adc will perform successive conversions independently of whether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, sing le conversions can be started by writing adsc in adcsra register to one. adsc can also be used to determine if a conversion is in progress. the ad sc bit will be read as one duri ng a conversion, independently of how the conversion was started. 4.18.5 prescaling and conversion timing figure 4-84. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50khz and 200khz to get maximum resolution. if a lower resolution than 10bits is nee ded, the input clock frequency to the adc can be higher than 200khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the prescaling is set by the adps bits in adcsra re gister. the prescaler starts counting from the moment the adc is switched on by setting the aden bi t in adcsra register. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by setting the adsc bit in adcsra register, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra register is set) takes 25 adc clock cycles in order to initialize the analog circuitry. edge detector conversion logic adc prescaler adif adsc adate start clk adc clk io adts[2:0] source 1 ... ... ... ... source n 7-bit adc prescaler aden start ck io adps0 adps1 adps2 reset ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 ck/128
195 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 14.5 adc clock cycles after the start of an first conversion. when a conversion is complete, the result is writt en to the adc data registers, and adif is set. in single conversion mode, adsc is clea red simultaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-a nd-hold takes place 2 adc clock cycles after the rising edge on the trigger source signal. thre e additional cpu clock cycles ar e used for synchronization logic. in free running mode, a new conversion w ill be started immediately after the conversion completes, while adsc remains high. for a summary of conversion times, see table 4-55 . figure 4-85. adc timing diagram, first conversion (single conversion mode) figure 4-86. adc ti ming diagram, si ngle conversion 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 cycle number first conversion sign and msb of result lsb of result next conversion mux and refs update conversion complete mux and refs update adc clock aden adsc adif adch adcl sample and hold 12345678910111213 123 cycle number one conversion next conversion mux and refs update conversion complete mux and refs update adc clock adsc adif adch adcl sample and hold sign and msb of result lsb of result
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 196 figure 4-87. adc timing diagram, auto triggered conversion figure 4-88. adc timi ng diagram, free running conversion table 4-55. adc conv ersion time condition sample and hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5cycles 25cycles normal conversions 1.5cycles 13cycles auto triggered conversions 2cycles 13.5cycles 12345678910111213 12 cycle number one conversion next conversion mux and refs update prescaler reset prescaler reset conversion complete adc clock trigger source adif adate adch adcl sample and hold sign and msb of result lsb of result 11 12 13 1 2 3 4 cycle number one conversion next conversion mux and refs update conversion complete adc clock adsc adif adch adcl sample and hold sign and msb of result lsb of result
197 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.6 changing channel or reference selection the mux[4:0] and refs[1:0] bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and refer ence selection only takes place at a safe point during the conversion. the channel and reference select ion is continuously updated until a conv ersion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra register is set). note that the conversion starts on the following rising adc clock edge after ad sc is written. the user is thus advised not to write new channel or reference selection values to admu x until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggering event can be indetermin istic. special care must be taken when updating the admux register, in order to control wh ich conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event ca n occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one a dc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 4.18.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simp lest method is to wait fo r the conversion to complete before changing the channel selection. in free running mode, always select the ch annel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simp lest method is to wait for the first conversion to complete, and then change the channel selection. si nce the next conversion has already star ted automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. 4.18.6.2 adc voltage reference the voltage reference for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either avcc, internal 1.1v/2.56v voltage reference or external aref pin. the first adc conversion result after swit ching voltage reference source may be inaccurate, and the user is advised to discard this result. 4.18.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adc is enabled and is not busy co nverting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the ad c will start a conversion once the cpu has been halted. c. if no other interrupts occur before t he adc conversion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interrup t will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu wi ll remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering ot her sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 198 4.18.7.1 analog input circuitry the analog input circuitry for single ended channels is illust rated in figure 4-89. an analog source applied to adcn is subjected to the pin capacitance and input l eakage of that pin, regardless of whether t hat channel is selected as input for the adc. when the channel is selected, t he source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wi th an output impedance of approximately 10k or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimize s the required charge transfer to the s/h capacitor. signal components higher than the nyquist frequency (f adc /2) should not be present to avoid distortion from unpredictable signal convolution. the user is advised to remove high fr equency components with a low-pa ss filter before applying the signals as inputs to the adc. figure 4-89. analog input circuitry 4.18.7.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from hi gh-speed switching digital tracks. b. use the adc noise canceler function to reduce induced noise from the cpu. c. if any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. i il v cc /2 c s/h = 14pf i ih adcn 1 to 100k
199 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.7.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: offset: the deviation of the fi rst transition (0x000 to 0x001) compared to t he ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 4-90. offset error gain error: after adjusting for offset, the gain error is foun d as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5lsb below maximum). ideal value: 0 lsb figure 4-91. gain error offset error output code ideal adc actual adc v ref input voltage output code ideal adc actual adc v ref input voltage gain error
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 200 integral mon-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0lsb. figure 4-92. integral non-linearity (inl) differential non-linearity (dnl): the maxi mum deviation of the actual code widt h (the interval between two adjacent transitions) from the ideal code width (1lsb). ideal value: 0lsb. figure 4-93. differential non-linearity (dnl) quantization error: due to the quantization of the input voltage into a fini te number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5lsb. absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5lsb. output code ideal adc inl actual adc v ref input voltage output code 0x3ff 0x000 0 1 lsb dnl v ref input voltage
201 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.8 adc conversion result after the conversion is complete (adif is high), the conversi on result can be found in the adc result registers (adcl, adch). the form of the conversion result depends on the type of the conversion as there are three types of conversions: single ended conversion, unipolar differential conv ersion and bipolar differential conversion. 4.18.8.1 single ended conversion for single ended conversion, the result is: where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 4-58 on page 203 and table 4-59 on page 204 ). 0x000 represents analog ground, and 0x3ff represents the select ed voltage reference minus one lsb. the result is presented in one-sided form, from 0x3ff to 0x000. 4.18.8.2 unipolar differential conversion if differential channels and an unipolar input mode are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference (see table 4-58 on page 203 and table 4-59 on page 204 ). the voltage on the positive pin must always be larger than the voltage on the negative pin or ot herwise the voltage difference is saturated to zero. the result is presented in one- sided form, from 0x000 (0 d ) to 0x3ff (+1023 d ). the gain is either 8x or 20x. 4.18.8.3 bipolar differential conversion as default the adc converter oper ates in the unipolar input mo de, but the bipolar input mode can be selected by writing the bin bit in the adcsrb register to one. in the bipolar input mode two-sided volt age differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. if differential channels and a bipolar input mode are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (?512 d ) through 0x000 (+0 d ) to 0x1ff (+511 d ). the gain is either 8x or 20x. however, if the signal is not bipolar by nature (9 bits + si gn as the 10th bit), this scheme loses one bit of the converter dynamic range. then, if the user wants to perform the conversion with the maximum dynamic range, the user can perform a quick polarity check of the result and use the unipolar differential c onversion with selectable diff erential input pair. when t he polarity check is performed, it is sufficien t to read the msb of the result (adc9 in adch register). if the bit is one, the res ult is negative, and if this bit is zero, the result is positive. adc v in 1024 v ref --------------------------- = adc v pos v neg ? () 1024 v ref ------------------------------------------------------- - gain = adc v pos v neg ? () 512 v ref ---------------------------------------------------- - gain =
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 202 4.18.9 temperature measurement the temperature measurement is based on an on-chip temperature sens or that is coupled to a single ended adc input. mux[4..0] bits in admux register enables the temperature se nsor. the internal 1.1v voltage reference must also be selected for the adc voltage reference source in the temper ature sensor measurement. wh en the temperature sensor is enabled, the adc converter can be used in single conversion mode to measure th e voltage over the te mperature sensor. the measured voltage has a linear relationship to the temperature as described in table 4-56 . the voltage sensitivity is approximately 1lsb/c and the accuracy of the temperature m easurement is 10c using manufacturing calibration values (ts_gain, ts_offset). the values described in table 4-56 are typical values. however, due to the process variation the temperature sensor output vari es from one chip to another. 4.18.10 manufacturing calibration calibration values determined during test are available in the signature row. the temperature in degrees celsius can be calculated using the formula: where: a. adch & adcl are the adc data registers, b. is the temperature sensor gain c. tsoffset is the temperature sensor offset correction term ts_gain is the unsigned fixed point 8-bi t temperature sensor gain factor in 1/128th units stored in the signature row ts_offset is the signed twos complem ent temperature sensor offset reading stored in the signature row. see table 4-65 on page 219 for signature row parameter address. the following code example allows to read signature row data: .equ ts_gain = 0x0005 .equ ts_offset = 0x0003 ldi r30,low(ts_gain) ldi r31,high (ts_gain) rcall read_signature_row mov r17,r16; save r16 result ldi r30,low(ts_offset) ldi r31,high (ts_offset) rcall read_signature_row ; r16 holds ts_offset and r17 holds ts_gain read_signature_row: in r16,spmcsr; wait for spmen ready sbrc r16,spmen; exit loop here when spmcsr is free rjmp read_signature_row ldi r16,((1< 203 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.11 internal voltage reference output the internal voltage reference is output on xref pin as described in table 4-57 if the adc is turned on (see section 4.7.2.1 ?voltage reference enable signals and start-up time? on page 70 ). addition of an external filter capacitor (5 - 10nf) on xref pin may be necessary. xref current load must be from 1a to 100a with vcc from 2.7v to 5.5v for xref = 1.1v and with vcc from 4.5v to 5.5v for xref = 2.56v. xref pin can be coupled to an analog input of the adc. 4.18.12 register description 4.18.12.1 admux ? adc multip lexer select ion register ? bit 7:6 ? refs1:refs0: voltage reference selection bits these bits and arefen bit from the analog miscellaneous cont rol register (amiscr) select the voltage reference for the adc, as shown in table 4-58 . if these bits are changed during a conversion , the change will not go in effect until this conversion is complete (adif in adcsra register is set). whenever these bits ar e changed, the next conversion will take 25 adc clock cycles. if active channels are used, using avcc or an external aref higher than (avcc - 1v) is not recommended, as this will affect adc accuracy. the internal voltage reference options may not be used if an external voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adla r bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see section 4.18.12.3 ?adcl and adch ? the adc data register? on page 206 . ? bits 4:0 ? mux4:0: analog channel and gain selection bits these bits select which combination of analog inputs are connected to the adc. in case of differential input, gain selection is also made with th ese bits. refer to table 4-59 for details. if these bits are changed during a conversion, the change will not go into effect until this conversion is complete (adif in adcsra register is set). table 4-57. internal voltage reference output xrefen (1) refs1 (2) refs0 (3) voltage reference output (i load 100a) 0 x x hi-z, the pin can be used as aref input or other alternate functions. 1 (2) 0 1 xref = 1.1v (3) 1 (1) 1 1 xref = 2.56v (3)(4) notes: 1. see ?bit 1 ? xrefen: internal voltage reference output enable? on page 208. 2. see ?bit 7:6 ? refs1:refs0: voltage reference selection bits? on page 203. 3. in these configurations, the pin pull-up must be turned off and the pin digital output must be set in hi-z. 4. vcc in range 4.5 - 5.5v. bit 76543210 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 4-58. voltage refere nce selections for adc refs1 refs0 arefen voltage reference (v ref ) selection x 0 0 avcc used as voltage reference, disconnected from aref pin. x 0 1 external voltage reference at aref pin (aref 2.0v) 0 1 0 internal 1.1v voltage reference. 1 1 0 internal 2.56v voltage reference.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 204 table 4-59. input channel selections mux[4..0] single ended input positive differential input negative differential input gain 0 0000 adc0 (pa0) na na na 0 0001 adc1 (pa1) 0 0010 adc2 (pa2) 0 0011 adc3 / isrc (pa3) 0 0100 adc4 (pa4) 0 0101 adc5 (pa5) 0 0110 adc6 (pa6) 0 0111 adc7 / aref (pa7) 0 1000 adc8 (pb5) 0 1001 adc9 (pb6) 0 1010 adc10 (pb7) 0 1011 temperature sensor 0 1100 bandgap reference (1.1 v) 0 1101 avcc/4 0 1110 gnd (0v) 0 1111 (reserved) 1 0000 n/a adc0 (pa0) adc1 (pa1) 8x 1 0001 20x 1 0010 adc1 (pa1) adc2 (pa2) 8x 1 0011 20x 1 0100 adc2 (pa2) adc3 (pa3) 8x 1 0101 20x 1 0110 adc4 (pa4) adc5 (pa5) 8x 1 0111 20x 1 1000 adc5 (pa5) adc6 (pa6) 8x 1 1001 20x 1 1010 adc6 (pa6) adc7 (pa7) 8x 1 1011 20x 1 1100 adc8 (pb5) adc9 (pb6) 8x 1 1101 20x 1 1110 adc9 (pb6) adc10 (pb7) 8x 1 1111 20x
205 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.18.12.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, the adc is turned o ff. turning the adc off while a conversion i s in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free runni ng mode, write this bit to one to start the first conversion. the first conversion after adsc has been writt en after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto tr iggering of the adc is enabled . the adc will start a conversion on a positive edge of the selected trigger signal. the trigger s ource is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and th e data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be di sabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion comp lete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. bit 76543210 aden adsc adate adif adie a dps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 4-60. adc prescaler selections adps2 adps1 adps0 division factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 206 4.18.12.3 adcl and adch ? the adc data register adlar = 0 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated until adch is read. consequ ently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwis e, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is clea red (default), the resu lt is right adjusted. ? adc9:0: adc conversion result these bits represent the result fr om the conversion, as detailed in section 4.18.8 ?adc conversion result? on page 201 . 4.18.12.4 adcsrb ? adc control and status register b ? bit 7? bin: bipolar input mode the gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the bin bit in the adcsrb register. in the unipolar mode on ly one-sided conversions are supported an d the voltage on the positive input must always be larger than the voltage on the nega tive input. otherwise the result is saturated to the voltage reference. in the bipolar mode two-sided conversions are supported and the resu lt is represented in the two?s complement form. in the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. ? bit 3 ? res: reserved bit this bit is reserved for future use. for compatibility with future devices it must be written to zero when adcsrb register is written. bit 15 14 13 12 11 10 9 8 ? ? ? ? ? ? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 15 14 13 12 11 10 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 76543210 bin acme acir1 acir0 ? adts2 adts1 adts0 adcsrb read/write r/w r/w r/w r/w r r/w r/w r/w initial value00000000
207 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bits 2:0 ? adts2:0: adc auto trigger source if adate in adcsra register is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect . a conversion will be triggered by the rising edge of the selected interrupt flag. note th at switching from a trigger sour ce that is cleared to a trigger source that is set, will genera te a positive edge on the trigger signal. if aden in adcsra register is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not caus e a trigger event, even if th e adc interrupt flag is set . 4.18.12.5 didr0 ? digital input disable register 0 ? bits 7:0 ? adc7d:adc0d: adc7:0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. wh en an analog signal is applied to the adc7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer . 4.18.12.6 didr1 ? digital input disable register 1 ? bit 7 ? res: reserved bit this bit is reserved for future use. for compatibility with future devices it mu st be written to zero when didr1 register is written. ? bits 6..4 ? adc10d..adc8d: adc1 0..8 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. wh en an analog signal is applied to the adc10:8 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer . ? bits 3:0 - reserved bits these bits are reserved for future use. for compatibility with fu ture devices, they must be written to zero when didr1 is written. table 4-61. adc auto trig ger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter1 compare match a 1 0 0 timer/counter1 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 capture event 1 1 1 watchdog interrupt request bit 76543210 adc7d / ain1d adc6d / ain0d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 - adc10d adc9d adc8d - - - - didr1 read/write r r/w r/w r/w r r r r initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 208 4.18.12.7 amiscr ? analog miscellaneous control register ? bits 7:3 ? reserved bits these bits are reserved for future use. for compatibility with fu ture devices, they must be written to zero when amiscr is written. ? bit 2 ? arefen: external voltage reference input enable when this bit is written logic one, the voltage referenc e for the adc is input from aref pin as described in table 4.18.11 on page 203 . if active channels are used, using avcc or an external aref higher than (avcc - 1v) is not recommended, as this will affect adc accuracy. the internal voltage reference options may not be used if an external voltage is being applied to the aref pin. it is recommended to use didr register bit function (digital input disable) when arefen is set. ? bit 1 ? xrefen: internal voltage reference output enable when this bit is written logic one, the internal voltage re ference 1.1v or 2.56v is output on xref pin as described in table 4.18.11 on page 203 . it is recommended to use didr register bit function (digital input disable) when xrefen is set. bit 76543210 -----arefenxrefen isrcen amiscr read/write rrrrrr/wr/wr/w initial value00000000
209 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.19 anacomp - analog comparator the analog comparator compares the input values on the positive pin (ain1) and negative pin (ain0). when the voltage on the positive pin is higher than the volta ge on the negative pin, the analog comparator output, aco, is set. the comparator can trigger a separate interrupt, exclusive to the analog com parator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 4-94 . figure 4-94. analog comparator block diagram (1)(2) notes: 1. see table 4-63 on page 212 and table 4-64 on page 212 2. refer to table 4-24 on page 92 for analog comparator pin placement. interrupt sensivity control internal 2.56/ 1.1v reference ain1 (pa7) avcc acis1 adc multiplexer output (1) (from adc) aden acis0 aci acie 16-bit timer/ counter input capture analog comparator interrupt acme 1.1v 2.56v 2.56v /2 2.56v /4 2.56v /8 acirs acd refs0 refs1 acir0 acir1 + - aco ain0 (pa6)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 210 4.19.1 register description 4.19.1.1 adc control and st atus register b ? adcsrb ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched of f (aden in adcsra is zero), the adc multiplexer selects the positive input to the analog comparator. when this bit is written logic zero, ain1 is applied to the positive input of the anal og comparator. when the analog to digital converter (adc) is configured as si ngle ended input channel, it is possible to select any of the adc[10..0] pins to replace the positive input to the analog co mparator. the adc multiplexer (mu x[4..0]) is used to select this input, and consequently, the adc must be switched off to utilize this feature. ? bits 5, 4 ? acir1, acir0: analog comparator internal voltage reference select when acirs bit is set in adcsra register, these bits se lect a voltage reference for the negative input to the analog comparator, see table 4-64 on page 212 . 4.19.1.2 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog compar ator is switched off. this bit can be set at any time to turn off the analog comparator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit of acsr register. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acirs: analog comparator internal reference select when this bit is set an in ternal reference voltage replaces the negat ive input to the analog comparator (c.f. table 4-64 on page 212 ). if acirs is cleared, ain0 is applied to th e negative input to the analog comparator. ? bit 5 ? aco: analog comparator output the output of the analog compar ator is synchronized and then di rectly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is execut ed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the stat us register is set, the analog comparator interrupt is activate d. when written logic zero, the interrupt is disabled. bit 7 6543210 bin acme acir1 acir0 ? adts2 adts1 adts0 adcsrb read/write r r/w r/w r/w r r/w r/w r/w initial value0 0000000 bit 76543210 acd acirs aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000
211 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparator out put is in this case directly connected to the input capture front- end logic, making the comparator utilize the noise c anceler and edge select features of the timer/ counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and t he input capture function exists. to make the comparator trigger the timer/counter1 input capture in terrupt, the icie1 bit in th e timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger th e analog comparator interrupt. the different settings are shown in table 4-62 . 4.19.1.3 didr0 ? digital input disable register 0 ? bits 7,6 ? ain1d, ain0d: ain1d and ain0d digital input disable when this bit is written logic one, the digital input buffe r on the corresponding analog compare pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain0/1 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 4-62. acis1 / acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 0 1 reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge note: when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its inter- rupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. bit 76543210 adc7d / ain1d adc6d / ain0d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 212 4.19.2 analog comparator inputs 4.19.2.1 analog compare positive input it is possible to select any of the inputs of the adc positive input multiplexer to replace the positive input to the analog comparator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparat or multiplexer enable bit (acme in adcsrb r egister) is set and the adc is switched off (aden in adcsra register is zero), mux[ 4..0] in admux register select the input pin to replace the positive input to the analog comparator, as shown in table 4-63 . if acme is cleared or aden is set, ai n1 pin is applied to the positive input to the analog comparator. 4.19.2.2 analog compare negative input it is possible to select an internal voltage reference to repl ace the negative input to the anal og comparator. the output of a 2-bit dac using the internal voltage refer ence of the dac is available when acirs bit of acsr register is set. the voltage reference division factor is done by acir[1 ..0] of adcsrb register. if acirs is clea red, ain0 pin is applied to the negative input to the analog comparator. table 4-63. analog comparator positive input acme aden mux[4..0] analog comparator positive input - comment 0 x x xxxx b ain1 adc switched on x 1 x xxxx b ain1 1 0 0 0000 b adc0 adc switched off 1 0 0 0001 b adc1 1 0 0 0010 b adc2 1 0 0 0011 b adc3 / isrc 1 0 0 0100 b adc4 1 0 0 0101 b adc5 1 0 0 0110 b adc6 1 0 0 0111 b adc7 1 0 0 1000 b adc8 1 0 0 1001 b adc9 1 0 0 1010 b adc10 1 0 other this doesn?t make sense - don?t use table 4-64. analog comparator negative input acirs acir[1..0] refs[1..0] analog comparator negative input - comment 0 x x ain0 1 x 0 0 b 0 1 b 1 0 b reserved 1 0 0 b 1 1 b 2.56v - using internal 2.56v voltage reference 1 0 1 b 1 1 b 1.28v ( 1 / 2 of 2.56v) - using internal 2.56v voltage reference 1 1 0 b 1 1 b 0.64v ( 1 / 4 of 2.56v - using internal 2.56v voltage reference 1 1 1 b 1 1 b 0.32v ( 1 / 8 of 2.56v) - using internal 2.56v voltage reference
213 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.20 debugwire on-chip debug system 4.20.1 features complete program flow control emulates all on-chip functions, both digital and analog, except reset pin real-time operation symbolic debugging support (both at c and assembler source level, or for other hlls) unlimited number of program break points (using software break points) non-intrusive operation electrical characteristics identical to real device automatic configuration system high-speed operation programming of non-volatile memories 4.20.2 overview the debugwire on-chip debug system uses a one-wire, bi-direc tional interface to control the program flow, execute avr ? instructions in the cpu and to progra m the different non-volatile memories. 4.20.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is co nfigured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 4-95. the debugwire setup figure 4-95 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. when designing a system where debugwire will be used, the following observations must be made for correct operation: pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. connecting the reset pin directly to vcc will not work. capacitors connected to the reset pin must be disconnected when using debugwire. all external reset sources must be disconnected. gnd dw (reset) vcc dw +1.8 to +5.5v
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 214 4.20.4 software break points debugwire supports program memory break points by the avr ? break instruction. setting a break point in avr studio ? will insert a break instruction in the program memory. the in struction replaced by the break instruction will be stored. when program execution is continued, the stored instruction will be exec uted before continuing from the program memory. a break can be inserted manually by putti ng the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio through the debugwire interface. the use of brea k points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 4.20.5 limitations of debugwire the debugwire communicatio n pin (dw) is physically located on the same pi n as external reset (reset ). an external reset source is therefore not support ed when the debugwire is enabled. the debugwire system accurately em ulates all i/o functions when running at full sp eed, i.e., wh en the program in the cpu is running. when the cpu is stopped, care must be taken wh ile accessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enables some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 4.20.6 debugwire related register in i/o memory the following section describes th e registers used with the debugwire. 4.20.6.1 debugwire data register ? dwdr the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose regist er in the normal operations. bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
215 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.21 flash programming the device provides a self-programming mechanism for down loading and uploading program code by the mcu itself. the self-programming can use any available data interface (i.e. li n, usart, ...) and associated pr otocol to read code and write (program) that code into the program memory. the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a pag e erase and a page write operation: alternative 1, fill the buffer before a page erase fill temporary page buffer perform a page erase perform a page write alternative 2, fill the buffer after page erase perform a page erase fill temporary page buffer perform a page write if only a part of the page needs to be changed, the rest of the page must be st ored (for example in the temporary page buffer) before the erase, and then be re-written. when using al ternative 1, the boot loader provides an effective read-modify- write feature which allows the user software to first read the page, do the necessary c hanges, and then write back the modified data. if alternative 2 is used, it is not possible to read the old data while loading since the page is already erased . the temporary page buffer can be accessed in a random sequenc e. it is essential that the page address used in both the page erase and page write operati on is addressing the same page. 4.21.1 self-programming the flash 4.21.1.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?00000011 b ? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointe r will be ignored during this operation. the cpu is halted during the page erase operation. 4.21.1.2 filling the tempor ary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001 b ? to spmcsr and execute spm within four clock cycles after writing spmcsr. t he content of pcword in the z-register is used to address the data in the temporary buffer. the temp orary buffer will auto-erase after a page writ e operation or by writing the ctpb bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an sp m page load operation, all data loaded will be lost. 4.21.1.3 performing a page write to execute page write, set up the a ddress in the z-pointer, write ?00000101 b ? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be writt en to zero during this operation. the cpu is halted during the page write operation.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 216 4.21.2 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer c onsists of the z-registers zl and zh in the register file. the number of bits actually used is implementation dependent. since the flash is organized in pages (see table 4-73 on page 225 ), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addre ssing the words within a page, while the mos t significant bits are addressing the pages. this is shown in figure 4-96 . note that the page erase and page write o perations are addressed independently. ther efore it is of major importance that the software addresses the same page in both the page erase and page write operation. the lpm instruction uses the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 4-96. addressing the flash during spm (1) note: 1. the different variables used in table 4-66 are listed in table 4-73 on page 225 . bit 151413121110 9 8 z15 z14 z13 z12 z11 z10 z9 z8 zh (r31) z7 z6 z5 z4 z3 z2 z1 z0 zl (r30) bit76543210 pagemsb pcmsb zpcmsb 15 1 0 0 z-pointer bit zpagemsb word address within a page page address within the flash pcword pcpage page instruction word program memory page program counter 02 01 00 pageend pcword [pagemsb:0]
217 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.21.2.1 store program memory control and status register ? spmcsr the store program memory control and status register contains the control bits n eeded to control the boot loader operations. ? bit 7 ? res: reserved bit this bit is a reserved bit in the atmel ? attiny87/167 and will always read as zero. ? bit 6 ? rwwsb: read-while-write section busy this bit is for compatibility with device s supporting read-while-write. it will alwa ys read as zero in atmel attiny87/167. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within thr ee clock cycles will read a byte fr om the signature row into the destination register. see section 4.21.2.4 ?reading the signature row from software? on page 219 for details. an spm instruction within four cycles after sigrd and spmen are set will have no effect. ? bit 4 ? ctpb: clear temporary page buffer if the ctpb bit is written while filling the temporary page bu ffer, the temporary page buffer will be cleared and the data will be lost. ? bit 3 ? rflb: read fuse and lock bits an lpm instruction within three cycles af ter rflb and spmen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z- pointer) into the destination register. see section 4.21.2.3 ?reading the fuse and lock bits from software? on page 218 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the sa me time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completi on of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire p age write operation. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spme n, the next spm instru ction within four clo ck cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon completion of a page erase, or if no spm instru ction is executed within four cl ock cycles. the cpu is halted during the entire pag e write operation. ? bit 0 ? spmen: self programming enable this bit enables the spm instruct ion for the next four clock cycles. if written to one together wi th either sigrd, ctpb, rflb, pgwrt, or pgers, the following spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporar y page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto- clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10 0001 b ?, ?01 0001 b ?, ?00 1001 b ?, ?00 0101 b ?, ?00 0011 b ? or ?00 0001 b ? in the lower six bits will have no effect. note: only one spm instruction sh ould be active at any time. bit7654321 0 ? rwwsb sigrd ctpb rflb pgwrt pgers spmen spmcsr read/write r r r r/w r/w r/w r/w r/w initial value0000000 0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 218 4.21.2.2 eeprom write pre vents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operati on. it is recommended that t he user checks the status bit (eepe) in the eecr register and veri fies that the bit is cleared befo re writing to the spmcsr register. 4.21.2.3 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the rflb and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the rflb and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the rflb and spmen bits will auto-clear upon co mpletion of reading the lo ck bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within f our cpu cycles. when rflb and spmen are cl eared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the rflb and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the rf lb and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. see table 4-71 on page 224 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte (fhb), load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the rflb and spmen bits are set in the spm csr, the value of the fuse high byte will be loaded in the destination register as shown below. see table 4-70 on page 223 for detailed description and mapping of the fuse high byte. similarly, when reading the extended fuse byte (efb), load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the rflb and spmen bits are set in the spmcsr, the value of t he extended fuse byte will be loaded in the destination register as shown below. see table 4-69 on page 223 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero . fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 rd (z=0x0001) ??????lb2lb1 bit 76543210 rd (z=0x0000) flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd (z=0x0003) fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd (z=0x0002) ???????efb0
219 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.21.2.4 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 4-65 on page 219 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the sigrd and spmen bits are set in spmcsr, the signature byte value will be loaded in the des tination register. the sigrd and spmen bits will auto-clear upon completion of reading the signature row lock bits or if no lpm instruction is executed within three cpu cycles. when sigrd and spmen are cleared, lp m will work as described in the instruction set manual. 4.21.2.5 preventing flash corruption during periods of low vcc, the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply voltage for exec uting instructions is too low. flash corruption can easily be avoided by followin g these design recommendations (one is sufficient): 1. keep the avr ? reset active (low) during periods of insuffic ient power supply voltag e. this can be done by enabling the internal brown-out detector (bod) if the o perating voltage matches the detection level. if not, an external low vcc reset protection circuit can be used. if a reset occurs while a write op eration is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low vcc. this will prevent the cpu from attempt- ing to decode and execute instructions, effectively prot ecting the spmcsr register and thus the flash from unintentional writes. 4.21.2.6 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 4-66 shows the typical programming time for flash accesses from the cpu. table 4-65. signature row addressing signature byte z-pointer address device signature byte 0 0x0000 device signature byte 1 0x0002 device signature byte 2 0x0004 8mhz rc oscillator calibration byte 0x0001 tsoffset - temp sensor offset 0x0003 tsgain - temp sensor gain 0x0005 note: all other addresses are reserved for future use. table 4-66. spm programming time symbol min programming time max programming time flash write (page erase, pa ge write, and write lock bits by spm) 3.7ms 4.5ms
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 220 4.21.2.7 simple assembly code example for a boot loader note that the rwwsb bit will always be read as zero in atmel ? attiny87/167. nevertheless, it is recommended to check this bit as shown in the code example, to ensure co mpatibility with devices supp orting read-while-write. ;- the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y-pointer ; the first data location in flash is pointed to by the z-pointer ;- error handling is not included ;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcsrval (r20) ; -storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size .equ pagesizeb = pagesize*2 ; agesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcsrval, (1< 221 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 rdloop: lpm r0, z+ ld r1, y+ cpse r0, r1 rjmp error sbiw loophi:looplo, 1 ; use subi for pagesizeb<=256 brne rdloop ; to ensure compatibility with devices supporting read-while-write ; return to rww section ; verify that rww section is safe to read return: in temp1, spmcsr sbrs temp1, rwwsb ; if rwwsb is set, the rww section is not ready yet ret ; clear temporary page buffer ldi spmcsrval, (1< ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 222 4.22 memory programming 4.22.1 program and data memory lock bits the atmel ? attiny87/167 provides two lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 4-68 . the lock bits can only be erased to ?1 ? with the chip erase command. the atmel attiny87/167 has no separate boot loader section. table 4-67. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) 5 ? 1 (unprogrammed) 4 ? 1 (unprogrammed) 3 ? 1 (unprogrammed) 2 ? 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) note: 1. ?1? means unprogrammed, ?0? means programmed. table 4-68. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 2 1 0 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode (1) . 3 0 0 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode (1) . notes: 1. pro gram the fuse bits before programming th e lb1 and lb2 . 2. ?1? means unprogrammed, ?0? means programmed.
223 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.22.2 fuse bit the atmel ? attiny87/167 has three fuse bytes. table 4-69 , table 4-70 & table 4-71 describe briefly the f unctionality of all the fuses and how they are mapped into the fuse bytes. the spm instruction is enabled for the whole flash if the sel fprgen fuse is programmed (?0?), otherwise it is disabled. note that the fuses are read as logi cal zero, ?0?, if they are programmed. table 4-69. extended fuse byte fuse extended byte bit no description default value ? 7 ? 1 (unprogrammed) ? 6 ? 1 (unprogrammed) ? 5 ? 1 (unprogrammed) ? 4 ? 1 (unprogrammed) ? 3 ? 1 (unprogrammed) ? 2 ? 1 (unprogrammed) ? 1 ? 1 (unprogrammed) selfprgen 0 self programming enable 1 (unprogrammed) table 4-70. fuse high byte fuse high byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) notes: 1. see section 4.10.3.4 ?alternate functions of port b? on page 97 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see section 4.7.3.3 ?watchdog timer control register - wdtcr? on page 74 for details. 4. see table 4-85 on page 240 for bodlevel fuse coding.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 224 4.22.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. 4.22.3 signature bytes all atmel microcontrollers have a three-by te signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. 4.22.4 calibration byte the atmel ? attiny87/167 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this by te is automatically written in to the osccal register to ensure correct frequency of the calibrated rc oscillator. table 4-71. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) notes: 1. the default value of sut1..0 results in maxi mum start-up time for the default clock source. see table 4-8 on page 48 for details. 2. the default setting of cksel3..0 results in internal rc oscillator at 8mhz. see table 4-7 on page 48 for details. 3. the ckout fuse allows the system clock to be output on portb5. see section 4.5.2.7 ?clock output buffer? on page 52 for details. 4. see section 4.5.4 ?system clock prescaler? on page 58 for details. table 4-72. signature bytes device address value signature byte description attiny167 0 0x1e indicates manufactured by atmel 1 0x94 indicates 16kb flash memory 2 0x87 indicates attiny167 device when address 1 contains 0x94
225 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.22.5 page size 4.22.6 parallel programmi ng parameters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmel ? attiny87/167. pulses are assumed to be at least 250ns unless otherwise noted. 4.22.6.1 signal names in this section, some pins of the atmel attiny87/167 are refe renced by signal names describing their functionality during parallel programming, see figure 4-97 and figure 4-98 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xta l1 pin is given a positive pulse. the bit coding is shown in figure 4-76 . when pulsing wr or oe , the command loaded determines the action exec uted. the different commands are shown in figure 4-77 . figure 4-97. parallel programming note: vcc ? 0.3v < avcc < vcc + 0.3v, however, avcc should always be within 4.5 to 5.5v table 4-73. number of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb attiny87 4k words 64 words pc[5:0] 64 pc[11:6] 11 attiny167 8k words 64 words pc[5:0] 128 pc[12:6] 12 table 4-74. number of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb attiny87 attiny167 512bytes 4bytes eea[1:0] 128 eea[8:2] 8 gnd pb0 pb1 pb2 pb3 xtal1/ pb4 dat a pb5 pb6 reset/ pb7 vcc avcc pb7 to pb0 +4.5 to +5.5v +4.5 to +5.5v wr oe rdy/ bsy xa1/ bs2 xa0 pagel/ bs1 +12v
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 226 figure 4-98. pin name mapping signal name in programming mode pin name i/o function wr pb0 i write pulse (active low). xa0 pb1 i xtal1 action bit 0 xa1 / bs2 pb2 i - xtal1 action bit 1 - byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) pagel / bs1 pb3 i - program memory and eeprom data page load - byte select 1 ( 0? selects low byte, ?1? selects high byte) pb4 i xtal1 (clock input) oe pb5 i output enable (active low). rdy / bsy pb6 o 0: device is busy programming, 1: device is ready for new command. +12v pb7 i - reset (active low) - parallel programming mode (+12v). data pa7-pa0 i/o bi-directional data bus (output when oe is low). table 4-75. pin values used to enter programming mode pin symbol value pagel / bs1 prog_enable[3] 0 xa1 / bs2 prog_enable[2] 0 xa0 prog_enable[1] 0 wr prog_enable[0] 0 table 4-76. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 4-77. command byte bit coding command byte command executed 1000 0000 b chip erase 0100 0000 b write fuse bits 0010 0000 b write lock bits 0001 0000 b write flash 0001 0001 b write eeprom 0000 1000 b read signature bytes and calibration byte 0000 0100 b read fuse and lock bits 0000 0010 b read flash 0000 0011 b read eeprom
227 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.22.7 parallel programming 4.22.7.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 4.5 - 5.5v between vcc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 4-75 on page 226 to ?0000 b ? and wait at least 100ns. 4. apply 11.5 - 12.5v to reset. any activity on prog_enable pins within 100ns after +12v has been applied to reset, will cause the device to fail entering programming mode. 5. wait at least 50s before sending a new command. 4.22.7.2 considerations for efficient programming the loaded command and address are retained in the device dur ing programming. for efficient programming, the following should be considered. the command needs only be loaded once when writing or reading multiple memory locations. skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 4.22.7.3 chip erase the chip erase will er ase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are no t changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?1,0 ?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000 b ?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this star ts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 4.22.7.4 programming the flash the flash is organized in pages, see table 4-73 on page 225 . when programming the flash, t he program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?1,0?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000 b ?. this is the command for write flash. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 228 c. load data low byte 1. set xa1, xa0 to ?0,1?. th is enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?0,1?. th is enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 4-100 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words wi thin the page, the higher bits address the pages within the flash. this is illustrated in figure 4-99 on page 228 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the ad dress low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?0,0?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programm ing of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 4-100 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. set xa1, xa0 to ?1,0?. this enables command loading. 2. set data to ?0000 0000 b ?. this is the comma nd for no operation. 3. give xtal1 a positive pulse. this loads the co mmand, and the internal write signals are reset. figure 4-99. addressing the flash which is organized in pages pagemsb pcmsb word address within a page page address within the flash pcword pcpage page instruction word program memory page program counter 02 01 00 pageend pcword [pagemsb:0]
229 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-100. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. 4.22.7.5 programming the eeprom the eeprom is organized in pages, see table 4-74 on page 225 . when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command, address and data loading): a: load command ?0001 0001 b ?. g: load address high byte (0x00 - 0xff). b: load address low byte (0x00 - 0xff). c: load data (0x00 - 0xff). e: latch data (give pagel a positive pulse). k: repeat a through e until the entire buffer is filled. l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 4-101 for signal waveforms). figure 4-101. pr ogramming the eepr om waveforms xtal1 rdy/ bsy oe reset +12v pagel/ bs1 xa0 xa1/ bs2 data abcdebcd f e gh 0x10 xx xx xx addr. high addr. low addr. low data high data high data low data low wr xtal rdy/ bsy oe reset +12v pagel/ bs1 xa0 xa1/ bs2 data wr abcebc k e g addr. high addr. low 0x11 data xx addr. low data xx l
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 230 4.22.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and address loading): 1. a: load command ?0000 0010 b ?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 4.22.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and address loading): 1. a: load command ?0000 0011 b ?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 4.22.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and data loading): 1. a: load command ?0100 0000 b ?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 4.22.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and data loading): 1. a: load command ?0100 0000 b ?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 4.22.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and data loading): 1. a: load command ?0100 0000 b ?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2 to ?0?. this selects low data byte.
231 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-102. programm ing the fuses waveforms 4.22.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to section 4.22.7.4 ?programmi ng the flash? on page 227 for details on command and data loading): 1. a: load command ?0010 0000 b ?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is pro- grammed), it is not possible to re-program th e lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. 4. the lock bits can only be cleared by executing chip erase. 4.22.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command loading): 1. a: load command ?0000 0100 b ?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of t he fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. xtal1 rdy/ bsy oe reset +12v pagel/ bs1 xa0 xa1/ bs2 data wr ac 0x40 dat a xx ac dat a dat a xx xx ac 0x40 0x40 write fuse low byte write fuse high byte write extended fuse byte
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 232 figure 4-103. mapping between bs1, bs2 an d the fuse and lock bits during read 4.22.7.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and address loading): 1. a: load command ?0000 1000 b ?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 4.22.7.14 reading the 8mhz rc oscillator calibration byte the algorithm for reading the 8mhz rc oscillator calibration byte is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and address loading): 1. a: load command ?0000 1000 b ?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the 8mhz rc oscillat or calibration byte can now be read at data. 4. set oe to ?1?. 4.22.7.15 reading the temperature sensor parameter bytes the algorithm for reading the te mperature sensor parameter by tes is as follows (refer to section 4.22.7.4 ?programming the flash? on page 227 for details on command and address loading): 1. a: load command ?0000 1000 b ?. 2. b: load address low byte, 0x0003 or 0x0005. 3. set oe to ?0?, and bs1 to ?1?. the temperature sensor parameter byte can now be read at data. 4. set oe to ?1?. fuse low byte extended fuse byte bs2 1 0 1 0 lock bits fuse high byte bs2 bs1 data 1 0
233 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.22.8 serial downloading both the flash and eeprom memory arrays can be programmed usi ng the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note: in table 4-78 , the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. figure 4-104. serial programming and verify (1) note: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only ) and there is no need to first execute the chip erase instru ction. the chip erase operatio n turns the content of every memory location in both the prog ram and eeprom arrays into 0xff. depending on cksel fuses, a vali d clock must be present. the minimum low an d high periods for the serial clock (sck) input are defined as follows: low : > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz hi gh : > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz table 4-78. pin mapping serial programming symbol pin name i/o function mosi pa4 i serial data in miso pa2 o serial data out sck pa5 i serial clock gnd pa5 pa2 reset/ pb7 vcc mosi miso sck +2.7 to +5.5v pa4
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 234 4.22.8.1 serial pr ogramming algorithm when writing serial data to the atmel ? attiny87/167, data is clocked on the rising edge of sck. when reading data from the atmel attiny87/167, data is clocked on the falling edge of sck. see figure 4-104 and figure 4-105 for timing details. to program and verify the atmel attiny87/167 in the seri al programming mode, the following sequence is recommended (see four byte instruction formats in table 4-80 on page 235 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in so me systems, the programmer can not guarantee that sck is held low dur ing power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles durati on after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if t he communication is out of syn chronization. when in sync. the second byte (0x53), will echo back when issuing the thir d byte of the programming enable instruction. whether the echo is correct or not, all four byte s of the instruction must be transmitt ed. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 5lsb of the address and data together with the load pr ogram memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before dat a high byte is applied for a given address. the program memory page is stored by loading the write program memo ry page instruction with th e 6msb of the address. if polling (rdy/bsy) is not used, the user must wait at least t wd_flash before issuing the next page (see table 4-79 ). accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically eras ed before new data is writ- ten. if polling (rdy/bsy) is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 4-79 ). in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by sup- plying the 2lsb of the address and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading the write eeprom memo ry page instruction with the 6msb of t he address. when using eeprom page access only byte locations l oaded with the load eeprom me mory page instruction is altered. the remaining locations remain unchanged. if polling (rdy/bsy) is not used, the used must wait at least t wd_eeprom before issuing the next page (see table 4-74 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn vcc power off. table 4-79. minimum wait delay before writ ing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 4.0ms t wd_erase 4.0ms t wd_fuse 4.5ms
235 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.22.8.2 serial progra mming instruction set table 4-80 on page 235 and figure 4-105 on page 236 describes the instruction set table 4-80. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable 0xac 0x53 0x00 0x00 chip erase (program memory/eeprom) 0xac 0x80 0x00 0x00 poll rdy/bsy 0xf0 0x00 0x00 data byte out load instructions load extended address byte (1) 0x4d 0x00 extended add. 0x00 load program memory page, high byte 0x48 add. msb add. lsb high data byte in load program memory page, low byte 0x40 add. msb add. lsb low data byte in load eeprom memory page (page access) 0xc1 0x00 0000 000aa b data byte in read instructions read program memory, high byte 0x28 add. msb add. lsb high data byte out read program memory, low byte 0x20 add. msb add. lsb low data byte out read eeprom memory 0xa0 0x00 00aa aaaa data byte out read lock bits 0x58 0x00 0x00 data byte out read signature byte 0x30 0x00 0000 000aa data byte out read fuse bits 0x50 0x00 0x00 data byte out read fuse high bits 0x58 0x08 0x00 data byte out read extended fuse bits 0x50 0x08 0x00 data byte out read calibration byte 0x38 0x00 0x00 data byte out write instructions (6) write program memory page 0x4c add. msb add. lsb 0x00 write eeprom memory 0xc0 0x00 00aa aaaa b data byte in write eeprom memory page (page access) 0xc2 0x00 00aa aa00 b 0x00 write lock bits 0xac 0xe0 0x00 data byte in write fuse bits 0xac 0xa0 0x00 data byte in write fuse high bits 0xac 0xa8 0x00 data byte in write extended fuse bits 0xac 0xa4 0x00 data byte in notes: 1. not all instructions are applicable for all parts. 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?). 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word a ddress. this address may be random within the page range. 7. see http://www.atmel.com/avr for applicat ion notes regarding programming and programmers.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 236 if the lsb in rdy/bsy data byte out is ?1?, a programming oper ation is still pending. wait until this bit returns ?0? before th e next instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buffer, program the eeprom page, see figure 4-105 . figure 4-105. serial progra mming instruction example 4.22.9 serial progra mming characteristics figure 4-106. serial programming waveforms for characteristics of the spi module, see section 4.23.8 ?spi timing characteristics? on page 245 . addr msb bit 15 b bit 15 b 0 0 load program memory page (high/low byte) load eeprom memory page (page access) write program memory page/ write eeprom memory page byte 1byte 2byte 3byte 4 page 0 page 1 page 2 page n-1 byte 1 byte 2 byte 3 byte 4 addr lsb page offset page number addr msb addr lsb page buffer serial programming instruction program memory/ eeprom memory msb serial data input (mosi) serial data output (miso) msb lsb lsb serial clock input (sck) sample
237 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.23 electrical characteristics note: all characteristics contained in this data sheet are based on simulation and characterization of atmel ? attiny87/167 avr ? microcontrollers manufactured in a typical pr ocess technology. these values are prelimi- nary values representing design targets, and will be updated after characterization of actual automotive silicon. 4.23.1 dc characteristics t a = ?40c to +125c, vcc = 2.7v to 5.5v (unless otherwise noted) parameters test conditions symbol min. typ. (1) max. unit input low voltage except xtal1 and reset pins v il ?0.5 0.2 vcc (2) v xtal1 pin - external clock selected v il1 ?0.5 0.1 vcc (2) v reset pin v il2 ?0.5 0.2 vcc (2) v reset pin as i/o v il3 ?0.5 0.2 vcc (2) v input high voltage except xtal1 and reset pins v ih 0.7 vcc (3) vcc + 0.5 v xtal1 pin - external clock selected v ih1 0.8 vcc (3) vcc + 0.5 v reset pin v ih2 0.9 vcc (3) vcc + 0.5 v reset pin as i/o v ih3 0.7 vcc (3) vcc + 0.5 v output low voltage (4) (ports a, b,) i ol = 10ma, vcc = 5v i ol = 5ma, vcc = 3v v ol 0.6 0.5 v output high voltage (5) (ports a, b) i oh = ?10ma, vcc = 5v i oh = ?5ma, vcc = 3v v oh 4.3 2.5 v input leakage current i/o pin vcc = 5.5v, pin low (absolute value) i il < 0.05 1 a input leakage current i/o pin vcc = 5.5v, pin high (absolute value) i ih < 0.05 1 a reset pull-up resistor r rst 30 60 k i/o pin pull-up resistor r pu 20 50 k notes: 1. ?typ.?, typical values at 25c. maximum values are characterized values and not test limits in production. 2. ?max.? means the highest value where t he pin is guaranteed to be read as low. 3. ?min.? means the lowest value where the pin is guaranteed to be read as high. 4. although each i/o port can sink more than the test conditio ns (10ma at vcc = 5v, 5ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: the sum of all iol, for all ports, should not exceed 120ma. if iol exceeds the test condition, vol may exceed the relate d specification. pins are not guaranteed to sink current greater than the listed test condition. 5. although each i/o port can source more than the test co nditions (10ma at vcc = 5v, 5ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: the sum of all ioh, for all ports, should not exceed 120ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 6. values using methods described in section 4.6.8 ?minimizing power consumption? on page 64 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 7. bod disabled.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 238 figure 4-107. maximum frequency versus vcc, atmel attiny87/167 power supply current (6) active mode (external clock) 16mhz, vcc = 5v i cc 10 13 ma 8mhz, vcc = 5v 5.5 7.0 ma 8mhz, vcc = 3v 2.8 3.5 ma 4mhz, vcc = 3v 1.8 2.5 ma power supply current (6) idle mode (external clock) 16mhz, vcc = 5v 3.5 5.0 ma 8mhz, vcc = 5v 1.8 2.5 ma 8mhz, vcc = 3v 1 1.5 ma 4mhz, vcc = 3v 0.5 0.8 ma power supply current (7) power-down mode wdt enabled, vcc = 5v 7 100 a wdt disabled, vcc = 5v 0.18 70 a wdt enabled, vcc = 3v 5 70 a wdt disabled, vcc = 3v 0.15 45 a analog comparator input offset voltage vcc = 5v v in = vcc/2 v acio ?10 +10 +40 mv analog comparator input leakage current vcc = 5v v in = vcc/2 i aclk ?50 +50 na analog comparator propagation delay common mode vcc/2 vcc = 2.7v t acid 170 ns vcc = 5.0v 180 ns 4.23.1 dc characteristics (continued) t a = ?40c to +125c, vcc = 2.7v to 5.5v (unless otherwise noted) parameters test conditions symbol min. typ. (1) max. unit notes: 1. ?typ.?, typical values at 25c. maximum values are characterized values and not test limits in production. 2. ?max.? means the highest value where t he pin is guaranteed to be read as low. 3. ?min.? means the lowest value where the pin is guaranteed to be read as high. 4. although each i/o port can sink more than the test conditio ns (10ma at vcc = 5v, 5ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: the sum of all iol, for all ports, should not exceed 120ma. if iol exceeds the test condition, vol may exceed the relate d specification. pins are not guaranteed to sink current greater than the listed test condition. 5. although each i/o port can source more than the test co nditions (10ma at vcc = 5v, 5ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: the sum of all ioh, for all ports, should not exceed 120ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 6. values using methods described in section 4.6.8 ?minimizing power consumption? on page 64 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 7. bod disabled. 16mhz 2.7v 4.5v safe operating area 5.5v 8mhz frequency voltage
239 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.23.2 clock characteristics 4.23.2.1 calibrate d internal rc oscillator accuracy 4.23.2.2 external clock drive waveforms figure 4-108. external clock drive waveforms 4.23.2.3 external clock drive 4.23.3 reset ch aracteristics table 4-81. calibration and accuracy of internal rc oscillator frequency vcc temperature accuracy factory calibration 8.0mhz 5v 25c 2% t chcx v ih1 v il1 t chcx t clch t chcl t clcx t clcl table 4-82. external clock drive parameter symbol vcc = 2.7 - 5.5v vcc = 4.5 - 5.5v unit min. max. min. max. oscillator frequency 1/t clcl 0 8 0 16 mhz clock period t clcl 125 62.5 ns high time t chcx 50 25 ns low time t clcx 50 25 ns rise time t clch 1.6 0.5 ms fall time t chcl 1.6 0.5 ms change in period from one clock cycle to the next t clcl 2 2 % table 4-83. external reset characteristics parameter condition symbol min typ max unit reset pin threshold voltage v cc = 5v v rst 0.1 vcc 0.9 vcc v minimum pulse width on reset pin v cc = 5v t rst 2.5 s bandgap reference voltage v cc = 2.7v, t a =25c v bg 1.0 1.1 1.2 v bandgap reference start-up time v cc = 2.7v, t a =25c t bg 40 70 s bandgap reference current consumption v cc = 2.7v, t a =25c i bg 15 a
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 240 4.23.4 internal voltage characteristics table 4-84. power on reset characteristics parameter symbol min typ max unit power-on reset threshold voltage (rising) v pot 1.0 1.4 v power-on reset threshold voltage (falling) (1) 0.9 1.3 v vcc maximum start voltage to ensure internal power-on reset signal v pormax 0.4 v vcc minimum start voltage to en sure internal power-on reset signal v pormin ?0.1 v vcc rise rate to ensure power-on reset v ccrr 0.01 v/ms reset pin threshold voltage v rst 0.1 vcc 0.9 vcc v note: 1. before rising, the supply has to be between vpormin and vpormax to ensure a reset. table 4-85. bodlevel fuse coding bodlevel 2:0 fuses min. v bot (1) typ. v bot max. v bot unit 1 1 1 b bod disabled 1 1 0 b 1.7 1.8 2.0 v 1 0 1 b 2.5 2.7 2.9 1 0 0 b 4.1 4.3 4.5 0 1 1 b reserved 0 1 0 b 0 0 1 b 0 0 0 b note: 1. v bot may be below nominal minimum operating voltage for so me devices. for devices where this is the case, the device is tested down to vcc = v bot during the production test. this guarantees that a brown-out reset will occur before vcc drops to a voltage where correct ope ration of the microcontrolle r is no longer guaranteed. the test is performed using bodlevel = 101 for low operating voltage and bodlevel = 100 for high oper- ating voltage. table 4-86. brown-out characteristics parameter symbol min. typ. max. unit brown-out detector hysteresis v hyst 80 mv min pulse width on brown-out reset t bod 2 s table 4-87. internal voltage reference characteristics parameter condition symbol min. typ. max. unit bandgap reference voltage vcc = 4.5 t a =25c v bg 1.0 1.1 1.2 v bandgap reference start-up time vcc = 4.5 t a =25c t bg 40 70 s bandgap reference current consumption vcc = 4.5 t a =25c i bg 10 a
241 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.23.5 current source characteristics 4.23.6 adc characteristics table 4-88. current source characteristics parameter condition symbol min. typ. max. unit current vcc = 2.7 v / 5.5 v t = -40c / +125c i isrc 94 106 a current source start-up time vcc = 4.5 t a = 25c t isrc 60 s table 4-89. adc characteri stics, single ended channels (-40c/+125c) parameter condition symbol min typ max unit resolution single ended conversion 10 bits absolute accuracy vcc = 4v, vref = 4v, adc clock = 200khz tue 2.0 3.5 lsb integral non linearity vcc = 4v, vref = 4v, adc clock = 200khz inl 0.6 2.0 lsb differential non linearity vcc = 4v, vref = 4v, adc clock = 200khz dnl 0.3 0.8 lsb gain error vcc = 4v, vref = 4v, adc clock = 200khz ?6.0 ?2.5 2.0 lsb offset error vcc = 4v, vref = 4v, adc clock = 200khz ?3.5 1.5 3.5 lsb ref voltage v ref 2.56 avcc v input bandwidth 38.5 khz internal voltage v int 2.4 2.56 2.7 v reference input resistance r ref 32 k analog input resistance r ain 100 m table 4-90. adc characteri stics, differential channels (?40c/+125c) parameter condition symbol min typ max unit resolution differential conversion 8 absolute accuracy gain = 8x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz tue 1.0 3.0 lsb gain = 20x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz 1.5 3.5 gain = 8x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 2.0 4.5 gain = 20x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 2.0 6.0
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 242 integral non linearity gain = 8x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz inl 0.2 1.0 lsb gain = 20x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz 0.4 1.5 gain = 8x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 0.5 2.0 gain = 20x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 1.6 5.0 differential non linearity gain = 8x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz dnl 0.3 0.8 lsb gain = 20x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz 0.3 0.8 gain = 8x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 0.4 0.8 gain = 20x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz 0.6 1.6 gain error gain = 8x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz ?3.0 1.0 3.0 lsb gain = 20x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz ?4.0 1.5 4.0 gain = 8x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz ?5.0 ?2.5 0.0 gain = 20x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz ?4.0 ?0.5 4.0 offset error gain = 8x or 20x, bipolar v ref = 4v, vcc = 5v adc clock = 200khz ?2.0 0.5 2.0 lsb gain = 8x or 20x, unipolar v ref = 4v, vcc = 5v adc clock = 200khz ?2.0 0.5 2.0 reference voltage v ref 2.56 avcc ? 0.5 v input differential voltage vdiff ?vref/gain +vref/gain v analog supply voltage avcc vcc ? 0.3 vcc + 0.3 v input voltage differential conversion vin 0 avcc v adc conversion output ?511 +511 lsb input bandwidth differential conversion 4 khz internal voltage reference vint 2.4 2.56 2.7 v reference input resistance rref 32 k analog input resistance rain 100 m table 4-90. adc characte ristics, differential channels (?40c/+125c) (continued) parameter condition symbol min typ max unit
243 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.23.7 parallel programming characteristics figure 4-109. parallel programmi ng timing, including some general timing requirements figure 4-110. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 4-109 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. xtal1 wr rdy/ bsy data and control (data, xa0, xa1/ bs2, pagel/ bs1) t xhxl t xlwl t dvxh t bvph t plbx t bvwl t wlbx t plwl t wlwh t rlrh t wlrh t xldx xtal1 pagel/ bs1 data xa0 xa1/ bs2 t xlxh load address (low byte) load data (low byte) load data (high byte) load address (low byte) addr0 (low byte) addr1 (low byte) data (low byte) data (high byte)
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 244 figure 4-111. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 4-109 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 pagel/ bs1 data oe xa0 xa1/ bs2 t xlol t oldv t ohdz t bvdv load address (low byte) load data (low byte) read data (high byte) load address (low byte) addr0 (low byte) addr1 (low byte) data (low byte) data (high byte) table 4-91. parallel programmi ng characteristics, v cc = 5v 10% parameter symbol min typ max unit programming enable voltage v pp 11.5 12.5 v programming enable current i pp 250 a data and control valid before xtal1 high t dvxh 67 ns xtal1 low to xtal1 high t xlxh 200 ns xtal1 pulse width high t xhxl 150 ns data and control hold after xtal1 low t xldx 67 ns xtal1 low to wr low t xlwl 0 ns bs1 valid before pagel high t bvph 67 ns bs1 hold after pagel low t plbx 67 ns bs2/1 hold after wr low t wlbx 67 ns pagel low to wr low t plwl 67 ns bs1 valid to wr low t bvwl 67 ns wr pulse width low t wlwh 150 ns wr low to rdy/bsy low t wlrl 0 1 s wr low to rdy/bsy high (1) t wlrh 3.7 4.5 ms wr low to rdy/bsy high for chip erase (2) t wlrh_ce 7.5 9 ms xtal1 low to oe low t xlol 0 ns bs1 valid to data valid t bvdv 0 250 ns oe low to data valid t oldv 250 ns oe high to data tri-stated t ohdz 250 ns notes: 1. t wlrh is valid for the write flash, write eeprom, wr ite fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command.
245 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.23.8 spi timing characteristics see figure 4-112 and figure 4-113 for details. figure 4-112. spi interface timi ng requirements (master mode) table 4-92. spi timing parameters no. description mode min. typ. max. unit 1 sck period master see table 4-43 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 s 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck note: in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12mhz - 3 t clcl for f ck >12mhz 6 msb ss sck (cpol = 0) sck (cpol = 1) miso (data input) mosi (data output) msb lsb lsb ... ... 45 8 7 1 2 2 3
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 246 figure 4-113. spi interface timing requirements (slave mode) 4.24 decoupling capacitors the operating frequency (i.e. system cl ock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. the hypotheses used as first evaluation for decoupling capacitors are: the operating frequency ( f op ) supplies itself the maximum peak levels of noise. the main peaks are located at f op and 2 f op . an smc capacitor connected to 2 micro-vias on a pcb has the following characteristics: 1.5 nh from the connection of the capacitor to the pcb, 1.5 nh from the capacitor intrinsic inductance. figure 4-114. capacitor description according to the operating frequency of the product, the de coupling capacitances are chosen considering the frequencies to filter, f op and 2 f op . the relation between frequencies to cut and decoupling characteristics are defined by: and where: l: the inductance equivalent to the global inductance on the vcc/gnd lines. c 1 & c 2 : decoupling capacitors (c 1 = 4 c 2 ). 9 msb ss sck (cpol = 0) sck (cpol = 1) mosi (data input) miso (data output) msb lsb lsb ... ... 13 14 17 18 15 10 16 11 11 12 pcb capacitor 1.5nh 0.75nh 0.75nh fop 1 2 lc 1 -------------------- - = 2fop 1 2 lc 2 -------------------- - =
247 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 then, in normalized value range, the decoupling capacitors become: these decoupling capacitors must to be implemented as cl ose as possible to each pair of power supply pins: 16-17 for logic sub-system, 5-6 for analogical sub-system. nevertheless, a bulk capacitor of 10-47f is also needed on the power distribution network of the pcb, near the power source. for further information, please refer to application notes avr040 ?emc design considerations? and avr042 ?hardware design considerations? on the atmel web site. table 4-93. decoupling capacitors versus frequency fop, operating frequency c 1 c 2 16mhz 33nf 10nf 12mhz 56nf 15nf 10mhz 82nf 22nf 8mhz 120nf 33nf 6mhz 220nf 56nf 4mhz 560nf 120nf
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 248 4.25 typical characteristics the data contained in this section is largely based on simu lations and characterization of similar devices in the same process and design methods. thus, the data should be treated as indications of how the part will behave. the following charts show typical behavior. these figures ar e not tested during manufactur ing. all current consumption measurements are performed with all i/o pi ns configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating fr equency, loading of i/o pins, switching rate of i/o pins, code exec uted and ambient temperature. the dominat ing factors are operating voltage and frequency. the current drawn from capacitive loaded pi ns may be estimated (for one pin) as c l vcc f where c l = load capacitance, vcc = operating voltage and f = aver age switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are no t guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. 4.25.1 active supply current figure 4-115. active supply current versus low frequency (0.1 - 1.0mhz) figure 4-116. active supply current versus frequency ( 1mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.1 2.0 frequency (mhz) i cc (ma) 1.8 1.6 0 2 4 6 8 10 12 14 16 18 20 14 16 12 10 8 6 4 2 0 frequency (mhz) i cc (ma) 6.0 5.5 5.0 4.5 4.5 3.6 3.3 3.0 2.7 2.4
249 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-117. active supply current versus v cc (internal rc oscillator, 8mhz) figure 4-118. active supply current versus v cc (internal rc osci llator, 128khz) 4.25.2 idle supply current figure 4-119. idle supply current versus frequency ( 1mhz) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 8 9 7 6 5 4 3 2 1 0 i cc (ma) v cc (v) 150 125 85 25 -40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.18 0.20 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 i cc (ma) v cc (v) 150 125 85 25 -40 0 2 4 6 8 10 12 14 16 18 20 9 10 8 7 6 5 4 3 2 1 0 frequency (mhz) i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 250 figure 4-120. idle supply current versus v cc (internal rc oscillator, 8mhz) figure 4-121. idle supply current versus 5v cc (internal rc oscillator, 128khz) 2.5 2 1.5 1 0.5 0 3 i cc (ma) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 150 125 85 25 -40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.07 0.08 0.06 0.05 0.04 0.03 0.02 0.01 0 i cc (ma) v cc (v) 150 125 85 25 -40
251 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.25.3 supply current of i/o modules the table below can be used to calculate the additional current consumption for the different i/o modules idle mode. the enabling or disabling of the i/o modules are co ntrolled by the power reduction register. see section 4.6.9.3 ?prr ? power reduction register? on page 66 for details. 4.25.4 power-down supply current figure 4-122. power-down supply current versus v cc (watchdog timer disabled) figure 4-123. power-down supply current versus v cc (watchdog timer enabled) table 4-94. additional current consumption for the different i/o modules (absolute values) module vcc = 5.0v freq. = 16mhz vcc = 5.0v freq. = 8mhz vcc = 3.0v freq. = 8mhz vcc = 3.0v freq. = 4mhz unit lin/uart 0.77 0.37 0.20 0.10 ma spi 0.31 0.14 0.08 0.04 ma timer-1 0.28 0.13 0.08 0.04 ma timer-0 0.41 0.20 0.10 0.05 ma usi 0.14 0.05 0.04 0.02 ma adc 0.48 0.22 0.10 0.05 ma 1.5 2 2.5 3 3.5 4 4.5 5 5.5 25 30 20 15 10 5 0 i cc (a) v cc (v) 150 125 85 25 -40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 35 40 30 25 20 15 10 5 0 i cc (a) v cc (v) 150 125 85 25 -40
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 252 4.25.5 pin pull-up figure 4-124. i/o pin pull-up resist or current versus input voltage (v cc = 2.7v) figure 4-125. i/o pin pull-up resist or current versus input voltage (v cc = 5v) figure 4-126. reset pull-up resistor current versus reset pin voltage (v cc = 2.7v) 00.5 1.5 122.53 80 90 70 60 50 40 30 20 10 0 -10 i op (a) v op (v) 150 125 85 25 -40 01 3 2 456 140 160 120 100 80 60 40 20 0 -20 i op (a) v op (v) 150 125 85 25 -40 00.5 1.5 122.53 70 60 50 40 30 20 10 0 -10 i reset (a) v reset (v) 150 125 85 25 -40
253 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-127. reset pull-up resistor current versus reset pin voltage (v cc = 5v) 4.25.6 pin driver strength figure 4-128. i/o pin output voltage versus sink current (v cc = 3v) figure 4-129. i/o pin output voltage versus sink current (v cc = 5v) 01 3 2456 120 100 80 60 40 20 0 -20 i reset (a) v reset (v) 150 125 85 25 -40 02 4681012141618 1.8 2.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v ol (v) i ol (ma) 150 125 85 25 -40 0 5 10 15 20 25 1.2 1.0 0.8 0.6 0.4 0.2 0 v ol (v) i ol (ma) 150 125 85 25 -40
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 254 figure 4-130. i/o pin output vo ltage versus source current (v cc = 3v) figure 4-131. i/o pin output vo ltage versus source current (v cc = 5v) 4.25.7 internal oscillator speed figure 4-132. calibrated 8.0mhz rc oscillator frequency versus vcc 0 2 4 6 8 10 12 14 16 18 20 3.0 2.5 2.0 1.5 1.0 0.5 0 v oh (v) i oh (ma) 150 125 85 25 -40 0 2 4 6 8 1012 14161820 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 v oh (v) i oh (ma) 150 125 85 25 -40
255 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 4-133. calibrated 8.0mhz rc oscillator frequency versus osccal value 4.25.8 current consumption in reset figure 4-134. reset supply current ver sus vcc, frequencies 0.1 - 1.0mhz (excluding current through the reset pull-up) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.30 0.25 0.20 0.15 0.10 0.05 0 i cc (ma) frequency (mhz) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.1 2.0 1.8 1.6
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 256 figure 4-135. reset supply current versus vcc, frequencies 1mhz (excluding current through the reset pull-up) 0 2 4 6 8 1012 14161820 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 i cc (ma) frequency (mhz) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.1 2.0 1.8 1.6 4.26 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) reserved (0xf9) reserved (0xf8) reserved (0xf7) reserved (0xf6) reserved (0xf5) reserved (0xf4) reserved (0xf3) reserved (0xf2) reserved (0xf1) reserved (0xf0) reserved (0xef) reserved (0xee) reserved (0xed) reserved notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
257 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 (0xec) reserved (0xeb) reserved (0xea) reserved (0xe9) reserved (0xe8) reserved (0xe7) reserved (0xe6) reserved (0xe5) reserved (0xe4) reserved (0xe3) reserved (0xe2) reserved (0xe1) reserved (0xe0) reserved (0xdf) reserved (0xde) reserved (0xdd) reserved (0xdc) reserved (0xdb) reserved (0xda) reserved (0xd9) reserved (0xd8) reserved (0xd7) reserved (0xd6) reserved (0xd5) reserved (0xd4) reserved (0xd3) reserved (0xd2) lindat ldata7 ldata6 ldata5 ldata4 ldata3 ldata2 ldata1 ldata0 187 (0xd1) linsel ? ? ? ? / lainc lindx2 lindx1 lindx0 187 (0xd0) linidr lp1 lp0 lid5/ldl1 lid4/ldl0 lid3 lid2 lid1 lid0 186 (0xcf) lindlr ltxdl3 ltxdl2 ltxdl1 ltxdl0 lrxdl3 lrxdl2 lrxdl1 lrxdl0 186 (0xce) linbrrh ? ? ? ? ldiv11 ldiv10 ldiv9 ldiv8 185 (0xcd) linbrrl ldiv7 ldiv6 ldiv5 ldiv4 ldiv3 ldiv2 ldiv1 ldiv0 185 (0xcc) linbtr ldisr ? lbt5 lbt4 lbt3 lbt2 lbt1 lbt0 185 (0xcb) linerr labort ltoerr loverr lferr lserr lperr lcerr lberr 184 (0xca) linenir ? ? ? ? lenerr lenidok lentxok lenrxok 184 (0xc9) linsir lidst2 lidst1 lidst0 lbusy lerr lidok ltxok lrxok 183 (0xc8) lincr lswres lin13 lconf1 lconf0 lena lcmd2 lcmd1 lcmd0 182 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 258 (0xc7) reserved (0xc6) reserved (0xc5) reserved (0xc4) reserved (0xc3) reserved (0xc2) reserved (0xc1) reserved (0xc0) reserved (0xbf) reserved (0xbe) reserved (0xbd) reserved (0xbc) usipp usipos 165 (0xbb) usibr usib7 usib6 usib5 usib4 usib3 usib2 usib1 usib0 161 (0xba) usidr usid7 usid6 usid5 usid4 usid3 usid2 usid1 usid0 161 (0xb9) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 162 (0xb8) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 163 (0xb7) reserved (0xb6) assr ? exclk as0 tcn0ub ocr0aub ? tcr0aub tcr0bub 116 (0xb5) reserved (0xb4) reserved (0xb3) reserved (0xb2) reserved (0xb1) reserved (0xb0) reserved (0xaf) reserved (0xae) reserved (0xad) reserved (0xac) reserved (0xab) reserved (0xaa) reserved (0xa9) reserved (0xa8) reserved (0xa7) reserved (0xa6) reserved (0xa5) reserved (0xa4) reserved (0xa3) reserved 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
259 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 (0xa2) reserved (0xa1) reserved (0xa0) reserved (0x9f) reserved (0x9e) reserved (0x9d) reserved (0x9c) reserved (0x9b) reserved (0x9a) reserved (0x99) reserved (0x98) reserved (0x97) reserved (0x96) reserved (0x95) reserved (0x94) reserved (0x93) reserved (0x92) reserved (0x91) reserved (0x90) reserved (0x8f) reserved (0x8e) reserved (0x8d) reserved (0x8c) reserved (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr1b8 145 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1b3 ocr1b2 ocr1b1 ocr1b0 145 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr1a8 145 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1a3 ocr1a2 ocr1a1 ocr1a0 145 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 145 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 145 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 144 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 144 (0x83) tccr1d oc1bx oc1bw oc1bv oc1bu oc1ax oc1aw oc1av oc1au 144 (0x82) tccr1c foc1a foc1b ? ? ? ? ? ? 144 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 143 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 141 (0x7f) didr1 ? ? ? ? ? adc10d adc9d adc8d 207 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 260 (0x7e) didr0 adc7d / ain1d adc6d / ain0d adc5d adc4d adc3d adc2d adc1d adc0d 207 , 211 (0x7d) reserved (0x7c) admux refs1 refs0 adl ar mux4 mux3 mux2 mux1 mux0 203 (0x7b) adcsrb bin acme acir1 acir0 ? adts2 adts1 adts0 206 , 210 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 205 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 206 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / - 206 (0x77) amiscr ? ? ? ? ? arefen xrefen isrcen 190 (0x76) reserved (0x75) reserved (0x74) reserved (0x73) reserved (0x72) reserved (0x71) reserved (0x70) reserved (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 145 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 117 (0x6d) reserved (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 82 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 82 (0x6a) reserved (0x69) eicra ? ? ? ? isc11 isc10 isc01 isc00 80 (0x68) pcicr ? ? ? ? ? ? pcie1 pcie0 81 (0x67) reserved (0x66) osccal cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 58 (0x65) reserved (0x64) prr ? ? prlin prspi prtim1 prtim0 prusi pradc 66 (0x63) clkselr ? cout csut1 csut0 csel3 csel2 csel1 csel0 61 (0x62) clkcsr clkcce ? ? clkrdy clkc3 clkc2 clkc1 clkc0 59 (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 59 (0x60) wdtcr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 74 0x3f (0x5f) sreg i t h s v n z c 32 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 32 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
261 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 32 0x3c (0x5c) reserved 0x3b (0x5b) reserved 0x3a (0x5a) reserved 0x39 (0x59) reserved 0x38 (0x58) reserved 0x37 (0x57) spmcsr ? rwwsb sigrd ctpb rflb pgwrt pgers spmen 217 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? bods bodse pud ? ? ? ? 65 , 90 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 70 0x33 (0x53) smcr ? ? ? ? ?sm1sm0se 65 0x32 (0x52) reserved 0x31 (0x51) dwdr dwdr7 dwdr6 dwdr5 dwdr4 dwdr3 dwdr2 dwdr1 dwdr0 214 0x30 (0x50) acsr acd acirs aco aci acie acic acis1 acis0 210 0x2f (0x4f) reserved 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 153 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x 153 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 151 0x2b (0x4b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 45 0x2a (0x4a) gpior1 gpior17 gpior16 gpior1 5 gpior14 gpior13 gpior12 gpior11 gpior10 45 0x29 (0x49) reserved 0x28 (0x48) ocr0a ocr0a7 ocr0a6 ocr0 a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 116 0x27 (0x47) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 115 0x26 (0x46) tccr0b foc0a ? ? ? ? cs02 cs01 cs00 115 0x25 (0x45) tccr0a com0a1 com0a0 ? ? ? ?wgm01wgm00 113 0x24 (0x44) reserved 0x23 (0x43) gtccr tsm ? ? ? ? ?psr0psr1 118 , 119 0x22 (0x42) eearh (1) ? ? ? ? ? ? ? eear8 43 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 43 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 44 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 44 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 45 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 80 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 81 0x1b (0x3b) pcifr ? ? ? ? ? ? pcif1 pcif0 82 0x1a (0x3a) reserved 0x19 (0x39) reserved 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 262 0x18 (0x38) reserved 0x17 (0x37) reserved 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 117 0x15 (0x35) tifr0 ? ? ? ? ? ?ocf0atov0 117 0x14 (0x34) reserved 0x13 (0x33) reserved 0x12 (0x32) portcr ? ? bbmb bbma ? ? pudb puda 91 0x11 (0x31) reserved 0x10 (0x30) reserved 0x0f (0x2f) reserved 0x0e (0x2e) reserved 0x0d (0x2d) reserved 0x0c (0x2c) reserved 0x0b (0x2b) reserved 0x0a (0x2a) reserved 0x09 (0x29) reserved 0x08 (0x28) reserved 0x07 (0x27) reserved 0x06 (0x26) reserved 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 101 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 101 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 101 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 101 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 101 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 101 4.26 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. address bits exceeding eeamsb ( table 4-74 on page 225 ) are don?t care. 2. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresses should never be written. 3. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 4. some of the status flags are clea red by writing a logical one to them. note that, unlike most other avr ? s, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 5. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? attiny87/167 is a complex microcontroller with more perip heral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used.
263 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 4.27 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from register rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd rr z,n,v 1 andi rd, k logical and register and constant rd rd k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call k direct subroutine call pc k none 4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 264 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1 v 1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1 t 1 4.27 instruction set summary (continued) mnemonics operands description operation flags #clocks
265 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd, y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, r r store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, r r out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 4.27 instruction set summary (continued) mnemonics operands description operation flags #clocks
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 266 5. application figure 5-1. typical lin slave application note: all open pins of the sip can be used for application-specific purposes. avr ? : internal clock, txd, rxd, nres, en and ntrig c onnected for lin slave. the software must be appro- priately programmed for the connec tion between the lin-sbc and the avr. sbc: lin slave operation with watchdog enabled, 5v regulator and kl15 wake up rf emissions: best results for rf emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (c1 and c2) between the micr ocontroller pins and the gnd/pvcc line. see also figure 5-1 . atmel ata6616c/ata6617c pb7 pa4 c2 c1 pb7 pvcc pb7 pa2 inh pa3 vs 38 32 112 13 19 + 31 20 pvcc isp pa4 pa3 wake vbat gnd lin pa2 pa5 pvcc 1 pa4 pb7 10f 100nf 100nf 100nf 220pf 47k 10k * 10k 10k 33k + 22f 100nf 100nf kl15 mode 47k en mode kl15 vcc vs ntrig pb5 tm pb2 gnd pb3 gnd gnd pb4 mcuvcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd mcuavcc pa3 lin pb1 pb0 pa0 pa1 pa2 rxd inh txd nres wd_osc gnd pvcc * the mode pin can be connected directly to gnd, if it is not needed to disable the watchdog
267 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 5-2. typical lin master application note: all open pins of the sip can be used for application-specific purposes. avr ? : txd, rxd, nres and en connected for lin master . the software must be appropriately programmed for the connection between the lin- sbc and the avr. system clock controlled by external crystal. lin-sbc: master application, 1k master resistance connected via diode to vs, local wake up via pin wake; watchdog is enabled. rf emissions: best results for rf emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (c1 and c2) between the micr ocontroller pins and the gnd/pvcc line. see also figure 5-2 . atmel ata6616c/ata6617c pb7 pa4 pb7 pvcc pb7 inh pa3 vs 38 32 112 13 19 + 31 20 pvcc isp xtal pa4 pa3 wake vbat gnd lin lin master pull-up pa2 pa5 pvcc 1 pa4 pb7 10f 100nf 560pf 22pf 51k 10k * 10k 10k 33k + 22f 100nf 22pf 100nf kl15 mode * 47k 1k en mode kl15 vcc vs ntrig pb5 tm pb2 gnd pb3 gnd gnd pb4 mcuvcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd mcuavcc pa3 lin pb1 pb0 pa0 pa1 pa2 rxd inh txd nres wd_osc gnd pvcc c2 100nf c1 100nf pa5 pa2 * the mode pin can be connected directly to gnd, if it is not needed to disable the watchdog
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 268 figure 5-3. typical lin master application 1k lin master pull-up switched off during sleep and silent mode note: all open pins of the sip can be used for application-specific purposes. avr ? : txd, rxd, nres and en connected for lin master . the software must be appropriately programmed for the connection between the lin- sbc and the avr. system clock controlled by external crystal. lin-sbc: master application, 10k mast er resistance connected via diode to vs, 1k master resistance will be switched off via pin inh during sleep mode, local wake up via pin wake; watchdog is enabled. rf emissions: best results for rf emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (c1 and c2) between the micr ocontroller pins and the gnd/pvcc line. see also figure 5-3 . atmel ata6616c/ata6617c pb7 pa4 pb7 pvcc pb7 pa3 vs 38 32 112 13 19 + 31 20 isp xtal pa4 pa3 wake vbat gnd lin lin master pull-up pa2 pa5 pvcc 1 pa4 pb7 10f 100nf 560pf 22pf 47k 10k * 10k 10k 10k 33k + 22f 100nf 22pf 100nf kl15 mode * 47k 1k en mode kl15 vcc vs ntrig pb5 tm pb2 gnd pb3 gnd gnd pb4 mcuvcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd mcuavcc pa3 lin pb1 pb0 pa0 pa1 pa2 rxd inh txd nres wd_osc gnd pvcc c2 100nf pvcc c1 100nf pa5 pa2 * the mode pin can be connected directly to gnd, if it is not needed to disable the watchdog
269 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 figure 5-4. lin slave application with minimum external components note: all open pins of the sip can be used for application-specific purposes. avr ? : internal clock, txd, rxd, nres and en connect ed for lin slave. the software must be appropriately programmed for the connection bet ween the lin-sbc and the avr. sbc: lin slave operation with 5v regulator, watchdog disabled. rf emissions: best results for rf emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (c1 and c2) between the micr ocontroller pins and the gnd/pvcc line. see also figure 5-4 . atmel ata6616c/ata6617c pb7 pb7 pvcc vs 38 32 112 13 19 + 31 20 isp pa4 vbat gnd lin pa2 pa5 pvcc 1 pa4 pb7 10f 220pf 10k + 22f 100nf en mode kl15 vcc vs ntrig pb5 tm pb2 gnd pb3 gnd gnd pb4 mcuvcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd mcuavcc pa3 lin pb1 pb0 pa0 pa1 pa2 rxd inh txd nres wd_osc gnd pvcc c2 100nf pvcc c1 100nf pa4 pa5 pa2
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 270 figure 5-5. 3 3 lin slave switch module matrix decoder with the atmel ata6616c/ata6617c note: note: all open pins of the sip can be used for application-specific purposes. avr ? : txd, rxd, nres and en connected for lin master . the software must be appropriately programmed for the connection between the lin-sbc and the avr. pa7 and pa2 are used as analog inputs. in addition, the application supports a 3 x 3 switch matrix. pa4, 5, 6 ar e used as pwm outputs to control the brightness of light emitting diodes. system clock controlled by external crystal. lin-sbc: lin slave applicatio n, local wake up via pin wake; watchdog is enabled. rf emissions: best results for rf emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (c1 and c2) between th e microcontroller pins and the gnd/pvcc line. see also figure 5-5 . atmel ata6616c/ata6617c pb7 pb0 pb7 pvcc isp pb7 pa3 vs vcc 32 38 112 13 19 + 31 20 pa4 pa3 wake (if needed) vbat gnd lin pa2 1 pa5 pvcc pa4 pb7 optional resistors for higher switch currents 10f 100nf 220pf s3 47k 10k * 10k 10k 33k + 22f 100nf 100nf kl15 mode * 47k en mode kl15 vcc vs ntrig pb5 tm pb2 gnd pb3 gnd gnd pb4 mcuvcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd mcuavcc pa3 lin pb1 pb0 pa0 pa1 pa2 rxd inh txd nres wd_osc gnd pvcc s2 s1 s6 s5 s4 s9 s8 s7 c2 100nf pvcc c1 100nf * the mode pin can be connected directly to gnd, if it is not needed to disable the watchdog
271 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 7. package information 6. ordering information extended type number program memory package moq ata6616c-p3qw 8-kb flash qfn38, 5 7 4,000 pieces ata6617c-p3qw 16-kb flash qfn38, 5 7 4,000 pieces package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5156.01-4 2 09/07/11 package: vqfn_5x7_38l exposed pad 3.6x5.6 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.02 0.05 0.0 a1 77.1 6.9 e 0.23 0.3 0.16 b 0.5 bsc e 0.4 0.5 0.3 l 5.6 5.75 5.45 e2 3.6 3.75 3.45 d2 55.1 4.9 d 0.2 0.25 0.15 a3 0.9 1 0.8 a top view d 1 38 pin 1 id e side view a3 a a1 b l z 10:1 bottom view e d2 standard singulation process 13 1 12 19 20 31 32 38 e2 z
ata6616c/ata6617 c [datasheet] 9132i?auto?06/14 272 8. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9132i-auto-06/14 ? put datasheet in the latest template 9132h-auto-04/13 ? section 2 ?atmel ata6616c/ata6617c lin system in package solution (sip)? on pages 2 to 3 updated ? section 3 ?absolute maximum ratings? on pages 4 to 5 added ? section 6 ?application? on pages 298 to 302 updated 9132g-auto-11/12 ? general features on page 1 updated 9132f-auto-02/12 ? general features on page 1 updated ? section 2.2 ?absolute maximum ratings? on page 3 updated ? section 3 ?lin system-basis-chip block? on pages 4 to 16 updated ? section 3.7 ?absolute maximum ratings? on page 19 updated ? section 3.8 ?electrical characteri stics? on pages 20 to 25 updated ? section 5 ?application? on pages 299 to 303 updated 9132e-auto-05/11 ? table 4-81 ?calibration and accuracy of internal rc oscillator? on page 269 updated ? section 4.5.2.2 ?calibrated inter nal rc oscillator? on page 50 updated 9132d-auto-12/10 ? section 3.1 ?features? on page 4 updated ? section 3.2 ?description? on page 4 updated ? section 3.3.3 ?ground pin? on page 6 updated ? section 3.3.12 ?mode input pi n (mode)? on page 7 updated ? figure 3.2 ?modes of operation? on page 10 updated ? section 3.4.4 ?fail-safe mode? on page 12 updated ? section 3.5.6 ?voltage regulator? on pages 15 to 16 updated ? section 3.8 ?electrical characteri stics? on pages 20 to 25 updated
273 ata6616c/ata6617c [datasheet] 9132i?auto?06/14 9. table of contents general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. atmel ata6616c/ata6617c lin syst em in package solution (sip) . . . . . . . . . . . . . . 3 1.1 pinning atmel ata6616c/ata6617c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. lin system-basis-chip block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 wake-up scenarios from silent or sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. atmel attiny87/attiny167 microcontroller block for atmel ata6616c/ata6617c . . . 26 4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 avr cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4 avr memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5 system clock and clock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6 power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.7 system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.9 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.10 i/o-ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.11 8-bit timer/counter0 and asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.12 timer/counter1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.13 16-bit timer/counter1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.14 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.15 usi ? universal serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.16 lin/uart - local interconnect network controller or uart . . . . . . . . . . . . . . . . . . . . . . . 166 4.17 isrc - current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.18 adc ? analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.19 anacomp - analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.20 debugwire on-chip debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.21 flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.22 memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.23 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 4.24 decoupling capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 4.25 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 4.26 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 4.27 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 5. application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 72 9. table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3
x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: rev.: 9132i?auto?06/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , avr studio ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade.

▲Up To Search▲

Price & Availability of ATA6617C-14

	To Download ATA6617C-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .