View GS3440_8059669.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 23 proprietary and confidential GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 extended reach 3g/hd/sd adaptive cable equalizer GS3440 www.semtech.com key features ? smpte st 424, smpte st 292 and smpte st 259 compliant ? automatic cable equalization ? multi-standard op eration from 125mb/s to 2.97gb/s ? performance optimized for 270mb/s, 1.485gb/s and 2.97gb/s. typical equalized length of belden 1694a cable up to: ? 210m at 2.97gb/s ? 300m at 1.485gb/s ? 550m at 270mb/s ? supports dvb-asi at 270mb/s ? supports madi at 125mb/s ? manual bypass (useful for low data rates with slow rise/fall times) ? programmable carrier detect with squelch threshold adjustment ? automatic power-down on loss of signal ? standby power <35mw (typical) ? differential output supports dc-coupling from 1.2v to 3.3v cml logic ? option to compensate for 6db flat attenuation prior to input of device ? selectable output de-emphasis: 2db, 4db and 6db ? standard eia/jedec logic control and status signal levels ? single 3.3v power supply operation ? 180mw power consumption (typical) ? wide operating temperature range of -40oc to +85oc ? small footprint qfn package (4mm x 4mm) ? footprint compatible wi th the gs2974a, gs2974b, gs2984 and gs2994 ? pb-free and rohs compliant applications ? smpte st 424, smpte st 292 and smpte st 259 coaxial cable serial digital interfaces description the GS3440 is a high-speed bi cmos device designed to equalize and restore signals received over 75 coaxial cable. the device is designed to support smpte st 424, smpte st 292 and smpte st 259, and is op timized for performance at 270mb/s, 1.485gb/s and 2.97gb/s. the GS3440 features dc restor ation to compensate for the dc content of smpte pathological signals. the carrier detect output pin (cd ) indicates whether an input signal has been detected. it can be connected directly to the sleep pin to enable automatic sleep on loss of carrier. a voltage programmable threshold, set via the sq_adj pin, forces cd high when the input signal amplitude falls below the threshold. this allows the GS3440 to distinguish between low-amplitude sdi signals and noise at the input of the device. the equalizing and dc restore stages are disengaged and no equalization occurs when the bypass pin is high. setting the bypass pin high is useful for signals launched at the signal source with low data rates and/or slow rise/fall times. the GS3440 features a gain se lection pin (gain_sel) which can be used to compensate for 6db flat attenuation prior to the input of the device. the differential output can be dc-coupled to semtech?s reclockers and cable drivers, as well as industry-standard 1.2v, 1.8v, 2.5v and 3.3v cml logic by changing the voltage applied to the vcc_o pin. in general, dc-coupling to any termination voltage between 1. 2v and 3.3v is supported. the GS3440 also features programmable output de-emphasis with three, user-selectable operating levels to support long pcb traces at the output of the device.
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 2 of 23 proprietary and confidential description (continued) the device comes in a 16-p in, 4mm x 4mm qfn package and is footprin t compatible with se mtech?s gs2974a, gs2974b, gs2984 and gs2994 equalizers. power consumption of the GS3440 is typi cally 180mw when dc-coupled at 1.2v. the GS3440 is pb-free, and the encaps ulation compound does not contain halogena ted flame retardant. this component and all homogeneous subcomponents are rohs compliant. GS3440 functional block diagram equalizer output agc sdi sleep ddo bypass cd sdi ddo agc agc sq_adj squelch adjust carrier detect mute dc restore vcc_o vee_o op_ctl vcc_a vee_a gain_sel
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 3 of 23 proprietary and confidential contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 description (continued) ........................................................................................................ ...........................2 1. pin out..................................................................................................................... ..........................................4 1.1 GS3440 pin assignment ..................................................................................................... ............4 1.2 GS3440 pin descriptions ................................................................................................... .............4 2. electrical characteristics .................................................................................................. ..........................7 2.1 absolute maximum ratings .................................................................................................. ........7 2.2 dc electrical characteristics ...... ....................................................................................... ...........7 2.3 ac electrical characterist ics ............................................................................................. ...........9 3. input/output circuits ....................................................................................................... ........................ 11 4. detailed description........................................................................................................ .......................... 13 4.1 serial digital inputs ..................................................................................................... ................. 13 4.2 automatic (adaptive) cable equalization ............... .............................................................. 13 4.3 differential digital data output .......................................................................................... ..... 13 4.4 programmable squelch adjust (sq_adj) .............................................................................. 14 4.5 carrier detect, sleep, and auto-sleep .................................................................................... 1 4 4.6 gain_sel .................................................................................................................. ....................... 15 4.7 adjustable output swing, de-emphasis and mute ............................................................ 15 5. application information ..................................................................................................... ..................... 17 5.1 high-gain adaptive cable equalizers .................................................................................... 17 5.2 pcb layout ................................................................................................................ ....................... 17 5.3 typical application circuit ............................................................................................... ......... 18 6. package & ordering information .............................................................................................. ............ 19 6.1 package dimensions ........................................................................................................ ............. 19 6.2 packaging data ............................................................................................................ ................... 19 6.3 recommended pcb footprint .. ........... ........... ........... ........... ........... ........... ........... ........... ....... .. 20 6.4 marking diagram ........................................................................................................... ................ 20 6.5 solder reflow profiles .................................................................................................... .............. 21 6.6 ordering information ...................................................................................................... ............. 21 appendix - relevant documentation .............................................................................................. ........ 21 revision history (document # 56482) ............................................................................................ ......... 22
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 4 of 23 proprietary and confidential 1. pin out 1.1 GS3440 pin assignment figure 1-1: gs 3440 pin out 1.2 GS3440 pin descriptions ground pad (bottom of packa g e) GS3440 16-pin qfn (top view) sq_adj agc vcc_o sleep vcc_a bypass 5678 16 15 14 13 agc gain_sel vee_a sdi 1 2 3 4 sdi vee_o ddo ddo op_ctl 12 11 10 9 cd table 1-1: GS3440 pin descriptions pin number name timing ty p e description 1 vee_a analog power most negative power supply c onne c tion for the input b uffer, c ore an d c ontrol c ir c uits. c onne c t to g nd. 2, 3 s di, s di analog input s erial d igital d ifferential input. 4 g ain_ s el not s yn c hronous input input s ensitivity c ontrol. please refer to the input logi c parameter in the d c ele c tri c al c hara c teristi c s ta b le for logi c level threshol d an d c ompati b ility. this pin is a 2.5v input that is tolerant to 3.3v levels. when hi g h, the d evi c e c ompensates for an a dd itional 6d b of loss a c ross the entire operating b an d . this pin has an internal pull- d own resistor. 5, 6 a gc , a gc analog ? external a gc c apa c itor c onne c tion.
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 5 of 23 proprietary and confidential 7bypa ss not s yn c hronous input c ore bypass c ontrol. please refer to the input logi c parameter in the d c ele c tri c al c hara c teristi c s ta b le for logi c level threshol d an d c ompati b ility. this pin is a 2.5v input that is tolerant to 3.3v levels. for c es the e q ualizer an d d c -restore stages into bypass mo d e when hi g h. no e q ualization o cc urs in this mo d e. this pin has an internal pull- d own resistor. 8 s q_ad j analog input sq uel c h threshol d a d just. a d justs the input signal amplitu d e threshol d of the c arrier d ete c t fun c tion. the serial d ata output of the d evi c e c an b e mute d when the serial d ata input signal amplitu d e is too low b y c onne c ting the c d an d op_ c tl pins using a suita b le resistor network (see figure 4-2 an d figure 4-3 ). this pin has an internal pull- d own resistor. note: the s q_ad j fun c tion is only availa b le when the d evi c e is not in auto-sleep mo d e. referen c e s e c tion 4.5 for more d etail. 9op_ c tl not s yn c hronous input c ontrols the output s wing, de-emphasis an d mute features of the ddo/ddo outputs. when this pin is c onne c te d to g nd, the output swing is 850mv pp d with no d e-emphasis applie d to the output signal. with this pin c onne c te d to 2.5v, the output is mute d . interme d iate voltages an d fun c tions are shown in ta b le 4-5 . these voltages c an b e a c hieve d as shown in figure 4-2 an d figure 4-3 . this pin has an internal pull- d own resistor. 10, 11 ddo, ddo analog output s erial d igital d ifferential output. 12 vee_o analog power most negative power supply c onne c tion for the output b uffer. c onne c t to g nd. 13 v cc _o analog power most positive power supply c onne c tion for the output b uffer. c onne c t to 1.2v - 3.3v d c . 14 s leep not s yn c hronous input s leep c ontrol. please refer to the input logi c parameter in the d c ele c tri c al c hara c teristi c s ta b le for logi c level threshol d an d c ompati b ility. this pin is a 2.5v input that is tolerant to 3.3v levels. when hi g h the part is powere d - d own ex c ept for the c arrier dete c t fun c tion. this pin c an b e c onne c te d d ire c tly to the c d pin to automati c ally put the d evi c e to sleep (low-power operation) on loss of c arrier. this pin has an internal pull- d own resistor. note : when s leep is c onne c te d to c d for automati c power re d u c tion on loss of c arrier, the s q_ad j pin will not mo d ify the c d threshol d . the c d threshol d will revert to the d efault value use d when s q_ad j is pulle d low. table 1-1: GS3440 pin descriptions (continued) pin number name timing ty p e description
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 6 of 23 proprietary and confidential 15 c d not s yn c hronous output c arrier dete c t s tatus output. please refer to the output logi c parameter in the d c ele c tri c al c hara c teristi c s ta b le for logi c level threshol d an d c ompati b ility. this pin is a 2.5v output. in d i c ates presen c e of an input signal. when the c d pin is low, a signal has b een d ete c te d at the input. when this pin is hi g h, this in d i c ates loss of input signal. 1 6 v cc _a analog power most positive power supply c onne c tion for the input b uffer, c ore an d c ontrol c ir c uits. c onne c t to +3.3v d c . ? c enter pa d ?power internally b on d e d to vee_a. c onne c t to g nd with at least 5 vias. table 1-1: GS3440 pin descriptions (continued) pin number name timing ty p e description
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 7 of 23 proprietary and confidential 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value s upply voltage - c ore/output driver -0.5v to +3. 6 v d c input e s d voltage (hbm) 5kv s torage temperature range (t s ) -50 c to 125 c input voltage range (any input) -0.3 to (v cc _a +0.3)v operating temperature range -40 c to +85 c s ol d er reflow temperature 2 6 0 c note: a b solute maximum ratings are those values b eyon d whi c h d amage may o cc ur. fun c tional operation outsi d e of the ranges shown in ta b le 2-1 is not implie d . table 2-2: dc electrical characteristics v cc _a = +3.3v 5%, t a = -40 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes s upply voltage - c ore v cc _a ? 3.135 3.3 3.4 6 5v ? s upply voltage - output driver v cc _o ?1.141.21.2 6 v 1 ? 2.375 2.5 2. 6 25 v 1 ? 3.135 3.3 3.4 6 5v 1 power c onsumption p d v cc _o = 1.2v v ddo = 425mv pp d ? 180 215 mw 2 v cc _o = 1.2v v ddo = 850mv pp d ? 195 230 mw 2 v cc _o = 2.5v v ddo = 425mv pp d ?19 6 231 mw 2 v cc _o = 2.5v v ddo = 850mv pp d ? 221 2 6 1mw 2 v cc _o = 3.3v v ddo = 425mv pp d ? 202 242 mw 2 v cc _o = 3.3v v ddo = 850mv pp d ? 240 283 mw 2 s upply c urrent - c ore i s ? ? 53 59 ma 2 , 3
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 8 of 23 proprietary and confidential s upply c urrent - output driver i output driver v ddo = 850mv pp d ?1924ma 2 v ddo = 425mv pp d ?1014ma 2 input c ommon mo d e voltage v c min ?1. 6 21.711.80 v ? c d output voltage v c d (oh) c arrier not present 2.0 ? ? v ? v c d (ol) c arrier present ? ? 0.4 v ? input voltage - digital pins v g ain_ s el v bypa ss v s leep minimum to assert 1.7 ? ? v 4 maximum to d e-assert ? ? 0.7 v 4 notes: 1. v cc_o operates from 1.2v through 3.3v (+/-5%). 2. de-emphasis off. 3. an additional 3ma when de-emphasis is enabled. 4. gain_sel, bypass, sleep pins are 2.5v, but 3.3v tolerant. table 2-2: dc electrical characteristics (continued) v cc _a = +3.3v 5%, t a = -40 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 9 of 23 proprietary and confidential 2.3 ac electrical characteristics table 2-3: ac electrical characteristics v cc _a = +3.3v 5%, t a = -40 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes s erial input d ata rate dr ddo ? 125 ? 2970 m b /s 1 input voltage s wing v s di differential, 270m b /s an d 1.485 gb /s 720 800 950 mv pp d 2 differential, 2.97 gb /s 720 800 880 mv pp d 3 output voltage s wing v ddo 100 loa d , d ifferential, op_ c tl set for high swing 700 850 1000 mv pp d ? 100 loa d , d ifferential, op_ c tl set for low swing 350 425 500 mv pp d ? output j itter at various c a b le lengths an d data rates ? 2.97 gb /s bel d en 1 6 94a: 0-120m ? ? 0.25 ui 3 , 4 , 5 ? 2.97 gb /s bel d en 1 6 94a: 120-150m ??0.3ui 3 , 4 , 5 ? 2.97 gb /s bel d en 1 6 94a: 150-170m ??0.4ui 3 , 4 , 5 ? 2.97 gb /s bel d en 1 6 94a: 170-200m ??0.5ui 3 , 4 , 5 ? 2.97 gb /s bel d en 1 6 94a: 200-210m ?0.5? ui 3 , 4 , 5 ? 1.485 gb /s bel d en 1 6 94a: 0-200m ??0.2ui 3 , 4 , 5 ? 1.485 gb /s bel d en 1 6 94a: 200-2 6 0m ??0.3ui 3 , 4 , 5 ? 1.485 gb /s bel d en 1 6 94a: 2 6 0-300m ?0.3? ui 3 , 4 , 5 ? 270m b /s bel d en 1 6 94a: 0-300m ? 0.1 0.15 ui 3 , 4 , 5 ? 270m b /s bel d en 1 6 94a: 300-500m ? ? 0.25 ui 3 , 4 , 5 270m b /s bel d en 1 6 94a: 500-550m ?0.25? ui 3 , 4 , 5 output rise/fall time ? 2.97 gb /s & 1.485 gb /s 20% - 80% ?75?ps? ? 270m b /s 20% - 80% ? 150 ? ps ? mismat c h in rise/fall time ? ? ? ? 30 ps ?
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 10 of 23 proprietary and confidential duty c y c le d istortion ? s d/hd/3 g ??30ps? overshoot ? ? ? ? 10 % ? input return loss ? 5mhz - 1.485 g hz 15 ? ? d b? ? 1.485 g hz - 2.97 g hz 10 ? ? d b? input resistan c e?single-en d e d ?1.9?k ? input c apa c itan c e?single-en d e d ?1.3? pf? output resistan c e?single-en d e d ?50? ? notes: 1. device performance is optimized for standard data rate s (sd = 270mb/s, hd = 1.485gb/s, 3g = 2.970gb/s) 2. 0m cable length. 3. all parts are production tested. in order to guara ntee jitter over the full range of specification (v cc_a = 3.3v 5%, t a = -40c to +85c, and 720-880mv pp launch swing from the sdi cable driver) the re commended applications circuit must be used. 4. based on validation data using the re commended applications circuit, at v cc_a = 3.3v, t a = -40c to +85cand 800mv pp launch swing from the sdi cable driver. 5. gain_sel = 0. table 2-3: ac electrical characteristics (continued) v cc _a = +3.3v 5%, t a = -40 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 11 of 23 proprietary and confidential 3. input/output circuits figure 3-1: input c ir c uit figure 3-2: s q_ad j c ir c uit figure 3-3: output c ir c uit 2.625k rc sdi sdi rc 2k 2k 2k vcc_a vcc_a vcc_a sq_adj 82.4k + - vcc_a 50 50 ddo ddo vcc_o vcc_o vcc_o
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 12 of 23 proprietary and confidential figure 3-4: s leep, bypa ss an d g ain_ s el c ir c uits figure 3-5: c d c ir c uit figure 3- 6 : op_ c tl sleep, bypass, gain_sel 100k vcc_a vcc_a cd internal 2.5v vcc_a vcc_a internal reference internal reference op_ctl internal circuitry 100k vcc_a
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 13 of 23 proprietary and confidential 4. detailed description the GS3440 is a high-speed bicmos ic design ed to equalize seri al digital signals. the GS3440 can equalize 3gb/s, hd and sd se rial digital signals, and will typically equalize up to 210m of belden 16 94a cable at 2.97gb/s, 300m at 1. 485gb/ s, and 550m at 270mb/s. the GS3440 can be po wered from a single +3.3v dc power supply, and is footprint-comp atible with semtech?s gs2974a, gs2974b, gs2984, and gs2994 equalizers. when dc coupling the output of a device to a 1.2v cml load, the GS3440 typically consumes 180mw of power. 4.1 serial digital inputs the received serial data signal is connected to the input pins (sdi/sdi ) in either a differential or single-ended configuration. ac-coupling of the inputs is recommended, because the sdi and sdi inputs are internally biased to approximately 1.71v. 4.2 automatic (adaptiv e) cable equalization the input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse of the cable (belden 1694a) loss charac teristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length ensuring that the correct amount of gain is automatically applied to the input signal for any cable length within the supported ranges. the equalized signal is dc-restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to ac-coupling. 4.3 differential digital data output the digital data output signals (ddo/ddo ) have a nominal output voltage swing of either 850mv ppd or 425mv ppd , as set by the op_ctl pin. table 4-1 shows the typical output common mode voltage levels related to the two output swing options and the chosen coupling (dc vs. ac). table 4-1: typical common mode output voltage levels supply voltage (vcc_o) 425mv ppd swing (dc-coupled output) 425mv ppd swing (ac-coupled output) 850mv ppd swing (dc-coupled output) 850mv ppd swing (ac-coupled output) 3.3v 3.2v 3.1v 3.1v 2.9v 2.5v 2.4v 2.3v 2.3v 2.1v 1.8v 1.7v 1. 6 v1. 6 v1.4v 1.2v 1.1v 1.0v 1.0v 0.8v
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 14 of 23 proprietary and confidential 4.4 programmable sque lch adjust (sq_adj) the GS3440 features a programmable squelch adjust (sq_adj) threshold. this feature can be useful in applications where there are multiple input channels using the GS3440 and the maximum gain can be limited to avoid crosstalk. the sq_adj pin acts to change the threshold of the carrier detect (cd ) pin. when the input signal drops below the threshold set by sq_adj, the cd pin will be driven high, indicating that there is not a valid input signal. in applications where programmable squelch adjust is not required, the sq_adj pin can be left unconnected. this feature has been designed for use in a pplications such as routers, where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the use of a carrier detect function with a fixed internal reference does not solve this problem, since the signal-to-noise ratio on the circuit board could be significantly less than the default signal detection level set by the on-chip reference. note : when using sq_adj to limit the maximum gain of the GS3440, cd should not be connected to sleep. 4.5 carrier detect, sl eep, and auto-sleep the carrier detect output pin (cd ) indicates the presence of a valid signal at the input of the GS3440. when cd is low, the device has detected a valid input on sdi and sdi . when cd is high, the device has not detected a valid input. the GS3440 includes a sleep input pin, which can be used to put the device into a low-power sleep mode, consuming less than 35mw. in this mode, the outputs are high impedance and will be pulled high by the on-chip termination. set the sleep pin high to place the chip in this low-power state. in this mode, the carrier detect output will still function to facilitate the detection of a valid serial input data signal. auto-sleep is enab led by connecting cd to sleep. when conn ected, the GS3440 will automatically go into low-power sleep mode when there is a loss of serial digital input signal. note 1: cd will only detect loss of carrier for data rate s greater than 19mb/s. note 2: if sq_adj is being used to limit the maximum gain of the device, and the maximum cable length is exceeded when bypass is set low, the cd pin will be set to high even if a carrier is present. note 3: if the cd pin is connected to the sleep pin, sq_adj must be either left open, or connected to ground. table 4-2: sleep input table sleep function 0the gs 3440 operates normally 1 the gs 3440 enters low-power sleep mo d e. c d output remains vali d
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 15 of 23 proprietary and confidential 4.6 gain_sel the GS3440 has an option of compensating fo r 6db of flat attenu ation prior to the equalizer. 4.7 adjustable output sw ing, de-emphasis and mute the op_ctl input pin determines the output swing and de-emphasis settings for ddo and ddo . the op_ctl pin is an analog input, allowing different combinations of output swing, de-emphasis and mute. the poss ible values are listed in table 4-5 . table 4-3: cd output table cd input status 0vali d input on s di, s di pins 1 input is not vali d table 4-4: gain_sel input table gain_sel function 0no flat b an d gain is applie d . 1 6d b of flat attenuation will b e c ompensate d b y the d evi c e. table 4-5: op_ctl functions and levels level swing de-emphasis mute voltage (v) 0850mv pp d off n 0.000 - 0.083 1850mv pp d 2 d b n 0.234 - 0.394 2850mv pp d 4 d b n 0.545 - 0.704 3850mv pp d 6d b n 0.85 6 - 1.015 4425mv pp d off n 1.1 66 - 1.333 5425mv pp d 2 d b n 1.484 - 1. 6 44 6 425mv pp d 4 d b n 1.795 - 1.954 7425mv pp d 6d b n 2.10 6 - 2.2 6 5 8425mv pp d n/a y 2.41 6 - 2.500
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 16 of 23 proprietary and confidential when muted, the output swing is set to 425mv ppd and the outputs are latched. automatic muting of the output can be enabled by connecting the cd pin to the op_ctl pin. if the connection is made directly, as shown in figure 4-1 , the output would be in its default mode (850mv ppd swing with no de-emphasis) when there is signal present. figure 4-1: dire c t loop b a c k to enable automatic muting while the output is configured for other settings, a resistor network should be used between cd and vcc_a. the intermediate voltages of this resistor ladder can set the output to any one of the nine different settings as shown in figure 4-2 and figure 4-3 . in figure 4-2 , the automatic muting of the output is established by connecting node 3 to the op_ctl pin. in this scenar io, the output would be 850mv ppd with 6db of de-emphasis when there is a signal present. in figure 4-3 , the op_ctl pin is connected to node 4. in this scenario, the output would be 425mv ppd with no de-emphasis when there is a signal present. in both cases, the output would be muted when no carrier is detected. note: when the device is in sleep mode, automatic muting and sq_adj do not function. asserting the sleep pin manually overrides all other functionality. op_ctl cd figure 4-2: resistor divi d er loop b a c k example #1 (fun c tion level 3 from ta b le 4-5 ) figure 4-3: resistor divi d er loop b a c k example #2 (fun c tion level 4 from ta b le 4-5 ) cd op_ctl vcc_a 1k 1k 1k 1k 1k 1k 1k 1k 2.6k 012345678 levels taps cd op_ctl vcc_a 1k 1k 1k 1k 1k 1k 1k 1k 2.6k 012345678 levels taps
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 17 of 23 proprietary and confidential 5. application information 5.1 high-gain adaptive cable equalizers the GS3440 is a multi-rate adaptive cable equalizer. in or der to continue to extend the cable length that the device can support, it is necessary to have high-gain in the equalizer. a video cable equalizer must provide wide band gain over a range of frequencies in order to accommodate the range of data rates and signal patterns that are present in a smpte-compliant serial video stream. small levels of signal or noise present at the input pins of the equalizer may cause chatter at the output. in order to prevent this from happening, particular attention must be paid to board layout. 5.2 pcb layout special attention must be paid to compon ent layout when desi gning serial digital interfaces for hdtv. an fr-4 dielectric can be used, however, controlled impedance transmission lines are required for pcb traces longer than approximately 1cm. note the following pcb artwork features used to optimize performance: ? pcb trace width for 3gb/s rate signals is closely matched to smt component width to minimize reflections due to change in trace impedance. ? high-speed traces are curved to minimize impedance changes. ? cutouts in the inner layers should be used under the GS3440 input and output components to minimize parasitic capacitance. for more detail on this and other layout recommendations, please refer to a guide for designing with gennum?s 3g-sdi equalizers .
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 18 of 23 proprietary and confidential 5.3 typical application circuit figure 5-1: gs 3440 typi c al appli c ation c ir c uit re c ommen d e d for exten d c a b le rea c h appli c ations figure 5-2: gs 3440 alternate appli c ation c ir c uit re c ommen d e d for drop in repla c ement appli c ations 1 4 5 6 2 3 8 7 12 11 14 15 9 10 75 1f 1f gs 3440 37.4 75 4.7f 4.7nh* op_ctl ddo ddo sq_adj bypass sdi sdi vcc_a 4.7f 470nf tab cd sleep vee_o agc agc gain_sel vee_a 4.7nh sdi *value dependent on layout vcc_o 10nf 13 16 10nf vcc_a vcc_o 75 6.2nh 7 10 1f 470nf 4 14 12 1 13 16 8 2 3 9 11 15 6 5 37.4 1f 10nf vcc_a 4.7f 75 vcc_o 4.7f gs 3440 op_ctl ddo ddo sq_adj bypass sdi sdi vcc_a tab cd sleep vee_o agc agc gain_sel vee_a vcc_o 10nf
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 19 of 23 proprietary and confidential 6. package & ordering information 6.1 package dimensions 6.2 packaging data 4.00 4.00 a b c datum a datum b 2.600.10 2.600.10 0.10 m cab 0.10 m cab detail a 0.30@45 r0.30 (3x) pin 1 area 0.15 c 0.15 c 0.10 c 0.08 c 16x seating plane 2x 2x 0.20 ref 0.900.10 0.02 +0.03 -0.02 0.10 m cab 0.05 m c 0.400.05 0.300.05 datum a or b 16x 0.65 0.65/2 detail a (scale 3:1) notes: 1. dimensioning and tolerance is in conformance to asme y14.5-1994 all dimensions are in millimeters in degrees 2. dimension of lead width applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip (both rows). if the terminal has optional radius on the end of the terminal, the lead width dimension should not be measured in that radius area parameter value pa c kage type 4mm x 4mm 1 6 -pin qfn pa c kage drawing referen c e j ede c m0220 moisture s ensitivity level 1 j un c tion to c ase thermal resistan c e, j- c 31.0 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 43.8 c /w psi, 11.0 c /w p b -free an d roh s c ompliant yes
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 20 of 23 proprietary and confidential 6.3 recommended pcb footprint the center pad should be connected to the most negative power supply plane for analog circuitry in the device (vee_a) by a minimum of 5 vias. note: suggested dimensions only. final dimensio ns should conform to customer design rules and process optimizations. 6.4 marking diagram 0.30 0.55 2. 6 0 3.70 2. 6 0 3.70 note: all d imensions are in millimeters. 0. 6 5 c enter pa d gs 3440 xxxxe3 yyww pin 1 id xxxx - last 4 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 21 of 23 proprietary and confidential 6.5 solder reflow profiles the GS3440 is available in a pb-free packag e. it is recommende d that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 6-1 . figure 6 -1: maximum p b -free s ol d er reflow profile 6.6 ordering information appendix - relevant documentation 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part number package temperature range gs 3440-ine3 1 6 -pin qfn -40 c to 85 c gs 3440-inte3 1 6 -pin qfn tape & reel (250p c s) -40 c to 85 c gs 3440-inte3z 1 6 -pin qfn tape & reel (2500p c s) -40 c to 85 c document name document identification a g ui d e for designing with g ennum?s 3 g - s di e q ualizers 55280
GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 22 of 23 proprietary and confidential revision history (document # 56482) version eco pcn date changes and/or modifications 2 010494 ? de c em b er 2012 c onverte d d o c ument to final data s heet. 1 009989 ? novem b er 2012 up d ates throughout the d o c ument. 0 158278 ? j une 2012 c onverte d to preliminary data s heet h 158055 ? may 2012 up d ate d the d es c ription for g ain_ s el, bypa ss , op_ c tl, s leep and c d in ta b le 1-1 . in c lu d e d a dd itional row with input voltage for digital pins in ta b le 2-2 . c hange in text throughout d o c ument for c larity g 157993 ? may 2012 mo d ifi c ations throughout the d o c ument. f 157289 ? novem b er 2011 remove d the typi c al usages se c tion. e 1571 6 2?novem b er 2011 up d ate d the d es c riptions for the s q_ad j an d g ain_ s el pins in ta b le 1-1 to in d i c ate that they have internal pull- d own resistors. d15 6 828 ? august 2011 up d ate d power an d c a b le rea c h num b ers in key features , des c ription , d c ele c tri c al c hara c teristi c s , a c ele c tri c al c hara c teristi c s an d detaile d des c ription . c 15 6 1 66 ? may 2011 up d ate d the power num b ers in ta b le 2-2: d c ele c tri c al c hara c teristi c s . b15 6 134 ? april 2011 up d ate d the m s l rating in pa c kaging data . a 155973 ? april 2011 new d o c ument.
? semtech 2012 all rights reserved. reproduction in whole or in part is pr ohibited without the prior writt en consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under pa tent or other industrial or intellectual property rights. semtech assumes no responsibili ty or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the sp ecified maximum ratings or operation outside the specified range. semtech products are not designed, intended, authori zed or warranted to be suitable for use in life-support applications, devices or systems or other critical applicatio ns. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized applic ation, the customer shall indemnify and hold semtech and its officers, employees, subs idiaries, affiliates, and distributors harmless against all claims, costs damages and atto rney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners . document identification final data sheet information relating to this product and the application or design described herein is believed to be reliable, ho wever such information is provided as a guide only and semtech assumes no liability for any errors in this document, or for the application or design described herein. semtech reserves the right to make changes to the product or this document at any time without notice. GS3440 adaptive cable equalizer final data sheet rev. 2 december 2012 23 of 23 23 proprietary and confidential contact information semtech corporation gennum products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com caution ele c tro s tati c s en s itive devi c e s do not open pa c ka g e s or handle ex c ept at a s tati c -free work s tation

▲Up To Search▲

Price & Availability of GS3440

	To Download GS3440 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .