june 2012 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c www.fairchildsemi.com 1 FDMC8588DC n-channel powertrench ? mosfet FDMC8588DC n-channel powertrench ? mosfet 25 v, 40 a, 5.7 m features ? max r ds(on) = 5.7 m at v gs = 4.5 v, i d = 17 a ? state-of-the-art switching performance ? lower output capacitance, gate resistance, and gate charge boost efficiency ? shielded gate technology reduces switch node ringing and increases immunity to emi and cross conduction ? rohs compliant general description this n-channel mosfet has been designed specifically to improve the overall efficiency and to minimize switch node ringing of dc/dc converters using either synchronous or conventional switching pwm cont rollers. it has been optimized for low gate charge, low r ds(on) , fast switching speed and body diode reverse recovery performance. applications ? high side switching for high end computing ? high power density dc-dc sy nchronous buck converter top power 33 bottom d d d d g s s s pin 1 pin 1 s s s g d d d d mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage (note 5) 25 v v gs gate to source voltage (note 4) 12 v i d drain current - continuous (package limited) t c = 25 c 40 a - continuous (silicon limited) t c = 25 c 73 - continuous (note 1a) 17 - pulsed 60 e as single pulse avalanche energy (note 3) 29 mj p d power dissipation t c = 25 c 41 w power dissipation t a = 25 c (note 1a) 3.0 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case (top source) 7.0 c/w r jc thermal resistance, junction to case (bottom drain) 3.0 r ja thermal resistance, junction to ambient (note 1a) 42 r ja thermal resistance, junction to ambient (note 1b) 105 r ja thermal resistance, junction to ambient (note 1i) 17 r ja thermal resistance, junction to ambient (note 1j) 26 r ja thermal resistance, junction to ambient (note 1k) 12 device marking device package reel size tape width quantity 08dc FDMC8588DC power 33 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a , v gs = 0 v 25 v bv dss t j breakdown voltage temperature coefficient i d = 250 a , referenced to 25 c 5 mv/c i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v 1 a i gss gate to source leakage current, forward v gs = 12 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 0.8 1.2 1.8 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a , referenced to 25 c -4 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 18 a 3.6 5.0 m v gs = 4.5 v, i d = 17 a 4.1 5.7 v gs = 10 v, i d = 18 a,t j = 125 c 5.5 7.6 g fs forward transconductance v dd = 5 v, i d = 17 a 103 s c iss input capacitance v ds = 13 v, v gs = 0 v, f = 1 mhz 1695 pf c oss output capacitance 493 pf c rss reverse transfer capacitance 63 pf r g gate resistance 0.4 t d(on) turn-on delay time v dd = 13 v, i d = 17a, v gs = 10 v, r gen = 6 8ns t r rise time 3ns t d(off) turn-off delay time 25 ns t f fall time 2ns q g(tot) total gate charge at 4.5v v dd = 13 v, i d = 17 a 12 nc q gs total gate charge 3.0 nc q gd gate to drain ?miller? charge 3.0 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 2 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 17 a (note 2) 0.8 1.2 v t rr reverse recovery time i f = 17 a, di/dt = 100 a/ s 25 ns q rr reverse recovery charge 10 nc
www.fairchildsemi.com 3 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet thermal characteristics notes: 1. r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. c. still air, 20.9x10.4x12.7mm aluminum heat sink, 1 in 2 pad of 2 oz copper d. still air, 20.9x10.4x12.7mm aluminum heat sink, minimum pad of 2 oz copper e. still air, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, 1 in 2 pad of 2 oz copper f. still air, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, minimum pad of 2 oz copper g. 200fpm airflow, no heat sink,1 in 2 pad of 2 oz copper h. 200fpm airflow, no heat sink, minimum pad of 2 oz copper i. 200fpm airflow, 20.9x10.4x12.7mm aluminum heat sink, 1 in 2 pad of 2 oz copper j. 200fpm airflow, 20.9x10.4x12.7mm aluminum heat sink, minimum pad of 2 oz copper k. 200fpm airflow, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, 1 in 2 pad of 2 oz copper l. 200fpm airflow, 45.2x41.4x11.7mm aavid thermalloy part # 10-l41b-11 heat sink, minimum pad of 2 oz copper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 29 mj is based on starting t j = 25 c, l = 1.2 mh, i as = 7 a, v dd = 23 v, v gs = 10v. 100% tested at l = 0.1 mh, i as = 16 a. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse occurrence only. no continuous rating is implied. 5. the continuous vds rating is 25v; however, a pulse of 28 v peak voltage for no longer than 3ns duration at 500khz frequency can be applied. r jc thermal resistance, junction to case (top source) 7.0 c/w r jc thermal resistance, junction to case (bottom drain) 3.0 r ja thermal resistance, junction to ambient (note 1a) 42 r ja thermal resistance, junction to ambient (note 1b) 105 r ja thermal resistance, junction to ambient (note 1c) 29 r ja thermal resistance, junction to ambient (note 1d) 40 r ja thermal resistance, junction to ambient (note 1e) 19 r ja thermal resistance, junction to ambient (note 1f) 23 r ja thermal resistance, junction to ambient (note 1g) 30 r ja thermal resistance, junction to ambient (note 1h) 79 r ja thermal resistance, junction to ambient (note 1i) 17 r ja thermal resistance, junction to ambient (note 1j) 26 r ja thermal resistance, junction to ambient (note 1k) 12 r ja thermal resistance, junction to ambient (note 1l) 16 42 c/w when mounted on a 1 in 2 pad of 2 oz copper a. 105 c/w when mounted on a minimum pad of 2 oz copper b. g df ds sf ss g df ds sf ss
www.fairchildsemi.com 4 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet typical characteristics t j = 25c unless otherwise noted figure 1. 0.0 0.2 0.4 0.6 0 10 20 30 40 50 60 v gs = 2.5 v v gs = 3 v v gs = 4 v v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 102030405060 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 4 v v gs = 3 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 2.5 v v gs = 4.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 17 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 0246810 0 5 10 15 20 t j = 125 o c i d = 17 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50 60 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.00.20.40.60.81.01.2 0.1 1 10 60 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 5 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet figure 7. 03691215 0.0 0.9 1.8 2.7 3.6 4.5 i d = 17 a v dd = 15 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 13 v gate charge characteristics figure 8. 0.1 1 10 30 30 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 1 10 50 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 20 40 60 80 v gs = 4.5 v r t jc = 3.0 o c/w v gs = 10 v i d , drain current (a) t c , c ase temperature ( o c ) limited by package m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 100 p s 10 ms 10 s 100 ms dc 1 s 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 105 o c/w t a = 25 o c figure 12. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.5 1 10 100 1000 single pulse r t ja = 105 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25c unless otherwise noted
www.fairchildsemi.com 6 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet figure 13. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 5e-4 1e-3 0.01 0.1 1 2 d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r t ja = 105 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25c unless otherwise noted
www.fairchildsemi.com 7 ?2012 fairchild semiconductor corporation FDMC8588DC rev.c FDMC8588DC n-channel powertrench ? mosfet dimensional outline and pad layout detail a scale: 2x 4 1 85 land pattern recommendation l c sym pkg c l notes: unless otherwise specified a) package stand ar d r eferenc e: jedec mo-240, issue a, var. ba, dated october 2002. b) al l d imension s ar e in mill imeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) it is recommended to have no traces or vias within the keep out ar ea. f) drawing file name: pqfn08crev3. 14 85 3. 40 3. 20 c l pkg a 3.40 3.20 b c l pkg 2.37 min (0.45) (0.40) (0.65) 0. 70 min 0.42 min 0.65 1.95 2.15 min see detail 'a' 1.05 0.95 0. 10 c 0. 08 c 0.23 0.18 0.05 0.00 seating plane c 0.37 0.27 1.95 0.65 0.50 0.30 2.10 1.90 (2 .27 ) 0. 52 (0.20) (0.39) 0.10 c a b 14 85 pkg c l keep out ar ea (0.62) (0.98) 3.40 1.70
FDMC8588DC n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMC8588DC rev.c trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life su pport device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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