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cx29704 optiphy-f155 sts-3/stm-1 sonet/sdh atm/pos framer evm user manual 29704-EVMD-001-C june 2005
? 2005, mindspeed technologies tm , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by minds peed as a service to its customers and may be used for informational purposes only. except as provided in mindspeed?s terms and conditions of sale for such products or in any separate agreement related to this document, mindspeed assumes no lia bility whatsoever. mindspeed assumes no responsibility for errors or omission s in these materials. mi ndspeed may make changes to specifications and product descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities ar ising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringeme nt of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, gr aphics or other items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed customers using or selling mindspeed prod ucts for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. www.mindspeed.com general information: (949) 579-3000 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660 29704-EVMD-001-C mindspeed technologies? mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer revision history revision level date description c released june 2005 updated document number. b advance november 2004 first revision for external use.
29704-EVMD-001-C mindspeed technologies? iii mindspeed proprietary and confidential revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1.0 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.2 hardware overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.2.1 evm top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.3 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.3.1 evm software grap hical user interface (gui) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1.4 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.4.1 mindspeed technologies do cuments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 installation procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.1 hardware assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.1.1 handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4.1.2 board assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4.1.3 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4.2 setting the ip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4.3 installing the evm gui software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 quick start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5.1 running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5.2 startup screen and loading a data file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5.2.1 new evm file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5.2.2 existing evm file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.0 gui operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 jump start screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 payload contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 framing format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 timing source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.5 packet/atm fpga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.6 log pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 cx29704 registers screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 reading a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 writing a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3 update command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 packet/atm fpga registers screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 oh fpga registers screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table of contents
29704-EVMD-001-C mindspeed technologies? iv mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.5 tap driver parameter screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2.5.1 cx29704 config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.2 cx29704 fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.3 cx29704 pm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5.4 fpga config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 evm software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 rtos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 cx29704 tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.4 fpga device driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.5 evm application code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 host software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 communications protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.2 graphical user interface (gui) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.0 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 hardware architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 cx29704 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 packet/atm fpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.3 overhead fpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.4 control subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.4.1 internal memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1.5 oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.6 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.6.1 external power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1.6.2 evm regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.2 line-side interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.1 optical front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 electrical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.3 test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.4 ul2 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.5 power interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.1 leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.2 jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
29704-EVMD-001-C mindspeed technologies? v mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.0 fpga description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 packet/atm fpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1.1 functional grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1.1.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.1.2 packet/atm fpga functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.1.3 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.3.1 cx29704 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.1.3.2 cx29704 side loopback muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.1.3.3 hdlc serdes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.1.4 packet/atm fpga register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 oh fpga description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2.1 clock selection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.2 oh fpga registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.0 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 evm environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 evm power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 7.0 physical design description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
29704-EVMD-001-C mindspeed technologies? vi mindspeed proprietary and confidential figure 1-1. cx29704 evm system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1-2. cx29704 evm hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 1-3. cx29704 evm top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 1-4. cx29704 evm software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 1-5. startup screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 1-6. new evm data file screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 1-7. open evm data file screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2-1. cx29704 evm jump start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2-2. mode switching dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2-3. evm gui application cx 29704.xml . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2-4. cx29704 registers screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2-5. cx29704 config screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2-6. cx29704 fm screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 2-7. cx29704 pm screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3-1. cx29704 evm software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 4-1. cx29704 evm component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4-2. cx29704 evm hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4-3. jtag test chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5-1. packet/atm fpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5-2. fpga context diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5-3. cx29704 evm packet/atm f pga block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 5-4. cx29704 packet/atm fpga: interfaces, dataflow, and clocking . . . . . . . . . . . . . 37 figure 5-5. oh fpga i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 5-6. clock selection subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 list of figures
29704-EVMD-001-C mindspeed technologies? vii mindspeed proprietary and confidential table 1-1. contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4-1. cx29704 evm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4-2. jtag signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5-1. pos phy/utopia 2 transmit cx29704 side interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5-2. pos phy/utopia 2 receive cx29704 si de interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5-3. system side pos phy 2 /utopia trans mit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5-4. system side pos phy2/utopia receiv e interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5-5. hdlc interface signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5-6. packet/atm fpga registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5-7. oh fpga registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 list of tables
29704-EVMD-001-C mindspeed technologies? 1 mindspeed proprietary and confidential 1.1 introduction the cx29704 evm is a fully integrated platform for eval uating the mindspeed technolo gies cx29704 device -- an optiphy-f155 sts-3/stm- 1 sonet/sdh atm/pos framer. the cx29704 evm includes the cx29704tap software program, a full featured driver available in c source code form under license from mindspeed technologies. 1.1.1 system overview the development system consists of the cx29704 evm connected to a power supply and a desktop pc or laptop, which runs the evm gui. this is shown in figure 1-1 . figure 1-1. cx29704 evm system 4 oc-3 cx29704 utopia/pos l2 pos l2 tester utopia l2 tester power supply evm gui cpu subsystem (optional test equipment) usb or 10/100 t fpgas 5v communications / optiphy- oc-3 1.0 getting started
29704-EVMD-001-C mindspeed technologies? 2 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.1.2 hardware overview figure 1-2 depicts the evm hardware architecture. figure 1-2. cx29704 evm hardware block diagram dcc / assi interface microprocessor i/f 4 19.44 mhz oscillator cx29704 fpga (oh) flash memory mpc8260 communications processor xcvr pci / local bus fcc1 fcc2 powerpc bus smc1 smc2 i/o com1 ethernet (10/100) xcvr xcvr pci connector (optional) utopia l2 eeprom sdram (sodimm) scc2 evm control user i/o evm p interface (rs-232) com2 (rs-232) fpga epld sdram fcc3 hdlc evm scc xcvr usb jtag emulator utopia l2 / pos-l2 fpga packet/atm utop/pos l2 tester pos l2 tester xcvr oc-3 sonet/sdh framer xcvr oc-3 sonet/sdh framer tx clock select 4 recovered clk 0 recovered clk 3 reference clock atm l2 tester (per-port) 19.44mhz
29704-EVMD-001-C mindspeed technologies? 3 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.1.2.1 evm top view figure 1-3 illustrates the componen t and connector placemen t for the cx29704 evm. figure 1-3. cx29704 evm top view mindspeed cx29704 evm cx29704 j31 rx tx tx rx fpga pos-phy l2 j10 j9 j7 j6 cx29704 utopia/pos-phy l2 5.0v 3.3v 3.3vdut 1.8v 1.5v s1 on/off +5vdc f1 fuse 3.3v reg. 3.3v reg. 1.5v reg. 1.8v reg. packet/atm fpga oh fpga mpc8260 usb rs-232 e-net elgin cpu subsystem sodimm led3 led2 led1 led0 debug active 100mbit led7 led6 led5 led4 cpu reset reset dut reset sd0 d10 op1 status leds dut fpga clk fpga clk in ext clk in port 0 optical module sd1 d11 op2 port 1 optical module sd2 d13 op3 port 2 optical module sd3 d21 op4 port 3 optical module out
29704-EVMD-001-C mindspeed technologies? 4 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.1.3 software architecture the cx29704 evm software consists of code running on the evm and code running on the host pc. figure 1-4 illustrates the soft ware components. 1.1.3.1 evm software graphical user interface (gui) the evm software package provides a graphical user interface (gui) application to communicate with the evm hardware module. the gui provides a means to configure the cx29704 and fpga devices, acquire status information, collect performance monitoring data, and direct ly read/write device registers. the gui uses a tcp/ip sockets based connection to exchange messages with the embedded tap drivers that reside on the evm. 1.1.4 reference documents 1.1.4.1 mindspeed tech nologies documents 1. 29704-dsh-001-x , cx29704 data sheet 2. 29704-swg-002-x, cx29704tap software programming guide figure 1-4. cx29704 evm software block diagram vxworks rtos cx29704tap driver communications fpga drivers evm application software communications evm evm graphical user interface (gui) host pc
29704-EVMD-001-C mindspeed technologies? 5 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.2 unpacking the contents of the evm shipping box should contain, at a minimum, the following items: 1.3 requirements the following external peripherals are required to support the cx29704 system: pc system requirements: any of the following operating systems: windows 98, nt, 2000 or xp 40 mb available hard drive space vt100-compatible monitor (eg., windows terminal, hyperterminal, xterm ) 10/100t ethernet card oc-3 test equipment esd-safe workstation 1.4 installation procedures the cx29704 evm is shipped in nearly ?plug-and-play? condition. the following setup procedures should take no longer than a few minutes. 1.4.1 hardware assembly 1.4.1.1 handling normal esd precautions should be practiced when handling and operating the cx29704 evm. 1.4.1.2 board assembly the cx29704 evm is a pre-assembled two module set and no additional assembly is required. 1.4.1.3 flash memory with the exception of occasional flashrom upgrades to the evm, there should never be a need to remove or replace socketed components from the module. table 1-1. contents qty description 1 cx29704 evm 1 120 v ac / 5v dc power converter 1 cx29704 evm user manual 2 sc-sc fiber optic patch cable 1 10/100t ethernet cable (straight-th rough for connection to switch or hub) 1 10/100t ethernet cross-over cable (cro ss-over for direct connection to a pc) 1 rs-232 cable (straight-through fo r connection to pc serial port) 1 db9/rj12 adaptor 1 cd-rom containing device a nd software documentation, ha rdware schema tics and bom
29704-EVMD-001-C mindspeed technologies? 6 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.4.2 setting the ip address before using the gui software, the ip address of the evm should be changed to one that is appropriate for the ethernet lan to which it will be attached. this is accomplis hed through the seri al port of the evm. the serial port settings are 9600 baud, 8 data bits, no-parity and 1 stop bit. follow these steps to change the default ip address to a local ip address: 1. connect to the evm serial port, connect and apply power. press and hold the cpu reset switch to reset the board. access the debug menu by pressing the key when prompted and before the time-out period expires. the following text is displayed: vxworks system boot copyright 1984-1998 wind river systems, inc. cpu: mpc8260 cpld: n-04 - mindspeed elgin - version: 5.4.2 bsp version: 2.0/00 creation date: jan 29 2003, 14:07:02 press any key to stop auto-boot... 1
29704-EVMD-001-C mindspeed technologies? 7 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2. enter ?c? and continue hitting until the ?inet on ethernet? field is displayed. enter the new ip address as show below. then continue to hit until the boot prompt is redisplayed. [vxworks boot]: c '.' = clear field; '-' = go to previous field; ^d = quit boot device : flash0 processor number : 0 host name : host file name : aurora.bin inet on ethernet (e) : 10.1.158.112 10.1.158.123 inet on backplane (b): host inet (h) : 10.1.158.127 gateway inet (g) : 10.1.158.1 user (u) : ftp password (pw) (blank = use rsh): flags (f) : 0x88 target name (tn) : startup script (s) : other (o) : motfcc [vxworks boot]: 3. reboot the evm by entering a ?@?. when the board comes out of reset, do not enter the debug menu. after the debug menu prompt times out, the board will load its applic ation software and begin wa iting for messages from the evm gui software. [vxworks boot]: @ 1.4.3 installing the evm gui software follow these steps to inst all the evm gui software: 1. place the evm gui software distribution cd into the cd drive. 2. run the program ? installer.exe ? on the cd. a ms-dos window appears and installs the program files to the c:\cx29704evm directory. this directory is fixed and can?t be changed. a list of the subdirectories and files installed is printed to the screen, and then the following prompt: to launch the application, please do one of the following: a. double click desktop icon labeled "cx29704 evm gui" b. at the command prompt, change to c:\cx29704evm directory and type "go" c. under window explorer, go to c:\cx29704evm\ directory and double click "go" or "go.bat" do you want to launch the application now (y/n)? 3. if the necessary ja va virtual machine is not alre ady loaded on the pc, the inst aller will issue a prompt to load the jvm. 4. after pressing any key to continue, a console window appears and the gui application automatically launches, displaying the start up screen illustrated in figure 1-5 .
29704-EVMD-001-C mindspeed technologies? 8 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.5 quick start procedure 1.5.1 running the software if the evm gui software has already been installed, run the software by following these steps: execute the ? go.bat ? batch file in the c:\cx29704evm directory. the evm gui software run screen will be displayed and the gui application will launch, di splaying the startup screen illustrated in figure 1-5 . 1.5.2 startup screen and loading a data file after the evm gui application is launched, the following startup screen is displayed: the evm gui application uses a data file containing all of the information necessary to restore parameter settings. users can either create a new data file using the evm template file cx29704evm.xml or alternatively, open a previously saved data file. the first time the gui is started, the ?new? option must be selected. all evm data files will have a .ser extension. figure 1-5. startup screen
29704-EVMD-001-C mindspeed technologies? 9 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.5.2.1 new evm file create a new evm data file by following these steps: 1. select the ?new? item under the ?file? menu. the following screen is displayed: 2. select the cx29704atmevm.xml file in the browser pane. the file will be highlighted in the ?file name? text box. 3. click the ?open? command button. 4. the jump start screen is displayed. see section 2.1 . figure 1-6. new evm data file screen
29704-EVMD-001-C mindspeed technologies? 10 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 1.5.2.2 existing evm file load an existing data file by following these steps: 1. select the ?open? item under the ?file? menu. the following screen is displayed: 2. select an evm serialization file in the browse pane. the file will be high lighted in the ?file name? text box. 3. click the ?open? command button. 4. the jump start screen in displayed. see section 2.1 . figure 1-7. open evm data file screen
29704-EVMD-001-C mindspeed technologies? 11 mindspeed proprietary and confidential 2.1 jump start screen the jump start screen allows easy access to commonly used functions to provision all or any one of the four tributary channels on the cx29704. the default values for all of the parameters are shown in figure 2-1 . figure 2-1. cx29704 evm jump start 2.0 gui operation
29704-EVMD-001-C mindspeed technologies? 12 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer at this point, the gui is in offline mode. s witch to online mode by following these steps: 1. select the ?online? item under the ?edit? menu. the following screen is displayed: 2. enter the ip address of the evm. 3. select the desired utopia bus clock source. to use the timing source present on the evm, select ?on board.? to use a clock supplied via the utopia connector, select ?connector.? 4. select the desired software settings synchronization option. the recommended option resets the evm and gui to default settings. 5. click the ?ok? command button. 6. four screens (as illustrated below in figure 2-3 ) are displayed: the jump start, cx29704 registers, oh fpga registers and atm fpga registers. figure 2-2. mode switching dialog
29704-EVMD-001-C mindspeed technologies? 13 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer the ?all tribs? column in the jump start screen can be used to set a parameter to the same value on all the channels of cx29704. the remaining columns configure an individual channel. 2.1.1 payload contents the payload contents determine whether atm cells or pack et over sonet is transported over the channels. this setting affects all channels in the device; therefore, it can only be selected under the all tribs column 2.1.2 framing format the framing format for the optical signal can either be sonet (sts-3c) or sdh (stm-1). 2.1.3 timing source a channel?s transmit data timing source can be set to either: ref clock - timing based on an onboard clock source. loop timing - timing based on the clock recovered from the receive signal. figure 2-3. evm gui application cx29704.xml
29704-EVMD-001-C mindspeed technologies? 14 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.1.4 loopback there are five loopback options on the jump start screen: off - disables loopback on the channel. line - enables a remote line loopback within the cx29704. payload - enables a remote payload loopback within th e cx29704. the cx29704 datasheet refers to this loopback as a sonet loopback. terminal - enables a local atm/pos loopback within the cx29704. fpga - enables a remote loopback within the packet/atm fpga of data received over the utopia/pos-phy interface. 2.1.5 packet/atm fpga mode there are three modes of operation for the packet/atm fpga: disabled - disables the packet/atm fpga, allowing test equipment to be attached to the utopia/pos-phy level 2 connectors (j9/j10). utopia - enables the utopia interface on the packet/atm fpga. pos2 - enables the pos_phy inte rface on the packet/atm fpga. 2.1.6 log pane when parameters are changed in the jump start screen, a series of commands are sent to the evm to configure the devices. these commands will app ear in the log pane at the bott om of the jump start screen.
29704-EVMD-001-C mindspeed technologies? 15 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.2 cx29704 registers screen the cx29704 registers screen allows the user to read and write any register in the cx29704. all register addresses and values are in hexadecimal format. 2.2.1 reading a register reading a register is a no n-invasive operation and will not influence the operation of the embedded driver. to read a register, follow these steps: 1. enter the register address to be read in the ?register? dialogue box. 2. click the ?read? command button. 3. the register value will appear in the ?value? dialogue box. a register can also be viewed via the update command. figure 2-4. cx29704 registers screen
29704-EVMD-001-C mindspeed technologies? 16 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.2.2 writing a register writing a register is an invasive operation and could in fluence the operation of the embedded driver. it bypasses the normal driver execution. this may lead to nond eterministic results in the execution of the driver. to write a register, follow these steps: 1. enter the register address to be written in the ?register? dialogue box. 2. enter the value to write to the specified register in the ?value? dialogue box. 3. click the ?write ? command button. 4. the new value will be writte n to the register. this action can be co nfirmed by reading back the value via the read register process or clicking the ?update? command button and viewing the new value in the register display window. 2.2.3 update command all of the register values since the last update are listed in the register display window. to force a refresh of these values manually, follow these steps: 1. click the ?update? command button. the register display values will be refreshed. any register values that have changed since the last upda te will be highlighted in red. 2.3 packet/atm fpga registers screen the packet/atm fpga registers screen allows the user to read and write the various registers in the packet/atm fpga. reading and writing a register is done in the same manner as described in section 2.2 . 2.4 oh fpga registers screen the oh fpga registers screen allows the user to read and write the various registers in the oh fpga. reading and writing a register is done in the same manner as described in section 2.2 . 2.5 tap driver parameter screens additional screens can be enabled via the ?windows? menu that provide more detailed access to the configuration and status of the cx29704 and fpga devices. these screens provide access to the tap driver (see section section 3.2.3 and section 3.2.4 ) parameters. refer to the cx29704 tap software programming guide (see section 1.1.4 ) for a description of the cx29704 parameters.
29704-EVMD-001-C mindspeed technologies? 17 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.5.1 cx29704 config this screen provides access to the configuration and diagnostic parameters in the cx29704 tap driver. figure 2-5. cx29704 config screen
29704-EVMD-001-C mindspeed technologies? 18 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.5.2 cx29704 fm this screen provides access to the failure monitoring parameters in the cx29704 tap driver. figure 2-6. cx29704 fm screen
29704-EVMD-001-C mindspeed technologies? 19 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 2.5.3 cx29704 pm this screen provides access to the performance monitoring parameters in the cx29704 tap driver. 2.5.4 fpga config these screens provide access to the configuration and diagnostic parameters in the fpga device drivers. figure 2-7. cx29704 pm screen
29704-EVMD-001-C mindspeed technologies? 20 mindspeed proprietary and confidential 3.1 software architecture the software developed for the cx29704 evm consists of code running on the evm and code running on the host pc. figure 3-1 illustrates the software components. figure 3-1. cx29704 evm software block diagram vxworks rtos cx29704tap driver communications fpga drivers evm application software communications evm evm graphical user interface (gui) host pc 3.0 software description
29704-EVMD-001-C mindspeed technologies? 21 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 3.2 evm software the software running on the evm is composed of generic software (rtos, communications protocol) and evm specific software (evm application software, device driver s). the following sections descr ibe the software in more detail. 3.2.1 rtos at the lowest level, the so ftware consists of a vxworks real-time operating system (rtos) with a board support package (bsp) spec ific to the mpc8260 based cpu subsystem. the rtos and basic bsp are available from windriver as a licensed sour ce code product. the bsp is customized in small ways to account for the limited differences between the hardware components on the cpu subsystem and windriver?s sbc8260 standard platform (a motorola reference design). 3.2.2 communications a communications driver / prot ocol software layer is provided on the evm to facilitate communications between the evm and the host pc. the communications function is provided in part by the rtos in th at it provides tcp/ip and com port support. usb extensions ar e written to enhance the available bsp software. higher level protocol software is required for implementing a message set that relies on these lower layers. 3.2.3 cx29704 tap the tap (telecom application program) is a full-featured device driver for the cx29704 family that builds on an existing line of software products and collateral for mindspeed wan access devices. the tap software includes a comprehensive set of software parameters and functions that translate the device control registers and features into the software realm, plus such value added feat ures as standards compliant failure monitoring and performance monitoring. 3.2.4 fpga device driver for each fpga device on the evm, a separate device driver will be included in the evm software. these drivers will control and monitor the loo pback and other diag nostic features of those devices. 3.2.5 evm application code in the category of miscellaneous, ad ditional application code and utilities will be provided on the evm to integrate the various drivers and software layers. given the independence of the some of the functions on the module, some of the high level features of the evm will be implemented partly on the evm and partly by so ftware on the host pc.
29704-EVMD-001-C mindspeed technologies? 22 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 3.3 host software in addition to the stan dard windows operating system running on the host pc, a so ftware program will be executed that is specific to the mindspeed evm product. similar to the evm resident software, the host software will include evm generic software and cx29704 evm specific software. 3.3.1 communications protocol a portion of the evm host software is software for communicating with th e evm. this software relies on windows lower layer communications protocols and drivers for transport through the hardware connections to the evm. 3.3.2 graphical user interface (gui) the user interface for the evm is a java based gui running on a pc and has the following functionality: device configuration and diagnostics failure monitoring performance monitoring low level register read/write evm test setup the gui provides the user with a view into the cx29704t ap software parameters and the cx29704 device itself plus adds ?macro? functions to eas e device setup and configuring of the test capabilit ies of the evm. section 2.0 describes the gui in more detail.
29704-EVMD-001-C mindspeed technologies? 23 mindspeed proprietary and confidential 4.1 hardware architecture figure 4-1 shows the component placement on the cx29704 evm. figure 4-1. cx29704 evm component placement mindspeed cx29704 evm cx29704 j31 rx tx tx rx fpga pos-phy l2 j10 j9 j7 j6 cx29704 utopia/pos-phy l2 5v 3.3v 3.3vdut 1.8v 1.5v s1 on/off +5vdc f1 fuse 3.3v reg. 3.3v reg. 1.5v reg. 1.8v reg. packet/atm fpga oh fpga mpc8260 usb rs-232 e-net elgin cpu subsystem sodimm led3 led2 led1 led0 debug active 100mbit led7 led6 led5 led4 cpu reset reset dut reset sd0 d10 op1 status leds dut fpga clk fpga clk in ext clk in port 0 optical module sd1 d11 op2 port 1 optical module sd2 d13 op3 port 2 optical module sd3 d21 op4 port 3 optical module out 4.0 hardware description
29704-EVMD-001-C mindspeed technologies? 24 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer figure 4-2. cx29704 evm hardware block diagram dcc / assi interface microprocessor i/f 4 19.44 mhz oscillator cx29704 fpga (oh) flash memory mpc8260 communications processor xcvr pci / local bus fcc1 fcc2 powerpc bus smc1 smc2 i/o com1 ethernet (10/100) xcvr xcvr pci connector (optional) utopia l2 eeprom sdram (sodimm) scc2 evm control user i/o evm p interface (rs-232) com2 (rs-232) fpga epld sdram fcc3 hdlc evm scc xcvr usb jtag emulator utopia l2 / pos-l2 fpga packet/atm utop/pos l2 tester pos l2 tester xcvr oc-3 sonet/sdh framer xcvr oc-3 sonet/sdh framer tx clock select 4 recovered clk 0 recovered clk 3 reference clock atm l2 tester (per-port) 19.44mhz
29704-EVMD-001-C mindspeed technologies? 25 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 4.1.1 cx29704 the cx29704 is an integrated circuit that implements fo ur-channel mapping functions for sonet/sdh processing and atm/hdlc at 155.52 mbps. the component contains both the pmd and the tc sublayers and provides an utopia level 2 interface for the atm layer or a pos-phy level 2 interface for the link layer. each port may be selected on a per port basis for either high level data link controller (hdlc) or atm cell delineator protocol options. the cx29704 line side interfaces support optical oc3/sts-3c. the system side interface may be chosen from the combination of utopia level 2 for atm or pos-phy level 2 for hdlc packets. the dual mode utopia level 2 / pos level 2 interface is brought out to a utopia 2 test connector and routed to the packet/atm fpga. this fpga provides pos level 2 transparency to external pos level 2 test equipment. the feature set of this fpga is described in section 5.1 . the sonet/sdh framer block provides access to the sts-3c transport dcc overhead, both insertion and extraction. the overhead interfaces of the cx29704 are routed to the oh fpga which allows access to overhead information on the sts-3c lines. the feature set of this fpga is described in section 5.2 . a full set of loopbacks is provided. 4.1.2 packet/atm fpga the packet/atm fpga provides a number of functions: external utopia l2 tester access to cx29704 utopia level 2 interface per-port active transmit utopia interface selection (system l2 interface, rx port loopback, optional cell generator) per-port tx and rx atm cell counters. external spi-2 tester access to cx29704 pos level 2 interface full packetization of hdlc traffic packet level loopback functionality cpu subsystem access (serial hdlc stream) to cx29704 pos level 2 interface packet and atm cell generation and monitoring features (tbd) 4.1.3 overhead fpga the oh fpga supports the assi alarm interface and cont ains miscellaneous glue logic for the evm. it also provides access to the sonet/sdh tran sport dcc overhead for sts-3c interface. 4.1.4 control subsystem the communications and control subsystem is implement ed on a daughter board known as the elgin processor board. elgin is comp rised of an mpc8260 microp rocessor with sdram, flash, eeprom, ethernet, usb, and rs232 serial ports. in customer applications of the evm, the ethern et and usb interfaces will be used. refer to the elgin processor hardware description document for more information.
29704-EVMD-001-C mindspeed technologies? 26 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 4.1.4.1 internal memory map table 4-1 summarizes the memory map for the cx29704 evm. the use of the other chip select lines are described in the elgin processor documentation. 4.1.5 oscillators the cx29704 evm employs the following oscillators: the cx29704 device uses a 19.44 mhz 20 ppm oscillator for its clad circuit. the packet/atm fpga uses a 10 0 mhz 50 ppm oscillator to gener ate and receive pos/atm data. 4.1.6 power 4.1.6.1 external power power is provided from a +5v/5a regulated tabletop power supply. typical current draw for the board is 3.8a with all channels operational. 4.1.6.2 evm regulators four voltage regulators (from +5v input supply) are implemented on the evm. +3.3v board supply +3.3v cx29704 supply +1.8v overhead fpga core voltage +1.5v packet/atm fpga core voltage status leds for all supply voltages are provided. if the voltages are below nominal, the board will be held in reset. the 3.3v regulators turn on first, followed by the fpga core voltage regulators. enable timing is adjustable by changing a voltage divider and capacitive loading on the regulator enable pin. as a build option, the board 3.3v and cx29704 3.3v supplies can be tied together by removing the cx29704 regulator and connecting the planes via a ferrite bead. these options allow the verification of various power schemes that customers may wish to implement. dual regulators for the board 3.3v and cx29704 3.3v ar e provided to allow individual control of the supply voltages. the regulators used are all the same adjustable regulator to minimize the number of different components used. they are placed on generic dual to-263-5/to-220-5 footprints. removal of r250 allows for placing an ammeter across j1 and j2 to measure the current to the cx29704 device. as an additional build option, the cx29704 3.3v may be sourced from an external supply. table 4-1. cx29704 evm memory map chip select evm base address address space required function cs8# 0xb0000000 128 kbyte cx29704 device cs9# 0xd0010000 64 kbyte packet/atm fpga cs11# 0xd0020000 64 kbyte overhead fpga
29704-EVMD-001-C mindspeed technologies? 27 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 4.2 line-side interface 4.2.1 optical front-end the evm line-side interface consists of four luminent 1310 nm single-mode optical transceivers, in an sc1x9 package. signal detect signals from each of the four transceiver modules are indicated by individual leds. all signals between the transceiver modules and the cx29704 device are lvpecl levels. 4.3 electrical interfaces 4.3.1 signal description in table 4-2 , the following defin itions are used: 4.3.2 jtag connector p1 is the jtag connector on the evm. it is used to perform boundary scan test on the board using the standard corelis pin-out. this jtag connector connects to a single chain of all of the jtag compliant devices on the board. any of these parts can be removed from the chain by removing the 33 ohm resistor at the device?s output and installing the zero ohm resi stor to bypass the part. p1 provides a 10 pin connector for use with standard jtag controllers. loc physical location of the i/o signal type classification of signa l (c -- 3.3v cmos compatible input or output, ct -- 3.3v cmos tristate able output, f - ds3/e3/ sts-1e facility, r -- rs232 compatible input or output, e -- 10/100 baset input or output, u -- usb, p -- vdd or vss) dir signal flow direction (i=inp ut, o=output, io=bidirectional) figure 4-3. jtag test chain table 4-2. jtag signal description name loc. type dir description trst p4-1 c i jtag reset tdi p4-3 c i jtag serial data input tdo p4-5 c o jtag serial data output tms p4-7 c i jtag mode select tck p4-9 c i jtag clock tdi tms trst tck tdo bdm tms trst tck tms trst tck tms trst tck cx29704 tx rx oh fpga tms tck 33 33 33 33 0 not installed 33 fpga packet 0 0 0 0 not installed not installed not installed ram ram
29704-EVMD-001-C mindspeed technologies? 28 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 4.3.3 test points connectors p2 and j8 are test points for fpga development. 4.3.4 ul2 connectors connectors j6 and j7 are connectors for interfacing st andard utopia test equipment (adtech ax4000, innocor phymaster) to the fpga. connectors j9 and j10 are connectors for interfacing standard utopia test equipment directly to the cx29704 utopia bus. 4.3.5 power interface the cx29704 evm accepts +5v through j3/j4. 4.4 other interfaces 4.4.1 leds the following leds are provided. reset: a green led indicates har dware reset when illuminated. dut_reset: a green led indicates cx 29704-only reset when illuminated. 5v, 3.3v dut, 1.5v, 1.8v: a green led indicates that the indicated power supply voltage is above the minimum acceptable value. led0 - led3: packet/atm fpga leds for development phymaster: indicates j9 and j10 are configured for use with innocor phymaster test pods. adtech: indicates j9 and j10 are configured for use with adtech ax4000 utopia test pods. utopia: indicates j9 and j10 are configured for operation with atm test pods. pos: indicates j9 and j10 are configured for operation with pos test pods. sd0 - sd3: a yellow led indicates receive signal detected at the optical interface. the following leds are controlled by the cx29704 assi interface: txc-p0 - txc-p3: indicates transmitte d cells or packets when illuminated. rxc-p0 - rxc-p3: indicates received cells or packets when illuminated. lcd0 - lcd3: indicates locd when illuminated. p-sd0 - p-sd3: indicate s p-sd when illuminated p-sf0 - p-sf3: indica tes p-sf when illuminated. lop0 - lop3: indicates lop when illuminated. ais-p0 - ais-p3: indicate s ais-p when illuminated. l-sd0 - l-sd3: indica tes l-sd when illuminated. l-sf0 - l-sf3: indicate s l-sf when illuminated. ais-l0 - ais-l3: indicates ais-l when illuminated. lof0 - lof3: indicates lof when illuminated. los0 - los3: indicates los when illuminated. 4.4.2 jumpers there are no jumpers to set on the board.
29704-EVMD-001-C mindspeed technologies? 29 mindspeed proprietary and confidential 5.1 packet/atm fpga 5.1.1 interfaces 5.1.1.1 functional grouping figure 5-1. packet/atm fpga transmit pos-phy 2/ interface receive pos-phy 2/ p sram intf dll intf hdlc intf transmit pos-phy 2/ interface receive pos-phy 2/ interface sram intf 16 data control sop,eop, etc 16 data control sop,eop, etc 8 or16 data control sop,eop, etc 8 or16 data control sop,eop, etc cx29704 system side side clock clock data addr cntl data addr cntl data addr cntl 100m clk clk 50m txd rxd tester 18 18 8 testpoints & leds tstpnts leds tx rx 50mhz cd# rts# cts# 4 4 25m clk utopia 2 utopia 2 50mhz interface utopia 1,2 utopia 1, 2 5.0 fpga description
29704-EVMD-001-C mindspeed technologies? 30 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.1.2 signal description in table 5-1 - table 5-5 , the following definitions are used: all signals are active high except for signal names ending in the symbol ?#?. 5.1.1.2.1 cx29704 interface the signals in table 5-1 connect directly to the cx29704 device. loc physical location of the i/o signal type classification of signal (c -- 3.3v cmos compatible input or output, ct -- 3.3v cmos trista teable output, p -- vdd or vss) dir signal flow direction (i=input, o=output, io=bidirectional , z=high impedance) table 5-1. pos phy/utopia 2 transmit cx29704 side interface name loc. type dir description txenb_u2_le# p18 ct o or z the tenb sign al (active low) is used to init iate writes to selected ports. pos & utopia. tdat_u2_le[15:0] r18,r19,r20,r21 r22,t18,t19,t20 t21,t22,u18,u19 u20,u21,u22,v22 ct o orz transmit packet-cell da ta bus[15:0] pos & utopia. tprty_u2_le aa202 ct o or z calculated pari ty for the tdat_u2_le bus. pos & utopia. tsop_u2_le w22 ct o or z tsop/soc indicates the first word of a packet. pos & utopia tadr_u2_le[4:0] aa18,v19,v20,v21, w21 ct o or z the tadr[4:0] bus is used to sele ct the port that is written to using the tenb signal, and the ports' whose pack et available signal is visible on the tpa output when polling. pos & utopia ptpa_u2_le ab18 c i ptpa/tclav tran sitions high when a predefined minimum number of bytes is available in the polled transmit port's fifo. once high, ptpa indicates that the transmit port's fifo is not full. when ptpa transitions low, it optionally indicates that the transmit fifo is full or near full (normally user programmable). ptpa allows to poll the port address selected by tadr[4:0] when tenb is asserted. ptpa is driven by a port when its address is polled on tadr[4:0]. pos & utopia. tmod_u2_le w20 ct o or z tmod indicates th e size of the current word. pos only. teop_u2_le y21 ct o or z teop mark s the end of a packet on the tdat[15:0] bus. pos only. terr_u2_le y22 ct o or z terr is used to indicate that the curren t packet is aborted and should be discarded. pos only. stpa_u2_le p17 c i stpa transitions high when a predefined minimum number of bytes is available in the selected transmit port's fifo . once high, stpa indicates that the transmit fifo is not full. when stpa transitions low, it optionally indicates that the transmit fifo is full or near full. stpa always provide status indication for th e selected port in order to avoid fifo overflows while polli ng is performed. pos only.
29704-EVMD-001-C mindspeed technologies? 31 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer the signals in table 5-2 directly connect to the cx29704 device. table 5-2. pos phy/utopia 2 receive cx29704 side interface name loc. type dir description renb_u2_le# a7 ct o or z the renb signal is used to initiate reads from the receive fifo's (in cx29704). when renb is asserted data is transferred from the selected phy and radr[4:0] is used to select the phy. pos & utopia. radr_u2_le[4:0] k1,k2,k3,k4 k6 ct o or z the raddr is used to select the phy device (or por t number) in which the system (fpga) wants to read da ta from, this done by placing the appropriate address on ra ddr one cycle before asserting renb. pos & utopia. rdat_u2_le[15:0] f1,f2,f3,f4 g1,g2,g3,g4 h1,h2,h3,h4 j1,j2,j3,j4 c i the rdata[15:0] bus carries the packet-cell words that are read from the selected port. pos & utopia. rprty_u2_le a6 c i the receive pari ty (rprty) signal indicates th e parity of the rdat bus. pos & utopia rsop_u2_le b7 c i rsop marks the first word of a packet-cell tr ansfer. pos & utopia prpa_u2_le c7 c i prpa (aka rcalv) i ndicates when data is avai lable in the polled port. when prpa is high, the port has at least one end of packet-cell or a predefined number of bytes to be read. pos & utopia rmod_u2_le b6 c i rmod indicates the number of bytes carried by the rdata[15:0] bus during the last word of a packet transfer. pos only rval_u2_le d7 c i rval indicates th e validity of the receive data signals. when rval is high, the receive signals rdat, rsop, reop, rmod, rprty and rerr are valid. pos only. rerr_u2_le c6 c i rerr is used to indicate that the cu rrent packet is aborted and should be discarded. pos only. reop_u2_le e7 c i reop marks the end of pack et on the rdata[15:0] bus. pos & utopia.
29704-EVMD-001-C mindspeed technologies? 32 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.1.2.2 system side pos phy 2 interface table 5-3. system side pos phy 2 /utopia transmit interface name loc. type dir description txenb_u2_sy# l20 c i the tenb signal (a ctive low) is used to initia te writes to selected ports. pos & utopia. tdat_u2_sy[15:0] g19,g20,g21,g22 h19,h20,h21,h22 j19,j20,j21,j22 k19,k20,k21,k22 c i transmit packet/cell data bus[15:0] pos & utopia. tprty_u2_sy f18 c i calculated parity for the tdat_u2_le bus. pos & utopia. tsop_u2_sy f19 c i tsop (a.k.a. soc) indicates the first word of a packet. pos & utopia. teop_u2_sy f20 c i teop marks th e end of a packet on the tdat[15:0] bus. pos only terr_u2_sy f21 c i terr is used to indicate that the current packet is aborted and should be discarded. pos only. tadr_u2_sy[4:0] e18,e19,e20,e21,e 22 c i tadr is the mphy address of the channel.pos & utopia. tmod_u2_sy f22 c i tmod indicates the si ze of the current word. pos only. tpa_u2_sy g18 c o ptpa (a.k.a. tclav) tran sitions high when a predefined minimum number of bytes is available in the polled transmit port's fifo. once high, ptpa indicates that the transmit port's fifo is not full. when ptpa transitions low, it optionally indicates that the transmit fifo is full or near full (normally user pr ogrammable). ptpa allows to poll the port address selected by tadr[4:0] when tenb is asserted (pos only feature). pos & utopia stpa_u2_sy a19 c o stpa contains information about the availa bility of pa ckets in the selected channel. pos only.
29704-EVMD-001-C mindspeed technologies? 33 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer table 5-4. system side pos phy2/utopia receive interface name loc. type dir description renb_u2_sy# a5 c i renb is used to control the fl ow of data from the receive fifos. pos & utopia rdat_u2_sy[15:0] t1,t2,t3,t4, t5,u1,u2,u3, u4,u5,v1,v2, v3,v4,v5,w1 c o packet/cell data. pos & utopia rprty_u2_sy b5 c o rprty indicates the calculat ed parity for the current octet. pos & utopia rsop_u2_sy v6 c o rsop indicate s the first word of a packet/cell. pos & utopia reop_u2_sy w6 c o reop indicates the fi rst word of a packet. pos only rerr_u2_sy c5 c o rerr is used to indicate that the current packet is aborted and should be discarded. pos only radr_u2_sy[4:0] y7,r1,r2,r3, r4 c i radr is the mphy address of the channel. pos & utopia. rpa_u2_sy aa5 c o rpa (a.k.a. rclav) indicates that the polled phy has a packet or cell to transfer. pos & utopia. rmod_u2_sy a4 c o rmod indicates the number of valid bytes on the last word. pos only. rval_u2_sy ab5 c o indicates the validity of the pos-phy receive data signals. pos only.
29704-EVMD-001-C mindspeed technologies? 34 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.1.2.3 hdlc interface table 5-5. hdlc interface signal description name loc. type dir description note the clock for this interf ace is provided to the 8260 via the pcb; the 25mhz clock driven by the packet/atm fpga. txd[3:0] h18,c22,k18,c21 c o serial data fr om the packet/atm fpga to the 8260 fcc rxd[3:0] f5,g5,h5,j5 c i serial data from the 8260 fcc to the packet/atm fpga rts# k17 c o rts# indicates the beginning of a fr ame, and can be used at the receiver for synchronization. note that rts# and cts# are used by a peripheral on the se rial link by the corresponding peripherals transmitter. cd # is used by the receiver on the other end of the link. a typical ap plication would connect the rts# on peripheral a to cd# on periph eral b via the serial bus. reference the motorola mpc 8260 user s manual chapters 28, and 32 for details of the timing. there are several combinations of timing, that depend on the nature of the data being moved. these combinations must be set up in the 8260 register structure. cts# e5 c i cts# indicates that the rece iving end is able to accept data. note that rts# and cts# are used by a peripheral on the seri al link by that peripherals transmitter. cd# is used by the receiver on the other end of the link. cd# e6 c i cd# is used by a peripherals receiver to know when a start of frame is occurring. note that rts# and cts# are used by a peripheral on the seri al link by that peripherals transmitter. cd# is used by the receiver on the other end of the link. a typical appl ication would connect the rts# on peripheral a to the cd# on peripheral b.
29704-EVMD-001-C mindspeed technologies? 35 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.2 packet/atm fpga functional description 5.1.2.1 block diagram figure 5-2. fpga context diagram utopia l2 / pos-l2 fpga (pkt/atm) utopia tester utopia tester mpc8260 p interface cx29704
29704-EVMD-001-C mindspeed technologies? 36 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer figure 5-3. cx29704 evm packet/atm fpga block diagram 16 cell-packet monitor rx hdlc serdes and cntl to 8260 hdlc internal clocks 16 tx_data rx_data rx_data tx_data tx_clk rx_clk (25-50)mhz (25-50)mhz fifos 8 /16 8/16 cx29704 data addr tx fifos cell-packet generator pos rx tx optional zbt sram controller optional zbt sram (transmit) pos optional zbt sram (receive) optional zbt sram controller pos/ dll c intf pos 2 (system side) to/from cpu (50mhz) u2 tx and rx clk rx tx utp phy 2 intf pos phy 2 intf pos phy2 pos phy2 phy2/ 2 tester utp intf intf utp utp utopia 2
29704-EVMD-001-C mindspeed technologies? 37 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer figure 5-4. cx29704 packet/atm fpga: interfaces, dataflow, and clocking 16 16 cell-packet monitor hdlc serdes and cntl to 8260 hdlc 25mhz clk,txd, rxd, internal clocks rx_data tx_data (100mhz) u3 tx and rx clk rx_data tx_data tx_clk rx_clk (25-50)mhz (25-50)mhz 8/16 8/16 cx29704 data addr cell-packet generator intf rx optional zbt sram controller optional zbt sram (transmit) pos optional zbt sram (receive) optional zbt sram controller pos dll1 c intf utopia 2 packet intf (system side) to/from cpu (50mhz) u2 tx and rx clk 8 8 18 data 18 data sync dual port 18 x 32k 100 mhz dll2 50 mhz 100m 50m 50mhz 50 mhz 50 mhz 100mhz 100mhz sync dual port 18 x 32k 100mhz 50mhz pos intf tx 100mhz 50mhz async fifo 18 x 16 pos2/ async fifo 18 x 16 pos2/ dll3 25 mhz phy 2 pos phy 2 phy 2 4 4 phy 2/ tester utp utp intf tx intf utp rx
29704-EVMD-001-C mindspeed technologies? 38 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.3 functional blocks 5.1.3.1 cx29704 interface the packet/atm fpga connects to cx29704 via standard pos-phy 2 and utopia 2 interfaces. the packet/ atm fpga allows only one cx29704 interface active at a time (sw control). there are 31 (pos-utopia 2) possible logical channels in which packet data may be transmitted or received; the packet/atm fpga supports any six physical channels active at a time (sw control). bo th packet interfaces are under the control of a single memory mapped bit that performs a ?run-stop? function (default is run), and individual channel enables. note that the pos-phy 2 interface outputs are tristatable to allow other masters on the pcb to communicate with the cx29704. data is continuously accepted by the packet/atm fpga po s2/utopia 2 interface in the rx direction (subject to the run-stop bit), even if the fpga?s buffers are full. no ?back pressure? is applied to the pos2/utopia 2 rx interface. one-word packets are discarded in the rx direction. two-word or greater length packets are buffered and forwarded normally. a limitation is imposed by the minimun packet size of the innocor phy master (5 bytes). packets received with the err signal asserted are buffered and forwarded with the err signal asserted. this is true in both tx and rx directions. parity is calculated at all the interfaces but not buffered. therefore parity errors do not loopback or pass thru the packet/atm fpga. 5.1.3.2 cx29704 side loopback muxes the packet/atm fpga provides pos-phy/utopia 2 channelized loopback under sw control. note that the loopbacks pass thru the packet buffers, therefore the full packetization function is active while in loopback. the loopback muxes also serves as the insertion point for the packet generator to drive packets toward the cx29704. 5.1.3.2.1 internal block ram used as packet buffers the packet/atm fpga collects packet fragments from the packet interfaces and accumulates them in a buffer until an entire packet is present. after a full packet is buffered the packet available signal on the system tester side is asserted. the tester can now remove the packet in its entir ety without any pauses on the packet bus. the xilinx virtex ii 1000 has enough block ram to implement six buffers each holding about 1.9k bytes. if the incoming packet size is larger than the buffer, then the packet will be a ccepted and truncate d to fit in the buffer, and that packet will be marked by the assertion of the err signal. if a missing end condition is created by faulty transmission or a switch to loopback mid-packet, the current packet is also marked with an err. utopia cells are always internally stored 54 bytes in length. this means that false data is inserted into the incoming stream when accepting 52 or 53 byte cells. also note that the extra bytes are removed from the outgoing stream when an outgoing interface is configured as 52 or 53 byte. this is true in both the tx and rx directions. note that utopia cells are marked with eop internally using counters. therefore much of the control logic to operates as if hdlc packet are being processed. this avoided a complete re-design of the packet based design when utopia features were added. 5.1.3.2.2 small asynchronous fifos small asynchronous fifos are used to decouple the inter nal and external clocks associated with the packet tester and the rest of the packet/atm fpga. data width conversion is done for the utopia interface using control logic near these fifos and their flags.
29704-EVMD-001-C mindspeed technologies? 39 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.3.2.3 master design the pos/utopia 2 masters poll until a packet available is detected. next, the transfer of a packet begins. the master continues to poll while the packet is being transferred. if another channel indicates packet available true, then that channel number is stored so that th e channel will be accessed when the current channel completes its transfer. the number of channels to poll is programmable using the memory mapped interface. 5.1.3.2.4 fpga system side interface the system side interface to the external test set is configured as a pos-phy2 or utopia 1/2 slave. the pos 2 interface will delay assertion of the pa cket available signal un til there is at least one eop in the buffer. 5.1.3.2.5 packet monitor packet data is generated going toward the cx29704 system side datacom interfaces in the tx direction on a per port basis. the target interface is pos2. packet length (1 -255 byte) and inter packet delay (16- 8192 clocks) is controllable in software. the packet genrator operates in either a one-shot mode (sends 5 packets 1 time) or a continuous run mode (packets are streamed). packet data consists of fixed byte patterns with each phy having a differnt pattern. the pattern for a phy is the phy number (phy1 has pattern value ==1) the rx packet monitor detects errors (based on packets generated by the fpga) and counts packets. 5.1.3.2.6 sram controller/external sram the sram controller provides an interface to an optional external sram to allow the packet/atm fpga to accommodate more and larger packet buffers. the sram technology used is zbt to allow full bandwidth access to the device at 100mhz. th e zbt sram uses a single physical data bu s so the bus traffic will be approximately 50mhz reads and 50 mhz writes. use of the external sram allows 12 32k byte storage buffers in each direction. 5.1.3.2.7 clock and dll the packet/atm fpga uses a free runnin g 100mhz clock (provided from an external oscillator) and derives a 50mhz clock from that using the xilin x virtex ii dlls. the derived 50mhz clo ck is approximately skew free from the 100mhz reference. the derived 50m hz clock is driven off the fpga (u sing a separate dll). the driving dll assures a the clk-data relationship on the pcb falls well within the pos2 spec. 5.1.3.3 hdlc serdes the main purpose of this block is serial to parallel and parallel to serial conversion of full duplex hdlc traffic. the traffic path is to/from the packet buffers in the packet/atm fpga to/from the 8260 fast communications controller (fcc3) located on the microprocessor plug in card.
29704-EVMD-001-C mindspeed technologies? 40 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.1.4 packet/atm fpga register description the fpga registers are accessible using cs11# on the evm. table 5-6 describes the general control registers for the cx29704 packet/atm fpga load. table 5-6. packet/atm fpga registers address r/w initial bit(s) contents 0x0 rw 0 7:0 diagnostic scratch register (scratch_reg) general purpose register for debug purposes 0x1 ro 5 7:0 fpga version (ver) current fpga version 0x2 ro 0xc2 7:0 fpga id (id) fpga device id 3,4, 7,8, 0x18,0x19 rw 0 thru 5 4:0 receive buffer ingress channel assignments address of channel to assi gn to rx buffers 0 thru 5 5,6, 0x16,0x17,0x 1a,0x1b rw 0 thru 5 4:0 transmit buffer egress channel assignments address of channel to assign to tx buffers 0 thru 5 0x9 ro 0x09 build number 0xa 0x06 7:6 5 4:0 transmission_cntl_reg 2 reserved reserved number of addresses to poll 0xb rw 0x0e 7 6 5 4 3 2 1 0 transmission_cntl_re g (xmit_cntl_reg) test mode 1=single phy only (no po ling, applies to pele side only) float pos-phy2 pele si de bus drivers. 0=float fpga system side utopia bus size, 1=8-bit 0 = 16-bit fpga system side clock s ource 1=adtech, 0=phymaster run (enable) receive side pos-phy interface. 1= run run (enable) transmit side pos-phy interface. 1= run reserved; write to 0 fpga interface mode. 1= utop ia-cells, 0= pos-packets 0xc -- -- -- -- -- cor cor cor 0 7 6 5 4 3 2 1 0 packet_fpga_performance_stat (pm_stat_1) reserved reserved reserved reserved reserved reserved pos_phy parity error (system test tx side pos2) pos_phy parity error (pele rcv side pos2)
29704-EVMD-001-C mindspeed technologies? 41 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 0xd cor cor ro ro ro ro rw ro 0x02 7 6 5 4 3 2 1 0 packet_fpga_performance_stat (pm_stat_2) reserved pele side pos2 aborted packet detected dll locked (up_clk) dll locked (tx_sy_clk) dll locked (rx_sy_clk) dll locked (50mhz for driving onto pcb using ddr registers) dcm reset. reset far syte m side, and clk_100 dcms. dll locked (driven by external 100m hz, produces internal 50 mhz clk) 0xe rw 0 7 6 5 4 3 2 1 0 cx29704 rx fifo flush (flush) reserved reserved reserved reserved insert pos2 tx e op errors (continuous) insert pos2 tx s op errors (continuous) reserved flush pele pos2 rx fifo. 1 = flush 0xf cor 0xc3 7 6 5 4 3 2 1 0 packet_fpga_performance_stat (pm_stat_3) rx_buffer_1 empty flag rx_buffer_0 empty flag rx_buffer_1 par full flag rx_buffer_0 par full flag tx_buffer_1 par full flag tx_buffer_0 par full flag tx_buffer_1 empty flag tx_buffer_0 empty flag 0x10-0x15 rw 0x80 7 6 5 4 3-1 0 per port enables port enable port packet generator enable port loopback enable port packet genera tor mode. 1=continous, 0=5 packet burst reserved port packet gene rator, one shot burst mode tr igger. rising edge sends burst 0x1c cor cor cor cor cor cor 0 0 0 0 0 0 0 7,6 5 4 3 2 1 0 pm_stat_3_det_rx_pattern_err reserved phy 5. rx err. 1 means rx da ta does not compare equal to 5 phy 4. rx err. 1 means rx da ta does not compare equal to 4 phy 3. rx err. 1 means rx da ta does not compare equal to 3 phy 2. rx err. 1 means rx da ta does not compare equal to 2 phy 1. rx err. 1 means rx da ta does not compare equal to 1 phy 0. rx err. 1 means rx da ta does not compare equal to 0 1d cor 0 7-0 rx_data_packet_count total number of packets received by device. 1e rw 6 7-0 xmt_packet_length packet length bytes. valid values are 1-0xff 1f rw 4 7-0 xmt_packet_delay delay between generated packtes. use this as a bandwidth control. table 5-6. packet/atm fpga registers (continued) address r/w initial bit(s) contents
29704-EVMD-001-C mindspeed technologies? 42 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.2 oh fpga description the oh fpga supports the assi alarm interface and cont ains miscellaneous glue logic for the evm. it provides software reset control of the cx29704 device as well as clock source control for refclk and the cx29704 utopia interface. the sonet/sdh transport dcc overhead for sts-3c interface signals from the cx29704 have been routed to this fpga to allow for future access to this interface. subsequent versions of this document w ill detail the available functionality. figure 5-5. oh fpga i/o signals cs9# refclk_sel[1:0] int7# tsdcc[4:1] psf[3:0] sw_reset# phymaster_en# cx29704evm oh fpga xc2s50e-ft256 tsdcd[4:1] rsdcc[4:1] ck_sel[1:0] up_d[31:24] up_a[15:0] en_ref lof[3:0] asenb sma_out sma_in clk_extra en_100 tldcc[4:1] fpga_clk_out adtech_en# pos_en# utopia_en# rsdcd[4:1] rldcc[4:1] rldcd[4:1] tldcd[4:1] asclk asdo asstb# up_rw# tp[15:0] mictor_clk up_clk2 up_reset# test up interface enable signals assi interface/leds dcc interface sma interface undefined recovered clks clock selects recclk[3:0] aisl[3:0] aisp[3:0] lop[3:0] lcd[3:0] lsf[3:0] lsd[3:0] txcp[3:0] rxcp[3:0] rlos[3:0] psd[3:0]
29704-EVMD-001-C mindspeed technologies? 43 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.2.1 clock selection diagram a block diagram of the clock selection subsystem appears in figure 5-1 . figure 5-6. clock selecti on subsystem block diagram 19.44mhz 20ppm oscillator refclk_sel0 refclk_sel1 sma_out oh fpga sma_in refclk fpga_clk_out rxutp_clk_up ck_sel0 txutp_clk rxutp_clk rxutp_clk_fpga rxutp_clk_test txutp_clk_up txutp_clk_fpga txutp_clk_test ck_sel1 1/2 74ac153 1/2 pi383253q 1/2 pi383253q mc100ept21 mc100ept21
29704-EVMD-001-C mindspeed technologies? 44 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 5.2.2 oh fpga registers the oh fpga has 8 registers accessible using cs9# on the evm. table 5-7. oh fpga registers address r/w initial bit contents 0x0 board id register r 0x2 7-5 board id code - 0x3 = cx29704 evm 4-0 reserved 0x1 version code register r 0x1 7-0 version code 0x01 = 0.1 0x2 utopia control register rw 0x0 7 disable_100 - this bit will disable the 100 mhz utopia oscillator when set to 1. set this bit to 0 to enable the oscillator. 6 reserved rw 0x0 5-4 ck_sel[1:0] - these bits select the source of the utopia clock: 0x0 = utopia clock from mi croprocessor daughterboard 0x1 = utopia clock from fpga 0x2 = utopia clock from external utopia tester 0x3 = reserved 3 phymaster_en - set this bit to 1 to enable the external phymaster interface 2 adtech_en - set this bit to 1 to enable the external adtech interface 1 pos_en - set this bit to 1 to use an external pos interface 0 utopia_en - set this bit to 1 to use an external utopia interface 0x3 refclk control register 7-3 reserved rw 0x0 2 disable_ref - this bit will di sable the 19.44mhz oscillator when set to 1. set this bit to 0 to enable the oscillator. rw 0x0 1-0 refclk_sel[1:0] - these bits se lect the source of the refclk signal: 0x0 = 19.44mhz oscillator 0x1 = refclk_in sma connector 0x2 = reserved 0x3 = reserved 0x4 sma out control register 7-4 reserved rw 0x0 3-0 sma_out_sel[3:0] - these bits se lect the source of the sma_out signal: 0x0 = recovered line clock from channel #0 (recclk0) 0x1 = recovered line clock from channel #1 (recclk1) 0x2 = recovered line clock from channel #2 (recclk2) 0x3 = recovered line clock from channel #3 (recclk3) 0x4 = microprocessor bus clock 0x5 = assi interface clock 0x6 = reserved 0x7 = reserved
29704-EVMD-001-C mindspeed technologies? 45 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer 0x5 cx29704 reset register 7-1 reserved rw 0x0 0 sw_dut_reset - set to 1 to reset the cx 29704. set to 0 to remove the reset condition. 0x6 assi control register rw 0x0 7 led_test - set to 1 to activate all 48 assi leds. set to 0 for normal operation. 6-1 reserved rw 0x0 0 assi_disable- set to 1 to disable cx29704 a ssi interface, set to 0 to enable the assi interface. 0x7 diagnostic data register rw 0x0 7-0 generic readable/writeable register for diagnostic purposes. table 5-7. oh fpga registers address r/w initial bit contents
29704-EVMD-001-C mindspeed technologies? 46 mindspeed proprietary and confidential 6.1 evm environmental conditions operating temperature 0 to +70 c storage temperature -40 to +125 c relative humidity 0 to 95%, non-condensing 6.2 evm power requirements voltage +5v dc 5% note: additional voltages on evm are supplied by the on-board voltage regulators current 4.5 amps maximum, 3.8 amps typical. 6.0 specifications
29704-EVMD-001-C mindspeed technologies? 47 mindspeed proprietary and confidential 7.1 schematics a pdf version of the schematics for the cx29704 evm are included on the cd-rom. they were created using the innoveda toolset. an electronic version of the design is available upon request. 7.2 bill of materials the components used on the cx29704 evm are also included in the b ill of materials spre adsheet on the cd- rom. an electronic version of this spreadsheet is available upon request. 7.0 physical design description
29704-EVMD-001-C mindspeed technologies? 48 mindspeed proprietary and confidential cx29704 evm user manual optiphy-f155 sts-3/stm-1 sonet/ sdh atm/pos framer www.mindspeed.com general information: (949) 579-3000 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660

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