1. general description the HEF4051B-Q100 is an 8-channel anal og multiplexer/demu ltiplexer with three address inputs (s1 to s3), an active low enable input (e ), eight independent inputs/outputs (y0 to y7) and a common input/ output (z). the device contains eight bidirectional analog switches, each with one side connected to an independent input/output (y0 to y7) and the other side connected to a common input/output (z). with e low, one of the eight switch es is selected (low-impedance on-state) by s1 to s3. with e high, all switches are in the high-impedan ce off-state, independent of s1 to s3. if break before make is needed, then it is necessary to use the enable input. v dd and v ss are the supply voltage connections for the digital control inputs (s1 to s3, and e ). the v dd to v ss range is 3 v to 15 v. the analog inputs/outputs (y0 to y7, and z) can swing between v dd as a positive limit and v ee as a negative limit. v dd ? v ee may not exceed 15 v. unused inputs must be connected to v dd , v ss , or another input. for operation as a digital multiplexer/demultiplexer, v ee is connected to v ss (typically ground). v ee and v ss are the supply voltage connections for the switches. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? fully static operation ? 5 v, 10 v, and 15 v parametric ratings ? standardized symmetrical output characteristics ? esd protection: ? mil-std-833, method 3015 exceeds 2000v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? complies with jedec standard jesd 13-b 3. applications ? analog multiplexing and demultiplexing ? digital multiplexing and demultiplexing ? signal gating HEF4051B-Q100 8-channel analog multiplexer/demultiplexer rev. 2 ? 11 september 2014 product data sheet
hef4051b_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all righ ts reserved. product data sheet rev. 2 ? 11 september 2014 2 of 21 nxp semiconductors HEF4051B-Q100 8-channel analog multiplexer/demultiplexer 4. ordering information 5. functional diagram table 1. ordering information all types operate from ? 40 ? c to +125 ? c. type number package name description version hef4051bt-q100 so16 plastic small outline pa ckage; 16 leads; body width 3.9 mm sot109-1 hef4051btt-q100 tssop16 plastic thin shrink small ou tline package; 16 leads; body width 4.4 mm sot403-1 fig 1. functional diagram 001aac277 logic level conversion 11 16 v dd 13 y0 s1 1 ? of ? 8 decoder 14 y1 15 y2 12 y3 1y4 5y5 2y6 4y7 3z 10 s2 9 s3 6 87 v ss v ee e
hef4051b_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all righ ts reserved. product data sheet rev. 2 ? 11 september 2014 3 of 21 nxp semiconductors HEF4051B-Q100 8-channel analog multiplexer/demultiplexer fig 2. schematic diagram (one switch) 001aac281 yn z v ee v dd v dd fig 3. logic symbol fig 4. iec logic symbol 001aac278 13 y0 14 11 y1 s1 10 s2 9 s3 6 e 15 y2 12 y3 1 y4 5 y5 z 3 2 y6 4 y7 3 1 mux/dmux 13 en 14 15 12 3 1 5 2 4 0 1 2 3 4 5 6 7 001aac279 x 0 7 11 10 9 6
hef4051b_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all righ ts reserved. product data sheet rev. 2 ? 11 september 2014 4 of 21 nxp semiconductors HEF4051B-Q100 8-channel analog multiplexer/demultiplexer fig 5. logic diagram 001aac280 y0 y1 y2 y3 y4 y5 y6 y7 z level converter level converter s1 level converter s2 level converter s3 e
hef4051b_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all righ ts reserved. product data sheet rev. 2 ? 11 september 2014 5 of 21 nxp semiconductors HEF4051B-Q100 8-channel analog multiplexer/demultiplexer 6. pinning information 6.1 pinning 6.2 pin description fig 6. pin configuration sot109-1 f ig 7. pin configuration sot403-1 + ( ) % 4 < 9 ' ' < < |