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c-mos peripheral control ic for r3000 (gate array)
- top view - CXD8986R (1/4)
il11 v dd (+5 v) v dd (+5 v) v dd (+5 v) v dd (+5 v) v dd (+5 v) v dd (+5 v) gnd gnd nc nc gnd gnd nc gnd gnd nc gnd nc gnd nc gnd gnd gnd gnd 132
130
125
120
115
110
105
100
95
90
89 133
135
140
145
150
155
160
165
170
175
176 1
5
10
15
20
25
30
35
40
44 88
85
80
75
70
65
60
55
50
45
CXD8986R (2/4) pin
no. i/o signal 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44 (v dd = +5 v) be8cs
beccs
gnd
scsird
scsiwr
nc
scsics1
scsics0
nc
dbclk
dmaccs
gnd
iord
iowr
mrd
mwr
dma _ aen
dmaak3
dmaak2
dmaak1
dmaak0
v dd
sys _ frame
sys _ 1/2v
sys _ field
rden
wren
ioen
vsbus _ rxdata
vsbus _ rxclk
vsbus _ reset
gnd
sioba
siocd
sio2rd
sio2wr
sio1rd
sio1wr
pio3cs
pio2cs
pio1cs
ctc2cs
ctc1cs
flashcs
o
o
? o
o
? o
o
? o
o
? i/o
i/o
i
i
i
i
i
i
i
? i
i
o
o
o
o
i
o
i
? o
o
o
o
o
o
o
o
o
o
o
o
pin
no. i/o signal 45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88 ram2cs
ram1cs
gnd
d0
d1
d2
d3
d4
d5
d6
d7
gnd
wrena
wrenb
wrenc
wrend
nc
ben0
ben1
ben2
ben3
v dd
a0
a1
a22
a23
a24
a25
a26
a27
a28
gnd
burst
last
rd
wr
dataen
sysclk
sys _ reset
nc
ack
v dd
rdcen
m _ strobe o
o
? i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
? o
o
o
o
? i
i
i
i
? i
i
i
i
i
i
i
i
i
? i
i
i
i
i
i
i
? o
? o
i pin
no. i/o signal 89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132 io _ strobe
extdataen
gnd
rxfifo3en
rxfifo2en
rxfifo1en
rxfifo0en
txfifo3en
txfifo2en
diagfifo1en
diagfifo0en
gnd
rxfifo _ rck
txfifo _ wck
sdc _ recen
sdc _ pben
dbwait
pio _ reset
ltc _ wen
ca2crck
ca1crck
v dd
acccs
ac8cs
ac4cs
ac0cs
sddirx2cs
sddirx1cs
sdditx2cs
sdditx1cs
sdc _ sddirden
gnd
dsp _ hbck
dsp _ hrs
dsp _ hxs
dsp _ hr
dsp _ hx
enc _ enn3 _ 3
enc _ enn2
enc _ enn1
dec _ enn3 _ 3
dec _ enn2
dec _ enn1
af8cs i
o
? o
o
o
o
o
o
o
o
? o
o
o
o
i
o
o
o
o
? o
o
o
o
o
o
o
o
o
? o
o
o
o
i
o
o
o
o
o
o
o pin
no. i/o signal 133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176 af4cs
af0cs
gnd
b40cs
b44cs
b48cs
b4ccs
b50cs
b54cs
b58cs
b5ccs
gnd
nc
b80cs
b84cs
b88cs
b8ccs
b90cs
b94cs
b98cs
b9ccs
v dd
afccs
ba0cs
ba4cs
ba8cs
baccs
bb0cs
bb4cs
bb8cs
bbccs
gnd
nc
bc0cs
bc4cs
bc8cs
bcccs
bd0cs
bd4cs
bd8cs
bdccs
v dd
be0cs
be4cs o
o
? o
o
o
o
o
o
o
o
? ? o
o
o
o
o
o
o
o
? o
o
o
o
o
o
o
o
o
? ? o
o
o
o
o
o
o
o
? o
o
CXD8986R (3/4) input/output
d0 - 7
iord
iowr
input
a0, a1, a22 - a28
ben0 - 3
burst
dataen
dbwait
dma _ aen
dmaak0 - 3
dsp _ hx
io _ strobe
last
m _ strobe
mrd
mwr
rd
sys _ 1/2v
sys _ frame
sys _ reset
sysclk
vsbus _ reset
vsbus _ rxdata
wr
; cpu data bus 0 - 7
; i/o read pulse for dma controller
; i/o write pulse for dma controller
; cpu address bus 0, 1, and 22 - 28
; cpu byte enable 0 - 3
; burst state
; data enable pulse
; cpu wait
; dma address enable
; dma acknowledge 0 - 3
; receive data for audio dsp i/f
; i/o strobe pulse
; last state
; memory strobe pulse
; memory read for controller
; memory write for controller
; cpu read pulse
; system 1/2 v pulse
; system frame pulse
; system reset
; 20 mhz reference clock
; vsbus rx clock reset
; vsbus input data
; cpu write pulse
CXD8986R (4/4) output
cs
ack
b4ccs
b48cs
ca1crck, ca2crck
ctc1cs
ctc2cs
dbclk
dec _ enn1, 2, 3 _ 3
diagfifo0en
diagfifo1en
dmaccs
dsp _ hbck
dsp _ hr
dsp _ hrs
dsp _ hxs
enc _ enn1, 2, 3 _ 3
extdataen
flashcs
ioen
ltc _ wen
pio _ reset
pio1cs
pio2cs
pio3cs
ram1cs
ram2cs
rdcen
rden
rxfifo _ rck
rxfifo0en
rxfifo1en
rxfifo2en
rxfifo3en
scsics0
scsics1
scsird
scsiwr
sdc _ pben
sdc _ recen
sdc _ sddirden
sddirx1cs
sddirx2cs
sdditx1cs
sdditx2cs
sio1rd
sio1wr
sio2rd
sio2wr
sioba
siocd
sys _ field
txfifo _ wck
txfifo2en
txfifo3en
vsbus _ rxclk
wren
wrena - wrend
; chip select (address : xxxxxh)
; acknowledge
; interrupt acknowledge (address : b4cxxxxxh)
; interrupt controller chip select (address : b48xxxxxh)
; sdi audio data write clock
; ctc 1 chip select (address : a60xxxxxh)
; ctc 2 chip select (address : a70xxxxxh)
; 1/2 dividing sysclk
; address enable 1 - 3 for dec-79
; chip select (address : b60xxxxxh)
; chip select (address : b64xxxxxh)
; dma controller chip select (address : ad0xxxxxh)
; bit clock for audio dsp i/f
; send data for audio dsp i/f
; send start for audio dsp i/f
; receive start for audio dsp i/f
; address enable 1 - 3 for enc-29
; extended data enable
; flash chip select (address : bf0xxxxxh)
; i/o enable
; ltc write enable
; parallel i/o reset
; pio 1 chip select (address : a40xxxxxh)
; pio 2 chip select (address : a50xxxxxh)
; pio 3 chip select (address : a58xxxxxh)
; sram chip select (address : a00xxxxxh)
; sram chip select (address : a10xxxxxh)
; read chip enable
; read enable
; read clock for rx fifo
; chip select (address : b70xxxxxh)
; chip select (address : b74xxxxxh)
; chip select (address : b78xxxxxh)
; chip select (address : b7cxxxxxh)
; spcr8 (address : ae8xxxxxh) or spcr16 (address : b10xxxxxh)
; spcdma chip select (address : b00xxxxxh)
; l : read for scsi
; spcr8 lower byte write enable
; sdc pb data bus enable
; sdc rec data bus enable
; sdc sddi read enable
; sddi decoder 2 chip select (address : ab0xxxxxh)
; sddi decoder 1 chip select (address : ab8xxxxxh)
; sddi encoder 2 chip select (address : aa0xxxxxh)
; sddi encoder 1 chip select (address : aa8xxxxxh)
; sio 1 read enable (address : a80xxxxxh)
; sio 1 write enable (address : a80xxxxxh)
; sio 2 read enable (address : a90xxxxxh)
; sio 2 write enable (address : a90xxxxxh)
; sio ba register select
; sio cd register select
; system field pulse
; write clock for tx fifo
; chip select (address : b68xxxxxh)
; chip select (address : b6cxxxxxh)
; vsbus rx clock
; write enable
; sram a - d write enable *** ***
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