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- 1 - oled specification WEG005016ALPP5N00000 model no: free datasheet http:///
- 2 - 7 8 6 52 54 60 7 9 24 32 28 6 5 51 29 11 free datasheet http:///
- 3 - specification version: a customer : module no. : WEG005016ALPP5N00000 approved by: ( for customer use only ) sales by approved by checked by prepared by issued date: free datasheet http:///
- 4 - modle no records of revision doc. first issue version date revised page no. summary 0 a 2010/11/18 2010.12.20 10 first issue 68 series only free datasheet http:///
- 5 - 1. module classification information w e g 005016 a l p p 5 n 00000 1 2 3 4 5 6 7 8 ? 1 brand winstar display corporation 2 e oled 3 display type h character type, g graphic type 4 number of dots 50*16 dots 5 serials code a amber r red b blue c full color g green w white 6 emitting color y yellow green l yellow 7 polarizer p with polarizer; n: without polarizer 8 display mode p passive matrix ; a: active matrix 9 driver voltage 3: 3.0 v; 5: 5.0v 10 touch panel n without touch panel; t: with touch panel 11 serial no. 00000: sales code free datasheet http:///
- 6 - 2. general specification item dimension unit number of characters 50*16 dots module dimension 58.0 x 32.0 x 10.0(max) mm view area 38.0 x 16.0 mm active area 29.96 x 11.16 mm dot size 0.56 x 0.66 mm dot pitch 0.60x 0.70 mm lcd type oled , yellow duty 1/16 3. absolute maximum ratings item symbol min max unit notes operating temperature t op -40 +80 storage temperature t st -40 +80 input voltage v i -0.3 vdd v supply voltage for logic vdd-v ss -0.3 5.3 v free datasheet http:///
- 7 - 4. electrical characteristicsical item symbol condition min typ max unit supply voltage for logic vdd-vss 3.0 5.0 5.3 v input high volt. vih 0.9 vdd vdd v input low volt. vil gnd 0.1vdd v output high volt. voh ioh=-0.5ma 0.8 vdd vdd v output low volt. vol iol=0.5ma gnd 0.2 vdd v supply current idd vdd=5v 16 ma ciex(yellow) x,y(cie1931) 0.44 0.48 0.52 ciey(yellow) x,y(cie1931) 0.46 0.50 0.54 5. optical characteristics item symbol condition min typ max unit (v) 160 deg view angle (h) 160 deg contrast ratio cr dark 2000:1 t rise 10 s response time t fall 10 s supply voltage for logic 5v 50% checkboard brightness with polarizer 125 nits supply voltage for logic 3v 50% checkboard brightness with polarizer 175 nits free datasheet http:///
- 8 - 6. interface pin function pin no. symbol level description 1 vss 0v ground 2 vdd 5.0v supply voltage for logic 3 nc 4 rs h/l h: data, l: instruction code 5 r/w h/l h: read(mpu module) l: write(mpu module) 6 e h,h l chip enable signal 7 db0 h/l data bit 0 8 db1 h/l data bit 1 9 db2 h/l data bit 2 10 db3 h/l data bit 3 11 db4 h/l data bit 4 12 db5 h/l data bit 5 13 db6 h/l data bit 6 14 db7 h/l data bit 7 15 nc 16 nc brightness control brightness(nits) power consumption(measured with random texts) 125(typical) 80mw(5v*16ma) notes: 1.when random texts pattern is running , averagely , at any instance , about 1/2 of pixels will be on. 2. you can to use the display off mode to make long life. free datasheet http:///
- 9 - 7. counter drawing & block diagram the non-specified tolerance of dimension is 0.3 mm . scale 10/1 dot sizes db4 12 14 13 db6 db5 vss 1 e 7 11 10 8 9 db3 db2 db1 db0 4 6 5 3 2 r/w rs nc vdd db7 14.02 29.96(aa) 10.0 38.0(va) 7.4 43.2 10.07 11.16(aa) 8.0 16.0(va) 4.4 23.1 58.0 0.5 32.0 0.5 2.5 53.0 2.5 27.0 29.0 4- 2.5 pth 4- 5.0 pad 1.6 10.0 max nc 15 nc 16 4.5 0.8 1.3 0.56 0.60 0.66 0.70 50*16 1 2 15 16 free datasheet http:///
- 10 - 8. function description free datasheet http:///
- 11 - registers ic provides two types of 8-bit registers, namely: in struction register (ir) and data register (dr). the register is selected using the rs pin. when the rs pin is set to "0", the instruction register type is selected. when rs pin is set to "1", the data register type is selected. please refer to the table below. rs r/wb operation 0 0 instruction register write as an internal operation. 0 1 read busy flag (db7) and address counter (db0 to db6) 1 0 data register write as an internal operation (dr to ddram or cgram) 1 1 data register read as an internal operation (ddram or cgram to dr) instruction register (ir) the instruction register is used to store the instruction code (i.e. display clear, cursor home and others), display data ram (ddram) address, and the character generator ram (cgram) address. instruction register can only be written from the mpu. data register (dr) the data register is used as a temporary storage for data that are going to be written into the ddram or cgram as well as those data that are going to be read from the ddram or cgram. busy flag (bf) the busy flag is used to determine whether ic is id le or internally operating. when ic is performing some internal operations, the busy flag is set to "1 ". under this condition, the no other instruction will not be accepted. when rs pin is set to "0" and r/wb pin is set to "1", the busy flag will be outputted to the db7 pin. when ic is idle or has completed its previous internal operation, the busy flag is set to "0". the next instruction can now be processed or executed. address counter (ac) the address counter is used to assign the disp lay data ram (ddram) address and the character generator ram (cgram) address. when address inform ation is written into the instruction register (ir), this address information is sent from the instruction register to the address counter. at the same time, the nature of the address (either cgram or ddram) is determined by the instruction. after writing into or reading from the ddram or cgram, the address counter is automatically increased or decreased by 1 (for write or read function). it must be noted that when the rs pin is set to "0" and r/wb is set to "1", the contents of the address counter are outputted to the pins -- db0 to db6. free datasheet http:///
12 display data ram (ddram) the display data ram (ddram) is used to store the display data which is represented as 8-bit character code. the display data ram supports an extended capacity of 128 x 8-bits or 128 characters. the display data ram address (add) is set in the address counter as a hexadecimal. high order bits low order bits address counter (hex) ac6 ac5 ac4 ac3 ac2 ac1 ac0 an example of a ddram address=39 is given below. ddram address: 39 ac6 ac5 ac4 ac3 ac2 ac1 ac0 0 1 1 1 0 0 1 1-line display (n=0) when the number of characters displayed is less th an 128, the first character is displayed at the head position. the relationship between the ddram address and position on the oled panel is shown below. display position (digit) 1 2 3 4 ????. 126 127 128 ddram address (hexadecimal) 00 01 02 03 ????. 7d 7e 7f for example, when only 8 characters are displayed in one display line, the relationship between the ddram address and position on the oled panel is shown below. display position 1 2 3 4 5 6 7 8 ddram address 00 01 02 03 04 05 06 07 shift left 01 02 03 04 05 06 07 08 shift right 7f 00 01 02 03 04 05 06 free datasheet http:///
13 2-line display (n=1 ) case 1: the number of characters displayed is less than 64 x 2 lines when the number of characters displayed is less than 64 x 2 lines, then the first character of the first and second lines are displayed starting from the head. it is important to note that every line reserve 64 x8bits ddram space. 1 st line is 00 to 3f,second line is 40 to 7f.please refer the figure below. display position 1 2 3 4 ???. 61 62 63 64 00 01 02 03 ???. 3c 3d 3e 3f ddram address (hexadecimal) 40 41 42 43 ???. 7c 7d 7e 7f to illustrate, for 2-line x 20 characters display, the relati onship between the ddram address and position of the oled panel is shown below. display position 1 2 3 4 ???. 18 19 20 00 01 02 03 ???. 11 12 13 ddram address (hexadecimal) 40 41 42 43 ???. 51 52 53 01 02 03 04 ???. 12 13 14 shift left 41 42 43 44 ???. 52 53 54 3f 00 01 02 ???. 10 11 12 shift right 7f 40 41 42 ???. 50 51 52 free datasheet http:///
14 case 2: 40-character x 2 lines display ic(master) can be extended to display 40 characters x 2 lines by cascade the other ic(slave). when there is a display shift operation, the ddram address is also shifted. please refer to the example below. display position 1 2 3 4 5 6 7 8 9 10 11 ?. 37 38 39 40 00 01 02 03 04 05 06 07 08 09 0a ?. 24 25 26 27 40 41 42 43 44 45 46 47 48 49 4a ?. 64 65 66 67 ddram address ic display (master) cascade 2 nd ic(slave) 01 02 03 04 05 06 07 08 09 0a 0b ?. 25 26 27 28 shift left 41 42 43 44 45 46 47 48 49 4a 4b ?. 65 66 67 68 3f 00 01 02 03 04 05 06 07 08 09 ?. 23 24 25 26 shift right 7f 40 41 42 43 44 45 46 47 48 49 ?. 63 64 65 66 free datasheet http:///
15 slave mode data input when ic is under slave mode, display data is send from the other ic(master).the input data ?d? is shifted at the falling edge of cl m/s mode d cl lat h master output output output l slave input input input free datasheet http:///

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