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gps rf downconverter adsst-gpsrf01 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?200 7 analog devices, inc. all rights reserved. features single chip gps downconverter gps l1 band c/a code (1575.42 mhz) receiver 2.7 v to 3.3 v power supply on-chip lna on-chip pll including complete vco on-chip reference oscillator on-chip nco for sampling clock option to choose 6.144 mhz, or 6.552 mhz, or external sampling clock 60 db agc dynamic range sign and magn outputs low power operation 55 ma supports power-down mode applications security applications asset tracking marine navigation portable gps receiver general description the adsst-gpsrf01 is a high performance, fully integrated, rf front-end chip for downconversion and amplification of gps signals. it has been desi gned for l1 (1575.42 mhz), c/a gps band receivers. the adsst-gpsrf01 is a dual conversion, superheterodyne receiver with an on-chip low noise amplifier (lna), local oscil- lator, two downconversion if stages (at 24.52 mhz and 8.194 mhz, respectively), an automatic gain controlled amplifier (agc), and a 2-bit analog-to-digital converter (adc). two selectable, fixed frequency sampling clocks from an on-chip nco can be used for output sampling (6.144 mhz or 6.552 mhz). in addition, an external sampling clock can be used up to 32 mhz. the chip can be interfaced with any active/passive gps antenna. functional block diagram 03233-001 1575.42mhz 24.52mhz 8.194mhz div 2 div 5 nco pf detector cmdphi 0:6.552mhz cmdphi 1:6.144mhz 0 1 cmdckadc ckin cmdphi quartz on/off 1575.42mhz 1550.9mhz mixer1 lna if1 if2 mixer2 16.3252910mhz ch pump vco adc magn ckout sign div 2 div 4 div 19 figure 1.
adsst-gpsrf01 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 theory of operation ........................................................................ 8 power supplies .............................................................................. 8 matching network ........................................................................ 8 lna matching network .............................................................. 8 mixer matching network .............................................................9 reference clock generation ..................................................... 10 pll filter ..................................................................................... 10 if input network ........................................................................ 10 mixer2 output network ............................................................ 10 agc/adc ................................................................................... 11 numerically controlled oscillator (nco) ............................. 11 power on/standby mode .......................................................... 12 adc sampling clock selection ............................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 3 /07 revision 0: initial version
adsst-gpsrf01 rev. 0 | page 3 of 16 specifications recommended operating conditions: vcc = 2.7 v to 3.3 v, vee = 0 v, typical is at vcc = 3 v, and t a @ 25c. table 1. parameter conditions min typ max unit lna characteristics see the lna matching network section rf frequency 1570 1575.42 1580 mhz input impedance with external matching network 50 input vswr with external matching network 1 2 output impedance with external matching network 50 output vswr with external matching network 1 2 gain with external matching network, typical simulation 17 21 25 db no external matching network 12 16 20 db op1db ?4 dbm noise figure typical simulation 3 db mixer characteristics see the mixer matching network section rf frequency 1570 1575.42 1580 mhz lo frequency 95 times the reference frequency 1550.9 mhz if frequency 24 24.51 25.5 mhz input impedance with external matching network 50 input vswr with external matching network 1 2 differential output impedance see mixer matching network section 1000 conversion gain with external matching network 7 12 16 db no external matching network 7 15 17 db op1db ?16 ?12 dbm ssb noise figure typical simulation 15 db pilote characteristics reference frequency 16.325291 mhz input magnitude level on a 50 load ?4 0 dbm gain 8 10 13 db output level high, v oh vcc v output level low, v ol vcc ? 0.8 v vco characteristics see the pll filter section nominal frequency with the reference frequency 1.45 1.55 1.68 ghz phase noise (free-running vco) typical simulations @ 400 khz ?78 dbc/hz phase noise (closed loop) with proposed filter (loop bandwidth 100 khz) typical simulation @ 100 khz ?66 dbc/hz nonharmonic spurious (closed loop) typical simulations @ 8 khz ?30 dbc @ 16 khz ?40 dbc @ 24 khz ?50 dbc vco slope typical simulations 1.2 2.4 3.5 ghz/v vtune voltage 0.6 vcc v if1/mixer characteristics input frequency with the reference frequency 24.51 mhz output frequency with the reference frequency 8.192 mhz differential input impedance see the if input network section 1000 differential output impedance see the if input network section 1000
adsst-gpsrf01 rev. 0 | page 4 of 16 parameter conditions min typ max unit gain (s21) (if1 + mixer2) without agc regulation maximum +41 +56 +72 db minimum ?29 ?26 ?20 db noise figure typical simulations s21 = +50 db 6 db s21 = +20 db 15 db s21 = ?10 db 45 db op1db typical simulations s21 = +50 db ?15 dbm s21 = +20 db ?18 dbm s21 = ?10 db ?45 dbm agc dynamic range 65 db agc slope typical simulations for a gain within 20 db 30 db range 300 2500 db/v agc voltage range (on camp pin) typical simulations 400 mv camp pin maximum rating voltage if externally controlled 1 vcc v magnitude bit duty cycle (use for agc regulation point) this rate allows adsst-gpsrf01 to fix the conversion loss below 0.6 db 23 33 43 % agc band-pass typical simulations 1 3 10 khz lo2 leakage on mixer2 output ?28 ?17 dbm output offset for a gain within 20 db 30 db range <100 mv if2 characteristics see the if input network section frequency 8.192 mhz differential input impedance see the if input network section 1000 gain 31 34 39 db op1db ?15 dbm lsb typical simulations 100 mv output test attenuation ?20 db output test level on a 50 load ?40 dbm input cmos levels ckin, cmdckadc, cmdphi, power on input cmos level high, v ih vcc 0.7 v input cmos level low, v il 0.3 vcc v output cmos levels magn, sign, ckout output cmos level high, v oh vcc 0.85 v output cmos level low, v ol 0.15 vcc v maximum rating output load 15 pf ckout to magn/sign skew typical simulations 20 ns power consumption standby measured 0.1 ma 3 v (min @ ?40c, max @ +85c ) 40 55 65 ma
adsst-gpsrf01 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating vcc to vee 1 ?0.3 v to +5 v analog i/o voltage to vee ?0.3 v to vcc + 0.3 v digital i/o voltage to vee ?0.3 v to vcc + 0.3 v operating temperature range ?40c to +85c storage temperature range ?40c to +150c maximum junction temperature +125c 1 vee = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
adsst-gpsrf01 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions 03233-002 48 veeif1 47 if1inb 46 if1in 45 agc 44 agcb 43 vccif1 42 mix2out 41 mix2outb 40 veeif2 39 if2inb 38 if2in 37 vccif2 35 iftest 34 camp 33 vccadc 30 ckin 31 vccdig 32 veeadc 36 veeadc 29 sign 28 magn 27 ckout 25 nc 26 veedig 2 mix1out 3 veelna 4 lnain 7 veelna 6 veelna 5 veelna 1 mix1outb 8 vcclna 9 lnaout 10 vccmix1 12 veemix1 11 mix1in nc = no connect 13 veevco 14 vccvco 15 veevco 16 vtuneb 17 vtune 18 power on 19 cmdphi 20 pilotein 21 piloteoutb 22 cmdckadc 23 veepll 24 vccpll pin 1 adsst-gpsrf01 top view (not to scale) figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic pin type description 1 mix1outb analog mixer1 output, if1 signal, (24.52 mhz). 2 mix1out analog complementary mixer1 output. 3, 5 to 7 veelna ground lna ground. 4 lnain analog lna rf input signal, (1575.42 mhz). 8 vcclna supply lna supply. 9 lnaout analog lna rf output signal, (1575.42 mhz). 10 vccmix1 supply mixer1 supply. 11 mix1in analog mixer1 rf input signal, (1575.42 mhz). 12 veemix1 ground mixer1 ground. 13, 15 veevco ground vco ground. 14 vccvco supply vco supply. 16 vtuneb analog vco input command. this pin is used for internal decoupling. 17 vtune analog external pll filter connection. 18 power on cmos power-on input. 19 cmdphi cmos nco frequency switch input control. 20 pilotein analog reference clock input. 21 piloteoutb analog reference cloc k output with 180 phase shift. 22 cmdckadc cmos nco/ckin switch input control. 23 veepll ground pll ground. 24 vccpll supply pll supply. 25 nc not connected. 26 veedig ground digital ground. 27 ckout cmos clock output. 28 magn cmos magnitude bit data output. 29 sign cmos sign bit data output. 30 ckin cmos external sampling clock input. 31 vccdig supply digital supply. 32, 36 veeadc ground adc ground. 33 vccadc supply adc supply. 34 camp analog amplitude bit capacitor signal.
adsst-gpsrf01 rev. 0 | page 7 of 16 pin no. mnemonic pin type description 35 iftest analog if test output. 37 vccif2 supply if2 supply. 38 if2in analog second amplifier if input, (8.194 mhz). 39 if2inb analog complementary second amplifier if input. 40 veeif2 ground substrate connection to die paddle. 41 mix2outb analog mixer2 output, if2 signal, (8.194 mhz). 42 mix2out analog complementary mixer2 output, if2 signal. 43 vccif1 supply if1 supply. 44 agcb analog agc capacitor signal. 45 agc analog complementary agc capacitor signal. 46 if1in analog first amplifier if input, (24.52 mhz). 47 if1inb analog complementary first amplifier if input. 48 veeif1 ground if1 ground.
adsst-gpsrf01 rev. 0 | page 8 of 16 theory of operation power supplies the adsst-gpsrf01 uses eight different power supply groups as follows: a. vcclna and veelna b. vccmix1 and veemix1 c. vccvco and veevco d. vccif1 and veeif1 e. vccif2 and veeif2 f. vccadc and veeadc g. vccdig and veedig h. vccpll and veepll these separate power groups increase isolation between internal components. each power supply group is externally decoupled by a single low value capacitor for oscillation risk reduction. there should be only one regulated 3 v power supply on the board and only one common ground. if isolation is not high enough, a separate 3 v regulated power supply should be used. matching network the rf input has an unmatched input impedance. the necessary 50 rf external input matching components must be mounted as close to the rf input as possible. input and output matching networks provide 50 source and load impedance. lna matching network lna input is internally biased; therefore, it should be externally ac-coupled. tests were made with lumped matching elements, performing maximum power transfer between lna and input and output. input matching impedances given in table 4 are designed for simultaneous input and output matching. input and output rf signals should be connected to the external devices via a 50 line. table 4. external components used for lna matching component name typical value unit l in 3.3 nh c in 2.7 pf l out 5.6 nh c out 1.2 pf c link 100 pf 03233-003 c link c in 50 ? line v cc l out l in 50 ? line c out figure 3. lna matching network connections
adsst-gpsrf01 rev. 0 | page 9 of 16 mixer matching network the mixer structure is double-balanced with open-collector outputs. the local oscillator (lo) input and if output are fully differential. one of the rf differential port inputs is internally decoupled. the other rf input must be externally ac-coupled. the rf inputs have unmatched input impedance. the 50 matching is obtained with external components. the if outputs require external dc bias to vcc. this bias is provided through two inductors that also cancel the imaginary part of the output impedance. rf input requires 50 matching to ensure maximum power transfer. due to its high impedance, the if output is not matched, but external components must be added to provide the filter input with a 1000 load. an external 1000 parallel resistor performs this task and also decreases the sensitivity to component toler- ances. this 1000 external resistor must not be confused with the 1000 load that represents the filter input. table 5. external components used for mixer matching component name typical value unit l in 5.6 nh c in not connected pf c link 100 pf l coil 10 h r out 1 k note that c in can be omitted due to the parasitic capacitor displayed by the board. 03233-004 c link l in c in lo r out v c c l coil l coi l figure 4. mixer matching network connections
adsst-gpsrf01 rev. 0 | page 10 of 16 table 6. mode crystal frequency with an equivalent c l load capacitance equivalent series resistances (typical) shunt capacitance (typical) drive level (typical) c1, c2 c l fundamental 16.3252910 mhz 10 5.5 pf 50 w 39 pf 22 pf reference clock generation the pilote input/output are internally biased, therefore, they must be externally ac-coupled. the pilote structure allows the adsst-gpsrf01 to be directly driven by an external reference clock or to be used as an oscillator with an external crystal (see figure 5 for the circuit connection and table 6 for the component values). 03233-005 crystal piloteoutb pilotein c1 c2 figure 5. crystal connections pll filter the pll generates the local oscillation. it includes a vco with an on-chip tank circuit, dividers, and a phase detector with external loop filter components. a reference frequency is required for the pll. the pll is a second- or a third-order loop, type 2 for zero frequency error. this vco is a monolithic lc voltage controlled oscillator. the loop gain is maintained high enou gh to ensure oscillations in all process, temperature, and power supply conditions. the voltage control is amplified by a low gain differential amplifier. the divider chain involves three dividers. the first one is a fast divider by two. the second one is a divider by five. the third one divides by 19. the whole divider divides the local oscillator (lo) frequency by 190 before being compared with the reference clock divided by 2. the pll provides a local oscillator frequency divided by a 40 mhz cmos output clock to an nco that, in turn, delivers either a 6.144 mhz or 6.552 mhz clock for the dsp serial link. the pilote provides a 16.3252910 mhz clock. the design of the pll depends on two criteria: the filtering of the reference frequency signal and the phase noise of the output signal of the pll. the phase noise of the vco is filtered by the pll. the pll includes a charge-pump active filter to perform a second-order loop. the pll loop filter components are selected to give a pll loop bandwidth of approximately 100 khz to minimize phase noise. an additional on-chip lpf (r = 10 k and c = 10 pf) is present in series in the vtune command and allows better rejection harmonics of the comparison frequency. the pll filter is listed in table 7 and displayed in figure 6 . table 7. external components used for the pll filter component name typical value unit c1 22 nf c2 1 nf r2 390 l2 shorted nh 03233-006 c1 r2 c2 l2 v tune figure 6. pll filter connections if input network iftest 03233-007 r1 r3 50 ? c1 v in c link r2 oc ?20db c link figure 7. if amplifier connections both if amplifier stages have to display, at minimum, 1000 at dc to get a good offset compensation. table 8 lists the limit offset values. these stages are internally biased requiring them to be ac-coupled. the iftest output is used for test purposes only; it checks the rf chain gain. table 8. external components used with if amplifiers component name typical value unit r1 3 k r2 1 k r3 2 k c1 1 nf c link 1 nf mixer2 output network the mixer structure is double-balanced with open-collector outputs. the if1 input, lo input, and if2 output are fully differential. the if1 outputs require external dc bias to vcc. this bias is provided through two 500 resistors that fix the differential output impedance to 1000 .
adsst-gpsrf01 rev. 0 | page 11 of 16 agc/adc to maximize the signal-to-noise ratio (snr) with a 2-bit adc, the agc regulation point is fixed at 1 to activate the amplitude bit 33% of the time. this mean time allows the adsst-gpsrf01 to fix the conversion loss below 0.6 db. when the whole chain gain is too high, the camp pin is at a high voltage (around 2 v depending on vcc) to reduce the if1 gain stage. when the whole chain gain is too low, the camp pin is at a low voltage (around 1.5 v depending on vcc) to reduce the if1 gain stage. in table 9 , if2 is the signal at the adc input and the lsb is the magnitude reference level. the data rate of the adc is dependent on the sampling clock employed in the design. table 9. sign and magn logic level vs. if2 magnitude level if2 magnitude level sign logic level magn logic level lsb < if2 1 1 0 < if2 < lsb 1 0 ?lsb < if2 < 0 0 0 if2 < ?lsb 0 1 03233-008 skew ckout magn, sign figure 8. ckout to magn/sign skew it is also necessary to stabilize the agc and to set the agc band-pass to be less sensitive to external strong spurious noise. therefore, some passive components are used on camp, agc, and agcb pins. table 10. external components used with the agc component name typical value unit r agc 2 k c agc 20 nf camp 20 nf 03233-009 r agc c agc camp camp agc agcb figure 9. agc connections numerically controlled oscillator (nco) the nco works with a 38.772 mhz (f crystal 19/8) master clock delivered by the pll. it includes a phase accumulator and delivers a fixed clock that has an average frequency of the nco clock selected. two frequencies are available: 6.144 mhz or 6.552 mhz. this clock has a phase jitter equal to a 38.772 mhz clock period. it is applied to both the adc and the clock input of the dsp serial link. the clock waveform is shown in figure 10 . the nco provides a 6.144 mhz/6.552 mhz clock with an accuracy of less than 2 hz. 0 3233-010 phase jitter 38.772mhz clock 6.144mhz/6.552mhz clock figure 10. nco clock behavior
adsst-gpsrf01 rev. 0 | page 12 of 16 power on/standby mode one digital input pad permits the adsst-gpsrf01 circuit to enter standby mode. table 11. power on logic control signal mode logic level power on active 1 stand by 0 adc sampling clock selection two digital input pins (cmdckadc and cmdphi) select the sampling clock. the sampling clock can come from the nco or from an external clock. this selection is performed by the cmdckadc pin (see table 1 2 ). table 12. cmdckadc logic control signal mode logic level cmdckadc nco sampling clock 0 ckin sampling clock 1 then, the cmdphi pin selects one of the two available frequencies generated by nco as listed in table 13 . table 13. cmdphi logic control signal nco frequency logic level cmdphi 6.552 mhz 0 6.144 mhz 1
adsst-gpsrf01 rev. 0 | page 13 of 16 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 11. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model operating voltage temperature range package description package option ADSST-GPSRF01BSTZ 1 3 v ?40c to +85c 48-lead lqfp st-48 1 z = pb-free part.
adsst-gpsrf01 rev. 0 | page 14 of 16 notes
adsst-gpsrf01 rev. 0 | page 15 of 16 notes
adsst-gpsrf01 rev. 0 | page 16 of 16 notes ?200 7 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03233-0- 3/07(0)

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