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| MCF51QU128 MCF51QU128 supports the MCF51QU128vlh, MCF51QU128vhs, mcf51qu64vlf, mcf51qu64vhs, mcf51qu32vhs, mcf51qu32vfm features ? operating characteristics C voltage range: 1.71 v to 3.6 v C flash write voltage range: 1.71 v to 3.6 v C temperature range (ambient): -40c to 105c ? core C up to 50 mhz v1 coldfire cpu C dhrystone 2.1 performance: 1.10 dmips per mhz when executing from internal ram, 0.99 dmips per mhz when executing from flash memory ? system C dma controller with four programmable channels C integrated coldfire debug_rev_b+ interface with single-wire bdm connection ? power management C 10 low power modes to provide power optimization based on application requirements C low-leakage wakeup unit (llwu) C voltage regulator (vreg) ? clocks C crystal oscillators (two, each with range options): 1 khz to 32 khz (low), 1 mhz to 8 mhz (medium), 8 mhz to 32 mhz (high) C multipurpose clock generator (mcg) ? memories and memory interfaces C flash memory, flexnvm, flexram, and ram C serial programming interface (ezport) C mini-flexbus external bus interface ? security and integrity C hardware crc module to support fast cyclic redundancy checks C 128-bit unique identification (id) number per chip ? analog C 12-bit sar adc C 12-bit dac C analog comparator (cmp) containing a 6-bit dac and programmable reference input C voltage reference (vref) ? timers C programmable delay block (pdb) C motor control/general purpose/pwm timers (ftm) C 16-bit low-power timers (lptmrs) C 16-bit modulo timer (mtim) C carrier modulator transmitter (cmt) ? communication interfaces C uarts with smart card support and fifo C spi modules, one with fifo C inter-integrated circuit (i2c) modules ? human-machine interface C up to 48 egpio pins C up to 16 rapid general purpose i/o (rgpio) pins C low-power hardware touch sensor interface (tsi) C interrupt request pin (irq) freescale semiconductor document number: MCF51QU128 data sheet: technical data rev. 4, 01/2012 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2010C2012 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 5 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 5 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 6 3.8 definition: typical value..................................................... 7 4 ratings ...................................................................................... 8 4.1 thermal handling ratings ................................................... 8 4.2 moisture handling ratings .................................................. 8 4.3 esd handling ratings ......................................................... 9 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 9 5.1 typical value conditions ................................................... 9 5.2 nonswitching electrical specifications ............................... 10 5.2.1 voltage and current operating requirements ...... 10 5.2.2 lvd and por operating requirements ................. 11 5.2.3 voltage and current operating behaviors .............. 12 5.2.4 power mode transition operating behaviors .......... 12 5.2.5 power consumption operating behaviors .............. 13 5.2.6 emc radiated emissions operating behaviors....... 17 5.2.7 designing with radiated emissions in mind ........... 18 5.2.8 capacitance attributes .......................................... 18 5.3 switching electrical specifications ..................................... 18 5.3.1 general switching specifications .......................... 18 5.4 thermal specifications ....................................................... 20 5.4.1 thermal operating requirements ........................... 20 5.4.2 thermal attributes ................................................. 21 6 peripheral operating requirements and behaviors .................... 21 6.1 core modules .................................................................... 21 6.1.1 debug specifications ............................................. 21 6.2 system modules ................................................................ 22 6.2.1 vreg electrical specifications .............................. 22 6.3 clock modules ................................................................... 23 6.3.1 mcg specifications ............................................... 23 6.3.2 oscillator electrical specifications ......................... 25 6.4 memories and memory interfaces ..................................... 27 6.4.1 flash (ftfl) electrical specifications.................... 27 6.4.2 ezport switching specifications ............................ 32 6.4.3 mini-flexbus switching specifications .................. 33 6.5 security and integrity modules .......................................... 36 6.6 analog ............................................................................... 37 6.6.1 adc electrical specifications ................................. 37 6.6.2 cmp and 6-bit dac electrical specifications ......... 39 6.6.3 12-bit dac electrical characteristics ..................... 42 6.6.4 voltage reference electrical specifications ............ 45 6.7 timers................................................................................ 46 6.8 communication interfaces ................................................. 47 6.8.1 spi switching specifications .................................. 47 6.9 human-machine interfaces (hmi)...................................... 50 6.9.1 tsi electrical specifications ................................... 50 7 dimensions ............................................................................... 51 7.1 obtaining package dimensions ......................................... 51 8 pinout ........................................................................................ 52 8.1 signal multiplexing and pin assignments .......................... 52 8.2 pinout diagrams................................................................. 54 8.3 module-by-module signals................................................. 58 9 revision history ........................................................................ 68 MCF51QU128 data sheet, rev. 4, 01/2012. 2 freescale semiconductor, inc. ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device: 1. go to http://www.freescale.com . 2. perform a part number search for the following partial device numbers: pcf51qu and mcf51qu. part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q cccc dd mmm t pp 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification cccc core code cf51 = coldfire v1 dd device number jf, ju, qf, qh, qm, qu table continues on the next page... 1 2 ordering parts MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 3 field description values mmm memory size (program flash memory) 1 ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb t temperature range, ambient (c) v = C40 to 105 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? hs = 44 laminate qfn (5 mm x 5 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) 1. all parts also have flexnvm, flexram, and ram. 2.4 example this is an example part number: MCF51QU128vlh terminology and guidelines 3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3 terminology and guidelines MCF51QU128 data sheet, rev. 4, 01/2012. 4 freescale semiconductor, inc. 3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. terminology and guidelines MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 5 3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range limited operating range - no permanent failure - possible decreased life - possible incorrect operation fatal range - probable permanent failure limited operating range - no permanent failure - possible decreased life - possible incorrect operation handling range - no permanent failure fatal range - probable permanent failure operating or handling rating (max.) operating requirement (max.) operating requirement (min.) operating or handling rating (min.) 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. terminology and guidelines MCF51QU128 data sheet, rev. 4, 01/2012. 6 freescale semiconductor, inc. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 7 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 solder temperature, leaded 245 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4 ratings MCF51QU128 data sheet, rev. 4, 01/2012. 8 freescale semiconductor, inc. 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v dio digital input voltage (except reset, extal, and xtal) C0.3 v dd + 0.3 v v aio analog, reset, extal, and xtal input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v vregin regulator input C0.3 6.0 v general 5.1 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 5 general MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 9 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v 1 v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v 2 i ic dc injection current single pin ? v in > v dd ? v in < v ss 0 0 2 C0.2 ma ma 3 dc injection current total mcu limit, includes sum of all stressed pins ? v in > v dd ? v in < v ss 0 0 25 C5 ma ma 3 v ram v dd voltage required to retain ram 1.2 v 1. the device always interprets an input as a 1 when the input is greater than or equal to v ih (min.) and less than or equal to v ih (max.), regardless of whether input hysteresis is turned on. 2. the device always interprets an input as a 0 when the input is less than or equal to v il (max.) and greater than or equal to v il (min.), regardless of whether input hysteresis is turned on. 3. all functional non-supply pins are internally clamped to vss and vdd. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. power supply must maintain regulation within operating vdd range during instantaneous and operating maximum current conditions. if positive injection current (vin > vdd) is greater than idd, the injection current may flow out of vdd and could result in external power supply going out of regulation. ensure external vdd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5.2 nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. 10 freescale semiconductor, inc. 5.2.2 lvd and por operating requirements table 2. lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 11 5.2.3 voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = - 9 ma ? 1.71 v v dd 2.7 v, i oh = -3 ma v dd C 0.5 v dd C 0.5 v v output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2 ma ? 1.71 v v dd 2.7 v, i oh = -0.6 ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 9 ma ? 1.71 v v dd 2.7 v, i ol = 3 ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2 ma ? 1.71 v v dd 2.7 v, i ol = 0.6 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) ? @ full temperature range ? @ 25 c 1.0 0.1 a a 1 i oz hi-z (off-state) leakage current (per pin) 1 a i oz total hi-z (off-state) leakage current (all input pins) 4 a r pu internal pullup resistors 22 50 k 2 r pd internal pulldown resistors 22 50 k 3 1. tested by ganged leakage method 2. measured at vinput = v ss 3. measured at vinput = v dd 5.2.4 power mode transition operating behaviors all specifications except t por and vllsx-run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 50 mhz ? bus clock (and flash and mini-flexbus clocks) = 25 mhz nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. 12 freescale semiconductor, inc. table 4. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls1 run 150 s 1 , 2 ? vlls2 run 75 s 1 , 2 ? vlls3 run 75 s 1 , 2 ? lls run 6.5 s 2 ? vlps run 4.6 s 2 ? stop run 4.6 s 2 1. normal boot (ftfl_fopt[lpboot] is 1) 2. the wakeup time includes the execution time for a small amount of firmware used to produce a gpio clear event. wakeup time is measured from the falling edge of the external wakeup event to the falling edge of a gpio clear performed by software. 5.2.5 power consumption operating behaviors table 5. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from ram ? @ 1.8 v ? @ 3.0 v 13 13 16 ma ma 2 i dd_run run mode current all peripheral clocks disabled, code executing from flash memory with page buffering disabled ? @ 1.8 v ? @ 3.0 v 14.3 14.5 17.9 ma ma 2 table continues on the next page... nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 13 table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current all peripheral clocks enabled, code executing from ram, exercising flash memory ? @ 1.8 v ? @ 3.0 v 20 20 23.5 25 ma ma 3 i dd_wait wait mode current at 3.0 v all peripheral clocks disabled 5.8 6.8 ma 4 i dd_stop stop mode current at 3.0 v ? @ C40 to 25 c ? @ 105 c 0.34 0.90 0.41 1.8 ma ma i dd_vlpr very low-power run mode current at 3.0 v all peripheral clocks disabled 0.63 1.32 ma 5 i dd_vlpr very low-power run mode current at 3.0 v all peripheral clocks enabled 0.78 1.46 ma 6 i dd_vlpw very low-power wait mode current at 3.0 v 0.15 0.62 ma 7 i dd_vlps very low-power stop mode current at 3.0 v ? @ C40 to 25 c ? @ 105 c 19 145 45 312 a 8 i dd_lls low leakage stop mode current at 3.0 v ? @ C40 to 25 c ? @ 105 c 3.0 53.3 4.8 157 a a 8 , 9 , 10 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25 c ? @ 105 c 1.8 39.2 3.3 115 a a 8 , 9 , 10 i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25 c ? @ 105 c 1.6 22.2 2.8 65 a a 8 , 9 i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25 c ? @ 105 c 1.4 17.6 2.6 50 a a 8 , 9 i dd_rtc average current adder for real-time clock function ? @ C40 to 25 c 0.7 a 11 1. the analog supply current is the sum of the active current for each of the analog modules on the device. see each module's specification for its supply current. 2. 50 mhz core and system clocks, and 25 mhz bus clock. mcg configured for fei mode. all peripheral clocks disabled. 3. 50 mhz core and system clocks, and 25 mhz bus clock. mcg configured for fei mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 50 mhz core and system clocks, and 25 mhz bus clock. mcg configured for fei mode. nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. 14 freescale semiconductor, inc. 5. 2 mhz core and system clocks, and 1 mhz bus clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash memory. 6. 2 mhz core and system clocks, and 1 mhz bus clock. mcg configured for blpe mode. all peripheral clocks enabled, but peripherals are not in active operation. code executing from flash memory. 7. 2 mhz core and system clocks, and 1 mhz bus clock. mcg configured for blpe mode. all peripheral clocks disabled. 8. osc clocks disabled. 9. all pads disabled. 10. data reflects devices with 32 kb of ram. for devices with 16 kb of ram, power consumption is reduced by 500 na. for devices with 8 kb of ram, power consumption is reduced by 750 na. 11. rtc function current includes lptmr with osc enabled with 32.768 khz crystal at 3.0 v 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode, except for 50 mhz core (fei mode) ? for the alloff curve, all peripheral clocks are disabled except ftfl ? for the allon curve, all peripheral clocks are enabled, but peripherals are not in active operation ? voltage regulator disabled ? no gpios toggled ? code execution from flash memory with cache enabled nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 15 figure 1. run mode supply current vs. core frequency nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. 16 freescale semiconductor, inc. figure 2. vlpr mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 6. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 20 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 19 v re3 radiated emissions voltage, band 3 150C500 17 v re4 radiated emissions voltage, band 4 500C1000 16 v re_iec iec level 0.15C1000 l 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions , and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 17 2. v dd = 3 v, t a = 25 c, f osc = 32 khz (crystal), f bus = 24 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method . 5.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com . 2. perform a keyword search for emc design. 5.2.8 capacitance attributes table 7. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 5.3 switching electrical specifications table 8. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 50 mhz f bus bus clock 25 mhz fb_clk mini-flexbus clock 25 mhz 1 f lptmr lptmr clock 25 mhz vlpr mode f sys system and core clock 2 mhz f bus bus clock 1 mhz fb_clk mini-flexbus clock 1 mhz 1 f lptmr lptmr clock 2 25 mhz 1. when the mini-flexbus is enabled, its clock frequency is always the same as the bus clock frequency. 2. a maximum frequency of 25 mhz for the lptmr in vlpr mode is possible when the lptmr is configured for pulse counting mode and is driven externally via the lptmr_alt1, lptmr_alt2, or lptmr_alt3 pin. nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. 18 freescale semiconductor, inc. 5.3.1 general switching specifications these general purpose specifications apply to all signals configured for egpio, mtim, cmt, pdb, irq, and i 2 c signals. the conditions are 50 pf load, v dd = 1.71 v to 3.6 v, and full temperature range. the gpio are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. table 9. egpio general control timing symbol description min. max. unit g1 bus clock from clk_out pin high to gpio output valid 32 ns g2 bus clock from clk_out pin high to gpio output invalid (output hold) 1 ns g3 gpio input valid to bus clock high 28 ns g4 bus clock from clk_out pin high to gpio input invalid 4 ns gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1 1.5 bus clock cycles gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 2 100 ns gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 2 50 ns external reset pulse width (digital glitch filter disabled) 100 ns mode select (ms) hold time after reset deassertion 2 bus clock cycles 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. g2 g1 g4g3 bus clock data outputs data inputs figure 3. egpio timing diagram nonswitching electrical specifications MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 19 the following general purpose specifications apply to all signals configured for rgpio, ftm, and uart. the conditions are 25 pf load, v dd = 3.6 v to 1.71 v, and full temperature range. the gpio are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. table 10. rgpio general control timing symbol description min. max. unit r1 cpuclk from clk_out pin high to gpio output valid 16 ns r2 cpuclk from clk_out pin high to gpio output invalid (output hold) 1 ns r3 gpio input valid to bus clock high 17 ns r4 cpuclk from clk_out pin high to gpio input invalid 2 ns r2 r1 r4r3 bus clock data outputs data inputs figure 4. rgpio timing diagram thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 115 c t a ambient temperature C40 105 c 5.4 thermal specifications MCF51QU128 data sheet, rev. 4, 01/2012. 20 freescale semiconductor, inc. 5.4.2 thermal attributes board type symbol description 64 lqfp 48 lqfp 44 laminate qfn 32 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 73 79 108 98 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 54 55 69 33 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 61 66 91 81 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 48 48 63 28 c/w 1 r jb thermal resistance, junction to board 37 34 44 13 c/w 2 r jc thermal resistance, junction to case 20 20 31 2.2 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 5.0 4.0 6.0 6.0 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditions junction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) . peripheral operating requirements and behaviors core modules 6.1.1 debug specifications table 12. background debug mode (bdm) timing number symbol description min. max. unit 1 t mssu bkgd/ms setup time after issuing background debug force reset to enter user mode or bdm 500 ns 2 t msh bkgd/ms hold time after issuing background debug force reset to enter user mode or bdm 1 100 s 6 6.1 peripheral operating requirements and behaviors MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 21 1. to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lvd . system modules 6.2.1 vreg electrical specifications table 13. vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 1.54 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.2 system modules MCF51QU128 data sheet, rev. 4, 01/2012. 22 freescale semiconductor, inc. clock modules 6.3.1 mcg specifications table 14. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 10 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 1.0 4.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 3.3 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2 , 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz table continues on the next page... 6.3 clock modules MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 23 table 14. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f vco = 48 mhz ? f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 7 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 7 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 50 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 8 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. clock modules MCF51QU128 data sheet, rev. 4, 01/2012. 24 freescale semiconductor, inc. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 9. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 15. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 200 300 950 1.2 1.5 na a a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 300 400 500 2.5 3 4 a a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 table continues on the next page... clock modules MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 25 table 15. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) ? 1 mhz resonator ? 2 mhz resonator ? 4 mhz resonator ? 8 mhz resonator ? 16 mhz resonator ? 20 mhz resonator ? 32 mhz resonator 6.6 3.3 0 0 0 0 0 k k k k k k k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. clock modules MCF51QU128 data sheet, rev. 4, 01/2012. 26 freescale semiconductor, inc. 6.3.2.2 oscillator frequency specifications table 16. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 1 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. memories and memory interfaces 6.4.1 flash (ftfl) electrical specifications this section describes the electrical characteristics of the ftfl module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. 6.4 memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 27 table 17. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk32k erase block high-voltage time for 32 kb 52 452 ms 1 t hversblk128k erase block high-voltage time for 128 kb 208 1808 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 18. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk32k t rd1blk128k read 1s block execution time ? 32 kb data flash ? 128 kb program flash 0.5 1.7 ms ms t rd1sec1k read 1s section execution time (data flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk32k t ersblk128k erase flash block execution time ? 32 kb data flash ? 128 kb program flash 55 220 465 1850 ms ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512 t pgmsec1k program section execution time ? 512 b flash ? 1 kb flash 4.7 9.3 ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 275 2350 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t pgmpart32k program partition for eeprom execution time ? 32 kb flexnvm 70 ms table continues on the next page... memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. 28 freescale semiconductor, inc. table 18. flash command timing specifications (continued) symbol description min. typ. max. unit notes t setramff t setram8k t setram32k set flexram function execution time: ? control code 0xff ? 8 kb eeprom backup ? 32 kb eeprom backup 50 0.3 0.7 0.5 1.0 s ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 s 3 t eewr8b8k t eewr8b16k t eewr8b32k byte-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 340 385 475 1700 1800 2000 s s s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 s t eewr16b8k t eewr16b16k t eewr16b32k word-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 340 385 475 1700 1800 2000 s s s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 s t eewr32b8k t eewr32b16k t eewr32b32k longword-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 545 630 810 1950 2050 2250 s s s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash (ftfl) current and power specfications table 19. flash (ftfl) current and power specfications symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 29 6.4.1.4 reliability specifications table 20. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years 2 t nvmretp1k data retention after up to 1 k cycles 10 100 years 2 t nvmretp100 data retention after up to 100 cycles 15 100 years 2 n nvmcycp cycling endurance 10 k 35 k cycles 3 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years 2 t nvmretd1k data retention after up to 1 k cycles 10 100 years 2 t nvmretd100 data retention after up to 100 cycles 15 100 years 2 n nvmcycd cycling endurance 10 k 35 k cycles 3 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years 2 t nvmretee10 data retention up to 10% of write endurance 10 100 years 2 t nvmretee1 data retention up to 1% of write endurance 15 100 years 2 n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree8k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 4096 ? eeprom backup to flexram ratio = 8192 35 k 315 k 1.27 m 10 m 20 m 175 k 1.6 m 6.4 m 50 m 100 m writes writes writes writes writes 4 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. 2. data retention is based on t javg = 55c (temperature profile over the lifetime of the application). 3. cycling endurance represents number of program/erase cycles at -40c t j 125c. 4. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. 30 freescale semiconductor, inc. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfl to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_flexram = write_efficiency n eeprom C 2 eeesize eeesize nvmcycd where ? writes_flexram minimum number of writes to each flexram location ? eeprom allocated flexnvm based on depart; entered with program partition command ? eeesize allocated flexram based on depart; entered with program partition command ? write_efficiency ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd data flash cycling endurance memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 31 figure 5. eeprom backup writes to flexram 6.4.2 ezport switching specifications all timing is shown with respect to a maximum pin load of 50 pf and input signal transitions of 3 ns. table 21. ezport switching specifications num description min. max. unit operating voltage 2.7 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 15 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 0.0 ns ep5 ezp_d input valid to ezp_ck high (setup) 15 ns table continues on the next page... memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. 32 freescale semiconductor, inc. table 21. ezport switching specifications (continued) num description min. max. unit ep6 ezp_ck high to ezp_d input invalid (hold) 0.0 ns ep7 ezp_ck low to ezp_q output valid (setup) 25 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0.0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 6. ezport timing diagram 6.4.3 mini-flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the mini-flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 22. flexbus switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation 25 mhz fb1 clock period 40 ns table continues on the next page... memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 33 table 22. flexbus switching specifications (continued) num description min. max. unit notes fb2 address, data, and control output valid 20 ns 1 fb3 address, data, and control output hold 1 ns 1 fb4 data and fb_ta input setup 20 ns 2 fb5 data and fb_ta input hold 10 ns 2 1. specification is valid for all fb_ad[31:0], fb_cs n , fb_oe, fb_r/ w, and fb_ts. 2. specification is valid for all fb_ad[31:0]. note the following diagrams refer to signal names that may not be included on your particular device. ignore these extraneous signals. also, ignore the aa=0 portions of the diagrams because this setting is not supported in the mini-flexbus. memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. 34 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb5 fb4 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 7. mini-flexbus read timing diagram memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 35 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 8. mini-flexbus write timing diagram 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. memories and memory interfaces MCF51QU128 data sheet, rev. 4, 01/2012. 36 freescale semiconductor, inc. analog 6.6.1 adc electrical specifications all adc channels meet the 12-bit single-ended accuracy specifications. 6.6.1.1 12-bit adc operating conditions table 23. 12-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd - v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss - v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl reference voltage low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capacitance ? 8/10/12 bit modes 4 5 pf r adin input resistance 2 5 k r as analog source resistance 12 bit modes f adck < 4mhz 5 k 3 f adck adc conversion clock frequency 12 bit modes 1.0 18.0 mhz 4 c rate adc conversion rate 12 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 analog source resistance. the r as / c as time constant should be kept to <1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit should be set and the adlpc bit should be clear. 6.6 analog MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 37 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 9. adc input impedance equivalency diagram 6.6.1.2 12-bit adc electrical characteristics table 24. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12 bit modes ? <12 bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12 bit modes ? <12 bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12 bit modes ? <12 bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 table continues on the next page... analog MCF51QU128 data sheet, rev. 4, 01/2012. 38 freescale semiconductor, inc. table 24. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e fs full-scale error ? 12 bit modes ? <12 bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error ? 12 bit modes 0.5 lsb 4 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope C40c to 105c 1.715 mv/c v temp25 temp sensor voltage 25c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock <16mhz, max hardware averaging (avge = %1, avgs = %11) 6.6.2 cmp and 6-bit dac electrical specifications table 25. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv table continues on the next page... analog MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 39 table 25. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 analog MCF51QU128 data sheet, rev. 4, 01/2012. 40 freescale semiconductor, inc. 0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 10. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) analog MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 41 0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 11. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 26. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature ?40 105 c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac 6.6.3 12-bit dac electrical characteristics MCF51QU128 data sheet, rev. 4, 01/2012. 42 freescale semiconductor, inc. 6.6.3.2 12-bit dac operating behaviors table 27. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 450 a i dda_dac hp supply current high-speed mode 1000 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0+100mv to v dacr ?100 mv 3. the dnl is measured for 0+100 mv to v dacr ?100 mv 4. the dnl is measured for 0+100mv to v dacr ?100 mv with v dda > 2.4v 12-bit dac electrical characteristics MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 43 5. calculated by a best fit curve from v ss +100 mv to v dacr ?100 mv 6. vdda = 3.0v, reference select set for vdda (dacx_co:dacrfs = 1), high power mode(dacx_c0:lpen = 0), dac set to 0x800, temp range from -40c to 105c figure 12. typical inl error vs. digital code 12-bit dac electrical characteristics MCF51QU128 data sheet, rev. 4, 01/2012. 44 freescale semiconductor, inc. figure 13. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 28. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature ?40 105 c c l output load capacitance 100 nf 1 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 12-bit dac electrical characteristics MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 45 table 29. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1965 1.2 1.2027 v v out voltage reference output with factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.198 1.202 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only (mode_lv = 00) current 80 a i tr tight-regulation buffer (mode_lv =10) current 1.1 ma v load load regulation (mode_lv = 10) ? current = + 1.0 ma ? current = - 1.0 ma 2 5 mv 1 t stup buffer startup time 100 s v vdrift voltage drift (vmax -vmin across the full voltage range) (mode_lv = 10, regen = 1) 2 mv 1. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 30. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 31. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 6.7 timers see general switching specifications . 12-bit dac electrical characteristics MCF51QU128 data sheet, rev. 4, 01/2012. 46 freescale semiconductor, inc. communication interfaces 6.8.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 70% v dd , unless noted, as well as input signal transitions of 3 ns and a 50 pf maximum load on all spi pins. all timing assumes slew rate control is disabled and high drive strength is enabled for spi output pins. table 32. spi master mode timing num. symbol description min. max. unit comment 1 f op frequency of operation f bus /2048 f bus /2 hz f bus is the bus clock as defined in table 8 . 2 t spsck spsck period 2 x t bus 2048 x t bus ns t bus = 1/ f bus 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t bus - 30 1024 x t bus ns 6 t su data setup time (inputs) 21 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 25 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t bus - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 6.8 communication interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 47 (output) (output) miso (input) mosi (output) ss 1 (output) 2 8 6 7 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 9 5 5 3 (cpol 0) (cpol 1) 4 11 11 10 10 spsck spsck = = 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. figure 14. spi master mode timing (cpha=0) < table 33. spi slave mode timing (continued) num. symbol description min. max. unit comment 2 t spsck spsck period 4 x t bus ns t bus = 1/ f bus 3 t lead enable lead time 1 t bus 4 t lag enable lag time 1 t bus 5 t wspsck clock (spsck) high or low time t bus - 30 ns 6 t su data setup time (inputs) 19.5 ns 7 t hi data hold time (inputs) 0 ns 8 t a slave access time t bus ns time to data active from high- impedanc e state 9 t dis slave miso disable time t bus ns hold time to high- impedanc e state 10 t v data valid (after spsck edge) 27 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t bus - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output (input) (input) mosi (input) miso (output) ss (input) 2 10 6 7 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 5 5 3 8 (cpol 0) (cpol 1) 4 13 note: not defined! 12 12 11 see 13 note 9 see note spsck spsck = = figure 16. spi slave mode timing (cpha=0) communication interfaces MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 49 (input) (input) mosi (input) miso (output) 2 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 5 5 10 12 13 11 (cpol 0) (cpol 1) ss (input) 3 12 13 4 note: not defined! slave 8 9 see note spsck spsck = = figure 17. spi slave mode timing (cpha=1) human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 34. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 5.5 14 mhz 2 f elemax electrode oscillator frequency 0.5 4.0 mhz 3 c ref internal reference capacitor 0.5 1 1.2 pf v delta oscillator delta voltage 100 600 760 mv 4 i ref reference oscillator current source base current ? 1ua setting (refchrg=0) ? 32ua setting (refchrg=31) 1.133 36 1.5 50 a 3 , 5 i ele electrode oscillator current source base current ? 1ua setting (extchrg=0) ? 32ua setting (extchrg=31) 1.133 36 1.5 50 a 3 , 6 pres5 electrode capacitance measurement precision 8.3333 38400 % 7 pres20 electrode capacitance measurement precision 8.3333 38400 % 8 pres100 electrode capacitance measurement precision 8.3333 38400 % 9 maxsens maximum sensitivity 0.003 12.5 ff/count 10 table continues on the next page... 6.9 human-machine interfaces (hmi) MCF51QU128 data sheet, rev. 4, 01/2012. 50 freescale semiconductor, inc. table 34. tsi electrical specifications (continued) symbol description min. typ. max. unit notes res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 11 i tsi_run current added in run mode 55 a i tsi_lp low power mode current adder 1.3 2.5 a 12 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. captrm=7, delvol=7, and fixed external capacitance of 20 pf. 3. captrm=0, delvol=2, and fixed external capacitance of 20 pf. 4. captrm=0, extchrg=9, and fixed external capacitance of 20 pf. 5. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 6. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 7. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 8. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 10. sensitivity defines the minimum capacitance change when a single count from the tsi module changes, it is equal to (c ref * i ext )/( i ref * ps * nscn). sensitivity depends on the configuration used. the typical value listed is based on the following configuration: iext = 5 a, extchrg = 4, ps = 128, nscn = 2, i ref = 16 a, refchrg = 15, c ref = 1.0 pf. the minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because its the smallest number). the minimum sensitivity parameter is based on the following configuration: i ext = 1 a, extchrg = 0, ps = 128, nscn = 32, i ref = 32 a, refchrg = 31, c ref = 0.5 pf 11. time to do one complete measurement of the electrode. sensitivity resolution of 0.0133 pf, ps = 0, nscn = 0, 1 electrode, delvol = 2, extchrg = 15. 12. captrm=7, delvol=2, refchrg=0, extchrg=4, ps=7, nscn=0f, lpscnitv=f, lpo is selected (1 khz), and fixed external capacitance of 20 pf. data is captured with an average of 7 periods window. dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 32-pin qfn 98are10566d 44-pin laminate qfn 98asa00239d 48-pin lqfp 98ash00962a 64-pin lqfp 98ass23234w 7 dimensions MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 51 pinout 8.1 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port mux control module is responsible for selecting which alt functionality is available on each pin. note ? on ptb0, ezp_ms_b is active only during reset. refer to the detailed boot description. ? ptc1 is open drain. 64- pin 48- pin 44- pin 32- pin default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 vdd vdd 2 vss vss 3 disabled disabled ptc6 uart0_tx i2c0_scl rgpio6 spi1_mosi fba_ad11 4 disabled disabled ptc7 uart0_rx i2c0_sda rgpio7 spi1_miso fba_ad12 5 1 disabled disabled ptd0 uart0_ct s_b i2c1_sda rgpio8 spi1_sclk fba_ad13 6 2 disabled disabled ptd1 uart0_rt s_b i2c1_scl rgpio9 spi1_ss fba_ad14 7 3 1 1 disabled disabled pta0 i2c2_scl ftm1_ch0 spi0_ss fba_ad15 8 4 2 2 disabled disabled pta1 i2c2_sda ftm1_ch1 fba_ad16 9 5 3 3 disabled disabled pta2 uart1_tx ftm1_ch2 spi1_ss 10 6 4 4 disabled disabled pta3 uart1_rx ftm1_ch3 spi1_sclk ezp_clk 11 7 5 5 adc0_se2 adc0_se2 pta4 uart1_ct s_b i2c2_scl ftm1_ch4 spi1_miso ezp_di 12 8 6 6 adc0_se3 adc0_se3 pta5 uart1_rt s_b i2c2_sda ftm1_ch5 spi1_mosi clkout ezp_do 13 9 7 7 vdda vdda 14 10 8 vrefh vrefh 15 11 9 vref_out vref_out 16 12 10 vrefl vrefl 17 13 11 8 vssa vssa 18 14 12 9 dac0_out dac0_out 19 15 13 10 adc0_se0 adc0_se0 20 16 14 11 adc0_se1 adc0_se1 21 17 15 12 vregin vregin 22 18 16 13 vout33 vout33 23 19 17 14 vss vss 8 pinout MCF51QU128 data sheet, rev. 4, 01/2012. 52 freescale semiconductor, inc. 64- pin 48- pin 44- pin 32- pin default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 24 20 18 vdd vdd 25 21 19 15 adc0_se8/ tsi0_ch0 adc0_se8/ tsi0_ch0 pta6 lptmr_al t1 ftm_flt1 fba_d7 fba_ad17 26 adc0_se9/ tsi0_ch1 adc0_se9/ tsi0_ch1 ptd2 ftm0_qd_ pha rgpio10 ftm0_ch0 27 22 20 adc0_se1 0/tsi0_ch2 adc0_se1 0/tsi0_ch2 ptd3 ftm0_qd_ phb rgpio11 ftm0_ch1 fba_d6 fba_ad0 28 adc0_se1 1/tsi0_ch3 adc0_se1 1/tsi0_ch3 ptd4 rgpio12 fba_d7 29 adc0_se1 2/tsi0_ch4 adc0_se1 2/tsi0_ch4 ptd5 rgpio13 fba_d6 30 23 21 16 adc0_se1 3/tsi0_ch5 adc0_se1 3/tsi0_ch5 pta7 uart0_tx ftm0_qd_ pha fba_d5 31 24 22 adc0_se1 4/tsi0_ch6 adc0_se1 4/tsi0_ch6 ptd6 uart0_rx rgpio14 fba_d4 32 adc0_se1 5/tsi0_ch7 adc0_se1 5/tsi0_ch7 ptd7 uart0_ct s_b i2c3_scl rgpio15 fba_d3 33 tsi0_ch8 tsi0_ch8 pte0 uart0_rt s_b i2c3_sda fba_d2 34 tsi0_ch9 tsi0_ch9 pte1 spi0_ss ftm_flt0 fba_d1 35 25 23 17 irq/ ezp_ms_b disabled ptb0 i2c0_scl irq/ ezp_ms_b ezp_cs_b 36 26 24 18 tsi0_ch10 tsi0_ch10 ptb1 spi0_sclk i2c0_sda ftm_flt2 lptmr_al t2 ftm0_qd_ phb fb_clkou t 37 tsi0_ch11 tsi0_ch11 pte2 i2c3_scl fba_d0 38 adc0_se1 6/ tsi0_ch12 adc0_se1 6/ tsi0_ch12 pte3 spi0_mosi i2c3_sda fba_oe_b 39 27 25 19 adc0_se1 7/ tsi0_ch13 adc0_se1 7/ tsi0_ch13 ptb2 spi0_miso fba_cs0_b 40 28 26 20 adc0_se1 8/ tsi0_ch14 adc0_se1 8/ tsi0_ch14 ptb3 spi0_mosi fba_cs1_b fba_ale 41 29 adc0_se1 9/ tsi0_ch15 adc0_se1 9/ tsi0_ch15 pte4 uart0_rt s_b lptmr_al t3 spi1_ss fba_ad1 42 30 adc0_se2 0 adc0_se2 0 pte5 uart0_ct s_b i2c1_scl spi1_sclk fba_ad2 43 adc0_se2 1 adc0_se2 1 pte6 uart0_rx i2c1_sda spi1_miso fba_ad3 44 31 27 adc0_se2 2 adc0_se2 2 pte7 uart0_tx pdb0_ext rg spi1_mosi fba_rw_b fba_ad4 45 32 28 21 bkgd/ms disabled ptb4 bkgd/ms 46 33 29 22 xtal2 xtal2 ptb5 47 34 30 23 extal2 extal2 ptb6 48 35 31 24 vdd vdd pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 53 64- pin 48- pin 44- pin 32- pin default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 49 36 32 25 vss vss 50 37 33 26 extal1 extal1 ptb7 i2c1_sda tmr_clki n1 51 38 34 27 xtal1 xtal1 ptc0 i2c1_scl tmr_clki n0 rgpio0 52 39 35 28 reset_b disabled ptc1 reset_b 53 cmp0_in0 cmp0_in0 ptf0 spi0_ss fba_ad5 54 disabled disabled ptf1 spi0_sclk cmp0_out fba_ad6 55 cmp0_in1 cmp0_in1 ptf2 spi0_miso fba_ad7 56 40 36 cmp0_in2 cmp0_in2 ptf3 spi0_mosi rgpio1 fba_ad8 57 41 37 29 cmp0_in3 cmp0_in3 ptc2 uart1_rt s_b spi1_ss rgpio2 fba_ad18 58 42 38 disabled disabled ptf4 uart1_ct s_b spi1_sclk fba_d3 fba_ad19 59 43 39 disabled disabled ptf5 uart1_rx spi1_miso fba_d2 fba_rw_b 60 44 40 disabled disabled ptf6 uart1_tx spi1_mosi fba_d1 fba_ad9 61 45 41 disabled disabled ptf7 uart0_rt s_b spi0_ss fba_d0 fba_ad10 62 46 42 30 disabled disabled ptc3 uart0_ct s_b rgpio3 spi0_sclk clkout 63 47 43 31 disabled disabled ptc4 uart0_rx rgpio4 spi0_miso pdb0_ext rg 64 48 44 32 disabled disabled ptc5 uart0_tx rgpio5 spi0_mosi cmt_iro 8.2 pinout diagrams the following diagrams show pinouts for the 64-pin, 48-pin, 44-pin, and 32-pin packages. these diagrams are representations for ease of reference. see the package drawings for mechanical details. for each pin, the diagrams show the default function or (when disabled is the default) the alt1 signal for a gpio function. however, many signals may be multiplexed onto a single pin. pinout MCF51QU128 data sheet, rev. 4, 01/2012. 54 freescale semiconductor, inc. adc0_se1 adc0_se0 dac0_out vssa vrefl vref_out vrefh vdda adc0_se3 adc0_se2 pta3 pta2 pta1 pta0 ptd1 ptd0 ptc7 ptc6 vss vdd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptc5 ptc4 ptc3 ptf7 ptf6 ptf5 ptf4 cmp0_in3 cmp0_in2 cmp0_in1 ptf1 cmp0_in0 reset_b xtal1 extal1 vss vdd extal2 xtal2 bkgd/ms adc0_se22 adc0_se21 adc0_se20 adc0_se19/tsi0_ch15 adc0_se18/tsi0_ch14 adc0_se17/tsi0_ch13 adc0_se16/tsi0_ch12 tsi0_ch11 tsi0_ch10 irq/ezp_ms_b tsi0_ch9 tsi0_ch8 adc0_se15/tsi0_ch7 adc0_se14/tsi0_ch6 adc0_se13/tsi0_ch5 adc0_se12/tsi0_ch4 adc0_se11/tsi0_ch3 adc0_se10/tsi0_ch2 adc0_se9/tsi0_ch1 adc0_se8/tsi0_ch0 vdd vss vout33 vregin figure 18. 64-pin lqfp pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 55 vrefl vref_out vrefh vdda adc0_se3 adc0_se2 pta3 pta2 pta1 pta0 ptd1 ptd0 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 ptc5 ptc4 ptc3 ptf7 ptf6 ptf5 ptf4 cmp0_in3 cmp0_in2 reset_b xtal1 extal1 36 35 34 33 vss vdd extal2 xtal2 32 31 30 29 28 27 26 25 bkgd/ms adc0_se22 adc0_se20 adc0_se19/tsi0_ch15 adc0_se18/tsi0_ch14 adc0_se17/tsi0_ch13 tsi0_ch10 irq/ezp_ms_b vdd vss vout33 vregin 24 23 22 21 20 19 18 17 adc0_se1 adc0_se0 dac0_out vssa 16 15 14 13 adc0_se14/tsi0_ch6 adc0_se13/tsi0_ch5 adc0_se10/tsi0_ch2 adc0_se8/tsi0_ch0 figure 19. 48-pin lqfp pinout MCF51QU128 data sheet, rev. 4, 01/2012. 56 freescale semiconductor, inc. 1 pta0 2 pta1 3 pta2 4 pta3 5 adc0_se2 6 adc0_se3 7 vdda 8 vrefh 9 vref_out 10 vrefl 11 vssa 23 irq/ezp_ms_b tsi0_ch10 25 adc0_se17/tsi0_ch13 adc0_se18/tsi0_ch14 27 adc0_se22 bkgd/ms 29 xtal2 extal2 31 vdd 24 26 28 30 32 vss 33 extal1 34 xtal1 reset_b 36 cmp0_in2 cmp0_in3 38 ptf4 ptf5 40 ptf6 ptf7 42 ptc3 ptc4 44 ptc5 35 37 39 41 43 12 dac0_out 13 adc0_se0 14 adc0_se1 15 vregin 16 vout33 17 vss 18 vdd 19 adc0_se8/tsi0_ch0 20 adc0_se10/tsi0_ch2 21 adc0_se13/tsi0_ch5 22 adc0_se14/tsi0_ch6 figure 20. 44-pin laminate qfn pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 57 32 31 30 29 28 27 26 25 ptc5 ptc4 ptc3 cmp0_in3 reset_b xtal1 extal1 vss vregin adc0_se1 adc0_se0 dac0_out 12 11 10 9 adc0_se13/tsi0_ch5 adc0_se8/tsi0_ch0 vss vout33 16 15 14 13 adc0_se18/tsi0_ch14 adc0_se17/tsi0_ch13 tsi0_ch10 irq/ezp_ms_b 24 23 22 21 20 19 18 17 vdd extal2 xtal2 bkgd/ms vssa vdda adc0_se3 adc0_se2 pta3 pta2 pta1 pta0 8 7 6 5 4 3 2 1 figure 21. 32-pin qfn 8.3 module-by-module signals note ? on ptb0, ezp_ms_b is active only during reset. refer to the detailed boot description. ? ptc1 is open drain. table 35. module signals by gpio port and pin 64-pin 48-pin 44-pin 32-pin port module signal(s) power and ground 1 vdd 24 20 18 vdd table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. 58 freescale semiconductor, inc. table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 48 35 31 24 vdd 2 vss 23 19 17 14 vss 49 36 32 25 vss system 45 32 28 21 ptb4 bkgd/ms 12 8 6 6 pta5 clkout 62 46 42 30 ptc3 clkout 10 6 4 4 pta3 ezp_clk 11 7 5 5 pta4 ezp_di 12 8 6 6 pta5 ezp_do 35 25 23 17 ptb0 irq/ezp_ms_b, ezp_cs_b 52 39 35 28 ptc1 reset_b osc 50 37 33 26 ptb7 extal1 47 34 30 23 ptb6 extal2 51 38 34 27 ptc0 xtal1 46 33 29 22 ptb5 xtal2 llwu 4 ptc7 llwu_p0 6 2 ptd1 llwu_p1 12 8 6 6 pta5 llwu_p2 30 23 21 16 pta7 llwu_p3 32 ptd7 llwu_p4 35 25 23 17 ptb0 llwu_p5 36 26 24 18 ptb1 llwu_p6 39 27 25 19 ptb2 llwu_p7 44 31 27 pte7 llwu_p8 45 32 28 21 ptb4 llwu_p9 55 ptf2 llwu_p10 56 40 36 ptf3 llwu_p11 57 41 37 29 ptc2 llwu_p12 59 43 39 ptf5 llwu_p13 62 46 42 30 ptc3 llwu_p14 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 59 table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 63 47 43 31 ptc4 llwu_p15 rgpio 51 38 34 27 ptc0 rgpio0 56 40 36 ptf3 rgpio1 57 41 37 29 ptc2 rgpio2 62 46 42 30 ptc3 rgpio3 63 47 43 31 ptc4 rgpio4 64 48 44 32 ptc5 rgpio5 3 ptc6 rgpio6 4 ptc7 rgpio7 5 1 ptd0 rgpio8 6 2 ptd1 rgpio9 26 ptd2 rgpio10 27 22 20 ptd3 rgpio11 28 ptd4 rgpio12 29 ptd5 rgpio13 31 24 22 ptd6 rgpio14 32 ptd7 rgpio15 lptmr 25 21 19 15 pta6 lptmr_alt1 36 26 24 18 ptb1 lptmr_alt2 41 29 pte4 lptmr_alt3 lptmr-tod 50 37 33 26 ptb7 extal1 47 34 30 23 ptb6 extal2 25 21 19 15 pta6 lptmr_alt1 36 26 24 18 ptb1 lptmr_alt2 41 29 pte4 lptmr_alt3 51 38 34 27 ptc0 xtal1 46 33 29 22 ptb5 xtal2 pta 7 3 1 1 pta0 pta0 8 4 2 2 pta1 pta1 9 5 3 3 pta2 pta2 10 6 4 4 pta3 pta3 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. 60 freescale semiconductor, inc. table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 11 7 5 5 pta4 pta4 12 8 6 6 pta5 pta5 25 21 19 15 pta6 pta6 30 23 21 16 pta7 pta7 ptb 35 25 23 17 ptb0 ptb0 36 26 24 18 ptb1 ptb1 39 27 25 19 ptb2 ptb2 40 28 26 20 ptb3 ptb3 45 32 28 21 ptb4 ptb4 46 33 29 22 ptb5 ptb5 47 34 30 23 ptb6 ptb6 50 37 33 26 ptb7 ptb7 ptc 51 38 34 27 ptc0 ptc0 52 39 35 28 ptc1 ptc1 57 41 37 29 ptc2 ptc2 62 46 42 30 ptc3 ptc3 63 47 43 31 ptc4 ptc4 64 48 44 32 ptc5 ptc5 3 ptc6 ptc6 4 ptc7 ptc7 ptd 5 1 ptd0 ptd0 6 2 ptd1 ptd1 26 ptd2 ptd2 27 22 20 ptd3 ptd3 28 ptd4 ptd4 29 ptd5 ptd5 31 24 22 ptd6 ptd6 32 ptd7 ptd7 pte 33 pte0 pte0 34 pte1 pte1 38 pte3 pte2 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 61 table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 39 27 25 19 ptb2 pte3 41 29 pte4 pte4 42 30 pte5 pte5 43 pte6 pte6 44 31 27 pte7 pte7 ptf 53 ptf0 ptf0 54 ptf1 ptf1 55 ptf2 ptf2 56 40 36 ptf3 ptf3 58 42 38 ptf4 ptf4 59 43 39 ptf5 ptf5 60 44 40 ptf6 ptf6 61 45 41 ptf7 ptf7 5 v vreg 22 18 16 13 vout33 21 17 15 12 vregin adc0 11 7 5 5 pta4 adc0_se2 12 8 6 6 pta5 adc0_se3 25 21 19 15 pta6 adc0_se8 26 ptd2 adc0_se9 27 22 20 ptd3 adc0_se10 28 ptd4 adc0_se11 29 ptd5 adc0_se12 30 23 21 16 pta7 adc0_se13 31 24 22 ptd6 adc0_se14 32 ptd7 adc0_se15 38 pte3 adc0_se16 39 27 25 19 ptb2 adc0_se17 40 28 26 20 ptb3 adc0_se18 41 29 pte4 adc0_se19 42 30 pte5 adc0_se20 43 pte6 adc0_se21 44 31 27 pte7 adc0_se22 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. 62 freescale semiconductor, inc. table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 13 9 7 7 vdda 14 10 8 vrefh 16 12 10 vrefl 17 13 11 8 vssa dac0 18 14 12 9 dac0_out vref 15 11 9 vref_out cmp0 53 ptf0 cmp0_in0 55 ptf2 cmp0_in1 56 40 36 ptf3 cmp0_in2 57 41 37 29 ptc2 cmp0_in3 54 ptf1 cmp0_out cmt 64 48 44 32 ptc5 cmt_iro tsi0 25 21 19 15 pta6 tsi0_ch0 26 ptd2 tsi0_ch1 27 22 20 ptd3 tsi0_ch2 28 ptd4 tsi0_ch3 29 ptd5 tsi0_ch4 30 23 21 16 pta7 tsi0_ch5 31 24 22 ptd6 tsi0_ch6 32 ptd7 tsi0_ch7 33 pte0 tsi0_ch8 34 pte1 tsi0_ch9 36 26 24 18 ptb1 tsi0_ch10 37 pte2 tsi0_ch11 38 pte3 tsi0_ch12 39 27 25 19 ptb2 tsi0_ch13 40 28 26 20 ptb3 tsi0_ch14 41 29 pte4 tsi0_ch15 pdb0 44 31 27 pte7 pdb0_extrg table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 63 table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 63 47 43 31 ptc4 pdb0_extrg ftm0 34 pte1 ftm_flt0 25 21 19 15 pta6 ftm_flt1 36 26 24 18 ptb1 ftm_flt2 / ftm0_qd_phb 26 ptd2 ftm0_ch0/ ftm0_qd_pha 27 22 20 ptd3 ftm0_ch1 / ftm0_qd_phb 30 23 21 16 pta7 ftm0_qd_pha 51 38 34 27 ptc0 tmr_clkin0 50 37 33 26 ptb7 tmr_clkin1 ftm1 34 pte1 ftm_flt0 25 21 19 15 pta6 ftm_flt1 36 26 24 18 ptb1 ftm_flt2 7 3 1 1 pta0 ftm1_ch0 8 4 2 2 pta1 ftm1_ch1 9 5 3 3 pta2 ftm1_ch2 10 6 4 4 pta3 ftm1_ch3 11 7 5 5 pta4 ftm1_ch4 12 8 6 6 pta5 ftm1_ch5 51 38 34 27 ptc0 tmr_clkin0 50 37 33 26 ptb7 tmr_clkin1 mtim 51 38 34 27 ptc0 tmr_clkin0 50 37 33 26 ptb7 tmr_clkin1 mini-flexbus 36 26 24 18 ptb1 fb_clkout 27 22 20 ptd3 fba_ad0 41 29 pte4 fba_ad1 42 30 pte5 fba_ad2 43 pte6 fba_ad3 44 31 27 pte7 fba_ad4 53 ptf0 fba_ad5 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. 64 freescale semiconductor, inc. table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 54 ptf1 fba_ad6 55 ptf2 fba_ad7 56 40 36 ptf3 fba_ad8 60 44 40 ptf6 fba_ad9 61 45 41 ptf7 fba_ad10 3 ptc6 fba_ad11 4 ptc7 fba_ad12 5 1 ptd0 fba_ad13 6 2 ptd1 fba_ad14 7 3 1 1 pta0 fba_ad15 8 4 2 2 pta1 fba_ad16 25 21 19 15 pta6 fba_ad17 57 41 37 29 ptc2 fba_ad18 58 42 38 ptf4 fba_ad19 40 28 26 20 ptb3 fba_ale 39 27 25 19 ptb2 fba_cs0_b 37 pte2 fba_d0 34 pte1 fba_d1 33 pte0 fba_d2 32 ptd7 fba_d3 31 24 22 ptd6 fba_d4 30 23 21 16 pta7 fba_d5 29 ptd5 fba_d6 28 ptd4 fba_d7 38 pte3 fba_oe_b 59 43 39 ptf5 fba_rw_b data_bus 8 4 2 2 pta1 fba_ad16 39 27 25 19 ptb2 fba_cs0_b 61 45 41 ptf7 fba_d0 60 44 40 ptf6 fba_d1 59 43 39 ptf5 fba_d2 58 42 38 ptf4 fba_d3 31 24 22 ptd6 fba_d4 30 23 21 16 pta7 fba_d5 table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 65 table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 27 22 20 ptd3 fba_d6 25 21 19 15 pta6 fba_d7 44 31 27 pte7 fba_rw_b i2c0 and i2c1 3 ptc6 i2c0_scl 35 25 23 17 ptb0 i2c0_scl 4 ptc7 i2c0_sda 36 26 24 18 ptb1 i2c0_sda 6 2 ptd1 i2c1_scl 42 30 pte5 i2c1_scl 51 38 34 27 ptc0 i2c1_scl 5 1 ptd0 i2c1_sda 43 pte6 i2c1_sda 50 37 33 26 ptb7 i2c1_sda i2c2 and i2c3 7 3 1 1 pta0 i2c2_scl 11 7 5 5 pta4 i2c2_scl 8 4 2 2 pta1 i2c2_sda 12 8 6 6 pta5 i2c2_sda 32 ptd7 i2c3_scl 37 pte2 i2c3_scl 33 pte0 i2c3_sda 38 pte3 i2c3_sda spi0 39 27 25 19 ptb2 spi0_miso 55 ptf2 spi0_miso 63 47 43 31 ptc4 spi0_miso 38 pte3 spi0_mosi 40 28 26 20 ptb3 spi0_mosi 56 40 36 ptf3 spi0_mosi 64 48 44 32 ptc5 spi0_mosi 36 26 24 18 ptb1 spi0_sclk 54 ptf1 spi0_sclk 62 46 42 30 ptc3 spi0_sclk 7 3 1 1 pta0 spi0_ss table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. 66 freescale semiconductor, inc. table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 34 pte1 spi0_ss 53 ptf0 spi0_ss 61 45 41 ptf7 spi0_ss spi1 4 ptc7 spi1_miso 11 7 5 5 pta4 spi1_miso 43 pte6 spi1_miso 59 43 39 ptf5 spi1_miso 3 ptc6 spi1_mosi 12 8 6 6 pta5 spi1_mosi 44 31 27 pte7 spi1_mosi 60 44 40 ptf6 spi1_mosi 5 1 ptd0 spi1_sclk 10 6 4 4 pta3 spi1_sclk 42 30 pte5 spi1_sclk 58 42 38 ptf4 spi1_sclk 6 2 ptd1 spi1_ss 9 5 3 3 pta2 spi1_ss 41 29 pte4 spi1_ss 57 41 37 29 ptc2 spi1_ss uart0 5 1 ptd0 uart0_cts_b 32 ptd7 uart0_cts_b 42 30 pte5 uart0_cts_b 62 46 42 30 ptc3 uart0_cts_b 6 2 ptd1 uart0_rts_b 33 pte0 uart0_rts_b 41 29 pte4 uart0_rts_b 61 45 41 ptf7 uart0_rts_b 4 ptc7 uart0_rx 31 24 22 ptd6 uart0_rx 43 pte6 uart0_rx 63 47 43 31 ptc4 uart0_rx 3 ptc6 uart0_tx 30 23 21 16 pta7 uart0_tx table continues on the next page... pinout MCF51QU128 data sheet, rev. 4, 01/2012. freescale semiconductor, inc. 67 table 35. module signals by gpio port and pin (continued) 64-pin 48-pin 44-pin 32-pin port module signal(s) 44 31 27 pte7 uart0_tx 64 48 44 32 ptc5 uart0_tx uart1 11 7 5 5 pta4 uart1_cts_b 58 42 38 ptf4 uart1_cts_b 12 8 6 6 pta5 uart1_rts_b 57 41 37 29 ptc2 uart1_rts_b 10 6 4 4 pta3 uart1_rx 59 43 39 ptf5 uart1_rx 9 5 3 3 pta2 uart1_tx 60 44 40 ptf6 uart1_tx 9 revision history the following table summarizes content changes since the previous release of this document. table 36. revision history rev. no. date substantial changes 4 01/2012 thermal operating requirements: changed maximum t j value from 125c to 115c revision history MCF51QU128 data sheet, rev. 4, 01/2012. 68 freescale semiconductor, inc. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com document number: MCF51QU128 rev. 4, 01/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor 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"typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2010C2012 freescale semiconductor, inc. |
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