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AK8181F draft - e - 02 dec - 2012 - 1 - features four differential 3.3v lv ds outputs selectable differential pclk0p/n or lvpecl clock in puts pclk0p/n pair can accept the following differential input levels; lvds, lvpecl, lvhstl, sstl, hcsl pclk1p/n supports the following input types; lvpecl, cml, sstl clock output frequency up to 650 mhz translates any single - ended input signal to 3.3v lv ds levels with resistor bias on pclk 0 n input o utput skew : 3 0 ps ( max imum ) part - to - part sk ew : 60 0 ps ( maximum ) propagation delay : 2 .5 ns ( maximum ) operating temperature range: - 4 0 to +85 package: 20 - pin tssop (pb free) pin compatible with ics85 4 3i description the ak 8181 f is a member of akm s lv ds clock fanout buffer family designed for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the ak 8181f distributes 4 buffered clocks . ak 8181 f are derived f r o m akm s long - term - experienced clock devic e technology , and enable clock output to perform low skew . the ak 8181 f is ava ilable in a 20 - pin tssop pa ckage. block diagra m 3.3v lv ds 1: 4 preliminary clock fanout buffer ak 8181 f
AK8181F dec - 2012 draft - e - 02 - 2 - pin d escription s package: 2 0 - pin tssop (top view) pin no. pin name pin type pullup down description 1 vss pwr --- negative power supply 2 clk_en in pull up synchronizing clock output enable (lvcmos/lvttl) pin is connected to vdd by internal re sistor. (typ. 51k ? ? high (open): clock outputs follow clock input. low: q outputs are forced low, qn outputs are forced high. 3 clk_sel in pull down clk select input (lvcmos/lvttl) pin is connected to vss by internal resistor. (typ. 51k ? ? high: selects pc lk1p/n inputs low (open): selects pclk0p/n inputs 4 pclk0p in pull down non - inverting differential clock input pin is connected to vss by internal resistor. (typ. 51k ? ? ? *when using pclk1 input (clk_sel=high), it should be connected to vss or opened. 5 pc lk0n in pull up inverting differential clock input pin is connected to vdd by internal resistor. (typ. 51k ? ? ? *when using pclk1 input (clk_sel=high), it should be connected to vdd or opened. 6 pclk1p in pull down non - inverting differential lvpecl clock inp ut pin is connected to vss by internal resistor. (typ. 51k ? ? ? *when using pclk0 input (clk_sel=low), it should be connected to vss or opened. 7 pclk1n in pull up inverting differential lvpecl clock input pin is connected to vdd by internal resistor. (typ. 51k ? ? ? *when using pclk0 input (clk_sel=low), it should be connected to vdd or opened. 8 oe in pull up output enable. controls enabling and disabling of outputs q0, q0n through q3, q3n pin is connected to vdd by internal resistor. (typ. 51k ? ) 9 vss pwr -- - negative power supply 10 vdd pwr --- positive power supply
AK8181F draft - e - 02 dec - 2012 - 3 - pin no. pin name pin type pullup down description 11, 12 q3n, q3 out --- differential clock output (lvds) 13 vss pwr --- negative power supply 14, 15 q2n, q2 out --- differential clock ou tput (lvds) 16, 17 q1n, q1 out --- differential clock output (lvds) 1 8 vdd pwr --- positive power supply 19, 20 q0n, q0 out --- differential clock output (lvds) ordering information part number marking shipping packaging package temperature range a k818 1 f ak 81 81 f tape and reel 20 - pin tssop - 4 0 to 85 c
AK8181F dec - 2012 draft - e - 02 - 4 - absolute maximum rating over operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage vdd - 0.3 to 4.6 v input voltage vin vss - 0.5 to vdd+0. 5 v inpu t c urrent (any pins except supplies) i in 1 0 ma storage temperature tstg - 5 5 to 15 0 ? c note (1) stress beyond those listed under absolute m ax imum r atings may cause perman ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guarant eed only over the recommended operating temperature range. (2) vss=0v this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and in stallation procedu res can cause damage . akm recommends that this device is handled with appropriate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vdd ? 5% 3. 135 3.3 3. 465 v (1) power of 3.3v require s to be supplied from a single source. a decoupling capacitor of 0.1 ? f for power supply line should be locat ed close to each vdd pin. pin characteristics parameter s ymbol conditions m in typ m ax unit input capacitance c in 4 pf input pullup resistor r pu 51 k input pulldown resistor r pd 51 k p ower supply c haracteristics parameter s ymbol conditions m in typ m ax unit power supply current i dd pclk0p/n = input 650mhz pclk1p/n = open 4 5 ma pclk0p/n = open pclk1p/n = input 650mhz 45 ma esd sensitive device
AK8181F draft - e - 02 dec - 2012 - 5 - dc characteristics (lvcmos/lvttl) all specifications at vdd = 3.3 v ? 5% , vss=0v, ta: - 4 0 to +85 , unless otherwise noted parameter symbol conditions min typ max unit i nput high v oltage v ih 2.0 vdd+0.3 v i nput low v oltage v il - 0.3 0.8 v input high c urrent clk_sel i h vin=vdd =3.465v 150 a a l vin=vss , vdd=3.465v - 5 a a dc characteristics (differential) all specifications at vdd=3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit input h igh c urrent pclk0p i h vin=vdd=3.465v 150 a a l vin=vss , vdd=3.465v - 5 a a pp 0.15 1.3 v common mode input voltage (1) (2) v cmr vss+0.5 vdd - 0.85 v (1) for single ended applications, the maximum input voltage for pclk0p and pclk0n is vdd+0.3v. (2) common mode voltage is defined as v ih . dc characteristics (lvpecl) all specifications at vdd= 3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless ot herwise noted parameter symbol conditions min typ max unit input high c urrent pclk1p i h vin=vdd=3.465v 150 a a l vin= vss , vdd=3.465v - 5 a a pp 0.3 1.0 v common mode input voltage (1) (2) v cmr vss+1.5 vdd v (1) for single ended applications, the maximum input voltage for pclk1p and pclk1n is vdd+0.3v. (2) common mode voltage is defined as v ih .
AK8181F dec - 2012 draft - e - 02 - 6 - dc characteristics (lvds) all speci fications at vdd=3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit differential output voltage v od 200 280 360 mv v od magnitude change od 0 40 mv offset voltage v os 1.125 1.25 1.375 v v os magnitude change o s 5 25 mv high impedance leakag e current i oz oe=l - 10 +10 a osd - 3.5 - 5 ma output voltage high v oh 1.34 1.6 v output voltage low v ol 0.9 1.06 v ac characteristics all spec ifications at vdd = 3.3v ? 5%, vss=0v, ta: - 40 to +85 , unless o therwise noted all parameters measured at f 650mhz unless noted otherwise. the cycle to cycle jitter on the input will equal the jitter on the output. the part does not add jitter. (1) measured from the differential input crossing point to the differential output crossing point. (2) defined as skew betwee n outputs at the same supply voltage and with equal lo ad conditions. (3) this parameter is defined in accordance with jedec standard 65. (4) defined as skew between output s on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. (5) design value. parameter symbol conditions min typ max unit output frequency f out 650 mhz propagation delay (1) t pd 0.9 2.5 ns output skew (2) (3) t sk(o) 30 ps part - to - part skew (3 ) (4) t skpp 60 0 ps output rise/fall time (5 ) t r , t f 20% to 8 0% @50mhz 1 00 3 00 p s output duty cycle dc out 4 5 50 55 %
AK8181F draft - e - 02 dec - 2012 - 7 - figure 1 3.3v output load ac test circuit figure 2 differential input level figure 3 output skew figure 4 output rise/fall time figure 5 propagation delay figure 6 output duty / pulse width/ period figure 7 differential output level figure 8 part - to - part skew
AK8181F dec - 2012 draft - e - 02 - 8 - figure 9 offset voltage setup figure 10 differential output voltage setup figure 11 high impedance leakage figure 12 differential output short circuit current setup setup
AK8181F draft - e - 02 dec - 2012 - 9 - function table the following table shows the input s /output s clock state configured through the control pins . table 1 : control input function t able inp uts outputs oe clk_en clk_sel selected source q0:q3 q0n:q3n 1 0 0 (open) pclk0p/n disabled: low disabled: high 1 0 1 pclk1p/n disabled: low disabled: high 1 1 (open) 0 (open) pclk0p/n enabled enabled 1 1 (open) 1 pclk1p/n enabled enabled 0 x x --- hi - z hi - z after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in figure 13 . in the active mode, the state of the outputs are a function of the pclk0p/n and pclk1p/n as described in table 2. figure 13 clk_en timing diagram table 2 clock input function table inputs outputs input to output polarity pc lk0/1p pclk0/1n q0:q3 q0n:q3n 0 1 l ow h igh differential to differential non inverting 1 0 h igh l ow differential to differential non inverting 0 biased (1) l ow h igh single ended to differential non inverting 1 biased (1) h igh l ow single ended to diffe rential non inverting biased (1) 0 h igh l ow single ended to differential inverting biased (1) 1 l ow h igh single ended to differential inverting (1) please refer to the application information section, wiring the differential input to accept single ended le vels .
AK8181F dec - 2012 draft - e - 02 - 10 - application information wiring the differential input to accept single ended levels figure.8 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = vdd/2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and vdd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 14 single ended signal driving differential input
AK8181F draft - e - 02 dec - 2012 - 11 - package information ? mechanical data : 20pin tssop ? marking ? rohs compli ance all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead free packages* are fully compliant (*) rohs compliant products from akm are identified with p b free letter indication on product label posted on the anti - shield bag and boxes. a: #1 pin i ndex b: part number c: d ate code ( 7 digits) 1 20 10 11 ak8181 f xxxxx xx a b c 2 0 1 1 1 0 1 0 . 1 0 0 . 0 5 0 . 9 0 0 . 0 5 1 . 1 0 m a x s 4 . 4 0 0 . 1 0 0 . 1 0 s 6 . 5 0 0 . 1 0 6 . 4 0 0 . 1 0 0 . 6 0 . 1 0 0 . 1 5 0 . 0 5 0 . 2 5 0 . 0 5 0 . 6 5 0 8
AK8181F dec - 2012 draft - e - 02 - 12 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales offi ce of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only t o illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. ak m assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency e xchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for t he use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of t he safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safe ty or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibil ity of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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