AK8181E draft - e - 01 feb - 2013 - 1 - features four differential 3.3v lvpecl outputs selectable crystal or differential clock in puts clock output frequency up to 650 mhz translates any single - ended input signal to 3.3v lvpecl leve ls with resistor bias on pclkn input o utput skew : 1 0ps ( typical ) part - to - part skew : 1 50ps ( maximum ) propagation delay : 0.9 ns ( typical ) add itive phase jitter(rms): pclkp/n@156.25mhz : 0.04 ps (typical) xtal@50mhz : 0.14ps (typ ical ) operating temper ature range: - 4 0 to +85 package: 20 - pin tssop (pb free) pin compatible with ics853 3i - 3 1 description the ak 8181 e is a member of akm s lvpecl clock fanout buffer family designed for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the ak 8181 e distributes 4 buffered clocks . ak 8181 e are derived f r o m akm s long - term - experienced clock devic e technology , and enable clock output to perform low skew . the ak 8181 e is ava ilable in a 20 - pin tssop pa ckage. block dia gram 3.3v lvpecl 1: 4 preliminary clock fanout buffer ak 8181 e
AK8181E feb - 2013 draft - e - 01 - 2 - pin d escription s package: 2 0 - pin tssop (top view) pin no. pin name pin type pullup d own description 1 vss pwr --- negative power supply 2 clk_en in pull up syn chronizing clock output enable (lvcmos/lvttl) pin is connected to vdd by internal r esistor. (typ. 51k ) h igh(open) : clock outputs follow clock input. l ow : q outputs are forced low, qn outputs are forced high. 3 clk_sel in pull down clk select input (lvcmos/lvttl) pin is connected to vss by internal resistor. (typ. 51k ) high: selects xt al inputs low(open): selects pclkp/n inputs 4 pclkp in pull down non - inverting differential clock input pin is connected to vss by internal resistor. (typ. 51k ) 5 pclkn in pull up inverting differential clock input pin is connected to vdd by internal re sistor. (typ. 51k ) 6 xtal_in in --- crystal oscillator interface 7 xtal_out in --- crystal oscillator interface 8, nc -- --- no connect 9 nc -- --- no connect 10 vdd pwr --- positive power supply 11, 12 q3n, q3 out --- differential clock output (lvp ecl) 13 vdd pwr --- power supply 14, 15 q2n, q2 out --- differential clock output (lvpecl) 16, 17 q1n, q1 out --- differential clock output (lvpecl) 1 8 vdd pwr --- positive power supply 19, 20 q0n, q0 out --- differential clock output (lvpecl) order ing information part number marking shipping packaging package temperature range ak818 1e ak 81 81 e tape and reel 20 - pin tssop - 4 0 to 85 c
AK8181E draft - e - 01 feb - 2013 - 3 - absolute maximum rating over operating free - air temperature range unless otherwise noted (1) items s ymbol ratings u nit s upply v oltage vdd - 0.3 to 4.6 v input voltage vin vss - 0.5 to vdd+0. 5 v input c urrent (any pins except supplies) i in 1 0 ma storage temperature tstg - 5 5 to 15 0 ? c note (1) stress beyond those listed under absolute m ax imum r atings may cause perma n ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions fo r extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. (2) vss=0v this device is manufactured on a cmos process, therefore, generically susceptible to damage by exc essive static voltage. failure to observe proper handling and in stallation procedures can cause damage . akm recommends that this device is handled with appropriate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax un it operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vdd ? 5% 3. 135 3.3 3. 465 v (1) power of 3.3v require s to be supplied from a single source. a decoupling capacitor of 0.1 ? f for power supply line should be locat ed close to each vdd pin. p in characteristics parameter s ymbol conditions m in typ m ax unit input capacitance c in 4 pf input pullup resistor r pu 51 k input pulldown resistor r pd 51 k p ower supply characteristics parameter s ymbol conditions m in typ m ax unit power sup ply current i dd pclkp/n = input 650mhz xtal = open 32 ma xtal = input 50mhz pclkp/n = open 35 ma esd sensitive devi ce
AK8181E feb - 2013 draft - e - 01 - 4 - dc characteristics (lvcmos/lvttl) all specifications at vdd = 3.3 v ? 5% , ta: - 4 0 to +85 , unless otherwise noted parameter symbol conditions min t yp max unit i nput high v oltage v ih 2.0 vdd+0.3 v i nput low v oltage v il - 0.3 0.8 v input high c urrent clk_sel i h vin=vdd =3.465v 150 a a l vin=vss , vdd=3.465v - 5 a a dc characteristics (differential) all specifications at vdd= 3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit input high c urrent pclk p i h vin=vdd=3.465v 150 a a l vin=vss , vdd=3.465v - 5 a a pp 0.15 1.3 v common mode input voltage (1) (2) v cmr vss+0.5 vdd - 0.85 v (1) for single ended applications, the maximum input vo ltage for pclkp and pclk n is vdd+0.3v. (2) common mode voltage is defined as v ih . dc characteristics (lvpecl) all specifications at vdd= 3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit output high voltage (3) v oh vdd - 1.4 vdd - 0.9 v output low voltage (3) v ol vdd - 2.0 vdd - 1.7 v peak - to - peak output voltage swing v swing 0.6 1.0 v (3) outputs terminated with 50 to vdd - 2v.
AK8181E draft - e - 01 feb - 2013 - 5 - ac characteristics all spec ifications at vdd = 3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted all parameters measured at f 650mhz unless noted otherwise. the cycle to cycle ji tter on the input will equal the jitter on the output. the part does not add jitter. (1) measured from the differential input crossing point to the differential output crossing point. (2) defined as skew between outputs at the same supply voltage and with equal lo ad conditions. (3) this parameter is defined in accordance with jedec standard 65. (4) defined as skew between output s on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outp uts are measured at the differential cross points. (5) design value crystal characteristics all specifications at vdd= 3.3v ? 5%, vss=0v, ta: - 40 to +85 c , unless otherwise noted parameter conditions min typ max unit mode of oscillation fundamental frequen cy 12 50 mhz equivalent series resistance (esr) 50 ? parameter symbol conditions min typ max unit output frequency f out 650 mhz propagation delay (1) t pd 0.9 n s output skew (2) (3) t sk(o) 10 ps part - to - part skew (3 ) (4) t sk pp 15 0 p s buffer additive jitter, rms (5) t jit pclkp/n 156.2 5mhz (12khz C C (5) t r , t f 20% to 80% 2 00 6 00 p s output duty cycle dc out pclkp/n 50 %
AK8181E feb - 2013 draft - e - 01 - 6 - figure 1 3.3v output load test circuit figure 2 differential input level figure 3 output skew figure 4 output rise/fall time figure 5 propagation delay figure 6 output duty / pulse width/ period c l o c k o u t p u t s 8 0 % q x t s k ( o ) q x n q y n q y t r t f 2 0 % 8 0 % 2 0 % v s w i n g
AK8181E draft - e - 01 feb - 2013 - 7 - function table the following table shows the i nput s /output s clock state configured through the control pins . table 1 : control input function t able inputs outputs clk_en clk_sel selected source q0:q3 q0n:q3n 0 0 (open) p clk p/n disabled: low disabled: high 0 1 xtal disabled: low disabled: high 1 (open) 0 (open) p clk p/n enabled enabled 1 (open) 1 xtal enabled enabled after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown in figure 7 . in the active mode, the state of the outputs are a function of the p clk p/n a nd xtal inputs as described in table 2 . figure 7 clk_en timing diagram table 2 clock input function table inputs outputs input to output polarity pclk p pclk n q0:q3 q0n:q3n 0 1 l ow h igh differential to differential non inverting 1 0 h igh l ow differential to differential non inverting 0 biased (1) l ow h igh single ended to differential non inverting 1 biased (1) h igh l ow sing le ended to differential non inverting biased (1) 0 h igh l ow single ended to differential inverting biased (1) 1 l ow h igh single ended to differential inverting (1) please refer to the application information section, wiring the differential input to accept single ended levels .
AK8181E feb - 2013 draft - e - 01 - 8 - application information wiring the differential input to accept single ended levels figure.8 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = vdd/2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and vdd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 8 single ended signal driving differential input
AK8181E draft - e - 01 feb - 2013 - 9 - package information ? mechanical data : 20pin tssop ? mark ing ? rohs compliance all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead free packages* are fully compliant (*) rohs co mpliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. a: #1 pin index b: part number c: d ate code ( 7 digits) 1 20 10 11 ak8181 e xxxxx xx a b c 2 0 1 1 1 0 1 0 . 1 0 0 . 0 5 0 . 9 0 0 . 0 5 1 . 1 0 m a x s 4 . 4 0 0 . 1 0 0 . 1 0 s 6 . 5 0 0 . 1 0 6 . 4 0 0 . 1 0 0 . 6 0 . 1 0 0 . 1 5 0 . 0 5 0 . 2 5 0 . 0 5 0 . 6 5 0 8
AK8181E feb - 2013 draft - e - 01 - 10 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of th ese products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related informat ion contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other relate d information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of ex port pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm as sumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result , whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed o r intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or d amage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
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