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m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 1 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 240pin unbuffered ddr2 sdram module based on 128 mx8 ddr2 sdra m g - die features performance: pc2 - 5300 pc2 - 6400 pc2 - 8500 unit speed sort - 3c - ac - bd dimm ??? latency * 5 5 6 f ck clock frequency 333 400 5 33 mhz t ck clock cycle 3 2.5 1.875 ns f dq dq burst freq uency 667 800 1066 m bps ? jedec standard 240 - p in dual in - line memory module ? 128mx 64 and 256mx64 ddr 2 unbuff ered dimm based on elixir 128 mx8 ddr2 sdram g - die component ? double data rate architecture ; two data transfer per clock cycle ? differential bi - di re ctional data strobe (dq s & ??? ) ? dqs is edge - aligned with data for reads and is cent er - aligned with data for writes ? differential clock inputs (ck & ?? ) ? intended for 333mhz /400mhz applications ? inputs and outputs are sstl - 1 8 compatible ? v dd = v ddq = 1.8v 0. 1 v ? 7.8 s max. a verage periodic refresh interval ? programmable operation: - d evice ??? latency: 3, 4, 5 , 6 - burst length: 4, 8 ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? 14/10/1 addressing (row/column/rank) C 1gb ? 14/10/2 addressing (row/column/rank) C 2gb ? serial presence detect ? on die termination (odt) ? ocd impedance adjustment. ? gold contacts ? sdrams in 6 0 - ball bga package ? rohs complian ce . description m2y1g64tu88 g7 b and m2y2g64tu8 h g 5 b are 24 0 - pin double data rate 2 (ddr 2 ) synchronous dram unbuff ered dual in - line memory module ( u dimm), organized as o ne rank 128 mx 64 and two ranks 256mx64 high - speed memory array. m 2y1g64tu88 g7 b u se s eight 128 mx8 ddr 2 sdrams and m2y2g64tu8 g 5 b use s sixteen 128mx8 ddr 2 sdrams in bga packages. these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation between suppliers. all elixir ddr 2 sdram dimms provide a high - performance, flexible 8 - byte interface in a 5.25 long space - saving foo tprint. the dimm is intended for use in applications operating up to 333mhz (or 400 mhz / 533mhz ) clock speeds and achieves high - speed data transfer rates of up to 667mbps (or 800 mbps /1066mbps ) . prior to any access operation, the device ??? latency and burst / length /operat ion type must be programmed into the dimm by address inputs a0 - a1 3 and i/o inputs ba0 , ba1 and ba 2 using the mode register set cycle. the dimm uses serial presence - detect implemented via a serial 2,048 - bit eeprom using a standard iic protocol. the first 12 8 bytes of serial pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer.
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 2 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ordering information part number speed organization leads power note m2y1g64tu88 g7b - 3c 333 mhz (3. 00 ns @ cl = 5 ) dd r2 - 667 pc2 - 5300 128 mx64 gold 1.8v m2y1g64tu88 g7b - ac 400 mhz ( 2.50 ns @ cl = 5 ) ddr2 - 800 pc2 - 6400 m2y1g64tu88 g7b - bd 533mhz (1.875ns @ cl = 6 ) ddr2 - 1066 pc2 - 8500 m2y2g64tu8h g5b - 3c 333 mhz (3. 00 ns @ cl = 5 ) ddr2 - 667 pc2 - 5300 256mx64 m2y2g64tu8h g5 b - ac 400 mhz ( 2.50 ns @ cl = 5 ) ddr2 - 800 pc2 - 6400 m2y2g64tu8h g5 b - bd 533mhz (1.875ns @ cl = 6 ) ddr2 - 1066 pc2 - 8500 pin description ck0 ~ck2 ??? ???? differential clock inputs dq0 - dq63 data input/output cke0 , cke1 clock enable dqs0 - dqs8 bidirectional data strobes ??? row address strobe dm0 - dm8 input data mask ??? column address strobe ???? - ???? differential data strobes ?? write enable v dd power ( 1.8 v) ??? , ??? chip selects v ref ref. voltage for sstl_18 inputs a0 - a9, a0 - a1 3 address inputs v ddspd serial eeprom positive power supply a10/ap column address input/auto - precharge v ss ground ba0 ~ ba 2 sdram ban k address inputs scl serial presence detect clock input reset reset pin sda serial presence detect data input/output odt0, odt1 on - die termination control lines sa0 ~ sa2 serial presence detect address inputs nc no connect note: odt1, cke1 and ??? ? a re only support in 2gb module type .
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 3 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pin out pin front pin front pin front pin back pin back pin back 1 v ref 42 nc 82 v ss 121 v ss 162 nc 202 dm4 2 v ss 43 nc 83 ???? 122 dq4 163 v ss 203 nc 3 dq0 44 v ss 84 dqs4 123 dq5 164 nc 204 v ss 4 dq1 45 nc ? 85 v ss 124 v ss 165 nc 205 dq38 5 v ss 46 nc 86 dq34 125 dm0 166 v ss 206 dq39 6 ???? ? 47 v ss 87 dq35 126 nc 167 nc 207 v ss 7 dqs0 48 nc 88 v ss 127 v ss 168 nc 208 dq44 8 v ss 49 nc 89 dq40 128 dq6 169 v ss 209 dq45 9 dq2 50 v ss 90 dq41 129 dq7 170 v ddq 210 v ss 1 0 dq3 51 v ddq 91 v ss 130 v ss 171 nc, cke1 211 dm5 11 v ss 52 cke0 92 ???? 131 dq12 172 v dd 212 nc 12 dq8 53 v dd 93 dqs5 132 dq13 173 nc 213 v ss 13 dq9 5 4 ba2 94 v ss 133 v ss 174 nc 214 dq46 14 v ss 55 nc 95 dq42 134 dm1 175 v ddq 215 dq47 15 ???? 56 v ddq 9 6 dq43 135 nc 176 a12 216 v ss 16 dqs1 57 a11 97 v ss 136 v ss 177 a9 217 dq5 2 17 v ss 58 a7 98 dq48 137 ck1 178 v dd 218 dq53 18 nc 59 v dd 99 dq 49 138 ??? ? 179 a8 219 v ss 19 nc 60 a5 100 v ss 139 v ss 180 a6 220 ck2 20 v ss 61 a4 10 1 sa2 140 dq1 4 181 v ddq 221 ??? ? 21 dq10 62 v ddq 102 nc 141 dq15 182 a3 222 v ss 22 dq11 63 a2 103 v ss 142 v ss 183 a1 223 dm6 23 v ss 64 v dd 104 ???? 143 dq20 184 v dd 224 nc 24 dq1 6 key 105 dqs6 144 dq21 key 225 v ss 25 dq 17 65 v ss 106 v ss 145 v ss 185 ck0 226 dq54 26 v ss 66 v ss 10 7 dq50 146 dm2 186 ??? 227 dq55 27 ???? 67 v dd 108 dq51 147 nc 187 v dd 228 v ss 28 dq s2 68 nc 109 v ss 148 v ss 188 a0 229 dq60 29 v ss 69 v dd 110 dq56 149 dq22 189 v dd 230 dq61 30 dq18 70 a10/ap 111 dq57 150 dq23 190 ba1 231 v ss 31 dq 19 71 ba0 112 v ss 15 1 v ss 191 v ddq 232 dm7 32 v ss 72 v ddq 113 ???? 152 dq28 192 ??? ? 233 nc 33 dq24 73 ?? ? 114 dqs7 1 5 3 dq29 193 ??? ? 234 v ss 34 dq25 74 ??? ? 115 v ss 154 v ss 194 v ddq 235 dq62 35 v ss 75 v ddq 116 dq58 155 dm3 195 odt0 236 dq63 36 ???? 76 nc, ??? ? 117 dq59 156 nc 196 a13 237 v ss 37 dq s3 77 nc, odt1 118 v ss 157 v ss 197 v dd 238 v ddspd 38 v ss 78 v ddq 119 sda 158 dq30 198 v ss 239 sa0 39 dq26 79 v ss 120 scl 159 dq31 199 dq36 240 sa1 40 dq27 80 dq32 160 v ss 200 dq37 41 v ss 81 dq33 161 nc 201 v ss note: 1 . nc = no connect . 2. ??? ? , odt1 and cke1 (pins 76, 77 and 171 ) are only support in 2gb module type .
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 4 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0 , ck1 , ck2 (sstl) positive edge the positive line of the differential pair of system clock inputs which drives the input to the on - dimm pll. all the ddr 2 sdram address and control inputs are sampled on the rising edge of their associated clocks. ??? , ??? , ??? (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on - dimm pll. cke0 , cke1 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self refresh mode. cke1 apply on 2gb udi mm only . ??? , ??? (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when th e command decoder is disabled, new commands are ignored but previous operations continue . ??? apply on 2gb udimm only . ??? , ??? , ?? (sstl) active low when sampled at the positive rising edge of the clock, ??? , ??? , ?? define the operation to be executed by the sdram. v ref supply reference voltage for sstl - 18 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity odt0, odt1 input active high on - die termination control signals . odt1 apply on 2gb udimm only . ba0 C ba 2 (sstl) - selects which sdram bank is to be active. a0 - a9 a10/ap a11 - a13 (sstl) - during a bank activ ate command cycle, a0 - a1 3 defines the row address (ra0 - ra1 3 ) when sampled at the rising clock edge. during a read or write command cycle, a0 - a 9 defines the column address (ca0 - ca 9 ) when sampled at the rising clock edge. in addition to the column address, a p is used to invoke autoprecharge operation at the end of the burst read or write cycle . if ap is high, a utoprecharge s selected and ba0/ba1 defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre - charge. dq0 C dq 63 (sstl) active hi gh data and check bit input /output pins. v dd, v ss supply power and ground for the ddr 2 sdram input buffers and core logic dq s 0 C dq s8 ???? C ???? (sstl) negative and positive edge data strobe for input and output data dm0 C dm 8 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dm8 is associated with check b its cb0 - cb7, and is not used on x64 modules. sa0 C sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi - directional pin is used to transfer data into or out of th e spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pull - up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull - up. v ddspd supply serial eeprom positive power supply.
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 5 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram (1gb, 1 rank, 128mx8 ddr2 sdrams) s e r i a l p d a 0 a 2 a 1 s c l w p s d a s a 0 s a 2 s a 1 s p d v d d s p d v d d / v d d q v r e f v s s c s 0 d m 1 d q s 1 d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 d q s 2 d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 d m 2 d q s 3 d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 d m 3 d m 0 d q s 0 d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 d m 5 d q s 5 d q s 5 d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 d 5 d q s d m d m 6 d q s 6 d q s 6 d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 d 6 d q s d m d m 7 d q s 7 d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 d 7 d q s d m d q s 4 d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 d 4 d q s d m d q s 4 d m 4 d 1 d q s d m d 2 d q s d m d 3 d q s d m c s d 0 d q s d q s d m b a 0 - b a 2 a 0 - a 1 3 r a s c a s c k e 0 w e a 0 - a 1 3 : b a 0 - b a 2 : r a s : c k e : c a s : w e : o d t 0 o d t : d q s 0 d q s 1 d q s 2 d q s 3 c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s d q s 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 d 0 - d 7 d 0 - d 7 d 0 - d 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 6 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram ( 2 gb , 2 rank s , 12 8 mx8 ddr 2 sdrams) s e r i a l p d a 0 a 2 a 1 s c l w p s d a s a 0 s a 2 s a 1 s p d v d d s p d v d d / v d d q v r e f v s s c s 0 d m 1 d q s 1 d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 d q s 2 d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 d m 2 d q s 3 d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 d m 3 d m 0 d q s 0 d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 d m 5 d q s 5 d q s 5 d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 d m 6 d q s 6 d q s 6 d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 d 6 d q s d m d m 7 d q s 7 d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 d 7 d q s d m d q s 4 d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 d q s 4 d m 4 d 2 d q s d m d 3 d q s d m d 1 0 d q s d m d 1 1 d q s d m d 1 4 d q s d m d 1 5 d q s d m b a 0 - b a 2 a 0 - a 1 3 r a s c a s c k e 0 w e a 0 - a 1 3 : b a 0 - b a 2 : r a s : c k e : c a s : w e : c k e 1 c k e : s d r a m s d 0 - d 1 5 o d t 0 o d t : o d t 1 o d t : c s 1 d q s 0 d q s 1 d q s 2 d q s 3 c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s d q s 7 s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 s d r a m s d 8 - d 1 5 s d r a m s d 8 - d 1 5 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 d 0 - d 1 5 d 0 - d 1 5 d 0 - d 1 5 d 0 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 8 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 1 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 1 2 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 4 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 9 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 5 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 d 1 3 d q s d m c s d q s i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7 i i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 / o 7
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 7 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on any pin relative to vss - 0.5 to 2.3 v v ddq vol tage on v ddq supply relative to vss - 0.5 to 2.3 v v ddql voltage on v ddql supply relative to vss - 0.5 to 2.3 v v dd voltage on vdd supply relative to vss - 1.0 to +2.3 v note : stresses greater than those listed under absolute maximum ratings may cause p ermanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the oper ational sec ti ons of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect reliability. dc o perating conditions symbol parameter rating units note t case operating temperature (ambient) 0 to 95 c 1,2,3 t stg storage temperature (plastic) - 55 to 100 c i l short circuit output current - 5 to 5 a note: 1. case temperature is measured at top and center side of any drams. 2. t case > 85 c ? t refi = 3.9 s 3. all dram specification only support 0 c < t case < 85 c dc electrical characteristics and operating conditions (t case = 0 c ~ 85 c; v ddq = 1.8v 0 .1v; v dd = 1.8v 0.1 v, see ac characteristics) symbol parameter min max units notes v dd supply voltage 1.7 1.9 v 1 v dd q supply voltage for output 1.7 1.9 v 1, 3 v ddl supply voltage for v dd q l 1.7 1.9 v 3 v ref input reference voltage 0.49 v dd q 0.51 v dd q mv 2 v tt termination voltage v ref C 0.04 v ref + 0.04 v 4 v ih (dc) input high (logic1) voltage v ref + 0.125 v ddq + 0.3 v v il (dc) input low (logic0) voltage - 0.3 v ref C 0. 125 v note: 1. inputs are not recognized as valid until vref stabilizes. 2. vref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak - to - peak noise on vref may not exceed 2% of the dc value. 3. vddq tracks with vdd, vddl tracks with vdd. 4. vtt of transmitting device track v ref of receiving device. environmental parameters symbol parameter rating units note t opr module operating temperature range (ambient) 0 to 55 c 3 h opr operating humidity (relative) 10 to 90 % t stg storage temperature (plastic) - 55 to 100 c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1,2 note: 1. stresses greater than those listed may cause permanent damage to the device. this is a tress rating only and device functiona l operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. up to 9850 ft. 3. the component maximum case temperature shall not exceed the value specified in the c omponent spec.
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 8 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0.1v ( 1 g b, 1 r ank, 128 mx8 ddr 2 sdrams) symbol parameter/condition pc2 - 53 00 pc2 - 6400 pc2 - 8500 unit i dd0 operating current: one bank; active/precharge; t rc = t rc ( m in); t ck = t ck ( min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd ma i dd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc ( min); cl=2.5; t ck = t ck ( min) ; i out = 0 ma ; address and control inputs changing once per clock cycle tbd tbd tbd ma i dd 2p precharge power - down standby current: all banks idle; power - down mode; cke ? v il ( max); t ck = t ck ( min ) tbd tbd tbd ma i dd2n idle standby current: cs ? v ih ( min); all ban ks idle; cke ? v ih (min ) ; t ck = t ck ( min); address and control inputs changing once per clock cycle tbd tbd tbd ma i dd2q precharge quiet standby current: all banks idle; ?? is high; cke is high; t ck = t ck (min) ; other control and address inputs are stable, data bus inputs are floating. tbd tbd tbd ma i dd3pf active power - down current: all banks open; t ck = t ck (min) , cke is low; other control and address inputs are stable, da ta bus inputs are floating. mrs a12 bit is set to low (fast power - down exit). tbd tbd tbd ma i dd3ps active power - down current: all banks open; t ck = t ck (min) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power - down exit). tbd tbd tbd ma i dd3n active standby current: one bank; active/precharge; cs ? v ih ( min); cke ? v ih ( min); t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inpu ts changing once per clock cycle tbd tbd tbd ma i dd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck ( min ) tbd tbd tbd ma i dd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck ( min); i out = 0 ma tbd tbd tbd ma i dd 5 auto - refre sh current: t rc = t rfc ( min ) tbd tbd tbd ma i dd6 self - refresh current: cke ? 0.2v tbd tbd tbd ma i dd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min); i out = 0 ma . tbd tbd tbd ma note: module idd was calculated from component idd. it may differ from the actual measurement.
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 9 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0.1v ( 2 g b, 2 r ank s , 128 mx8 ddr 2 sdra ms) symbol parameter/condition pc2 - 53 00 pc2 - 6400 pc2 - 8500 unit i dd0 operating current: one bank; active/precharge; t rc = t rc ( min); t ck = t ck ( min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd ma i dd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc ( min); cl=2.5; t ck = t ck ( min); i out = 0 ma ; address and control inputs changing once per clock cycle tbd tbd tbd ma i dd 2p precharge power - down standb y current: all banks idle; power - down mode; cke ? v il ( max); t ck = t ck ( min ) tbd tbd tbd ma i dd2n idle standby current: cs ? v ih ( min); all banks idle; cke ? v ih (min ) ; t ck = t ck ( min); address and control inputs changing once per clock cycle tbd tbd tbd ma i dd2q precharge quiet standby current: all banks idle; ?? is high; cke is high; t ck = t ck (min) ; other control and address inputs are stable, data bus inputs are floating. tbd tbd tbd ma i dd3pf active power - down current: all banks open; t ck = t ck (min) , cke is low; other control and address inputs are stable, da ta bus inputs are floating. mrs a12 bit is set to low (fast power - down exit). tbd tbd tbd ma i dd3ps active power - down current: all banks open; t ck = t ck (min) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power - down exit). tbd tbd tbd ma i dd3n active standby current: one bank; active/precharge; cs ? v ih ( min); cke ? v ih ( min); t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control in puts changing once per clock cycle tbd tbd tbd ma i dd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck ( min ) tbd tbd tbd ma i dd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck ( min); i out = 0 ma tbd tbd tbd ma i dd 5 auto - refresh current: t rc = t rfc ( min ) tbd tbd tbd ma i dd6 self - refresh current: cke ? 0.2v tbd tbd tbd ma i dd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min); i out = 0 ma . tbd tbd tbd ma note: module idd was calculated from component idd. it may differ from the actual measurement.
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 10 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specifications for ddr 2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0 .1v; v dd = 1 .8v 0.1 v, see ac characteristics) (part 1 of 2) symbol parameter pc2 - 53 00 pc2 - 64 00 pc2 - 8500 unit min. max. min. max. min max t ck clock cycle time (average) 3000 8 000 2500 8 000 1875 8000 ps t ch ck high - level width (average) 0.4 8 0.5 2 0.4 8 0.52 0.48 0.52 t ck t cl ck low - level width (av erage) 0.4 8 0.5 2 0.4 8 0.52 0.48 0.52 t ck wl write command to dqs associated clock edge rl - 1 rl - 1 rl - 1 nck rl - 1 t dqss write command to 1 st dqs latching transition - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 t ck t dss dqs falling edge to ck setup time (write cycle) 0.2 - 0.2 - 0.2 - t ck t dsh dqs fallin g edge hold time from ck (write cycle) 0.2 - 0.2 - 0.2 - t ck t dqsl , ( h ) dqs input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - t ck t wpre write preamble 0.35 - 0. 3 5 - 0. 3 5 - t ck t wpst write postamble 0.4 0.6 0.4 0.6 0.4 0.6 t ck t is address and control input setup time 2 0 0 - 175 - 125 - ps t ih address and control input hold time 2 75 - 25 0 - 2 00 - ps t ipw input pulse width 0.6 - 0.6 - 0.6 - t ck t ds dq and dm input setup time (differential data strobe) 100 - 50 - 0 - ps t dh dq and dm input hold time(differential data strobe) 175 - 1 2 5 - 7 5 - p s t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - 0.35 - t ck t ac dq output access time from ck/ ?? dqsck dqs output access time from ck/ ?? hz data - out high - impedance time from ck/ ?? ac max - t acmax - t ac max ps t lz (dqs) dqs low - impedance time from ck / ?? ac min t ac max t acmin t acmax t ac min t ac max ps t lz (dq) dq low - impedance time from ck / ?? ac min t ac max 2t ac min t ac max 2t ac min t ac max ps t dqsq dqs - dq skew (dqs & associated dq signals) - 240 - 2 00 - 175 p s t hp minimum half clk period for any given cycle; defined by clk high ( t ch ) or clk low ( t cl ) time min( t ch (abs), t cl (abs) ) - min( t ch (abs), t cl (abs) ) - min( t ch (a bs), t cl (abs) ) - ps t qhs data hold skew factor - 3 4 0 - 3 00 - 250 ps t qh data output hold time from dqs t hp C qhs - t hp C qhs - t hp - t qh s - p s t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.4 0.6 0.4 0.6 0.4 0.6 t ck t rrd active bank a to active bank b command 7.5 - 7.5 - 7.5 - ns t faw four activate window for 1kb page size products 37.5 - 35 - 35 - ns t ccd ??? ??? wr write recovery time without auto - precharge 15 - 15 - 15 - ns t dal auto precharge write recovery + precharge t ime wr +t n rp - wr +t n rp - wr + t nrp - nck t wtr internal write to read command delay 7.5 - 7.5 - 7.5 - ns t rtp internal read to precharge comman d delay 7.5 7.5 7.5 - ns t cke cke minimum pulse width 3 3 3 - nck t xsn r exit self r efresh to a non - read command t rfc +10 - t rfc +10 t rfc +10 - ns t xsrd exit self r efresh to a read command 200 - 200 200 - nck t xp exit precharge power down to a ny non - read command 2 - 2 - 3 - nck
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 11 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specifications for ddr 2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0 .1v; v dd = 1.8v 0.1 v, see ac characteristics) (part 2 of 2) symbol parameter pc2 - 5300 pc2 - 6400 pc2 - 8500 unit min. max. min. max. min max t xard exit active power down to read command 2 - 2 - 3 - nck t xards exit active power down to read command 7 - al 8 - al 10 - al - nck t aond odt turn - on delay 2 2 2 2 2 2 nck t aon odt turn - on t ac (min) t ac (max) + 0.7 t ac (min) t ac (max)+ 0.7 t ac min t ac max + 2.575 ns t aonpd odt turn - on (power down mode) t ac (min) +2 2 t ck + t ac (max) +1 t ac (min) +2 2 t ck + t ac (max) +1 t ac min + 2 3 t ck + t ac max + 1 ns t aofd odt turn - off delay 2.5 2.5 2.5 2.5 2.5 2.5 nck t aof odt turn - off t ac (min) t ac (max) +0.6 t ac (min) t ac (max) +0.6 t ac min t ac max + 0.6 ns t aofpd odt turn - off (power down mode) t ac (min) +2 2 .5 t ck + t ac (max) +1 t ac (min) +2 2 .5 t c k + t ac (max) +1 t ac min + 2 2 .5 t ck + t ac max + 1 ns t anpd odt to power down entry latency 3 - 3 - 4 - nck t axpd odt power down exit latency 8 8 11 - nck t mrd mode register set command cycle time 2 - 2 - 2 - nck t mod mrs command to odt update delay 0 12 0 12 0 12 ns t oit ocd drive mode output delay 0 12 0 12 0 12 ns t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck + t ih - t is + t ck + t ih - t is + t ck + t ih - ns trfc refresh to active/refresh command time 127.5 127.5 105 ns t refi average periodic refresh interval (85oc < t case 95oc) s (0oc t case 85oc) s speed grade definition symbol parameter pc2 - 53 00 pc2 - 64 00 pc2 - 8500 unit min max min max min max t ras row active time 45 70 ,000 45 70 ,000 45 70000 ns t rc row cycle time 60 - 57.5 - 56.25 - ns t rcd ras to cas delay 15 - 12.5 - 11.25 - ns t rp row precharge time 1 5 - 12.5 - 11.25 - ns
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 12 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions ( raw card version: d , 1 gb , 1 rank, 128 mx8 ddr2 sdrams) f r o n t 1 . 5 0 + / - 0 . 1 d e t a i l a 0 . 0 3 9 d e t a i l b 0 . 8 + / - 0 . 5 b a c k 0 . 0 5 9 + / - 0 . 0 0 4 3 . 8 0 0 . 1 5 0 . 1 5 7 4 . 0 0 0 . 0 3 1 + / - 0 . 0 2 1 . 0 0 p i t c h d e t a i l a d e t a i l b 0 . 0 9 8 ? 2 . 5 1 0 . 0 0 . 3 9 4 1 3 3 . 3 5 1 3 1 . 3 5 1 2 8 . 9 5 5 . 2 5 0 5 . 1 7 1 5 . 0 7 7 1 7 . 8 0 2 . 3 0 0 . 0 9 1 0 . 7 0 0 3 0 . 0 0 1 . 1 8 0 ( 2 x ) 4 . 0 0 0 . 1 5 7 n o t e : a l l d i m e n s i o n s a r e t y p i c a l w i t h t o l e r a n c e s o f + / - 0 . 1 5 ( 0 . 0 0 6 ) u n l e s s o t h e r w i s e s t a t e d . u n i t s : m i l l i m e t e r s ( i n c h e s ) s i d e 3 . 1 8 m a x 1 . 2 7 + / - 0 . 1 0 0 . 1 2 5 0 . 0 5 0 + / - 0 . 0 0 4 2 . 5 0 0 . 1 0 5 . 0 0 0 . 2 0 5 5 . 0 0 2 . 1 6 5 6 3 . 0 0 2 . 4 8 0
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 13 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions ( raw card version: e , 2 gb , 2 rank s , 128 mx8 ddr 2 sdram s) f r o n t 1 . 5 0 + / - 0 . 1 d e t a i l a 0 . 0 3 9 d e t a i l b 0 . 8 + / - 0 . 5 b a c k 0 . 0 5 9 + / - 0 . 0 0 4 3 . 8 0 0 . 1 5 0 . 1 5 7 4 . 0 0 0 . 0 3 1 + / - 0 . 0 2 1 . 0 0 p i t c h d e t a i l a d e t a i l b 0 . 0 9 8 ? 2 . 5 1 0 . 0 0 . 3 9 4 1 3 3 . 3 5 1 3 1 . 3 5 1 2 8 . 9 5 5 . 2 5 0 5 . 1 7 1 5 . 0 7 7 1 7 . 8 0 2 . 3 0 0 . 0 9 1 0 . 7 0 0 3 0 . 0 0 1 . 1 8 0 ( 2 x ) 4 . 0 0 0 . 1 5 7 n o t e : a l l d i m e n s i o n s a r e t y p i c a l w i t h t o l e r a n c e s o f + / - 0 . 1 5 ( 0 . 0 0 6 ) u n l e s s o t h e r w i s e s t a t e d . u n i t s : m i l l i m e t e r s ( i n c h e s ) s i d e 4 . 0 0 m a x 1 . 2 7 + / - 0 . 1 0 0 . 1 5 7 0 . 0 5 0 + / - 0 . 0 0 4 2 . 5 0 0 . 1 0 5 . 0 0 0 . 2 0 5 5 . 0 0 2 . 1 6 5 6 3 . 0 0 2 . 4 8 0
m2y1 g64 t u8 8 g 7 b / m2y2g 64 t u8 h g5b 1gb: 128m x 64 / 2gb : 256m x 64 unbuffer ed ddr2 sdram dimm preliminary rev 0 .1 14 0 1 /20 1 0 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. revision log rev date modification 0.1 0 1 /20 1 0 preliminary edition

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