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| specification subject to change without notice, as is a nd for reference only. for purchasing, please contact sales representatives. it8511e/te/g embedded controller preliminary specification 0.4.1 ite tech. inc. free datasheet http:///
copyright ? 2006 ite tech. inc. this is preliminary document release. all spec ifications are subject to change without notice. the material contained in this document supersedes all previous documentation issued for the related products included herein. please contact ite tech. inc. for the late st document(s). all sales are subject to ite?s standard terms and conditions, a copy of which is included in the back of this document. ite, it8511e/te/g is a trademark of ite tech. inc. all other trademarks are claimed by their respective owners. all specifications are subject to change without notice. additional copies of this manual or other ite literature may be obtained from: ite tech. inc. phone: (02) 2912-6889 marketing department fax: (02) 2910-2551, 2910-2552 8f, no. 233-1, bao chiao rd., hsin tien, taipei county 231, taiwan, r.o.c. if you have any marketing or sales questions, please contact: p.y. chang , at ite taiwan: e-mail: p.y.chang@ite.com.tw , tel: 886-2-29126889 x6052, fax: 886-2-29102551 to find out more about ite, visit our world wide web at: http://www.ite.com.tw or e-mail itesupport@ite.com.tw for more product information/services free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 1 1 revision history section revision page no. 7 ? in section 7.5.4 alternate function selection, the followings were revised: 1. the ?output driving? of gpiob3-4 was revised to ? 4 ?. 2. the ?output driving? of gpioc1-2 was revised to ? 4 ? and gpioe7 was revised to ? 4 ?. 3. gpioe0-3 don?t support neit her ?pull-up? nor ?pull-down?. 4. the ?default pull? of gpioi7 was revised to ? up ?. 181 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 i contents contents 1. features ...................................................................................................................... ................................. 1 2. general desc ription ............................................................................................................ ........................... 3 3. system blo ck diagram........................................................................................................... ........................ 5 3.1 block diagram.................................................................................................................. ................... 5 3.2 host/ec mapped me mory space .................................................................................................... ... 6 3.3 ec mapped memo ry space......................................................................................................... ....... 9 3.4 register a bbrevia tion.......................................................................................................... .............. 10 4. pin config uration .............................................................................................................. ........................... 11 4.1 top vi ew ....................................................................................................................... .................... 11 5. pin descri ptions ............................................................................................................... ............................ 17 5.1 pin descri ptions ............................................................................................................... ................. 17 5.2 chip power planes and power states ............................................................................................. . 23 5.3 pin power plane s and states .................................................................................................... ....... 24 5.4 pwrfail# interru pt to intc .................................................................................................... ....... 28 5.5 reset source s and ty pes........................................................................................................ ......... 29 5.5.1 relative interr upts to intc................................................................................................... 29 5.6 chip power mode a nd clock domain ............................................................................................... 30 5.7 pins with pull, schmitt-trig ger or open-dra in function ................................................................... 34 5.8 power consumption consideration ................................................................................................ .. 35 6. host domain functions.......................................................................................................... ...................... 37 6.1 low pin count interf ace........................................................................................................ ............ 37 6.1.1 overview....................................................................................................................... ........ 37 6.1.2 features ....................................................................................................................... ........ 37 6.1.3 accepted lpc cycle type ................................................................................................... 37 6.1.4 debug port function ............................................................................................................ 38 6.1.5 serialized ir q (ser irq) ..................................................................................................... 39 6.1.6 relative interr upts to wuc................................................................................................... 39 6.1.7 lpcpd# and clkrun#....................................................................................................... 39 6.1.8 check items.................................................................................................................... ...... 39 6.2 plug and play config uration (p npcfg) ........................................................................................... 40 6.2.1 logical device assignment .................................................................................................. 42 6.2.2 super i/o configur ation registers ....................................................................................... 43 6.2.2.1 logical device nu mber (ldn)................................................................................. 43 6.2.2.2 chip id byte 1 (chipid1) ........................................................................................ 43 6.2.2.3 chip id byte 2 (chipid2) ........................................................................................ 43 6.2.2.4 chip versi on (chipver)......................................................................................... 43 6.2.2.5 super i/o control r egister (s ioctrl ) ................................................................... 43 6.2.2.6 super i/o irq configurat ion register (sioirq)..................................................... 44 6.2.2.7 super i/o general purpos e register (siogp)........................................................ 44 6.2.2.8 super i/o power mode register (siopwr) ........................................................... 44 6.2.3 standard logical device c onfiguration regist ers................................................................ 45 6.2.3.1 logical device activate register (lda)................................................................... 45 6.2.3.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 45 6.2.3.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 45 6.2.3.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 46 6.2.3.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 46 6.2.3.6 interrupt request number and wake -up on irq enable (irqnumx)................... 46 6.2.3.7 interrupt request ty pe select (irqtp) .................................................................. 46 6.2.3.8 dma channel sele ct 0 (dmas0) ............................................................................ 47 6.2.3.9 dma channel sele ct 0 (dmas1) ............................................................................ 47 6.2.4 system wake-up control (swuc) configurati on registers ............................................... 47 6.2.4.1 logical device activate register (lda)................................................................... 48 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 ii it8511 e /te/ g 6.2.4.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 48 6.2.4.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 48 6.2.4.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 48 6.2.4.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 48 6.2.4.6 interrupt request number and wake -up on irq enable (irqnumx)................... 48 6.2.4.7 interrupt request ty pe select (irqtp) .................................................................. 48 6.2.5 kbc / mouse interface co nfiguration registers .................................................................. 49 6.2.5.1 logical device activate register (lda)................................................................... 49 6.2.5.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 49 6.2.5.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 49 6.2.5.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 49 6.2.5.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 50 6.2.5.6 interrupt request number and wake -up on irq enable (irqnumx)................... 50 6.2.5.7 interrupt request ty pe select (irqtp) .................................................................. 50 6.2.6 kbc / keyboard interface c onfiguration registers.............................................................. 50 6.2.6.1 logical device activate register (lda)................................................................... 50 6.2.6.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 50 6.2.6.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 51 6.2.6.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 51 6.2.6.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 51 6.2.6.6 interrupt request number and wake -up on irq enable (irqnumx)................... 51 6.2.6.7 interrupt request ty pe select (irqtp) .................................................................. 51 6.2.7 shared memory/flash interface (s mfi) configuration registers ........................................ 51 6.2.7.1 logical device activate register (lda)................................................................... 52 6.2.7.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 52 6.2.7.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 52 6.2.7.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 52 6.2.7.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 52 6.2.7.6 interrupt request number and wake -up on irq enable (irqnumx)................... 52 6.2.7.7 interrupt request ty pe select (irqtp) .................................................................. 52 6.2.7.8 shared memory configur ation regist er (shmc) .................................................... 53 6.2.8 real time clock (rtc) co nfiguration registers ................................................................. 53 6.2.8.1 logical device activate register (lda)................................................................... 53 6.2.8.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 53 6.2.8.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 54 6.2.8.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 54 6.2.8.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 54 6.2.8.6 interrupt request number and wake -up on irq enable (irqnumx)................... 54 6.2.8.7 interrupt request ty pe select (irqtp) .................................................................. 54 6.2.8.8 ram lock register (rlr) ....................................................................................... 54 6.2.8.9 date of month alarm regi ster offset (domao) ..................................................... 55 6.2.8.10 month alarm register offset (monao) .................................................................. 55 6.2.8.11 p80l begin index (p80lb) ...................................................................................... 55 6.2.8.12 p80l end inde x (p80le)......................................................................................... 55 6.2.8.13 p80l current i ndex (p 80lc) ................................................................................... 55 6.2.9 power management i/f channel 1 configuratio n registers................................................ 56 6.2.9.1 logical device activate register (lda)................................................................... 56 6.2.9.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 56 6.2.9.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 56 6.2.9.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 56 6.2.9.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 57 6.2.9.6 interrupt request number and wake -up on irq enable (irqnumx)................... 57 6.2.9.7 interrupt request ty pe select (irqtp) .................................................................. 57 6.2.10 power management i/f channel 2 configuratio n registers................................................ 57 6.2.10.1 logical device activate register (lda)................................................................... 57 6.2.10.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ........................ 58 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 iii contents 6.2.10.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) ............................ 58 6.2.10.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ........................ 58 6.2.10.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) ............................ 58 6.2.10.6 i/o port base address bits [15:8] for descriptor 2 (iobad2[15:8]) ........................ 58 6.2.10.7 i/o port base address bits [7:0] for descriptor 2 (iobad2[7:0]) ............................ 58 6.2.10.8 interrupt request number and wake -up on irq enable (irqnumx)................... 59 6.2.10.9 interrupt request ty pe select (irqtp) .................................................................. 59 6.2.11 programming guide ............................................................................................................. 60 6.3 shared memory flash in terface brid ge (smfi) ................................................................................ 62 6.3.1 overview....................................................................................................................... ........ 62 6.3.2 features ....................................................................................................................... ........ 62 6.3.3 function desc ription........................................................................................................... .. 62 6.3.3.1 supported flash ...................................................................................................... 62 6.3.3.2 host to m bus translation ....................................................................................... 62 6.3.3.3 memory ma pping ..................................................................................................... 62 6.3.3.4 host-indirect me mory read/write transaction ....................................................... 63 6.3.3.5 ec-indirect memory r ead/write tran saction.......................................................... 63 6.3.3.6 locking between host and ec domains................................................................. 64 6.3.3.7 host access protection............................................................................................ 64 6.3.3.8 response to a fo rbidden access............................................................................ 64 6.3.3.9 scratch sram ......................................................................................................... 64 6.3.3.10 dma for scra tch sram ........................................................................................... 66 6.3.3.11 trusted rom/ram .................................................................................................. 66 6.3.3.12 flash programming via host lpc interface with scratch sram............................ 66 6.3.4 ec interface registers ......................................................................................................... 67 6.3.4.1 fbiu configuration register (fbcfg) .................................................................... 68 6.3.4.2 flash programming c onfiguration regi ster (fpcfg)............................................. 68 6.3.4.3 flash ec code banking sele ct register (fecbsr)............................................... 69 6.3.4.4 flash memory size sele ct register (fmssr) ........................................................ 70 6.3.4.5 shared memory ec control and status regist er (smeccs)................................. 71 6.3.4.6 shared memory host sem aphore register (smhsr) ............................................ 71 6.3.4.7 shared memory ec override read prot ect registers 0-1 (smecorpr0-1) ........ 72 6.3.4.8 shared memory ec override write pr otect registers 0-1 (smecowpr0-1) ....... 72 6.3.4.9 host control 2 regi ster (hctrl2r) ....................................................................... 72 6.3.4.10 trusted rom regi ster (tromr) ............................................................................ 73 6.3.4.11 ec-indirect memory addre ss register 0 (ecindar0) ........................................... 73 6.3.4.12 ec-indirect memory addre ss register 1 (ecindar1) ........................................... 73 6.3.4.13 ec-indirect memory addre ss register 2 (ecindar2) ........................................... 73 6.3.4.14 ec-indirect memory addre ss register 3 (ecindar3) ........................................... 73 6.3.4.15 ec-indirect memory data register (ecinddr)...................................................... 73 6.3.4.16 scratch sram 0 address low byte register (scar0l) ........................................ 74 6.3.4.17 scratch sram 0 address middl e byte register (scar0m) ................................... 74 6.3.4.18 scratch sram 0 address high byte register (scar0h)....................................... 74 6.3.4.19 scratch sram 1 address low byte register (scar1l) ........................................ 74 6.3.4.20 scratch sram 1 address middl e byte register (scar1m) ................................... 74 6.3.4.21 scratch sram 1 address high byte register (scar1h)....................................... 74 6.3.4.22 scratch sram 2 address low byte register (scar2l) ........................................ 75 6.3.4.23 scratch sram 2 address middl e byte register (scar2m) ................................... 75 6.3.4.24 scratch sram 2 address high byte register (scar2h)....................................... 75 6.3.4.25 scratch sram 3 address low byte register (scar3l) ........................................ 75 6.3.4.26 scratch sram 3 address middl e byte register (scar3m) ................................... 75 6.3.4.27 scratch sram 3 address high byte register (scar3h)....................................... 75 6.3.4.28 scratch sram 4 address low byte register (scar4l) ........................................ 76 6.3.4.29 scratch sram 4 address middl e byte register (scar4m) ................................... 76 6.3.4.30 scratch sram 4 address high byte register (scar4h)....................................... 76 6.3.5 host interfac e registers....................................................................................................... 76 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 iv it8511 e /te/ g 6.3.5.1 shared memory indirect memory address register 0 (smimar0) ........................ 76 6.3.5.2 shared memory indirect memory address register 1 (smimar1) ........................ 77 6.3.5.3 shared memory indirect memory address register 2 (smimar2) ........................ 77 6.3.5.4 shared memory indirect memory address register 3 (smimar3) ........................ 77 6.3.5.5 shared memory indirect memo ry data regist er (smimdr) ................................... 77 6.3.5.6 shared memory host sem aphore register (smhsr) ............................................ 77 6.3.5.7 m-bus control regi ster (mbctrl) ......................................................................... 78 6.4 system wake-up control (swuc) .................................................................................................. . 79 6.4.1 overview....................................................................................................................... ........ 79 6.4.2 features ....................................................................................................................... ........ 79 6.4.3 functional de script ion......................................................................................................... . 79 6.4.3.1 wake-up status....................................................................................................... 79 6.4.3.2 wake-up events...................................................................................................... 80 6.4.3.3 wake-up out put events .......................................................................................... 81 6.4.3.4 other swuc cont rolled op tions............................................................................. 81 6.4.4 host interfac e registers....................................................................................................... 83 6.4.4.1 wake-up event status register (wkstr) ............................................................. 83 6.4.4.2 wake-up event enable register (wker)............................................................... 84 6.4.4.3 wake-up signals monito r register (wksm r) ........................................................ 84 6.4.4.4 wake-up acpi status register (wkacpir) .......................................................... 85 6.4.4.5 wake-up smi enable re gister (w ksmier) ........................................................... 85 6.4.4.6 wake-up irq enable re gister (wk irqer) ........................................................... 86 6.4.5 ec interface registers ......................................................................................................... 86 6.4.5.1 swuc control status 1 register (swct l1) .......................................................... 86 6.4.5.2 swuc control status 2 register (swct l2) .......................................................... 87 6.4.5.3 swuc control status 3 register (swct l3) .......................................................... 88 6.4.5.4 swuc host configuratio n base address low byte register (swcbalr)............ 88 6.4.5.5 swuc host configuratio n base address high by te register (swcbahr) .......... 88 6.4.5.6 swuc interrupt enable register (swcier)........................................................... 88 6.4.5.7 swuc host event status register (swchstr).................................................... 89 6.4.5.8 swuc host event interrupt enable register (swchier) ..................................... 90 6.5 keyboard contro ller (kbc) ...................................................................................................... ......... 91 6.5.1 overview....................................................................................................................... ........ 91 6.5.2 features ....................................................................................................................... ........ 91 6.5.3 functional de script ion......................................................................................................... . 91 6.5.4 host interfac e registers....................................................................................................... 92 6.5.4.1 kbc data input r egister (k bdir)........................................................................... 93 6.5.4.2 kbc data output r egister ( kbdor) ...................................................................... 93 6.5.4.3 kbc command regi ster (kbcmdr) ...................................................................... 93 6.5.4.4 kbc status regi ster (kbstr) ................................................................................ 93 6.5.5 ec interface registers ......................................................................................................... 94 6.5.5.1 kbc host interface cont rol register (kbh icr)...................................................... 94 6.5.5.2 kbc interrupt control register (kbirqr)............................................................... 95 6.5.5.3 kbc host interface keyboard/mou se status register (kbhisr)........................... 96 6.5.5.4 kbc host interface keyboard data output register (kbhikdor) ........................ 96 6.5.5.5 kbc host interface mouse data output register (kbhimdor) ............................ 96 6.5.5.6 kbc host interface keyb oard/mouse data input register (kbhidir) ................... 97 6.6 power management channel (pmc) ................................................................................................ 98 6.6.1 overview....................................................................................................................... ........ 98 6.6.2 features ....................................................................................................................... ........ 98 6.6.3 functional de script ion......................................................................................................... . 98 6.6.3.1 general desc ription ................................................................................................. 98 6.6.3.2 compatible mode..................................................................................................... 99 6.6.3.3 enhanced pm mode .............................................................................................. 100 6.6.3.4 pmc2ex ................................................................................................................ 101 6.6.4 host interfac e registers..................................................................................................... 102 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 v contents 6.6.4.1 pmc data input r egister (pmdir)........................................................................ 102 6.6.4.2 pmc data output r egister (pmdor) ................................................................... 103 6.6.4.3 pmc command regist er (pmcmdr) ................................................................... 103 6.6.4.4 status regist er (pmstr) ...................................................................................... 103 6.6.5 ec interface registers ....................................................................................................... 104 6.6.5.1 pm status regi ster (pmsts)................................................................................ 104 6.6.5.2 pm data out port (pmdo) .................................................................................... 105 6.6.5.3 pm data out port wi th sci (pmdosci)................................................................ 105 6.6.5.4 pm data out port wi th smi (pmdosmi)............................................................... 105 6.6.5.5 pm data in port (pmdi)......................................................................................... 106 6.6.5.6 pm data in port wi th sci (pmdisci) .................................................................... 106 6.6.5.7 pm control (pmctl) ............................................................................................. 106 6.6.5.8 pm interrupt c ontrol (p mic).................................................................................. 107 6.6.5.9 pm interrupt enable (p mie) .................................................................................. 107 6.6.5.10 pm interrupt enable (p mie) .................................................................................. 108 6.6.5.11 16-byte pmc2ex mailbox 0-15 (mbxec0-15)...................................................... 108 6.7 trusted mobile kbc (tmk bc)..................................................................................................... ... 109 6.7.1 overview....................................................................................................................... ...... 109 6.7.2 features ....................................................................................................................... ...... 109 6.7.3 functional de script ion........................................................................................................ 109 6.7.4 host interfac e registers..................................................................................................... 109 6.7.4.1 tmkbc vendor id r egister (tvendid) ............................................................... 109 6.7.4.2 tmkbc device id r egister (tdevid) .................................................................. 110 6.7.4.3 tmkbc version re gister (tver) ......................................................................... 110 6.7.4.4 generic capabilities re porting regist er (cap) .................................................... 110 6.7.4.5 tmkbc revision id r egister (trevid)................................................................ 110 6.7.4.6 configuration r egister (cnf) ................................................................................ 111 6.7.4.7 control regist er (cnt) .......................................................................................... 111 6.7.4.8 irq capabilities reportin g register (irqcap) .................................................... 112 6.7.4.9 status regist er (sts)............................................................................................ 112 6.7.4.10 extended status regi ster (extsts) .................................................................... 112 6.7.4.11 interrupt trigger enable register (inttrig) ........................................................ 113 6.7.4.12 tmkbc data input r egister (t datin).................................................................. 113 6.7.4.13 tmkbc data output r egister (tdatout)........................................................... 113 6.7.5 ec interface registers ....................................................................................................... 114 6.7.5.1 ec side configuration register (eccon) ............................................................ 114 6.7.5.2 status control r egister (s tscon) ....................................................................... 114 6.7.5.3 ec data input r egister (e datin) ......................................................................... 115 6.7.5.4 ec data output r egister (edatout) .................................................................. 115 6.7.5.5 ec buffer status re gister (ebufsts) ................................................................. 115 6.7.5.6 ec status regi ster (ests) ................................................................................... 115 6.7.5.7 ec vendor id low register (evenl) ................................................................... 116 6.7.5.8 ec vendor id high register (evenh).................................................................. 116 6.7.5.9 ec device id low register (edevl).................................................................... 116 6.7.5.10 ec device id high register (edevh) .................................................................. 116 6.7.5.11 ec version low r egister (everl) ....................................................................... 116 6.7.5.12 ec version high re gister (everh)...................................................................... 117 6.7.5.13 ec revision id re gister (e revid) ....................................................................... 117 6.8 real-time cl ock (rtc).......................................................................................................... ......... 118 6.8.1 overview....................................................................................................................... ...... 118 6.8.2 feature ........................................................................................................................ ....... 118 6.8.3 functional de script ion........................................................................................................ 118 6.8.3.1 timek eeping .......................................................................................................... 118 6.8.3.2 update cycles ....................................................................................................... 118 6.8.3.3 interrupts................................................................................................................ 118 6.8.3.4 p80l ...................................................................................................................... 119 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 vi it8511 e /te/ g 6.8.4 host interfac e registers..................................................................................................... 119 6.8.4.1 rtc bank 0 register............................................................................................. 121 6.8.4.1.1 seconds register (secreg) ....................................................... 121 6.8.4.1.2 seconds alarm 1 regi ster (seca1reg) ...................................... 121 6.8.4.1.3 minutes regist er (minreg) ......................................................... 122 6.8.4.1.4 minutes alarm 1 register (mina1reg) ........................................ 122 6.8.4.1.5 hours register (hrreg)............................................................... 122 6.8.4.1.6 hours alarm 1 regi ster (hra1reg)............................................. 122 6.8.4.1.7 day of week regi ster (d owreg) ............................................... 122 6.8.4.1.8 date of month r egister (domreg).............................................. 123 6.8.4.1.9 month register (monreg) ........................................................... 123 6.8.4.1.10 year regist er (y rreg) ................................................................. 123 6.8.4.1.11 rtc control regist er a (ctlrega)............................................. 123 6.8.4.1.12 rtc control regist er b (ctlregb)............................................. 124 6.8.4.1.13 rtc control regist er c (ctlregc) ............................................ 125 6.8.4.1.14 rtc control regist er d (ctlregd) ............................................ 126 6.8.4.1.15 date of month alarm 1 register (doma1reg)............................. 126 6.8.4.1.16 month alarm 1 regi ster (mona1reg) ......................................... 126 6.8.4.2 rtc bank 1 register............................................................................................. 126 6.8.4.2.1 seconds alarm 2 regi ster (seca2reg) ...................................... 126 6.8.4.2.2 minutes alarm 2 register (mina2reg) ........................................ 126 6.8.4.2.3 hours alarm 2 regi ster (hra2reg)............................................. 127 6.8.4.2.4 date of month alarm 2 register (doma2reg)............................. 127 6.8.4.2.5 month alarm 2 regi ster (mona2reg) ......................................... 127 6.8.4.3 rtc i/o register ................................................................................................... 127 6.8.4.3.1 rtc index register of bank 0 (rirb0) ......................................... 127 6.8.4.3.2 rtc data register of bank 0 (rdrb0)......................................... 127 6.8.4.3.3 rtc index register of bank 1 (rirb1) ......................................... 128 6.8.4.3.4 rtc data register of bank 1 (rdrb1)......................................... 128 7. ec domain functions ............................................................................................................ .................... 131 7.1 8032 embedded cont roller (ec).................................................................................................. ... 131 7.1.1 overview....................................................................................................................... ...... 131 7.1.2 features ....................................................................................................................... ...... 131 7.1.3 general desc ription............................................................................................................ 131 7.1.4 functional de script ion....................................................................................................... 131 7.1.5 memory organization ......................................................................................................... 132 7.1.6 on-chip pe ripherals........................................................................................................... 133 7.1.7 timer / counter................................................................................................................ ... 135 7.1.8 idle and doze /sleep mode ................................................................................................. 144 7.1.9 ec internal regist er description ........................................................................................ 144 7.1.9.1 port 0 regist er (p0r) ............................................................................................ 145 7.1.9.2 stack pointer r egister (spr) ................................................................................ 145 7.1.9.3 data pointer low register (dplr)........................................................................ 145 7.1.9.4 data pointer high register (dphr) ...................................................................... 145 7.1.9.5 data pointer 1 low register (dp1lr)................................................................... 145 7.1.9.6 data pointer 1 high register (dp1hr) ................................................................. 145 7.1.9.7 data pointer select register (dpsr).................................................................... 145 7.1.9.8 power control r egister (pco n)............................................................................ 146 7.1.9.9 timer control r egister (tcon)............................................................................. 146 7.1.9.10 timer mode regi ster (tmod) ............................................................................... 147 7.1.9.11 timer 0 low byte register (tl0r) ........................................................................ 147 7.1.9.12 timer 1 low byte register (tl1r) ........................................................................ 147 7.1.9.13 timer 0 high byte register (th0r)....................................................................... 147 7.1.9.14 timer 1 low byte register (th1r) ....................................................................... 148 7.1.9.15 clock control regi ster (ckcon) .......................................................................... 148 7.1.9.16 port 1 regist er (p1r) ............................................................................................ 148 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 vii contents 7.1.9.17 serial port contro l register (sco n) ..................................................................... 149 7.1.9.18 serial port buffer register (sbufr) ..................................................................... 149 7.1.9.19 port 2 regist er (p2r) ............................................................................................ 149 7.1.9.20 interrupt enable register (ie)................................................................................ 150 7.1.9.21 port 3 regist er (p3r) ............................................................................................ 150 7.1.9.22 interrupt priority register (ip)................................................................................ 151 7.1.9.23 status register (status) ................................................................................... 151 7.1.9.24 timer 2 control r egister (t2con)........................................................................ 151 7.1.9.25 timer mode regist er (t2mod) ............................................................................. 152 7.1.9.26 timer 2 capture low byte register (rcap2lr) .................................................. 152 7.1.9.27 timer 2 capture high byte register (rcap2hr)................................................. 152 7.1.9.28 timer 2 low byte register (tl2r) ........................................................................ 152 7.1.9.29 timer 2 high byte register (th2r)....................................................................... 153 7.1.9.30 program status word register (psw) .................................................................. 153 7.1.9.31 watch dog timer contro l register (wdtcon).................................................... 153 7.1.9.32 accumulator regi ster (acc) ................................................................................. 154 7.1.9.33 b register (b r)...................................................................................................... 154 7.1.10 programming guide ........................................................................................................... 154 7.1.10.1 code snippet of enteri ng idle/doze/sleep mode.................................................. 154 7.1.10.2code snippet of copying flash cont ent to scratch rom 4 (movc-movx by pio) .............................................................................................................................. ........... .............................................................................................................................. ..... 155 7.1.10.3 code snippet of copying flash content to scratch rom (dma) ......................... 156 7.2 interrupt cont roller (intc) .................................................................................................... .......... 157 7.2.1 overview....................................................................................................................... ...... 157 7.2.2 features ....................................................................................................................... ...... 157 7.2.3 functional de script ion........................................................................................................ 157 7.2.3.1 power fail interrupt ............................................................................................... 157 7.2.3.2 rom match interrupt ............................................................................................. 157 7.2.3.3 programmable interrupts ....................................................................................... 157 7.2.4 ec interface registers ....................................................................................................... 158 7.2.4.1 interrupt status r egister 0 (isr0) ......................................................................... 159 7.2.4.2 interrupt status r egister 1 (isr1) ......................................................................... 159 7.2.4.3 interrupt status r egister 2 (isr2) ......................................................................... 160 7.2.4.4 interrupt status r egister 3 (isr3) ......................................................................... 160 7.2.4.5 interrupt enable re gister 0 (ier0) ........................................................................ 160 7.2.4.6 interrupt enable re gister 1 (ier1) ........................................................................ 161 7.2.4.7 interrupt enable re gister 2 (ier2) ........................................................................ 161 7.2.4.8 interrupt enable re gister 3 (ier3) ........................................................................ 161 7.2.4.9 interrupt edge/level-triggere d mode register 0 (ielmr0).................................. 161 7.2.4.10 interrupt edge/level-triggere d mode register 1 (ielmr1).................................. 162 7.2.4.11 interrupt edge/level-triggere d mode register 2 (ielmr2).................................. 162 7.2.4.12 interrupt edge/level-triggere d mode register 3 (ielmr3).................................. 162 7.2.4.13 interrupt polarity r egister 0 (ipolr0)................................................................... 162 7.2.4.14 interrupt polarity r egister 1 (ipolr1)................................................................... 163 7.2.4.15 interrupt polarity r egister 2 (ipolr2)................................................................... 163 7.2.4.16 interrupt polarity r egister 3 (ipolr3)................................................................... 163 7.2.4.17 interrupt vector register (ivct)............................................................................ 163 7.2.4.18 8032 int0# status (int0st)................................................................................. 164 7.2.4.19 power fail regist er (pfailr) ............................................................................... 164 7.2.5 intc interrupt assignments ............................................................................................... 165 7.2.6 programming guide ........................................................................................................... 167 7.3 wake-up cont rol (wuc) .......................................................................................................... ...... 168 7.3.1 overview....................................................................................................................... ...... 168 7.3.2 features ....................................................................................................................... ...... 168 7.3.3 functional de script ion........................................................................................................ 168 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 viii it8511 e /te/ g 7.3.4 ec interface registers ....................................................................................................... 168 7.3.4.1 wake-up edge mode r egister (wuemr1) .......................................................... 168 7.3.4.2 wake-up edge mode r egister (wuemr2) .......................................................... 169 7.3.4.3 wake-up edge mode r egister (wuemr3) .......................................................... 169 7.3.4.4 wake-up edge mode r egister (wuemr4) .......................................................... 169 7.3.4.5 wake-up edge sense re gister (wuesr1).......................................................... 169 7.3.4.6 wake-up edge sense re gister (wuesr2).......................................................... 170 7.3.4.7 wake-up edge sense re gister (wuesr3).......................................................... 170 7.3.4.8 wake-up edge sense re gister (wuesr4).......................................................... 170 7.3.4.9 wake-up enable regi ster (wuenr1) .................................................................. 171 7.3.4.10 wake-up enable regi ster (wuenr2) .................................................................. 171 7.3.4.11 wake-up enable regi ster (wuenr3) .................................................................. 171 7.3.4.12 wake-up enable regi ster (wuenr4) .................................................................. 171 7.3.5 wuc input a ssignment s .................................................................................................... 172 7.3.6 programming guide ........................................................................................................... 173 7.4 keyboard matrix scan cont roller ................................................................................................ .... 174 7.4.1 overview....................................................................................................................... ...... 174 7.4.2 features ....................................................................................................................... ...... 174 7.4.3 ec interface registers ....................................................................................................... 174 7.4.3.1 keyboard scan out low byte data regist er (ksol) ........................................... 174 7.4.3.2 keyboard scan out high byte data 1 regist er (ksoh1)..................................... 174 7.4.3.3 keyboard scan out control register (k soctrl)................................................ 174 7.4.3.4 keyboard scan out high byte data 2 regist er (ksoh2)..................................... 175 7.4.3.5 keyboard scan in data register (ksir) ............................................................... 175 7.4.3.6 keyboard scan in control register ( ksictrlr).................................................. 175 7.5 general purpose i/o port (gpio) ................................................................................................ ... 176 7.5.1 overview....................................................................................................................... ...... 176 7.5.2 features ....................................................................................................................... ...... 176 7.5.3 ec interface registers ....................................................................................................... 176 7.5.3.1 general control r egister (gcr) ........................................................................... 176 7.5.3.2 port data registers a-m (gpdra -gpdrm)......................................................... 177 7.5.3.3 port data mirror regist ers a-m (gpdmr a-gpdmrm) ........................................ 177 7.5.3.4 port control n register s (gpcrn, n = a0-i7)........................................................ 178 7.5.3.5 output type registers a-i (gpota -gpoti)......................................................... 180 7.5.4 alternate function selection .............................................................................................. 181 7.5.5 programming guide ........................................................................................................... 186 7.6 ec clock and power mana gement contro ller (e cpm) .................................................................. 187 7.6.1 overview....................................................................................................................... ...... 187 7.6.2 features ....................................................................................................................... ...... 187 7.6.3 ec interface registers ....................................................................................................... 187 7.6.3.1 clock frequency select register (cfselr) ........................................................ 187 7.6.3.2 clock gating control 1 register (cgctrl1r) ..................................................... 187 7.6.3.3 clock gating control 2 register (cgctrl2r) ..................................................... 188 7.6.3.4 clock gating control 3 register (cgctrl3r) ..................................................... 189 7.6.3.5 pll control (pllctrl) ........................................................................................ 189 7.6.3.6 auto clock gating (autocg)............................................................................... 189 7.7 sm bus interf ace (s mb) ......................................................................................................... ........ 191 7.7.1 overview....................................................................................................................... ...... 191 7.7.2 features ....................................................................................................................... ...... 191 7.7.3 functional de script ion........................................................................................................ 191 7.7.3.1 smbus master interface....................................................................................... 191 7.7.3.2 smbus porti ng guide ........................................................................................... 192 7.7.4 ec interface registers ....................................................................................................... 196 7.7.4.1 host status register (hosta).............................................................................. 196 7.7.4.2 host control regi ster (hoctl)............................................................................. 197 7.7.4.3 host command regi ster (hocmd) ...................................................................... 198 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 ix contents 7.7.4.4 transmit slave addres s register (trasla) ........................................................ 198 7.7.4.5 data 0 regist er (d0reg)...................................................................................... 198 7.7.4.6 data 1 regist er (d1reg)...................................................................................... 198 7.7.4.7 host block data byte register (hobdb) .............................................................. 198 7.7.4.8 packet error check register (pecerc)............................................................... 199 7.7.4.9 smbus pin control r egister (smbpctl) ............................................................ 199 7.7.4.10 host control regi ster 2 (h octl2)........................................................................ 199 7.7.4.11 4.7 s low register (4p7usl) .............................................................................. 200 7.7.4.12 4.0 s low register (4p0usl) .............................................................................. 200 7.7.4.13 300 ns register (300nsreg) ............................................................................... 200 7.7.4.14 250 ns register (250nsreg) ............................................................................... 200 7.7.4.15 25 ms register (25msreg).................................................................................. 200 7.7.4.16 45.3 s low register (45p3uslreg) .................................................................. 201 7.7.4.17 45.3 s high register (45p3ushreg)................................................................. 201 7.7.4.18 4.7 s and 4.0 s high register (4p7a4p0h) ....................................................... 201 7.8 ps/2 inte rface ................................................................................................................. ................ 202 7.8.1 overview....................................................................................................................... ...... 202 7.8.2 features ....................................................................................................................... ...... 202 7.8.3 functional de script ion........................................................................................................ 202 7.8.3.1 hardware mo de selected ...................................................................................... 202 7.8.3.2 software mode selected ....................................................................................... 203 7.8.4 ec interface registers ....................................................................................................... 203 7.8.4.1 ps/2 control register 1-4 (psctl1-4) ................................................................. 203 7.8.4.2 ps/2 interrupt control r egister 1-4 (psint1-4).................................................... 204 7.8.4.3 ps/2 status register 1-4 (psst s1-4)................................................................... 204 7.8.4.4 ps/2 data register 1-4 (psd at1-4) ..................................................................... 205 7.9 digital to analog converter (dac).............................................................................................. ... 206 7.9.1 overview....................................................................................................................... ...... 206 7.9.2 feature ........................................................................................................................ ....... 206 7.9.3 functional de script ion........................................................................................................ 206 7.9.4 ec interface registers ....................................................................................................... 206 7.9.4.1 dac control regist er (dacctrl)........................................................................ 206 7.9.4.2 dac data channel 0~3 re gister (dacdat0~3) .................................................. 207 7.9.4.3 dac power down register (dacpdreg) ........................................................... 207 7.10 analog to digital converter (adc) .............................................................................................. .... 208 7.10.1 overview....................................................................................................................... ...... 208 7.10.2 features ....................................................................................................................... ...... 208 7.10.3 functional de script ion........................................................................................................ 208 7.10.3.1 adc general descrip tion ...................................................................................... 209 7.10.3.2 voltage measurement and automati c hardware ca libration ................................ 209 7.10.3.3 adc oper ation ...................................................................................................... 210 7.10.4 ec interface registers ....................................................................................................... 211 7.10.4.1 adc status regi ster (adcsts) ........................................................................... 211 7.10.4.2 adc configuration r egister (adccfg)................................................................ 212 7.10.4.3 adc clock control r egister (adcctl) ................................................................ 213 7.10.4.4 voltage channel 0 control register (v ch0ctl) .................................................. 213 7.10.4.5 calibration data contro l register (kdctl) .......................................................... 214 7.10.4.6 voltage channel 1 control register (v ch1ctl) .................................................. 215 7.10.4.7 volt channel 1 data buffer lsb (vch1datl)...................................................... 215 7.10.4.8 volt channel 1 data buffer msb (v ch1datm).................................................... 215 7.10.4.9 voltage channel 2 control register (v ch2ctl) .................................................. 216 7.10.4.10 volt channel 2 data buffer lsb (vch2datl)...................................................... 216 7.10.4.11 volt channel 2 data buffer msb (v ch2datm).................................................... 216 7.10.4.12 voltage channel 3 control register (v chn3ctl) ............................................... 216 7.10.4.13 volt channel 3 data buffer lsb (vch3datl)...................................................... 217 7.10.4.14 volt channel 3 data buffer msb (v ch3datm).................................................... 217 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 x it8511 e /te/ g 7.10.4.15 volt high scale calibration data buffer l sb (vhscdbl) .................................... 217 7.10.4.16 volt high scale calibration data buffer m sb (vhscdbm) .................................. 217 7.10.4.17 voltage channel 0 data buffer lsb (vch0datl)................................................ 218 7.10.4.18 voltage channel 0 data buffer msb (v ch0datm).............................................. 218 7.10.4.19 volt high scale gain-error calibra tion data buffer lsb (vhsgcdbl) ............... 218 7.10.4.20 volt high scale gain-error calibra tion data buffer msb (vhsgcdbm) ............. 218 7.10.5 adc programmi ng guide................................................................................................... 219 7.11 pwm and smartauto fa n control (pwm) ...................................................................................... 222 7.11.1 overview....................................................................................................................... ...... 222 7.11.2 features ....................................................................................................................... ...... 222 7.11.3 functional de script ion........................................................................................................ 222 7.11.3.1 general desc ription ............................................................................................... 222 7.11.3.2 cr256 descri ption................................................................................................. 224 7.11.3.3 how to decide cr256 duty time.......................................................................... 224 7.11.3.4 how to progra m cr256 pwm............................................................................... 225 7.11.3.5 smartauto fan control mode................................................................................ 226 7.11.3.6 manual fan c ontrol mode ..................................................................................... 228 7.11.4 ec interface registers ....................................................................................................... 229 7.11.4.1 channel 0 clock prescale r register (c0cprs) ................................................... 229 7.11.4.2 cycle time regi ster (ctr) ................................................................................... 230 7.11.4.3 pwm duty cycle regi ster 0 to 7(dcri) ................................................................ 230 7.11.4.4 pwm polarity regi ster (p wmpol) ....................................................................... 230 7.11.4.5 prescaler clock frequency se lect register (pcfsr) .......................................... 231 7.11.4.6 prescaler clock source se lect group low (pcssgl) ......................................... 231 7.11.4.7 prescaler clock source se lect group hi gh (pcssgh)........................................ 232 7.11.4.8 cr256 prescaler clock source select gr oup (cr256pcssg) ........................... 232 7.11.4.9 prescaler clock source ga ting register (pcsgr)............................................... 233 7.11.4.10 fan 1 configuration re gister (fan1cnf)............................................................. 233 7.11.4.11 fan 2 configuration re gister (fan2cnf)............................................................. 234 7.11.4.12 smartauto fan minimum-region sp eed range regist er (afmisrr) .................. 235 7.11.4.13 smartauto fan maximum-region s peed range register (afmasrr)................ 236 7.11.4.14 min/off pwm limit register (mopl)..................................................................... 237 7.11.4.15 fan 1 minimum pwm duty cy cle register (f1mpdcr) ...................................... 237 7.11.4.16 fan 2 minimum pwm duty cy cle register (f2mpdcr) ...................................... 237 7.11.4.17 fan 1 temperature limit register (f1tlimitr) ................................................. 238 7.11.4.18 fan 2 temperature limit register (f2tlimitr) ................................................. 238 7.11.4.19 fan 1 absolute temperature li mit register (f1atlimitr) ................................ 238 7.11.4.20 fan 2 absolute temperature li mit register (f2atlimitr) ................................ 239 7.11.4.21 zone hysteresis r egister (z hysr)....................................................................... 239 7.11.4.22 fan 1 temperature record register (f1trr)...................................................... 239 7.11.4.23 fan 2 temperature record register (f2trr)...................................................... 240 7.11.4.24 fan 1 tachometer lsb readi ng register (f1tlrr) ........................................... 240 7.11.4.25 fan 1 tachometer msb readi ng register (f1tmrr) ......................................... 240 7.11.4.26 fan 2 tachometer lsb readi ng register (f2tlrr) ........................................... 240 7.11.4.27 fan 2 tachometer msb readi ng register (f2tmrr) ......................................... 240 7.11.4.28 zone interrupt status cont rol register (zintscr)............................................... 241 7.11.4.29 zone temperature interrupt enable register (ztier).......................................... 241 7.11.4.30 channel 4 clock prescale r register (c4cprs) ................................................... 242 7.11.4.31 channel 4 clock prescaler msb register (c4mcprs)........................................ 242 7.11.4.32 channel 6 clock prescale r register (c6cprs) ................................................... 242 7.11.4.33 channel 6 clock prescaler msb register (c6mcprs)........................................ 243 7.11.4.34 channel 7 clock prescale r register (c7cprs) ................................................... 243 7.11.4.35 channel 7 clock prescaler msb register (c7mcprs)........................................ 243 7.11.4.36 fan 1 temperature criterion register 1-3 (f1tc1-3)........................................... 244 7.11.4.37 fan 2 temperature criterio n register 1-3(f2tc1-3)............................................ 244 7.11.4.38 fan 1 pwm duty cycle criterio n register 1- 3(f1pdc1-3) .................................. 244 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xi contents 7.11.4.39 fan 2 pwm duty cycle criterio n register 1- 3(f2pdc1-3) .................................. 244 7.11.5 pwm programmi ng guide ................................................................................................. 245 7.12 ec access to host contro lled modules (e c2i bridge) ................................................................... 248 7.12.1 overview....................................................................................................................... ...... 248 7.12.2 features ....................................................................................................................... ...... 248 7.12.3 functional de script ion........................................................................................................ 248 7.12.4 ec interface registers ....................................................................................................... 248 7.12.4.1 indirect host i/o addr ess register (ihioa)........................................................... 249 7.12.4.2 indirect host data register (ihd).......................................................................... 249 7.12.4.3 lock super i/o host acce ss register (lsioha) .................................................. 249 7.12.4.4 super i/o access lock viol ation register (siolv)............................................... 250 7.12.4.5 ec to i-bus modules access enable regist er (ibmae)........................................ 250 7.12.4.6 i-bus control regi ster (ibctl).............................................................................. 250 7.12.5 ec2i progra mming guide .................................................................................................. 252 7.13 external timer and exte rnal watchdo g (etw d) ............................................................................ 254 7.13.1 overview....................................................................................................................... ...... 254 7.13.2 features ....................................................................................................................... ...... 254 7.13.3 functional de script ion........................................................................................................ 254 7.13.3.1 external time r operation ...................................................................................... 254 7.13.3.2 external wdt operation ....................................................................................... 255 7.13.4 ec interface registers ....................................................................................................... 255 7.13.4.1 external timer/wdt configur ation register (etwcfg) ...................................... 255 7.13.4.2 external timer prescale r register (etpsr) ......................................................... 256 7.13.4.3 external timer counter high byte (e tcntlhr) .................................................. 256 7.13.4.4 external timer counter low byte (etcntllr) ................................................... 256 7.13.4.5 external timer/wdt contro l register (etwctrl) .............................................. 256 7.13.4.6 external wdt counter hi gh byte (ewdcntlhr) ............................................... 257 7.13.4.7 external wdt low co unter (ew dcntllr) ......................................................... 257 7.13.4.8 external wdt key r egister (e wdkeyr) ............................................................. 257 7.13.4.9 reset scratch regi ster (rstscr) ....................................................................... 257 7.14 general contro l (gctrl) ........................................................................................................ ....... 259 7.14.1 overview....................................................................................................................... ...... 259 7.14.2 features ....................................................................................................................... ...... 259 7.14.3 functional de script ion........................................................................................................ 259 7.14.4 ec interface registers ....................................................................................................... 259 7.14.4.1 chip id byte 1 (echip id1) ................................................................................... 259 7.14.4.2 chip id byte 2 (echip id2) ................................................................................... 260 7.14.4.3 chip version (echipver) .................................................................................... 260 7.14.4.4 identify input r egister (idr) .................................................................................. 260 7.14.4.5 reset status (rsts) ............................................................................................. 260 7.14.4.6 reset control 1 (rstc1) ...................................................................................... 261 7.14.4.7 reset control 2 (rstc2) ...................................................................................... 261 7.14.4.8 reset control 3 (rstc3) ...................................................................................... 262 7.14.4.9 wait next clo ck rising (wnck r) ......................................................................... 262 7.14.4.10 oscillator control r egister (o sctrl)................................................................... 262 7.14.4.11 special contro l 1 (spc trl1)................................................................................ 262 7.14.4.12 reset control host side (rstch) ........................................................................ 263 7.15 battery-backed sram (b ram)..................................................................................................... .. 265 7.15.1 overview....................................................................................................................... ...... 265 7.15.2 features ....................................................................................................................... ...... 265 7.15.3 functional de script ion........................................................................................................ 265 7.15.3.1 p80l ...................................................................................................................... 265 7.15.4 ec interface registers ....................................................................................................... 266 7.15.4.1 sram byte n registers (sbtn, n= 0-255). ........................................................... 266 7.16 consumer ir (cir) .............................................................................................................. ........... 267 7.16.1 overview....................................................................................................................... ...... 267 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xii it8511 e /te/ g 7.16.2 features ....................................................................................................................... ...... 267 7.16.3 functional de script ion........................................................................................................ 267 7.16.3.1 transmit operation ................................................................................................ 268 7.16.3.2 receive operation ................................................................................................. 268 7.16.3.3 wakeup(power on) controller progra mming sequence ...................................... 268 7.16.4 ec interface registers ....................................................................................................... 269 7.16.4.1 cir data regi ster (c0dr) .................................................................................... 269 7.16.4.2 cir master control r egister (c0mstcr)............................................................. 270 7.16.4.3 cir interrupt enable register (c0ier) ................................................................. 270 7.16.4.4 cir interrupt identificat ion register (c0iir).......................................................... 271 7.16.4.5 cir carrier frequency register (c0cfr)............................................................. 271 7.16.4.6 cir receiver control register (c0rcr) .............................................................. 273 7.16.4.7 cir transmitter contro l register (c0tcr)........................................................... 275 7.16.4.8 cir slow clock contro l register (c0sck) ........................................................... 276 7.16.4.9 cir baud rate divisor low byte register (c0bdlr) .......................................... 277 7.16.4.10 cir baud rate divisor high byte regist er (c0b dhr) ......................................... 277 7.16.4.11 cir transmitter fifo stat us register (c0tfsr)................................................. 277 7.16.4.12 cir receiver fifo stat us register (c0rfsr) .................................................... 278 7.16.4.13 cir wakeup code length register (c0wcl) ...................................................... 278 7.16.4.14 cir wakeup code read/write register (c0wcr) .............................................. 278 7.16.4.15 cir wakeup power co ntrol/status regi ster (c0wps) ........................................ 279 7.17 debugger (dbgr)................................................................................................................ ........... 280 7.17.1 overview....................................................................................................................... ...... 280 7.17.2 features ....................................................................................................................... ...... 280 7.17.3 functional de script ion........................................................................................................ 280 7.17.3.1 rom address ma tch inte rrupt............................................................................... 280 7.17.3.2 ec memory snoop (e cms) .................................................................................. 280 7.17.4 ec interface registers ....................................................................................................... 281 7.17.4.1 trigger 1 address low by te register (bka1l) ..................................................... 281 7.17.4.2 trigger 1 address middle byte register (bka1m) ................................................ 281 7.17.4.3 trigger 1 address high by te register (bka1 h).................................................... 281 7.17.4.4 trigger 2 address low by te register (bka2l) ..................................................... 281 7.17.4.5 trigger 2 address middle byte register (bka2m) ................................................ 281 7.17.4.6 trigger 2 address high by te register (bka2 h).................................................... 282 7.17.4.7 trigger 3 address low by te register (bka3l) ..................................................... 282 7.17.4.8 trigger 3 address middle byte register (bka3m) ................................................ 282 7.17.4.9 trigger 3 address high by te register (bka3 h).................................................... 282 7.18 parallel po rt (pp) ............................................................................................................. ............... 283 7.18.1 overview....................................................................................................................... ...... 283 7.18.2 features ....................................................................................................................... ...... 283 7.18.3 functional de script ion........................................................................................................ 283 7.18.3.1 kbs connection with para llel port connector ...................................................... 283 7.18.3.2 in-system programmi ng operation ....................................................................... 283 8. register list .................................................................................................................. ............................. 285 9. dc characte ristics ............................................................................................................. ........................ 295 10. ac characteristics ............................................................................................................. ........................ 297 11. analog device ch aracteristics.................................................................................................. ................. 305 12. package info rmation ............................................................................................................ ...................... 307 13. ordering in format ion ........................................................................................................... ....................... 311 14. top marking in formation ........................................................................................................ .................... 313 figures figure 3-1. host/flash and ec/flash mappi ng (gener al).......................................................................... ......... 6 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xiii contents figure 3-2. host/flash and ec/flash mapping (flash size = 512k, ec code = 64k, a specific example) ........ 7 figure 3-3. ec 8032 da ta/code memory map....................................................................................... ............. 9 figure 5-1. power state transitions............................................................................................ ...................... 23 figure 5-2. clock tree......................................................................................................... .............................. 31 figure 5-3. le d connection..................................................................................................... .......................... 36 figure 6-1. host view regist er map via i ndex-data pair ......................................................................... ........ 42 figure 6-2. program fl ow chart fo r pnpcfg ...................................................................................... ............ 61 figure 6-3. scratch sr am in data space......................................................................................... ................ 65 figure 6-4. wakeup event and gatherin g scheme .................................................................................. ........ 79 figure 6-5. kbrst# output scheme............................................................................................... ................. 82 figure 6-6. ga20 output scheme................................................................................................. .................... 82 figure 6-7. kbc host in terface block diagram................................................................................... .............. 91 figure 6-8. irq cont rol in kbc module.......................................................................................... .................. 92 figure 6-9. pmc host in terface bloc k diagram ................................................................................... ............. 98 figure 6-10. ec interr upt request for pmc...................................................................................... ................ 99 figure 6-11. irq/sci#/smi# cont rol in pmc com patible mode .................................................................... 100 figure 6-12. irq/sci#/smi# cont rol in pmc e nhanced mode ...................................................................... 101 figure 6-13. typical pmc2 ex mailbox op eration .................................................................................. ........ 102 figure 6-14. regist er map of rtc ............................................................................................... ................... 120 figure 7-1. interrupt contro l system conf iguration ............................................................................. ........... 133 figure 7-2. interrupt response time ............................................................................................ .................. 134 figure 7-3. timer 0/1 in mode 0 and mode 1..................................................................................... ............. 135 figure 7-4. timer 0/1 in mode 2, au to-reload................................................................................... ............. 136 figure 7-5. timer 0 in m ode 3 two 8- bit timers ................................................................................. ............ 136 figure 7-6. timer 2: capture mode.............................................................................................. ................... 137 figure 7-7. timer 2: au to reload (decn = 0) .................................................................................... ............ 138 figure 7-8. timer 2: auto reload mode (decn = 1) ............................................................................... ....... 139 figure 7-9. timer 2: clock out mode............................................................................................ .................. 140 figure 7-10. wa tchdog timer.................................................................................................... ...................... 140 figure 7-11. serial po rt block diagram......................................................................................... .................. 141 figure 7-12. data fram e (mode 1, 2 and 3) ...................................................................................... ............. 142 figure 7-13. timer 2 in ba ud rate gene rator mode ............................................................................... ....... 143 figure 7-14. intc si mplified di agram ........................................................................................... ................. 166 figure 7-15. program fl ow chart for intc ....................................................................................... .............. 167 figure 7-16. wuc si mplified diagram ............................................................................................ ................ 173 figure 7-17. program fl ow chart for wuc........................................................................................ ............. 173 figure 7-18. gpio si mplified di agram........................................................................................... ................. 186 figure 7-19. adc channel s control diagram...................................................................................... ........... 208 figure 7-20. adc softwar e calibrati on flow ..................................................................................... ............. 220 figure 7-21. adc software calibrati on flow in a special case ................................................................... .. 221 figure 7-22. pwm & sm artauto f an block......................................................................................... ............ 222 figure 7-23. pw m clock tree.................................................................................................... ..................... 223 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xiv it8511 e /te/ g figure 7-24. cr256 pw m block di agram ........................................................................................... ........... 224 figure 7-25. cr256 base puls e vs. additi onal pulse............................................................................. ........ 226 figure 7-26. smartauto mode 0 fan pw m output vs. temper ature reading................................................ 227 figure 7-27. smartauto mode 1 fan pw m output vs. temper ature reading................................................ 228 figure 7-28. program flow ch art for pwm c hannel ou tput ......................................................................... . 245 figure 7-29. program flow chart for cr256 pwm c hannel output .............................................................. 246 figure 7-30. program flow chart fo r smartauto fan channel output........................................................... 247 figure 7-31. program flow chart for ec2i read.................................................................................. .......... 252 figure 7-32. program flow chart for ec 2i write ................................................................................. ........... 253 figure 7-33. simp lified di agram................................................................................................ ...................... 254 figure 7-34. bram mapping di agram .............................................................................................. .............. 265 figure 7-35. simp lified di agram................................................................................................ ...................... 267 figure 7-36. parallel port fe male 25-pin connector ............................................................................. ......... 283 figure 10-1. vstby powe r-on reset timing ....................................................................................... .......... 297 figure 10-2. re set timing..................................................................................................... ......................... 297 figure 10-3. warm reset timing ................................................................................................. ................... 298 figure 10-4. wakeup from doze mode timing ...................................................................................... ......... 298 figure 10-5. wake up fr om sleep mode timing.................................................................................... ......... 298 figure 10-6. asynchronous external wakeup /interrupt source ed ge detected timing................................. 298 figure 10-7. lpc an d serirq timing ............................................................................................. .............. 299 figure 10-8. swuc wake up timing .............................................................................................. .............. 299 figure 10-9. flash read cycle timing........................................................................................... ................. 300 figure 10-10. flash write cycl e timing........................................................................................ ................. 300 figure 10-11. pw m output timing ............................................................................................... ................. 301 figure 10-12. pmc smi#/sci# timing............................................................................................ ............... 301 figure 10-13. pmc ibf/sci# timing ............................................................................................. ................ 302 figure 10-14. ps/2 rece ive/transmit timing .................................................................................... ............ 302 figure 10-15. smbus timing .................................................................................................... .................... 303 figure 10-16. consumer ir (cir) timing ......................................................................................... .............. 304 tables table 3-1. host/f lash mapping .................................................................................................. ......................... 7 table 3-2. ec/f lash mapping .................................................................................................... ......................... 8 table 3-3. flash read/write pr otection controlle d by ec side ................................................................... ...... 8 table 3-4. trus ted rom range................................................................................................... ....................... 8 table 4-1. pins listed in nume ric order (176-p in lqfp/tqfp) .................................................................... .. 13 table 4-2. pins listed in nu meric order (180 -pin tfbga) ........................................................................ ...... 14 table 4-3. pins listed in alphabetic al order................................................................................... .................. 15 table 5-1. pin descriptions of lpc bus interface............................................................................... .............. 17 table 5-2. pin descriptions of external flas h interface........................................................................ ............ 17 table 5-3. pin descriptions of keyboard matrix sc an interface .................................................................. ..... 18 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xv contents table 5-4. pin descriptions of sm bus interface ................................................................................ .............. 18 table 5-5. pin descripti ons of ps/2 interface .................................................................................. ................. 18 table 5-6. pin descripti ons of pwm interface ................................................................................... ............... 18 table 5-7. pin descriptions of wake up cont rol inte rface ....................................................................... ........ 19 table 5-8. pin descripti ons of uart interface .................................................................................. ............... 19 table 5-9. pin descripti ons of cir interface................................................................................... .................. 19 table 5-10. pin descriptions of parallel port interface ........................................................................ ............. 19 table 5-11. pin descripti ons of gpio interface ................................................................................. ............... 20 table 5-12. pin descripti ons of hardware strap................................................................................. .............. 20 table 5-13. pin descriptions of adc inpu t interface ............................................................................ ............ 20 table 5-14. pin descriptions of dac output interface ........................................................................... .......... 21 table 5-15. pin descri ptions of clock .......................................................................................... ..................... 21 table 5-16. pin descriptions of power/gr ound sig nals........................................................................... ......... 21 table 5-17. po wer st ates....................................................................................................... ........................... 23 table 5-18. quick table of power pl ane for pins ................................................................................ ............. 24 table 5-19. pin states of lpc bus interface .................................................................................... ................ 24 table 5-20. pin states of external flas h interface............................................................................. ............... 25 table 5-21. pin states of key board matrix sc an interf ace ....................................................................... ........ 25 table 5-22. pin states of sm bus interface ..................................................................................... ................. 25 table 5-23. pin states of ps/2 in terface....................................................................................... .................... 25 table 5-24. pin states of pwm interface........................................................................................ .................. 26 table 5-25. pin states of wa ke up control interface ............................................................................ ........... 26 table 5-26. pin states of uart interface....................................................................................... .................. 26 table 5-27. pin states of cir interface ........................................................................................ .................... 26 table 5-28. pin states of gpio in terface....................................................................................... ................... 26 table 5-29. pin states of adc input interface .................................................................................. ................ 27 table 5-30. pin states of dac output interface ................................................................................. .............. 27 table 5-31. pin st ates of clock................................................................................................ ......................... 27 table 5-32. re set sources...................................................................................................... .......................... 29 table 5-33. reset type s and applie d module ..................................................................................... ............. 29 table 5-34. cl ock types ........................................................................................................ ........................... 30 table 5-35. power saving by ec clock oper ation mode ............................................................................ ..... 32 table 5-36. module status in each power state/cl ock operation .................................................................. . 33 table 5-37. pins wi th pull function............................................................................................ ....................... 34 table 5-38. pins with sc hmitt-trigge r function ................................................................................. ............... 34 table 5-39. signals with open-drain function ................................................................................... .............. 34 table 6-1. lpc/ fwh response.................................................................................................... .................... 38 table 6-2. host view register map, pnpcfg ...................................................................................... ........... 40 table 6-3. host view regi ster map, logi cal devices ............................................................................. .......... 40 table 6-4. host view register map via index-data i/o pair, standard plug and play configuration registers 41 table 6-5. interrupt request (irq) number assignment, logi cal device ir q via serirq ............................ 41 table 6-6. logical device number (ldn) assignments ............................................................................. ...... 42 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xvi it8511 e /te/ g table 6-7. host view register map via index-data i/o pair, swuc logica l device ....................................... 47 table 6-8. host view register map via index-dat a i/o pair, kbc / mouse interface logical device.............. 49 table 6-9. host view register m ap via index-data i/o pair, kbc / ke yboard interface logical device ......... 50 table 6-10. host view register map via index -data i/o pair, smfi in terface logica l device ........................ 51 table 6-11. host view register map vi a index-data i/o pair , rtc logica l device......................................... 53 table 6-12. host view register map via index-data i/o, pm1 logical device ................................................ 56 table 6-13. host view register map via index-data i/o, pm2 logical device ................................................ 57 table 6-14. mapped host memory address ......................................................................................... ............ 62 table 6-15. ec view register map, smfi ......................................................................................... ............... 67 table 6-16. host view register map, smfi....................................................................................... ............... 76 table 6-17. host view register map, swuc ....................................................................................... ............ 83 table 6-18. ec view register m ap, swuc......................................................................................... ............. 86 table 6-19. host view register map, kbc ........................................................................................ ............... 92 table 6-20. ec view register map, kbc .......................................................................................... ............... 94 table 6-21. host view register map, pmc ........................................................................................ ............ 102 table 6-22. ec view register map, pmc.......................................................................................... ............. 104 table 6-23. host view register map, tmkbc...................................................................................... .......... 109 table 6-24. ec view r egister map, tmkbc ........................................................................................ .......... 114 table 6-25. host view register map, rtc ........................................................................................ ............. 119 table 6-26. host view register map via index-data i/o pa ir, rtc b ank 0 ................................................... 121 table 6-27. host view register map via index-data i/o pa ir, rtc b ank 1 ................................................... 121 table 7-1. 8032 port usage .................................................................................................... ....................... 131 table 7-2. system interrupt table.............................................................................................. ..................... 133 table 7-3. timer 2 mo des of operation .......................................................................................... ................ 139 table 7-4. serial port signals................................................................................................. ......................... 141 table 7-5. selecting the baud rate ge nerator(s)................................................................................ ........... 143 table 7-6. inte rnal ram map .................................................................................................... ...................... 144 table 7-7. ec view register map, intc .......................................................................................... .............. 158 table 7-8. intc in terrupt assignments.......................................................................................... ................. 165 table 7-9. ec view register map, wuc ........................................................................................... ............. 168 table 7-10. wuc i nput assi gnments.............................................................................................. ................ 172 table 7-11. ec view r egister map, kb scan...................................................................................... ........... 174 table 7-12. ec view register map, gpio......................................................................................... ............. 176 table 7-13. gpio al ternate function............................................................................................ .................. 181 table 7-14. ec view register m ap, ecpm ......................................................................................... ........... 187 table 7-15. ec view r egister map, smbus ........................................................................................ .......... 196 table 7-16. ec view register map, ps/2 ......................................................................................... .............. 203 table 7-17. ec view register m ap, dac .......................................................................................... ............. 206 table 7-18. ec view register map, adc .......................................................................................... ............. 211 table 7-19. detail step of adc channel conver sion .............................................................................. ....... 219 table 7-20. cr 256 wave form ..................................................................................................... ................... 225 table 7-21. cr256 added a dditional puls e position.............................................................................. ........ 226 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 xvii contents table 7-22. ec view register map, pwm .......................................................................................... ............ 229 table 7-23. ec view register map, ec2i......................................................................................... .............. 249 table 7-24. ec view register m ap, etwd ......................................................................................... ........... 255 table 7-25. ec view r egister map, gctrl........................................................................................ ........... 259 table 7-26. modulation carrier fr equency ....................................................................................... .............. 272 table 7-27. receiver demodulat ion low frequenc y (hcfs = 0) .................................................................. 274 table 7-28. receiver demodulatio n high frequency (hcfs = 1).................................................................. 275 table 7-29. i2ec/d2ec accessable targets....................................................................................... ........... 280 table 7-30. ec view register map, dbgr ......................................................................................... ........... 281 table 9-1. powe r consumption................................................................................................... .................... 296 table 10-1. vstby powe r-on reset ac table ...................................................................................... ........ 297 table 10-2. rese t ac table..................................................................................................... ....................... 297 table 10-3. warm reset ac table ................................................................................................ ................. 298 table 10-4. wakeup from doze mode ac table ..................................................................................... ....... 298 table 10-5. wake up from sleep mode ac table................................................................................... ....... 298 table 10-6. asynchronous external wakeup/in terrupt source edge detected ac table.............................. 299 table 10-7. lpc and serirq ac table ............................................................................................ ............ 299 table 10-8. swuc wa ke up ac table .............................................................................................. ............ 299 table 10-9. flash read cycle ac table.......................................................................................... ............... 300 table 10-10. flash wri te cycle ac table........................................................................................ ............... 300 table 10-11. pwm ou tput ac table ............................................................................................... ............... 301 table 10-12. pmc sm i#/sci# ac table............................................................................................ ............. 301 table 10-13. pmc ib f/sci# ac table ............................................................................................. .............. 302 table 10-14. ps/2 receiv e/transmit ac table .................................................................................... .......... 302 table 10-15. sm bus ac table .................................................................................................... .................. 303 table 10-16. consumer ir (cir) ac table ........................................................................................ ............ 304 table 11-1. adc ch aracteristics................................................................................................ ..................... 305 table 11-2. dac ch aracteristics................................................................................................ ..................... 305 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 itpm-pn-200644 specifications subject to change wit hout notice by jimmy hou, 10/26/2006 1 features 1. features ? 8032 embedded controller twin turbo version/3-stage pipeline 10mhz for ec domain and 8032 internal timer 10mhz for 8032 code-fetch instruction set compatible with standard 8051/2 ? lpc bus interface compatible with the lpc specification v1.1 supports i/o read/write supports tmkbc trusted port cycle supports memory read/write supports fwh read/write serial irq ? flash interface supports external parallel flash with 10 mhz base clock up to 4m bytes flash space shared by the host and ec side (parallel flash) 8-bit data bus ? sm bus controller sm bus spec. 2.0 sm bus host only 2 sm bus channels ? system wake up control modem ri# wake up telephone ring# wake up irq/smi routing ? ec wake up control 32 external/internal wake up events ? interrupt controller 32 interrupt events to ec fixed priority ? timer / watch dog timer 3 16-bit multi-function timers inside 8032, which is based on ec clock 1 watch dog timer inside 8032, which is based on ec clock 1 external timer in etwd module, which is based on 32.768 k clock source 1 external wdt in etwd module, which is based on 32.768 k clock source ? uart full duplex uart ? acpi power management channel 2 power management channels compatible and enhanced mode ? rtc supports 2 lockable memory areas supports power-switch circuit supports two alarms ? battery-backed sram ec registers shared with host rtc sram ? gpio supports 98-bit gpio programmable pull up/pull down schmitt trigger for input ? kbc interface 8042 style kbc interface legacy irq1 and irq12 fast a20g and kb reset ? adc 14 adc channels (10 external) 10-bit adc resolution (accuracy 4lsb) digital filter for noise reduction conversion time for 14 channels within 100 ms ? dac 4 dac channels 8-bit dac ? pwm with smartauto fan control 8 pwm channels smartauto fan control base clock frequency is 32.768 khz 8/16-bit duty cycle resolution 8/16-bit common input clock prescaler 4 prescalers for 8 pwm output used for devices with different frequencies 2 tachometers for measuring fan speed complete resolution 256 pwm output supported. (cr256)? ? ps/2 interface 4 ps/2 interface hardware/software mode selection ? kb matrix scan hardware keyboard scan 18x8 keyboard matrix scan free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 2 it8511 e /te/ g ? in-system programming isp via parallel port interface on existing kbs connector fast flash programming with software provided by ite ? consumer ir supports 27-58 khz, 400-500 khz device supports remote power-on switch ? tmkbc supports v0.95 ? power consumption standby with sleep mode current: 100 p a ? package lqfp 176/tqfp 176/tfbga 180 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 3 general description 2. general description the it8511 is a highly integrated embedded controller with system functions suitable for mobile system applications. the it8511 directly interfaces to the lp c bus and provides acpi embedded controller function, keyboard controller (kbc) and matrix scan, external fl ash interface for system bi os and ec code, pwm, adc and smartauto fan control for hardware monitor, ps/2 in terface for external keyboard/mouse devices, rtc, bram, cir and system wake up functions for system pow er management. it also supports the external flash ( or eprom) to be shared by the host and ec side. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 4 it8511 e /te/ g this page is intentionally left blank. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 5 system block diagram 3. system block diagram 3.1 block diagram m bus smfi (flash controller) lpc to i bus / serirq pnpcfg regs i bus arbiter internal bus(i bus) ec dedicated bus (ec bus) tmkbc i2ec ec (r8032tt) kbc swuc pmc1/2 2k scratch sram gpio ps/2 pwm/ smartauto fan adc wuc( wakeup ctrl) sm bus ecpm(pmu clock gen) kb scan etwd dac parallel flash rtc intc bram(battery- backed sram) gctrl(gernal control) cir pp(parallel port) sram ec2i ? host domain: lpc, pnpcfg, rtc logic device, host parts of smfi/swuc/kbc/pmc/tmkbc logical devices and host parts of ec2i. ? ec domain: ec 8032, intc, wuc kb scan, gpio, ecpm, smb, ps/2, dac, adc, pwm, hws, etwd, ec2i, bram, gctrl, cir, egpc, dbgr, ec parts of smf i/swuc/kbc/pmc/tmkbc and ec parts of ec2i. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 6 it8511 e /te/ g 3.2 host/ec mapped memory space figure 3-1. host/flash and ec/flash mapping (general) out of range out of range common bank bank 0 bank 1 bank 3 bank 2 host memory space expansion flash space ec code memory space ffff_ffffh fffe_ffffh ffff_0000h 00_0000h fffe_0000h 1_0000_0000h - flash_size ffff_ffffh - flash_size flash_size - 1 flash_size - 01_0000h flash_size - 01_0001h flash_size - 02_0000h fffd_ffffh flash_size - 02_0001h bank 3 (32k) bank 2 (32k) bank 1 (32k) bank 0 (32k) common bank (32k) 64k 64k ec code: max 160k flash_size 64k 64k 0000h 7fffh 8000h ffffh 000f_ffffh 000e_ffffh 000f_0000h 000e_0000h 000d_ffffh 4g top flash space top 32k 32k 0000_0000h variable, not necessary on 32k boundary variable, not necessary on 32k boundary these five banks are arragned in order and totally 160k mapped. each bank is always mapped but it is only valid if it is used by ec code. if ec code size <= 64k, bank 0 is valid to be selected. if ec code size <= 96k, bank 0-1 are valid to be selected. if ec code size <= 128k, bank 0-2 are valid to be selected. if ec code size <= 160k, bank 0-3 are valid to be selected. if ec code size is not mutiple of 32k, the remainder can be used by host memory. bank 0, 1, 2 and 3 occupy the same code memory space. only one of these four banks can be selected at once time. it is selected by ecbb or p1 register. the range 4 shows space used by ec code and five banks are all used. the interface line will be lower if ec code size is smaller than 160k. (byte) (byte) (byte) range 1 range 4 range 2 range 3 range 1 range 4 range 2 range 3 range 1 range 2 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 7 system block diagram figure 3-2. host/flash and ec/flash mapping (flash size = 512k, ec code = 64k, a specific example) out of range out of range common bank bank 0 host memory space expansion flash space ec code memory space ffff_ffffh fffe_ffffh ffff_0000h 00_0000h fffe_0000h fff8_0000h fff7_ffffh 07_ffffh 07_0000h 06_ffffh 06_0000h fffd_ffffh 05_ffffh bank 0 (32k) common bank (32k) 64k 64k 64k 512k 64k 64k 0000h 7fffh 8000h ffffh 000f_ffffh 000e_ffffh 000f_0000h 000e_0000h 000d_ffffh 4g top flash space top 32k 32k 0000_0000h 00_ffffh 01_0000h fff9_0000h fff8_ffffh bank 1-3 are not valid to be selected and are not shown. (byte) (byte) (byte) range 1 range 4 range 2 range 3 range 1 range 4 range 2 range 3 range 1 range 2 the flash memory space is shared between t he host side and ec side, and it is shown in figure 3-1. an example of 512k flash size, 64k ec code size is shown in figure 3-2. the host memory 4g byte top is always mapped into the top of flash space and the host processor fetches the first instruction after reset at ffff_fff0h in the host memory, which is 16 bytes below the uppermost flash space. the bottom of ec code is always mapped into the bo ttom of flash space and ec r8032tt micro-controller fetches the first instruction after reset at 00_0000h in the ec code memory, which is 1 byte in the lowermost flash space. the interface line of host memory and ec code is variable and not necessary on 32k boundary. table 3-1. host/flash mapping host memory space on lpc bus (byte) mapped expansion flash space (byte) size (byte) mapping condition (1_0000_0000h?flash_size)~ ffff_ffffh 00_0000h~ (flash_size-1) flash_size always 000f_0000h ~ 000f_ffffh (flash_size-01_0000h)~ (flash_size-1) 64k always 000e_0000h ~ 000e_ffffh (flash_size-02_0000h)~ (flash_size-01_0001h) 64k biosexts= 1 note: the host side can map all flash range regardless of ec code space. note: all host mappings are controlled by hbren bit in hctrl2r register. note: flash size is defined in fmssr register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 8 it8511 e /te/ g table 3-2. ec/flash mapping ec code memory space (byte) mapped flash address range (byte) size (byte ) mapping conditio n bank selected condition bank 3: 8000h ~ ffffh 02_0000h ~ 02_7fffh 32k always ecbb=11 bank 2: 8000h ~ ffffh 01_8000h ~ 01_ffffh 32k always ecbb=10 bank 1: 8000h ~ ffffh 01_0000h ~ 01_7fffh 32k always ecbb=01 bank 0: 8000h ~ ffffh 00_8000h ~ 00_ffffh 32k always ecbb=00 common bank: 0000h ~ 7fffh 00_0000h ~ 00_7fffh 32k always always note: ec code can use the maximum 160k by banking. note: all ec code memory space is mapped to both ec and ho st side at the same time. the ec size is not necessary on 32k boundary. note: note: if bso=1, ecbb is replaced with p1 register of 8032. ecbb means ec bb field in fecbsr register. bso means bso bit in fpcfg register. table 3-3. flash read/write prot ection controlled by ec side flash address range (byte) read control register bits write control register bits note 02_8000h ~ top orpla8 in smecorpr1 orpla8 in smecowpr1 remainder 02_0000h ~ 02_7fffh orpla7 in smecorpr0 orpla7 in smecowpr0 32k bytes 01_8000h ~ 01_ffffh orpla6 in smecorpr0 orpla6 in smecowpr0 32k bytes 01_0000h ~ 01_7fffh orpla5 in smecorpr0 orpla5 in smecowpr0 32k bytes 00_8000h ~ 00_ffffh orpla4 in smecorpr0 orpla4 in smecowpr0 32k bytes 00_6000h ~ 00_7fffh orpla3 in smecorpr0 orpla3 in smecowpr0 8k bytes 00_4000h ~ 00_5fffh orpla2 in smecorpr0 orpla2 in smecowpr0 8k bytes 00_2000h ~ 00_3fffh orpla1 in smecorpr0 orpla1 in smecowpr0 8k bytes 00_0000h ~ 00_1fffh orpla0 in smecorpr0 orpla0 in smecowpr0 8k bytes all ranges are write-control by hostwa, too. table 3-4. trusted rom range flash address range (byte) trusted rom range enable note 02_0000h ~ 02_7fffh tromrng7 in tromr 32k bytes 01_8000h ~ 01_ffffh tromrng6 in tromr 32k bytes 01_0000h ~ 01_7fffh tromrng5 in tromr 32k bytes 00_8000h ~ 00_ffffh tromrng4 in tromr 32k bytes 00_6000h ~ 00_7fffh tromrng3 in tromr 8k bytes 00_4000h ~ 00_5fffh tromrng2 in tromr 8k bytes 00_2000h ~ 00_3fffh tromrng1 in tromr 8k bytes 00_0000h ~ 00_1fffh always 8k bytes trusted rom is where tmkbc firmware locates. only trusted rom can access trusted ram, which is scratch ram with asserted trust flag (trsf bit in scar0h~scar4h registers, respectively). tromr register can be modified only by trusted rom. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 9 system block diagram 3.3 ec mapped memory space figure 3-3. ec 8032 data/code memory map ec internal ec external ec data memory space data memory space code memory space ffffh 2600h reserved 2500h dbgr (byte) 2400h tmkbc 2300h cir adjustable 2200h bram 2100h reserved 2000h gctrl 1f00h etwd bank 1e00h ecpm 0,1,2 or 3 1d00h kb scan 1c00h sm bus 1b00h wuc 1a00h dac 1900h adc 1800h pwm 1700h ps/2 be a ram or 1600h gpio ram/rom 1500h pmc 1400h swuc 1300h kbc 1200h ec2i common 1100h intc bank 1000h smfi 0800h 0800h-0fffh=0000h-07ffh 0700h scratch sram no.4 (256b) ffh 0600h scratch sram no.3 (256b) 7fh indirect sfr 0400h scratch sram no.2 (512b) 00h direct & indirect 0000h scratch sram no.1 (1024b) corresponging move corresponging read/write corresponging read instruction: mov instruction: movx instruction: movc see also figure 6-3. scratch sram in data space on page 65, which also shows scratch sram no 0. there are five internal scratch sram no 0-4 (no 0 is s hared with the same physical sram with no 1-4, and is omitted in figure 3-3. ec 8032 data/code memory map), which are always mapped into data space and may be mapped into code space if their corresponding c ode space mapping registers are enabled. it means that scratch sram may be mapped into data and code space at the same time and the firmware on scratch rom can access the same scratch ram. it is called scratc h ram when being located at data space (default after reset) and called scratch rom when being located at code space. the ec code space is 64k bytes and physically occupi es the maximum 160 k bytes at the bottom of the flash space. refer to figure 3-1 on page 6 for the details. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 10 it8511 e /te/ g 3.4 register abbreviation the register abbreviations and access rules are listed below: r read only . if a register is read only, writing to this register has no effect. w write only . if a register is write only, reading to this register returns all zero. r/w read/write . a register with this attribute can be read and written. rc read clear . if a register is read clear, reading to th is register clears the register to ?0?. r/wc read/write clear . a register bit with this attribute can be read and written. however, writing 1 clears the corresponding bit and writing 0 has no effect. bfname@regname this abbreviation may be shown in figures to represent one bit in a register or one field in a register. the used radix indicator suffixes in this specification are listed below: decimal number: "d" suffix or no suffix binary number: "b" suffix hexadecimal number: "h" suffix free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 11 pin configuration 4. pin configuration 4.1 top view it8511e/te top view pinout top view 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 52 51 49 48 47 50 54 53 56 62 61 59 58 57 60 55 64 63 66 72 71 69 68 67 70 65 74 73 76 82 81 79 78 77 80 75 84 83 86 88 87 85 gpc5 tmri1/wui3/gpc6 gpi6 tmri0/wui2/gpc4 fcs# smdat1/gpc2 gpc3 smclk1/gpc1 vss gpi5 ring#pwrfail#/lpcrst#/gpb7 vstby smdat0/gpb4 gpb2 smclk0/gpb3 ck32ke vbat vss vstby ck32k gp13 gp14 txd/gpb1 gp12 rxd/gpb0 frd# fwr# gpi1 fd7 gpi0 fd5 fd6 fd4 fa9/id1 fa8/id0 fd2 fd3 fd1 vss fd0 vstby fa11/id3 fa10/id2 fa7 fa5/shbm fa6 fa12/id4 fa4/ppen fa13/id5 fa2/baddr0 fa3/baddr1 fa1/tm vstby fa0 fa14/id6 vss fa15/id7 ps2clk3/gpf6 ps2dat3/gpf7 ps2clk2/gpf4 ps2dat2/gpf5 ps2dat1/gpf3 fa16/gpg0 ps2clk1/gpf2 ps2dat0/gpf1 fa17/gpg1 ps2clk0/gpf0 gpl7 gpi7 gpl5 gpl6 gph7 fa19/gpg3 fa18/gpg2 dac2/gpj2 dac3/gpj3 dac1/gpj1 gpj5 dac0/gpj0 avss gpj4 avcc adc8/gpk4 adc9/gpk5 crx/gpm5 adc7/gpe3 ctx/gpm4 adc6/gpe2 adc4/gpe0 adc5/gpe1 kso17/gpm3 adc3/gpk3 kso16/gpm2 adc1/gpk1 adc2/gpk2 adc0/gpk0 ksi6 ksi7 ksi4 ksi5 gph6 ksi3/slin# gph5 ksi1/afd# ksi2/init# ksi0/stb# gph3 gph4 kso14 kso15 kso13 kso11/err# kso12/slct tach1/gpd7 tach0/gpd6 kso9/busy kso10/pe kso7/pd7 kso8/ack# kso6/pd6 gph2 kso5/pd5 kso4/pd4 gph1 kso3/pd3 kso0/pd0 kso1/pd1 gph0 vss clkout/gpc0 vstby pwm7/gpa7 wui5/gpe5 gint/gpd5 pwm6/gpa6 gpd4 pwm4/gpa4 pwm5/gpa5 pwm3/gpa3 vss pwm2/gpa2 pwm1/gpa1 vstby pwm0/gpa0 lpcrst#/wui4/gpd2 ecsci#/gpd3 lpc80ll/gpg7 ri2#/wui1/gpd1 lpc80hl/gpg6 clkrun#/wui7/gpe7 ri1#/wui0/gpd0 pwureq#/gpm1 lpcpd#/wui6/gpe6 ecsmi#/gpm0 gpl3 gpl4 lpcclk wrst# vss lad0 vcc lad2 lad1 gpl2 lad3 gpl1 gpl0 lframe# serirq ga20/gpb5 kbrst#/gpb6 fa21/gpg5 pwrsw/gpe4 fa20/gpg4 ck32kout/gpc7 kso2/pd2 it8511 e/te free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 12 it8511 e /t e / g IT8511G top view smclk1/ gpc1 smclk0/ gpb3 vbat vstby frd# fd3 fd0 fa6 fa13/ id5 nc nc gpi1 fd6 fd5 gpi6 gpc3 smdat1/ gpc2 gpb2 gpi2 rxd/ gpb0 fwr# fd7 fa8/ id0 fd2 fa10/ id2 fa5/ shbm fa3/ baddr1 fa14/ id6 fa20/ gpg4 tmri1/ wui3/ gpc6 tmri0/ wui2/ gpc4 gpi5 smdat0/ gpb4 ck32k gpi3 txd/ gpb1 fd4 fd1 fa7 fa4/ pp fa0 fa15/ id7 kbrst#/ gpb6 fa21/ gpg5 pwrsw/ gpe4 fcs# ring#/ pwrfail#/ lpcrst#/ gpb7 gpi4 ck32ke gpi0 fa9/ id1 fa11/ id3 fa12/ id4 fa1/ tm ps2dat3/ gpf7 ps2clk2/ gpf4 lad3 serirq gpl0 ga20/ gpb5 gpc5 fa2/ baddr0 ps2clk3/ gpf6 ps2dat1/ gpf3 ps2clk1/ gpf2 lad1 lad2 gpl1 lframe# ck32kout/ gpc7 ps2dat2/ gpf5 gpi7 fa16/ gpg0 fa17/ gpg1 vcc gpl2 lad0 gpl3 lpcclk wrst# ecsmi#/ gpm0 pwureq#/ gpm1 gpl4 lpcpd#/ wui6/ gpe6 ri1#/ wui0/ gpd0 ri2#/ wui1/ gpd1 clkrun#/ wui7/ gpe7 l80hlat/ gpg6 lpcrst#/ wui4/ gpd2 pwm/ gpa4 gpl7 gpl6 ps2dat0/ gpf1 ps2clk0/ gpf0 adc8/ gpk4 fa19/ gpg3 fa18/ gpg2 gph7 gpl5 l80llat/ gpg7 ecsci#/ gpd3 pwm/ gpa3 gint/ gpd5 pwm0/ gpa0 pwm2/ gpa2 pwm6/ gpa6 wui5/ gpe5 pwm1/ gpa1 pwm5/ gpa5 pwm7/ gpa7 kso0 gpd4 gph0 kso2 dac1/ gpj1 gpj5 dac2/ gpj2 dac3/ gpj3 adc7/ gpe3 adc9/ gpk5 gpj4 dac0/ gpj0 kso16/ gpm2 adc6/ gpe2 crx/ gpm5 avss ksi7 adc3/ gpk3 adc4/ gpe0 avcc gph6 adc0/ gpk0 adc2/ gpk2 kso17/ gpm3 ksi3 ksi4 adc1/ gpk1 ctx/ gpm4 kso7 gph3 ksi5 adc5/ gpe1 clkout/ gpc0 kso4 kso8 kso13 ksi2 ksi6 kso1 kso5 kso9 kso12 gph4 gph5 kso3 gph2 kso10 kso11 kso15 ksi1 gph1 kso6 tach0/ gpd6 tach1/ gpd7 kso14 ksi0 vstby vss vstby vss vstby vss vstby vss vstby vss vstby vss nc nc IT8511G pinout top view free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 13 pin configuration table 4-1. pins listed in numeric order (176-pin lqfp/tqfp) pin signal pin signal pin signal pin signal 1 ck32kout/gpc 7 45 vstby 89 adc6/gpe2 133 fa7 2 pwrsw/gpe4 46 vss 90 adc7/gpe3 134 fa11 3 fa20/gpg4 47 clkout/gpc0 91 ctx/gpm4 135 fa10 4 fa21/gpg5 48 gph0 92 crx/gpm5 136 vstby 5 ga20/gpb5 49 kso0/pd0 93 adc8/gpk4 137 vss 6 kbrst#/gpb6 50 kso1/pd1 94 adc9/gpk5 138 fd0 7 serirq 51 kso2/pd2 95 avcc 139 fd1 8 gpl0 52 kso3/pd3 96 avss 140 fd2 9 lframe# 53 kso4/pd4 97 gpj4 141 fd3 10 lad3 54 gph1 98 gpj5 142 fa9 11 gpl1 55 gph2 99 dac0/gpj0 143 fa8 12 gpl2 56 kso5/pd5 100 dac1/gpj1 144 fd4 13 lad2 57 kso6/pd6 101 dac2/gpj2 145 fd5 14 lad1 58 kso7/pd7 102 dac3/gpj3 146 fd6 15 lad0 59 kso8/ack# 103 fa19/gpg3 147 fd7 16 vcc 60 kso9/busy 104 fa18/gpg2 148 gpi0 17 vss 61 kso10/pe 105 gph7 149 gpi1 18 lpcclk 62 tach0/gpd6 106 gpl5 150 frd# 19 wrst# 63 tach1/gpd7 107 gpl6 151 fwr# 20 gpl3 64 kso11/err# 108 gpl7 152 gpi2 21 gpl4 65 kso12/slct 109 gpi7 153 rxd/gpb0 22 ecsmi#/gpm0 66 kso13 110 ps2clk0/gpf0 154 txd/gpb1 23 pwureq#/gpm1 67 kso14 111 ps2dat0/gpf1 155 gpi3 24 lpcpd#/wui6/ gpe6 68 kso15 112 fa17/gpg1 156 gpi4 25 clkrun#/wui7/ gpe7 69 gph3 113 fa16/gpg0 157 vstby 26 ri1#/wui0/gpd0 70 gph4 114 ps2clk1/gpf2 158 ck32k 27 lpc80hl/gpg6 71 ksi0/stb# 115 ps2dat1/gpf3 159 vss 28 lpc80ll/gpg7 72 ksi1/afd# 116 ps2clk2/gpf4 160 ck32ke 29 ri2#/wui1/gpd1 73 ksi2/init# 117 ps2dat2/gpf5 161 vbat 30 lpcrst#/wui4/ gpd2 74 ksi3/slin# 118 ps2clk3/gpf6 162 gpb2 31 ecsci#/gpd3 75 gph5 119 ps2dat3/gpf7 163 smclk0/gpb3 32 pwm0/gpa0 76 gph6 120 fa15 164 smdat0/gpb4 33 pwm1/gpa1 77 ksi4 121 fa14 165 ring#/ pwrfail#/ lpcrst#/gpb7 34 vstby 78 ksi5 122 vss 166 vstby 35 vss 79 ksi6 123 vstby 167 vss 36 pwm2/gpa2 80 ksi7 124 fa0 168 gpi5 37 pwm3/gpa3 81 adc0/gpk0 125 fa1/tm 169 smclk1/gpc1 38 pwm4/gpa4 82 adc1/gpk1 126 fa2/baddr0 170 smdat1/gpc2 39 pwm5/gpa5 83 adc2/gpk2 127 fa3/baddr1 171 gpc3 40 pwm6/gpa6 84 adc3/gpk3 128 fa4/ppen 172 tmri0/wui2/ gpc4 41 gpd4 85 kso16/gpm2 129 fa13 173 fcs# 42 gint/gpd5 86 kso17/gpm3 130 fa12 174 gpi6 43 pwm7/gpa7 87 adc4/gpe0 131 fa5/shbm 175 gpc5 44 wui5/gpe5 88 adc5/gpe1 132 fa6 176 tmri1/wui3/ gpc6 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 14 it8511 e /te/ g table 4-2. pins listed in numeric order (180-pin tfbga) pin signal pin signal pin signal pin signal a1 nc d4 fcs# h1 lpcclk l12 adc6/gpe2 a2 smclk1/gpc1 d5 ring#/ pwrfail#/ lpcrst#/gpb7 h2 wrst# l13 crx/gpm5 a3 smclk0/gpb3 d6 gpi4 h3 ecsmi#/gpm0 l14 avss a4 vbat d7 ck32ke h4 pwureq#/gpm1 m1 pwm0/gpa0 a5 vstby d8 gpi0 h5 vstby m2 pwm2/gpa2 a6 frd# d9 fa9/id1 h10 adc8/gpk4 m3 pwm6/gpa6 a7 gpi1 d10 fa11/id3 h11 fa19/gpg3 m4 wui5/gpe5 a8 fd6 d11 fa12/id4 h12 fa18/gpg2 m5 kso1 a9 fd5 d12 fa1/tm h13 gph7 m6 kso5 a10 fd3 d13 ps2dat3/gpf7 h14 gpl5 m7 kso9 a11 fd0 d14 ps2clk2/gpf4 j1 gpl4 m8 kso12 a12 fa6 e1 lad3 j2 lpcpd#/wui6 /gpe6 m9 gph4 a13 fa13/id5 e2 serirq j3 ri1#/wui0/gpd0 m10 gph5 a14 nc e3 gpl0 j4 ri2#/wui1/gpd1 m11 ksi7 b1 gpi6 e4 ga20/gpb5 j5 vss m12 adc3/gpk3 b2 gpc3 e5 gpc5 j10 ctx/gpm4 m13 adc4/gpe0 b3 smdat1/gpc2 e6 vstby j11 dac1/gpj1 m14 avcc b4 gpb2 e7 vss j12 gpj5 n1 pwm1/gpa1 b5 gpi2 e8 vstby j13 dac2/gpj2 n2 pwm5/gpa5 b6 rxd/gpb0 e9 vss j14 dac3/gpj3 n3 pwm7/gpa7 b7 fwr# e10 vstby k1 clkrun#/wui7/ gpe7 n4 kso0 b8 fd7 e11 fa2/baddr0 k2 l80hlat/gpg6 n5 kso3 b9 fa8/id0 e12 ps2clk3/gpf6 k3 lpcrst#/wui4/ gpd2 n6 gph2 b10 fd2 e13 ps2dat1/gpf3 k4 pwm4/gpa4 n7 kso10 b11 fa10/id2 e14 ps2clk1/gpf2 k5 vstby n8 kso11 b12 fa5/shbm f1 lad1 k6 vss n9 kso15 b13 fa3/baddr1 f2 lad2 k7 kso7 n10 ksi1 b14 fa14/id6 f3 gpl1 k8 gph3 n11 gph6 c1 fa20/gpg4 f4 lframe# k9 ksi5 n12 adc0/gpk0 c2 tmri1/wui3 /gpc6 f5 ck32out/gpc7 k10 adc5/gpe1 n13 adc2/gpk2 c3 tmri0/wui2 /gpc4 f10 vss k11 adc7/gpe3 n14 kso17/gpm3 c4 gpi5 f11 ps2dat2/gpf5 k12 adc9/gpk5 p1 nc c5 smdat0/gpb4 f12 gpi7 k13 gpj4 p2 gpd4 c6 ck32k f13 fa16/gpg0 k14 dac0/gpj0 p3 gph0 c7 gpi3 f14 fa17/gpg1 l1 l80llat/gpg7 p4 kso2 c8 txd/gpb1 g1 vcc l2 ecsci#/gpd3 p5 gph1 c9 fd4 g2 gpl2 l3 pwm3/gpa3 p6 kso6 c10 fd1 g3 lad0 l4 gint/gpd5 p7 tach0/gpd6 c11 fa7 g4 gpl3 l5 clkout/gpc0 p8 tach1/gpd7 c12 fa4/pp g5 vss l6 kso4 p9 kso14 c13 fa0 g10 vstby l7 kso8 p10 ksi0 c14 fa15/id7 g11 gpl7 l8 kso13 p11 ksi3 d1 kbrst#/gpb6 g12 gpl6 l9 ksi2 p12 ksi4 d2 fa21/gpg5 g13 ps2dat0/gpf1 l10 ksi6 p13 adc1/gpk1 d3 pwrsw/gpe4 g14 ps2clk0/gpf0 l11 kso16/gpm2 p14 nc free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 15 pin configuration table 4-3. pins listed in alphabetical order signal pin signal pin signal pin signal pin adc0/gpk0 81/n12 fa8/id0 143/b9 kbrst#/gpb6 6/d1 ps2dat0/gpf1 111/g13 adc1/gpk1 82/p13 fa9/id1 142/d9 ksi0 71/p10 ps2dat1/gpf3 115/e13 adc2/gpk2 83/n13 fcs# 173/d4 ksi1 72/n10 ps2dat2/gpf5 117/f11 adc3/gpk3 84/m12 fd0 138/a11 ksi2 73/l9 ps2dat3/gpf7 119/d13 adc4/gpe0 87/m13 fd1 139/c10 ksi3 74/p11 pwm0/gpa0 32/m1 adc5/gpe1 88/k10 fd2 140/b10 ksi4 77/p12 pwm1/gpa1 33/n1 adc6/gpe2 89/l12 fd3 141/a10 ksi5 78/k9 pwm2/gpa2 36/m2 adc7/gpe3 90/k11 fd4 144/c9 ksi6 79/l10 pwm3/gpa3 37/l3 adc8/gpk4 93/h10 fd5 145/a9 ksi7 80/m11 pwm4/gpa4 38/k4 adc9/gpk5 94/k12 fd6 146/a8 kso0 49/n4 pwm5/gpa5 39/n2 avcc 95/m14 fd7 147/b8 kso1 50/m5 pwm6/gpa6 40/m3 avss 96/l14 frd# 150/a6 kso10 61/n7 pwm7/gpa7 43/n3 ck32k 158/c6 fwr# 151/b7 kso11 64/n8 pwrsw/gpe4 2/k3 ck32ke 160/d7 ga20/gpb5 5/e4 kso12 65/m8 pwureq#/gpm1 23/h4 ck32kout/gp c7 1/f5 gint/gpd5 42/l4 kso13 66/l8 ri1#/wui0/gpd0 26/j3 clkout/gpc0 47/l5 gpb2 162/b4 kso14 67/p9 ri2#/wui1/gpd1 29/j4 clkrun#/wui 7/gpe7 25/k1 gpc3 171/b2 kso15 68/n9 ring#/pwrfail#/l pcrst#/gpb7 165/d5 crx/gpm5 92/l13 gpc5 175/e5 kso16/gpm2 85/l11 rxd/gpb0 153/b6 ctx/gpm4 91/j10 gpd4 41/p2 kso17/gpm3 86/n14 serirq 7/e2 dac0/gpj0 99/k14 gph0 48/p3 kso2 51/p4 smclk0/gpb3 163/a3 dac1/gpj1 100/j11 gph1 54/p5 kso3 52/n5 smclk1/gpc1 169/a2 dac2/gpj2 101/j13 gph2 55/n6 kso4 53/l6 smdat0/gpb4 164/c5 dac3/gpj3 102/j14 gph3 69/k8 kso5 56/m6 smdat1/gpc2 170/b3 ecsci#/gpd3 31/l2 gph4 70/m9 kso6 57/p6 tach0/gpd6 62/p7 ecsmi#/gpm0 22/h3 gph5 75/m10 kso7 58/k7 tach1/gpd7 63/p8 fa0 124/c13 gph6 76/n11 kso8 59/l7 tmri0/wui2/gpc4 172/c3 fa1/tm 125/d12 gph7 105/h13 kso9 60/m7 tmri1/wui3/gpc6 176/c2 fa10/id2 135/b11 gpi0 148/d8 l80hlat/gpg6 27/k2 txd/gpb1 154/c8 fa11/id3 134/d10 gpi1 149/a7 l80llat/gpg7 28/l1 vbat 161/a4 fa12/id4 130/d11 gpi2 152/b5 lad0 15/g3 vcc 16/g1 fa13/id5 129/a13 gpi3 155/c7 lad1 14/f1 17,35, fa14/id6 121/b14 gpi4 156/d6 lad2 13/f2 46,122, fa15/id7 120/c14 gpi5 168/c4 lad3 10/e1 vss 137,159, fa16/gpg0 113/f13 gpi6 174/b1 lframe# 9/f4 167/e7, fa17/gpg1 112/f14 gpi7 109/f12 lpcclk 18/h1 e9,f10, fa18/gpg2 104/h12 gpj4 97/k13 lpcpd#/wui6/gpe6 24/j2 g5,j5, k6 fa19/gpg3 103/h11 gpj5 98/j12 lpcrst#/wui4/gp d2 30/k3 vstby (pll) 157/a5 fa2/baddr0 126/e11 gpl0 8/e3 nc --/a1 34,45, fa20/gpg4 3/c1 gpl1 11/f3 nc --/a14 123,136, fa21/gpg5 4/d2 gpl2 12/g2 nc --/p1 vstby 166/ fa3/baddr1 127/b13 gpl3 20/g4 nc --/p14 e6,e8, fa4/pp 128/c12 gpl4 21/j1 ps2clk0/gpf0 110/g14 e10,g10 fa5/shbm 131/b12 gpl5 106/h14 ps2clk1/gpf2 114/e14 h5,k5 fa6 132/a12 gpl6 107/g12 ps2clk2/gpf4 116/d14 wrst# 19/h2 fa7 133/c11 gpl7 108/g11 ps2clk3/gpf6 118/e12 wui5/gpe5 44/m4 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 16 it8511 e /te/ g this page is intentionally left blank. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 17 pin descriptions 5. pin descriptions 5.1 pin descriptions table 5-1. pin descriptions of lpc bus interface pin(s) no. signal attribute description lpc bus interface (3.3v cmos i/f, 5v tolerant) 165 or 30 lpcrst# ik lpc hardware reset lpc hardware reset will reset lpc interface and host side modules. the source is determined by ec side register bit lpcrsten. this pin can be omitted if external lpc reset is not required. 18 lpcclk pi lpc clock 33 mhz clock for lpc domain functions. 10, 13-15 lad[3:0] pio lpc address data 9 lframe# pi lpc lframe# signal 24 lpcpd# io2 lpc lpcpd# signal 25 clkrun# io6 lpc clkrun# signal 7 serirq pio serirq signal 22 ecsmi# o8 ec smi# signal this is smi# signal driven by swuc module. 31 ecsci# o8 ec sci# signal this is sci# signal driven by pmc module. 5 ga20 io2 gate a20 signal this is ga20 signal driven by swuc module. 6 kbrst# io2 kb reset signal this is kbrst# signal driven by swuc module. 19 wrst# ik warm reset for ec domain function reset after power up. wrst# is not 5v tolerant. 23 pwureq# o2 system power on request this is pwureq# signal driven by swuc module. 27 lpc80hl o4 lpc i/o port 80, high-nibble lad latch an active high signal to latch port 80 high-nibble for the debug purpose. 28 lpc80ll o4 lpc i/o port 80, low-nibble lad latch an active high signal to latch port 80 low-nibble for the debug purpose. table 5-2. pin descriptions of external flash interface pin(s) no. signal attribute description flash interface (3.3v cmos i/f, 5v tolerant) 120-121, 129-130, 134-135, 142-143, 133-131, 128-124 fa[15:0] o4 flash address [15:0] these are dedicated external flash address pins. in addition to being the flash address output, fa[5:2] serve as hardware strap pins described below. fa[5] : shbm, shared bios mode enable. fa[4] : ppen, enable in-system progra mming via parallel port interface fa[3] : baddr[1], used in pnpcfg base address. fa[2] : baddr[0], used in pnpcfg base address. 3-4, 103-104, 112-113 fa[21:16] iok4 flash address [21:16]/alternate gpio these pins can be used as gpio pins depending on the external flash size. 147-144, 141-138 fd[7:0] iok4 flash data [7:0] flash data bus. please do not place pull-up resistor on these pins. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 18 it8511 e /te / g pin(s) no. signal attribute description 150 frd# o4 flash read flash read control. please do not place pull-up resistor on this pin. 151 fwr# o4 flash write flash write control. please do not place pull-up resistor on this pin. 173 fcs# o4 flash chip select fcs# is the external flash chip select. please do not place pull-up resistor on this pin. table 5-3. pin descriptions of keyboard matrix scan interface pin(s) no. signal attribute description kb matrix interface (3.3v cmos i/f, 5v tolerant) 86-85 68-64, 61-56, 53-49 kso[17:0] o8 keyboard scan output keyboard matrix scan output. 80-77, 74-71 ksi[7:0] ik keyboard scan input keyboard matrix scan input for switch based keyboard. table 5-4. pin descriptions of sm bus interface pin(s) no. signal attribute description sm bus interface (3.3v cmos i/f, 5v tolerant) 169, 163 smclk[1:0] iok2 sm bus clk 2 sm bus interface provided. smclk0-1 correspond to channel a and b, respectively. 170, 164 smdat[1:0] iok2 sm bus data 2 sm bus interface provided. smdat0-1 correspond to channel a and b, respectively. table 5-5. pin descriptions of ps/2 interface pin(s) no. signal attribute description ps/2 interface (3.3v cmos i/f, 5v tolerant) 118, 116, 114, 110, ps2clk[3:0] iok8 ps/2 clk 4 sets of ps/2 interface, alternate function of gpio. ps2clk0-3 correspond to channel 1-4, respectively. 119, 117 115, 111 ps2dat[3:0] iok8 ps/2 data 4 sets of ps/2 interface, alternate function of gpio. ps2dat0-3 correspond to channel 1-4, respectively. table 5-6. pin descriptions of pwm interface signal pin(s) no. attribute description pwm interface (3.3v cmos i/f, 5v tolerant) 43, 40-36, 33-32 pwm[7:0] iok8 pulse width modulation output two of the eight pwm outputs can be se lected as smartauto fan control if enabled. others are general-purpose pwm signals. pwm0-7 correspond to channel 0-7, respectively. 63-62 tach[1:0] iok2 tachometer input tach[1:0] are tachometer inputs from external fans. they are used for measuring the external fan speed. 176,172 tmri[1:0] iok2 counter input tmri[1:0] are timer/counter input signals connected to timer2 and timer1 of 8032. notice that the frequency must be slower than 8032 clock to be sampled. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 19 pin descriptions table 5-7. pin descriptions of wake up control interface pin(s) no. signal attribute description wake up control interface (3 .3v cmos i/f, 5v tolerant) 25-24, 44, 30, 176, 172, 29, 26 wui[7:0] iok2-8 ec wake up input supplied by vstby, used for ec wake up. 2 pwrsw iok2 power switch input supplied by vstby, used to indicate the status of power switch. 29,26 ri[2:1]# iok4 ring indicator input supplied by vstby, used for system wake up. 165 ring# iok2 telephone line ring input supplied by vstby, used for system wake up. table 5-8. pin descriptions of uart interface pin(s) no. signal attribute description uart interface (3.3v cm os i/f, 5v tolerant) 154 txd iok2 uart tx output uart tx output from 8032 153 rxd iok2 uart rx input uart rx input from 8032 table 5-9. pin descriptions of cir interface pin(s) no. signal attribute description cir interface (3.3v cmos i/f, 5v tolerant) 91 ctx iok2 cir tx output transmission data for cir interface 92 crx iok2 cir rx input receive data for cir interface table 5-10. pin descriptions of parallel port interface pin(s) no. signal attribute description adc interface (3.3v cmos i/f) 65 slct o8 printer select 61 pe o8 printer paper end 60 busy o8 printer busy 59 ack# o8 printer acknowledge 74 slin# ik printer select input 73 init# ik printer initialize 64 err# o8 printer error 72 afd# ik printer auto line feed 71 stb# ik printer strobe 58-56, 53-49 pd[7:0] o8 parallel port data[7:0] *: the interface can be connected to parallel port of computer through ite-specified cable. the programmer can directly read/write flash through this interface. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 20 it8511 e /te / g table 5-11. pin descriptions of gpio interface pin(s) no. signal attribute description gpio interface (3.3v cmos i/f, 5v tolerant) refer to pins list table gpa[7:0], gpb[7:0], gpc[7:0], gpd[7:0], gpe[7:0], gpf[7:0], gpg[7:0], gph[7:0], gpi[7:0] gpj[5:0] gpk[5:0] gpl[7:0] gpm[5:0] iok refer to table 7-13 on page 181 for output driving capability gpio signals the 98 gpio pins are divided into 13 groups. each of them contains 8 gpio pins. some gpio pins have alternative function. 42 gint ik general purpose interrupt general purpose interrupt directly input to int28 of intc. table 5-12. pin descriptions of hardware strap pin(s) no. signal attribute description hardware strap (3.3v cmos i/f, 5v tolerant) 131 shbm i share host bios memory configuration sampled at vstby power up reset. no pull resistor: disable shared memory with host bios external 10k ohm pull up resistor: enable shared memory with host bios 128 ppen i parallel port enable sampled at vstby power up reset. no pull resistor: normal. external 10k ohm pull up resistor: kbs interface pins are switched to parallel port interface for in-system programming. 127,126 baddr[1:0] i i/o base address configuration sampled at vstby power up reset. no pull resistor: the register pair to access pnpcfg is 002eh and 002fh. 10k ohm external pull-up resistor on baddr0: the register pair to access pnpcfg is 004eh and 004fh. 10k ohm external pull-up resistor on baddr1: the register pair to access pnpcfg is determined by ec domain registers swcbalr and swcbahr. 125 tm ik trust mode this pin indicates the chip is in trust mode. 120-121, 129-130, 134-135, 142-143 id[7:0] ik identify input these hardware straps are used to ident ify the version for firmware usage. these input signals will be latched when vstby powers up. note that these hardware straps are on ly available if these pins are not driven by other components on pcb. table 5-13. pin descriptions of adc input interface pin(s) no. signal attribute description adc interface (3.3v cmos i/f) 84-81 adc[3:0] ai adc input dedicated adc input pins. 90-87 adc[7:4] aio2 adc input/alternate gpio these 4 adc inputs can be used as gpio pins depending on the adc channels required. 93 adc[8] ai adc input free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 21 pin descriptions pin(s) no. signal attribute description 94 adc[9] ai adc input table 5-14. pin descriptions of dac output interface pin(s) no. signal attribute description dac interface (3.3v cmos i/f) 102-99 dac[3:0] o dac output table 5-15. pin descriptions of clock pin(s) no. signal attribute description clock interface (3.3v cmos i/f) 158 ck32k osci 32.768k hz crystal x1 it is connected to inter nal crystal oscillator. 160 ck32ke oscio 32.768k hz crystal x2 it is connected to inter nal crystal oscillator. 1 ck32kout o4 32.768k hz oscillator output 32.768 khz clock output. 47 clkout o2 ec clock output ec domain clock output. table 5-16. pin descriptions of power/ground signals pin(s) no. signal attribute description power ground signals 167, 159, 137, 122, 46, 35, 17 vss i ground digital ground. 16 vcc i system power supply of 3.3v the power supply of lpc and related functions, which is main power of system. 166, 157, 136, 123, 45, 34 vstby i standby power supply of 3.3v the power supply of ec domain func tions, which is standby power of system. note that the power of pll is source d by pin 157 only. (pin a5 for IT8511G) 161 vbat i battery power supply of 3.3v the power supply for rtc, and 32.768khz oscillator. internal vbs power is supplied by vstby when it is valid and is supplied by vbat when vstby is not supplied. if vbat is not used, tie this pin to ground. 96 avss i analog ground for analog component 95 avcc i analog vcc for analog component notes: i/o cell types are described below: i: input pad. ai: analog input pad. ik: schmitt trigger input pad. ikd: schmitt trigger input pad (i ntegrated one pull-down resistor). piu: pci bus specified input pad (integrated one pull-up resistor). osci: oscillator input pad. ao: analog output pad. o2: 2 ma output pad. o4: 4 ma output pad. o6: 6 ma output pad. o8: 8 ma output pad. pio: pci bus specified bidirectional pad. oscio: oscillator bidirectional pad. aio2: 2 ma bidirectional pad with analog input pad. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 22 it8511 e /te / g iok2: 2 ma bidirectional pad with schmitt trigger input pad. iok4: 4 ma bidirectional pad with schmitt trigger input pad. iok6: 6 ma bidirectional pad with schmitt trigger input pad. iok8: 8 ma bidirectional pad with schmitt trigger input pad. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 23 pin descriptions 5.2 chip power planes and power states table 5-17. power states power state vcc pin vstby/avcc pin vbat pin internal vbs active supplied supplied supplied or not switched from vstby active with power saving supplied supplied ec is in idle, doze or sleep mode supplied or not switched from vstby standby not supplied supplied supplied or not switched from vstby standby with power saving not supplied supplied ec is in idle, doze or sleep mode supplied or not switched from vstby power fail not supplied not supplied supplied switched from vbs battery fail not supplied not supplied not supplied not supplied note: (1) the avcc should be derived from vstby. (2) all other combinations of vcc / vstby / vbat are invalid. (3) in power saving mode, 8032 program counter is stopped and no instruction will be executed no matter whether ec clock is running or not. (4) vbs is the battery-backed power . when vstby is valid, vbs is s upplied by vstby. when vstby is not valid, vbs is supplied by vbat. figure 5-1. power state transitions active standby with power saving active with power saving battery fail power fail standby (s3, s4, s5) ec firmware sets pcon bit reset or int0#, int1# asserted ec firmware sets pcon bit reset or int0#, int1# asserted vcc on vcc off vstby on vstby off vbat on vbat off vstby on vstby off vbat off vcc off vstby off free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 24 it8511 e /te / g 5.3 pin power planes and states table 5-18. quick table of power plane for pins power plane pins no. vcc 7-18 vstby otherwise vbs 158-161 in the following tables of this secti on, standby means that the vcc is not va lid but vstby is supplied (s3, s4 or s5) and ec is in normal operation. standby with sle ep means that 8032 and most of its functions are out of work due to pll powe r-down while vstby is still supplied. power fail means only batte ry-backed power is supplied. the abbreviations used in the following tables are described below: h means ec drives high or driven high. l means ec drives low or driven to low or output pin power off. z means ec tri-stated the i/o pin or output pin with enable. run means that output or i/o pins are in normal operation. driven means that the input pin is dr iven by connected chip or logic. stop means that the output pin keeps its l ogical level before the clock is stopped. off means i/o pin power off. note that reset sources of ?reset finish? columns depend on reset types and applied module table and it means the reset is finished when its corresponding power plane is supplied. note that gpio pins listed in different functional tabl es except gpio table indicate their pin status of the corresponding alternative function. table 5-19. pin states of lpc bus interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail lpcrst# (y) vstby driven l l l lpcclk vcc driven l l l lad[3:0] vcc run off off off lframe# vcc driven l l l serirq vcc z off off off lpcpd# (y) vstby driven l l l clkrun# (y) vstby driven off l off ecsmi# vstby run run z off ecsci# (y) vstby driven run z off ga20 (y) vstby driven run stop off kbrst# (y) vstby h run stop off wrst# vstby driven driven driven l pwureq# vstby z run stop off lpc80hl (y) vstby driven l l off lpc80ll (y) vstby driven l l off free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 25 pin descriptions table 5-20. pin states of external flash interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail fa[15:0] vstby run run afstby=1: depends on corresponding hardware strap on fa[15:0] afstby=0 stop off fa16 (y) fa17 (y) fa18 (y) fa19 (y) fa20 (y) fa21 (y) vstby l (pull-down) run afstby=1: l afstby=0 stop off fd[7:0] vstby run run afstby=1: z with pull-down afstby=0: stop off frd# vstby l run l off fwr# vstby h run h off fcs# vstby l run afstby=1: h afstby=0: l off table 5-21. pin states of keyboard matrix scan interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail kso[15:0] vstby l run stop off ksi[7:0] vstby driven driven driven l table 5-22. pin states of sm bus interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail smclk0 (y) smclk1 (y) vstby driven run z off smdat0 (y) smdat1 (y) vstby driven run z off table 5-23. pin states of ps/2 interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail ps2clk0 (y) ps2clk1 (y) ps2clk2 (y) ps2clk3 (y) vstby driven run z off ps2dat0 (y) ps2dat1 (y) ps2dat2 (y) ps2dat3 (y) vstby driven run z off free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 26 it8511 e /te / g table 5-24. pin states of pwm interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail pwm0 (y) pwm1 (y) pwm2 (y) pwm3 (y) pwm4 (y) pwm5 (y) pwm6 (y) pwm7 (y) vstby driven run stop off tach0 (y) tach1 (y) vstby driven driven driven off tmri0 (y) tmri1 (y) vstby driven driven driven off table 5-25. pin states of wake up control interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail wui0 (y) wui1 (y) wui2 (y) wui3 (y) wui4 (y) wui5 (y) wui6 (y) wui7 (y) vstby driven driven driven off pwrsw (y) vstby driven driven driven off ri1# (y) ri2# (y) vstby driven driven driven off ring# (y) vstby driven driven driven off pwrfail# (y) vstby driven driven driven off table 5-26. pin states of uart interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail rxd (y) vstby driven driven driven off txd (y) vstby driven run stop off table 5-27. pin states of cir interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail crx (y) vstby driven driven driven off ctx (y) vstby driven run stop off table 5-28. pin states of gpio interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail gpa0-gpi6 vstby driven z or by alternative function. stop off free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 27 pin descriptions table 5-29. pin states of adc input interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail adc[3:0] avcc driven driven driven l adc4 (y) adc5 (y) adc6 (y) adc7 avcc driven driven driven l adc8 avcc driven run run l adc9 avcc driven driven driven l table 5-30. pin states of dac output interface signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail dac[3:0] avcc l run run off table 5-31. pin states of clock signal (alt func of gpio ?) power plane reset finish standby standby with sleep power fail ck32k vbs driven run run run ck32ke vbs driven run run run ck32kout/gpc7 vstby driven run run off clkout/gpc0 vstby driven run stop off free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 28 it8511 e /te / g 5.4 pwrfail# interrupt to intc the firmware may use the pwrfail# to do some nec essary response if vstby is being lost. corresponded int0# has higher priority than int1#. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 29 pin descriptions 5.5 reset sources and types table 5-32. reset sources reset source description vbs power-up reset activated after vbs is power up vstby power-up reset activated after vstby is power up and pll is stable it takes t plls for pll stabling, and the exter nal flash must be ready before vstby power-up reset finish vcc power-up reset activated after vcc is power up warm reset activated if wrst# is asserted lpc hardware reset activated if lpcrst# is asserted super i/o software reset activated if sioswrst of pnpcfg is writing 1 watch dog reset activated if 8032 wdt or external wdt time-out table 5-33. reset types and applied module reset type sources applied module vbs region reset vbs power-up reset rtc, swuc host domain hardware reset warm reset, vcc power-up reset or lpc hardware reset lpc hardware reset may be unused see also hrsts in rsts register. lpc, pnpcfg, logical devices and ec2i host domain software reset super i/o software reset pnpcfg, logical devices and ec2i ec domain reset warm reset, vstby power-up reset or watch dog reset ec domain the wrst# should be driven low for at least t wrstw before going high (refer to table 10-3. warm reset ac table on page 298) . if the firmware wants to assert an ec domain reset, star t an internal of external watchdog without clearing its counter or write invalid data to ewdkeyr regist er (refer to ewdkeyen and ewdkeyr registers). if the firmware wants to determine the source of the last ec domain reset, use the reset scratch register (rstscr). 5.5.1 relative interrupts to intc ? interrupt to intc lpcrst# may come from pin lpcrst#/wui4/gpd2 or ring#/pwrfail#/lpcrst#/gpb7. both pins have another interrupt relative alternat ive function. lpcrst# can be treat ed as an orthogonal input and lpcrst# event can be handled in the same interrupt routine of another alternative function. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 30 it8511 e /te / g 5.6 chip power mode and clock domain table 5-34. clock types type description 32.768 k clock 32.768 khz generated by internal oscillator pll clock clock (frequency = freqp ll) generated by internal pll which feds 32.768 k. pll clock is also the base clock of flash interface. (freqpll is listed in table 10-1 on page 297.) ec clock it?s from internal pll and its frequency is listed in table 10-1 on page 297. 8032 clock the clock of internal timer/wdt is from ec clock. host lpc clock 33 mhz or slower from lpcclk pin and applied on host domain. see also slwpci bit in mbctrl register in the host side and shbr bit in hctrl2r register in ec side. the 8032 can enter idle/doze/sleep mode to reduce some power consumption. after entering the idle mode, timers and the watch dog timer of 8032 still work. afte r entering doze/sleep mode, clock of 8032 is stopped and internal timers are stopped but the external timer st ill works. after entering doze mode, ec domain clock is stopped and all internal timers are stopped. also see table 5-36 on page 33 for the details. the way to wake up 8032 from the idle mode is to enable in ternal or external interrupts, or hardware reset. the way to wake up 8032 from doze/sleep mode is to enable external interrupts or har dware reset. firmware may set pllctrl bit before setting pd bit to enter the sleep mode, since stopping pll can reduce more power consumption, but it takes more time to wake up from sleep mode due to waiting for pll being stable. the steps to enter and exit idle/doze/sleep are listed below: (a) set relative bits of ie register if they are cleared. (b) set channels of wuc which wants to wake up 8032 and disable unwanted channels. (c) set channels of intc which wants to wake up 8032 and disable unwanted channels. (d) set pllctrl bit for sleep mode, or clear it for doze mode. (e) set idl bit in pcon to enter the idle mode, or set pd bit in pcon to enter the doze/sleep mode. (f) 8032 waits for an interrupt to wake up. (g) after an interrupt is asserted, 8032 executes the corresponding interrupt routine and return the next instruction after setting pcon. the following figure describes the drivers and branches of the three clocks. in this figure, clk_32khz represents 32.768 k clock; clk_src a nd its branches represent ec clock; clk_ibus represents lpc clock. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 31 pin descriptions figure 5-2. clock tree internal oscillator internal pll it8512: 32.2mhz for lpc/fwh flash it8542/it8582: 9.2mhz for embedded parallel flash 32.768 hz clk_fnd pwmcg@cgctrl1r gating adccg@cgctrl1r gating kbscg@cgctrl1r gating gpiocg@cgctrl1r gating smbcg@cgctrl1r gating daccg@cgctrl1r gating pmccg@cgctrl2r gating kbccg@cgctrl2r gating ec2icg@cgctrl2r gating tmkcg@cgctrl2r gating smfig@cgctrl2r gating 8032 adc ps2 pwm kb scan smb gpio dac ec2i kbc pmc swuc smfi divider gating adcen@adccfg sclkdiv@adcctl adc operation adc analog circuit adc operation divider clk_ec clk_pwm_78khz clk_pwm pwmtm@ztier pwmcg@cgctrl1r gating clk_pwm_10mhz clk_pwm_10mhz 1 0 tachometer pwmtm@ztier clk_32hz 1 0 smartauto fan pwmtm@ztier clk_32khz clk_pwm 1 0 pwm prescaler clk_pwm_78khz clk_pwm_78khz 78.125khz gating ps2cg@cgctrl1r etwdcg@cgctrl1r gating etwd divider divider 1 khz 32 hz clk_32hz clk_1khz clk_32khz lpc, pnpcfg, ec2i, smfi, swuc, kbc, tmkbc, pmc 33 mhz clk_ibus clk_ec clk_32khz clk_1mhz clk_32hz counter ewdsrc@etwcfg 1 0 counter external watchdog external timer ck32k test pin ck32ke lpcclk etwd clk_32khz gating powen@dacctrl dac analog circuit etps@etpsr clk_plls clk_ec 8032 internal timer/wdt gating gating clk_fnd_lf clk_fnd_isa divider 9.2mhz 32.2mhz 9.2mhz clock generator clock generator clk_uc_isa clk_uc_lf clk_uc clock generator clock generator isa flash base clock lpc/fwh flash clock clk_lf clk_isa 32.768k clock ec clock host lpc clock exgcg@cgctrl2r gating circg@cgctrl2r gating smfig@cgctrl2r gating egpc cir tmkbc freqpll/freqec are listed in table 10-1 on page 297. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 32 it8511 e /te / g table 5-35. power saving by ec clock operation mode mode item description enter vstby is supplied and hardware reset done exit enter other modes normal 32.768 k clock on pll on ec domain clock driven by pll 8032 clock the same as ec domain clock comment power consumption can be reduced by selectively disabling modules (refer to ecpm module) enter set idl bit in pcon of 8032 exit interrupt from intc, interrupt from 8032 timer, watchdog reset or hardware reset idle 32.768 k clock on pll on ec domain clock driven by pll 8032 clock core: off internal timer/wdt: on comment power consumption can be reduced by selectively disabling modules (refer to ecpm module) enter set pd bit in pcon of 8032 exit interrupt from intc or hardware reset doze 32.768 k clock on pll on, clearing pllctrl of ecpm module is required ec domain clock driven by pll 8032 clock off comment power consumption can be reduced by selectively disabling modules (refer to ecpm module) enter set pd bit in pcon of 8032 exit interrupt from intc or hardware reset sleep 32.768 k clock on pll off, setting pllctrl of ecpm module is required ec domain clock driven by pll 8032 clock off comment power consumption can be reduced by selectively disabling modules (refer to ecpm module) note: the pd bit in pcon register may trigger the doze or sleep mode of ec domain. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 33 pin descriptions table 5-36. module status in each power state/clock operation power state and/or clock operation running module stopped module off module note active active with power saving lpc, pnpcfg, ec2i, host parts of smfi/ swuc/ kbc/ pmc/ rtc list host relative modules only standby standby with power saving lpc, pnpcfg, ec2i, host parts of smfi/ swuc/ kbc/ pmc/ bram list host relative modules only active with idle mode standby with idle mode all other ec modules 8032 internal timer/wdt 8032 core logic except its internal timer/wdt list ec modules only active with doze mode standby with doze mode all other ec modules 8032 list ec modules only active with sleep mode standby with sleep mode gpio, wuc and its sources, intc and its sources from running modules, swuc wakeup logic, pwm channel outputs, kbs, etwd, rtc all other ec modules list all power fail rtc all others list all battery fail all list all note: running module means this module works well. stopped module means this module is frozen because its clock is stopped. off module means this module is turned off due to power lost. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 34 it8511 e /te / g 5.7 pins with pull, schmitt-trigger or open-drain function table 5-37. pins with pull function pin pull function note ksi[7:0] programmable 75k pull-up resistor default off kso[15:0] programmable 75k pull-up resistor default off gpe4-e7 and their alternative functions programmable 75k pull-up resistor gpe0-e3 have no pull function default on/off refer to table 7-13 on page 181 . gpg0-g7 and their alternative functions programmable 75k pull-down resistor default on/off refer to table 7-13 on page 181 . all other gpio pins and their alternative functions programmable 75k pull-up resistor default on/off refer to table 7-13 on page 181 . fa[21:0], fd[7:0], fcs#, frd#, fwr# operational 75k pull-down resistor pull-down if power-saving fa[5:2] operational 75k pull-down resistor pull-down after vstby power on until its pin state is sampled for hardware strap function note: 75k ohm is typical value. refer to section 9 dc characteristics on page 295 for details table 5-38. pins with schmitt-trigger function pin pull function note all gpio pins except gpe0-e3 and their alternative functions fixed schmitt-trigger input ksi[7:0] fixed schmitt-trigger input warmrst# fixed schmitt-trigger input fd[7:0] fixed schmitt-trigger input table 5-39. signals with open-drain function signal open-drain function note serirq open-drain bi-directional signal clkrun# open-drain output signal kso[15:0] programmable open-drain output signal default is push-pull ps2clk0, ps2dat0 ps2clk1, ps2dat1 ps2clk2, ps2dat2 ps2clk3, ps2dat3 open-drain bi-directional signal smclk0, smdat0 smclk1, smdat1 open-drain bi-directional signal sci#, smi#, pwureq# open-drain output signal all gpio signals except gpe0-e3 and their alternative functions programmable open-drain output signal default is push-pull free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 35 pin descriptions 5.8 power consumption consideration ? each input pin should be driven or pulled input floating causes leakage current and should be prevented. pins can be pulled by an external pull resistor or internal pull for a pin with programmable pull. ? each output-drain output pin should be pulled if an output-drain output pin is not used and is not pulled by an external pull resistor or internal pull for a pin with programmable pull, make it drive low by the firmware. gpe*/gpk* have analog inputs as their alternative function, and these four pins can prevent leakage current by switching to the alternative function, too. ? each input pin which belongs to vstby power plane is connected or pulled up to vcc power plane such cases may cause leakage current when vcc is not supplied and a diode may be used to isolate leakage current from vstby to vcc. for example, use diodes for kbrst# and ga20 if they are connected to vcc logic of south-bridge. ? any pin which belongs to vstby power plane should not be pulled to vcc in most cases. it may cause a leakage current path when vcc is shut down. refer to the above consideration. ? program gpio ports as output mode as soon as possible any gpio port used in output mode should be programmed as soon as possible since this pin may not be driven (be floating) if its default value of pull is off. ? disable unnecessary pull in power saving mode prevent from driving a pin low or letting a pin be driven low but its pull high function is enabled in power saving mode. prevent from driving a pin high or letting a pin be driv en high but its pull low function is enabled in power saving mode. ? handle the connector if no cable is plugged into it the firmware or the hardware should prevent the wire co nnected to the connector from no driving if no cable is plugged into the connector such as ps/2 mouse and so on. ? disable unnecessary pull for a programmable pull pin pull control may be enabled for an input pin or an open-drain output pin and should be disabled for a push-pull output pin. pull control should be disabled if an external pull resistor exists. external pull resistor can control the pull current precisel y since the register value of the internal pull has large tolerance. refer to section 9 dc characteristics on page 295 for details. ? flash standby mode make flash enter standby mode to reduce power consumption if it is not used. it's controlled by afstby bit in fpcfg register. ? prevent accessing scratch ram bef ore entering power-saving mode there is unnecessary power consumption after scratc h ram is accessed in data space. read any other registers of external data memory once to prevent this condition. ? use doze mode rather than idle mode doze mode has less power consumption than idle m ode because 8032 internal timer/wdt clock is gated (stopped) in doze mode. firmware design using idle mode should be replaced with doze mode by replacing internal timer and watchdog by external timer and watchdog. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 36 it8511 e /te / g ? use sleep mode rather than doze mode sleep mode has less power consumption than doze mode because pll is power-down and ec clock is stopped in sleep mode, although most ec modules are not available. refer to table 5-36 on page 33 for the details. ? gate clock by module in ec domain all modules in ec domain are not clock gated in de fault but can be gated by module to get less power consumption. it?s controlled by cgctrl1r and cgctrl2r registers. ? power-down adc/dac analog ci rcuit if it is unnecessary. adc/dac analog circuits are power-down in def ault and should be activated only if necessary. adc analog circuit power-down is contro lled by adcen bit in adccfg register. dac analog circuit power-down is contro lled by powdn bit in dacctrl register. ? connect led cathode to output pin it doesn?t reduce total power consumption although it reduces power consumption of it8511. the advantage is to reduce the temperature of it85 11 and prevent the output pad fr om driving large current. figure 5-3. led connection v s t b y g p i o p i n g p i o p i n g o o d b a d free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 37 host domain functions 6. host domain functions 6.1 low pin count interface 6.1.1 overview the low pin count (lpc) is an interface for modern i sa-free system. it is defined in intel?s lpc interface specification, revision 1.1. there are seven host-cont rolled modules that can be accessed by the host via the lpc interface. these host-controlled modules are ?logical devices? defined in plug and play isa specification, version 1.0a. 6.1.2 features ? complies with intel?s lpc interface specification, revision 1.1 ? supports serirq and complies with serialized irq support for pci systems, revision 6.0 ? supports lpcpd#/clkrun# ? supports plug and play isa registers 6.1.3 accepted lpc cycle type the supported lpc cycle types are listed below: * lpc i/o read (16-bit address, 8-bit data) * lpc i/o write (16-bit address, 8-bit data) * trusted port read (16-bit address, 8-bit data) * trusted port write (16-bit address, 8-bit data) * lpc memory read (32-bit address, 8-bit data) * lpc memory write (32-bit address, 8-bit data) * fwh read (32-bit address, 8-bit data) * fwh write (32-bit address, 8-bit data) i/o cycles are used to access pnpcfg and logical device s. memory or fwh is used to access flash content through smfi module host-indirect memo ry cycles based on i/o cycles can also access flash. refer to smfi module for details about host-indirect memory access. the following table describes how lpc module responds the i/o, memory and fwh cycles from host side in different conditions. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 38 it8511 e /te/ g table 6-1. lpc/fwh response cycle type/condition read response write response all cycles before pll stable note 4 long-wait long-wait i/o cycle to pnpcfg or logical devices long-waits until ready long-waits until ready i/o cycle but address out of range cycle ignored cycle ignored i/o cycle to locked pnpcfg/rtc by ec2i returns 00h cycle ignored host-indirect memory address note 3 ready ready memory cycle, fwh cycle or host-indirect memory data long-waits until ready long-waits until ready note 1 memory cycle, fwh cycle or heres=00* long-wait cycle ignored host-indirect memory data heres=01 returns 00h cycle ignored but address protected by smfi heres=10 error-sync error-sync heres=11 long-wait error-sync memory cycle or host-indirect memory data but address out of range cycle ignored cycle ignored fwh cycle but address out of range ready ready fwh cycle but fwh id is unmatched note 2 cycle ignored cycle ignored lpc cycle or host-indirect memory data but lpcmen bit in shmc register cleared cycle ignored cycle ignored fwh cycle but fwhen bit in shmc register cleared cycle ignored cycle ignored note 1: after reset, it8511 responses long-waits before ready for fwh write cycle. if lpc host (south-bridge) fails to recognize long-wait sync during fwh write cycle, it is recommended to use host-indirect memory. note 2: fwh id is defined in fwhid field in shmc register. note 3: host-indirect memory cycles access the flash via lpc i/o cycle. host-indi rect memory address is combined with smimar0, smimar1, smimar2 and smimar3 regi sters. host-indirect me mory data is smimdr register. note 4: the host lpc interface is disabled in sleep mode. 6.1.4 debug port function lpc module implements two latch signals for main-board debug purpose. lpc i/o write cycles with address equal to 80h will cause the lpc module to assert lpc80hl and lpc80ll signals which provide a simple external logic to latch it in order to display on led, even though i/o port 80h is not recognized by pnpcfg or any logical device. lpc80hl goes high when it is time to latch the high-nibble of the data written to port 80h, and lpc80ll means the low-nibble. port 80h data can be read via parallel port with the software provided by ite. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 39 host domain functions 6.1.5 serialized irq (serirq) it8511 has programmable irq number for each logical device. av ailable irq numbers are 1, 2, 3, 4 5, 6, 7, 8, 9, 10, 11, 12, 14, and 15. different logical devices inside it8511 can share the same irq number if they have the same irqps bit in irqtp register and are configured as the same triggered mode (all level-triggered or all edge triggered) in their ec side registers. but it is not allowed to share an irq number with a logical device outside it8511. note that edge-triggered interrupts are not suitable for sharing in most cases. 6.1.6 relative interrupts to wuc ? interrupt to wuc if the lpc address of an i/o, lpc memory or fwh cycl e on lpc bus is accepted, wu42 interrupt will be asserted. 6.1.7 lpcpd# and clkrun# ? lpcpd# lpcpd# is used as internal ?power good? signal to indicate the status of vcc. it is recommend to be implemented. see also vccdo bit in rsts register in 7.14.4.5 on page 260. 6.1.8 check items if ec fails in lpc memory or i/o cycles at boot, check the following recommended items first. ? lpc/fwh memory cycles check whether corresponding gpio ports of necessary fa21-17 are switched to their alternative function. check whether lpcrst# reset source from gpd2 or gpb7 is logic low if it is in alternative function. check whether lpcpd# signal from gpe6 is l ogic low if it is in alternative function. check whether hardware strap shbm is enabled or set fwhen/lpcmen bit in shmc register. check whether the firmware doesn?t change the read protection control. ? lpc i/o cycles check whether lpcrst# reset source from gpd2 or gpb7 is logic low if it is in alternative function. check whether lpcpd# signal from gpe6 is l ogic low if it is in alternative function. check whether hardware strap bad dr1-0 are in correct setting. check whether ec2i is not locking pnpcfg access from the host side. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 40 it8511 e /te/ g 6.2 plug and play configuration (pnpcfg) the host interface registers of pnpcfg (plug and play configuration) are listed below. the base address can be configured via hardware strap baddr1-0. note that bit 0 of swcbalr must be zero. to access a register of pnpcfg, writ e target index to address port and access this pnpcfg register via data port. if accessing the data port without writing index to addr ess port, the latest value written to address port is used as the index. reading the address port regi ster returns the last value written to it. table 6-2. host view register map, pnpcfg baddr1-0 =00b baddr1-0 =01b baddr1-0 =10b baddr1-0 =11b 7 0 i/o port address address port 2eh 4eh (swcbahr, swcbalr) reserved data port 2fh 4fh (swcbahr, swcbalr+1) reserved note 1: swcbalr should be on boundary = 2, which means bit 0 must be 0. note 2: only use baddr1-0=10b if the port pair is not 2eh/2fh or 4eh/4fh. the host interface registers for logic device control are listed below. the base address can be configured via the following plug and play configuration registers. note that if a logica l device is activated but with base address equal to 0000h, the host side cannot access this logical device since 0000h means i/o address range is disabled. table 6-3. host view register map, logical devices 7 0 i/o port address system wake-up control (swuc) depend on pnp sw used addr: (iobad0+00h,+02h,+06h,+07h,13h,15h) base address boundary = 32 kbc / mouse interface unused kbc / keyboard interface depend on pnp sw used addr: (iobad0+00h), (iobad1+00h) base address boundary = none, none legacy address = 60h,64h shared memory/flash interface (smfi) depend on pnp sw used addr: (iobad0+0h, ?+8h,+0ch) base address boundary = 16 real time clock (rtc) depend on pnp sw used addr: (iobad0+0h,+1h), (iobad1+0h,+1h) base address boundary = 2, 2 legacy address = 70h-73h power management i/f channel 1 (pm1) depend on pnp sw used addr: (iobad0+0h), (iobad1+0h) base address boundary = none, none legacy address = 62h,66h power management i/f channel 2 (pm2) depend on pnp sw used addr: (iobad0+0h), (iobad1+0h) base address boundary = none, none legacy address = 68h,6ch note: the boundary number means the address must be the multiple of this number. the host interface registers for standard plug and play configuration of pnpcfg are listed below. these registers are accessed via the index-data i/o ports defined in table 6-3 on page 40. note pnpcfg registers are not allowed to be accessed if lkcfg bit in lsioha regi ster of ec2i module is set. they are divided into two parts, super i/o configuration registers and logical device registers. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 41 host domain functions table 6-4. host view register map via index-data i/o pair, standard plug and play configuration registers 7 0 index register name logical device number (ldn) 07h chip id byte 1(chipid1) 20h chip id byte 2(chipid2) 21h chip version (chipver) 22h super i/o control (sioctrl) 23h super i/o reserved 24h configuration super i/o irq configuration (sioirq) 25h registers super i/o general purpose (siogp) 26h reserved 27h reserved 28h reserved 29h reserved 2ah reserved 2bh super i/o power mode (siopwr) 2dh reserved 2eh logical device activate register (lda) 30h logical device i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 62h i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 63h selected by interrupt request number and wake-up on irq enable (irqnumx) 70h ldn register interrupt request type select (irqtp) 71h dma channel select 0 (dmas0) 74h dma channel select 0 (dmas1) 75h device specific logical device configuration 1 to 10 f0h-f9h the irq numbers for logic device irq via lpc/serir q are listed below. the irq numbers can be configured via the above plug and play configuration registers. table 6-5. interrupt request (irq) number assignment, logical device irq via serirq logical device irq number system wake-up control (swuc) depend on pnp sw kbc / mouse interface depend on pnp sw, legacy irq num=12 kbc / keyboard interface depend on pnp sw, legacy irq num=01 shared memory/flash interface (smfi) unused real time clock (rtc) depend on pnp sw, legacy irq num=08 power management i/f channel 1 (pm1) depend on pnp sw, legacy irq num=01 power management i/f channel 2 (pm2) depend on pnp sw, legacy irq num=01 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 42 it8511 e /te/ g 6.2.1 logical device assignment table 6-6. logical device number (ldn) assignments ldn functional block 04h system wake-up control (swuc) 05h kbc/mouse interface 06h kbc/keyboard interface 0fh shared memory/flash interface (smfi) 10h real time clock (rtc) 11h power management i/f channel 1 (pm1) 12h power management i/f channel 2 (pm1) the following figure indicates the pnpcfg registers is combined with super i/o configuration registers and logical device configuration registers. logical device c onfiguration registers of a specified logical device is accessable only when logical device number register is filled with corresponding logical device number listed in table 6-6 on page 42 . figure 6-1. host view register map via index-data pair select logical device (04h,05h,06h,0fh,10h,11h,12h) super i/o configuration registers special (vendor-defined) logical device configuration registers standard logical device configuration registers logical device number register logical device control register 07h 20h 2fh 30h 60h 75h f0h feh free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 43 host domain functions 6.2.2 super i/o configuration registers registers with index from 07h to 2eh c ontain super i/o configuration settings. 6.2.2.1 logical device number (ldn) this register contains general super i/o configurations. index: 07h bit r/w default description 7-0 r/w 04h logical device number (ldn) this register selects the current logical device. valid values are 04h, 05h, 06h, 0fh, 10h, 11h and 12h. all other values are reserved. 6.2.2.2 chip id byte 1 (chipid1) index: 20h bit r/w default description 7-0 r 85h chip id byte 1 (chipid1) this register contains the chip id byte 1. 6.2.2.3 chip id byte 2 (chipid2) index: 21h bit r/w default description 7-0 r 11h chip id byte 2 (chipid2) this register contains the chip id byte 2. 6.2.2.4 chip version (chipver) this register contains revision id of this chip index: 22h bit r/w default description 7-0 r 10h chip version (chipver) 6.2.2.5 super i/o control register (sioctrl) this register contains general super i/o configurations. index: 23h bit r/w default description 7-6 - 0h reserved 5-4 - 0h reserved 3-2 - 0h reserved 1 w 0b software reset (sioswrst) read always returns 0. 0: no action. 1: software reset the logical devices. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 44 it8511 e /te/ g bit r/w default description 0 r/w 1b super i/o enable (sioen) 0: all super i/o logical devices are disabled except swuc and smfi. 1: each super i/o logical device is enabled according to its activate register. (index 30h) 6.2.2.6 super i/o irq configuration register (sioirq) this register contains general super i/o configurations. index: 25h bit r/w default description 7-5 - 0h reserved 4 r/w 0b smi# to irq2 enable (smi2irq2) this bit enables using irq number 2 in the serirq protocol as a smi# interrupt. this bit is similar to ldact bit in lda register. 0: disabled 1: enabled 3-0 - 0h reserved 6.2.2.7 super i/o general purpose register (siogp) this register contains general super i/o configurations. index: 26h bit r/w default description 7 r/w 0b siogp software lock (sc6slk) 0: writing to bit 0-6 of siogp is allowed. other bits in this register can be cleared by hardware and software reset (sioswrst). 1: not allowed. bit 6-0 of this register are read-only. all bits in this register can be cleared by hardware reset only. 6-5 r/w 00b general-purpose scratch (gpscr) reading returns the value that was prev iously written. note that the ec side can access whole pnpcfg registers via ec2i. 4 r/w 0b rtc disabled (rtcde) 0: rtc is enabled according to its activate register and sioen bit in sioctrl register. 1: disabled 3-0 - 0h reserved 6.2.2.8 super i/o power mode register (siopwr) this register is a battery-backed regi ster used by the ec side. see also 6.4.5.2. index: 2dh bit r/w default description 7-2 - 0h reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 45 host domain functions bit r/w default description 1 r/w 0b power supply off (pwrsly) it indicates the ec side that the host requests to shut down the power in legacy mode. refer to scrdpso bit in swctl2 register on page 87 0: no action 1: it indicates power shut down if pwrsly is legacy mode. note: it always returns 0 when read. 0 r/w 0h power button mode (pwrbtn) this bit controls the power button mode in the swuc. refer to scrdpbm bit in swctl2 register on page 87 0: legacy 1: acpi 6.2.3 standard logical device configuration registers registers with index from 30h to f9h contain logical devi ce configuration settings. ld n of the wanted logical device should be written to ldn regist er before accessing these registers. this section lists a standard description of these regi sters. some default values for each register and more detailed information for each logical device should be referred in each section. 6.2.3.1 logical device activate register (lda) index: 30h bit r/w default description 7-1 - 0h reserved 0 r/w 0b logical device activation control (ldact) 0: disabled the registers (index 60h-feh) are not accessible. refer to sioen bit in sioctrl 1: enabled 6.2.3.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) this register will be read-only if it is unused by a logical device. the 16-bit base address must not be 0000h and migh t have the boundary limit for each logical device. index: 60h bit r/w default description 7-0 r/w depend on logical device i/o port base address bits [15:8] for descriptor 0 (ioba[15:8]) this register indicates selected i/o base address bits 15-8 for i/o descriptor 0. 6.2.3.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) this register will be read-only if it is unused by a logical device. the 16-bit base address must not be 0000h and migh t have the boundary limit for each logical device. index: 61h bit r/w default description 7-0 r/w depend on logical device i/o port base address bits [7:0] for descriptor 0 (ioba[7:0]) this register indicates selected i/o base address bits 7-0 for i/o descriptor 0. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 46 it8511 e /te/ g 6.2.3.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) this register will be read-only if it is unused by a logical device. the 16-bit base address must not be 0000h and migh t have the boundary limit for each logical device. index: 62h bit r/w default description 7-0 r/w depend on logical device i/o port base address bits [15:8] for descriptor 1 (ioba[15:8]) this register indicates selected i/o base address bits 15-8 for i/o descriptor 1. 6.2.3.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) this register will be read-only if it is unused by a logical device. the 16-bit base address must not be 0000h and migh t have the boundary limit for each logical device. index: 63h bit r/w default description 7-0 r/w depend on logical device i/o port base address bits [7:0] for descriptor 0 (ioba[7:0]) this register indicates selected i/o base address bits 7-0 for i/o descriptor 1. 6.2.3.6 interrupt request number a nd wake-up on irq enable (irqnumx) this register will be read-only if it is unused by a logical device. index: 70h bit r/w default description 7-5 - 0h reserved 4 r/w 0 wake-up irq enable (wkirqen) allow this logical device to trigger a wake-up event to swuc. this bit should not be set in swuc logical device since it is used to collect irq sources for swuc. 0: disabled 1: enabled 3-0 r/w depend on logical device irq number (irqnum) select the irq number (level) assert ed by this logical device via serirq. 00d: this logical device doesn?t use irq. 01d-012d: irq1-12 are selected correspondingly. 14d-15d: irq14-15 are selected correspondingly. otherwise: invalid irq routing configuration. 6.2.3.7 interrupt request type select (irqtp) this register will be read-only if it is unused by a logical device. index: 71h bit r/w default description 7-2 - 0h reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 47 host domain functions bit r/w default description 1 r/w depend on logical device interrupt request pola rity select (irqps) this bit indicates the polarity of the interrupt request. 0: irq request is buffered and applied on serirq. 1: irq request is inverted before being applied on serirq. this bit should be configured before the logical device is activated. 0 r/w depend on logical device interrupt request triggered mode select (irqtms) this bit indicates that edge or level triggered mode is used by this logical device and should be updated by ec firm ware via ec2i since the triggered mode is configured in ec side registers. this bit is just read as previously written (scratch register bit) and doesn?t affect serirq operation. 0: edge triggered mode 1: level triggered mode 6.2.3.8 dma channel select 0 (dmas0) index: 74h bit r/w default description 7-3 - 0h reserved 2-0 r 4h dma channel select 0 a value of 4 indicates that no dma channel is active. 6.2.3.9 dma channel select 0 (dmas1) index: 75h bit r/w default description 7-3 - 0h reserved 2-0 r 4h dma channel select 1 a value of 4 indicates that no dma channel is active. 6.2.4 system wake-up control (swuc) configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-7. host view register map via index-data i/o pair , swuc logical device 7 0 index register name super i/o control reg logical device number (ldn = 04h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8])-unused 62h i/o port base address bits [7:0] fo r descriptor 1 (iobad1[7:0]) -unused 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=04h interrupt request type select (irqtp) 71h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 48 it8511 e /te/ g 6.2.4.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. 6.2.4.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. 6.2.4.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) index: 61h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.3 on page 45. bits 4-0 (iobad0[4:0]) are forced to 00000b and can?t be written. it means the base address is on the 32-byte boundary. 6.2.4.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) this register is unused and read-only. index: 62h bit r/w default description 7-0 r 00h refer to section 6.2.3.4 on page 46. 6.2.4.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) this register is unused and read-only. index: 63h bit r/w default description 7-0 r 00h refer to section 6.2.3.5 on page 46. 6.2.4.6 interrupt request number a nd wake-up on irq enable (irqnumx) index: 70h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.6 on page 46. 6.2.4.7 interrupt request type select (irqtp) index: 71h bit r/w default description 7-0 r/w 03h refer to section 6.2.3.7 on page 46. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 49 host domain functions 6.2.5 kbc / mouse interface configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-8. host view register map via index-da ta i/o pair, kbc / mouse interface logical device 7 0 index register name super i/o control reg logical device number (ldn = 05h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) ?unused 60h and configuration i/o port base address bits [7:0] fo r descriptor 0 (iobad0[7:0]) ?unused 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) ?unused 62h i/o port base address bits [7:0] fo r descriptor 1 (iobad1[7:0]) ?unused 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=05h interrupt request type select (irqtp) 71h 6.2.5.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. 6.2.5.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) this register is unused and read-only. index: 60h bit r/w default description 7-0 r 00h refer to section 6.2.3.2 on page 45. 6.2.5.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) this register is unused and read-only. index: 61h bit r/w default description 7-0 r 00h refer to section 6.2.3.3 on page 45. 6.2.5.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) this register is unused and read-only. index: 62h bit r/w default description 7-0 r 00h refer to section 6.2.3.4 on page 46. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 50 it8511 e /te/ g 6.2.5.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) this register is unused and read-only. index: 63h bit r/w default description 7-0 r 00h refer to section 6.2.3.5 on page 46. 6.2.5.6 interrupt request number a nd wake-up on irq enable (irqnumx) index: 70h bit r/w default description 7-0 r/w 0ch refer to section 6.2.3.6 on page 46. 6.2.5.7 interrupt request type select (irqtp) index: 71h bit r/w default description 7-0 r/w 03h refer to section 6.2.3.7 on page 46. 6.2.6 kbc / keyboard interface configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-9. host view register map via index-data i/o pair, kbc / keyboard interface logical device 7 0 index register name super i/o control reg logical device number (ldn = 06h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 62h i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=06h interrupt request type select (irqtp) 71h 6.2.6.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. 6.2.6.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. bits 7-3 (iobad0[15:11]) are forc ed to 00000b and can?t be written. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 51 host domain functions 6.2.6.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) index: 61h bit r/w default description 7-0 r/w 60h refer to section 6.2.3.3 on page 45. 6.2.6.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) index: 62h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.4 on page 46. bits 7-3 (iobad1[15:11]) are forc ed to 00000b and can?t be written. 6.2.6.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) index: 63h bit r/w default description 7-0 r/w 64h refer to section 6.2.3.5 on page 46. 6.2.6.6 interrupt request number a nd wake-up on irq enable (irqnumx) index: 70h bit r/w default description 7-0 r/w 01h refer to section 6.2.3.6 on page 46. 6.2.6.7 interrupt request type select (irqtp) index: 71h bit r/w default description 7-0 r/w 03h refer to section 6.2.3.7 on page 46. 6.2.7 shared memory/flash interface (smfi) configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-10. host view register map via index-data i/o pair, smfi interface logical device 7 0 index register name super i/o control reg logical device number (ldn = 0fh) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8])-unused 62h i/o port base address bits [7:0] fo r descriptor 1 (iobad1[7:0])-unused 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) ?unused 70h ldn register=0fh interrupt request type select (irqtp) -unused 71h shared memory configuration register (shmc) f4h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 52 it8511 e /te/ g 6.2.7.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. 6.2.7.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. 6.2.7.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) index: 61h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.3 on page 45. bits 3-0 (iobad0[3:0]) are forced to 0000b and can?t be written. it means the base address is on the 16-byte boundary. 6.2.7.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) this register is unused and read-only. index: 62h bit r/w default description 7-0 r 00h refer to section 6.2.3.4 on page 46. 6.2.7.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) this register is unused and read-only. index: 63h bit r/w default description 7-0 r 00h refer to section 6.2.3.5 on page 46. 6.2.7.6 interrupt request number a nd wake-up on irq enable (irqnumx) this register is unused and read-only. index: 70h bit r/w default description 7-0 r 00h refer to section 6.2.3.6 on page 46. 6.2.7.7 interrupt request type select (irqtp) this register is unused and read-only. index: 71h bit r/w default description 7-0 r 00h refer to section 6.2.3.7 on page 46. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 53 host domain functions 6.2.7.8 shared m emory configuration register (shmc) index: f4h bit r/w default description 7-4 r/w 0h bios fwh id (fwhid) these bits correspond to the 4-bit id which is part of a fwh transaction. 3 - - reserved 2 - - reserved 1 r/w 0b bios extended space enable (biosexts) this bit expands the bios address space to make this chip response the extended bios address range. 0 - - reserved 6.2.8 real time clock (rtc) configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-11. host view register map via index-data i/o pair, rtc logical device 7 0 index register name super i/o control reg logical device number (ldn = 10h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 62h i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=10h interrupt request type select (irqtp) 71h ram lock register (rlr) f0h date of month alarm register offset (domao) f1h month alarm register offset (monao) f2h p80l begin index (p80lb) f3h p80l end index (p80le) f4h p80l current index (p80lc) f5h 6.2.8.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. refer to sioen bit in sioctrl and sioen bit in sioctrl register. 6.2.8.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 54 it8511 e /te/ g 6.2.8.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) index: 61h bit r/w default description 7-0 r/w 70h refer to section 6.2.3.3 on page 45. bit 0 (iobad0[0]) is forced to 0b and can?t be written. it means the base address is on the 2-byte boundary. 6.2.8.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) index: 62h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.4 on page 46. 6.2.8.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) index: 63h bit r/w default description 7-0 r/w 72h refer to section 6.2.3.5 on page 46. bit 0 (iobad0[0]) is forced to 0b and can?t be written. it means the base address is on the 2-byte boundary. 6.2.8.6 interrupt request number a nd wake-up on irq enable (irqnumx) index: 70h bit r/w default description 7-0 r/w 08h refer to section 6.2.3.6 on page 46. 6.2.8.7 interrupt request type select (irqtp) index: 71h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.7 on page 46. 6.2.8.8 ram lock register (rlr) index: f0h bit r/w default description 7 r/w 0b block standard ram r/w (cmossrw) 0: r/w to 38h-3fh of the standard ram is allowed. 1: not allowed. writes are ignored and reads return ffh. 6 r/w 0b block ram write (cmosw) 0: write to standard and extended ram is allowed. 1: not allowed. writes are ignored. 5 r/w 0b block extended ram write (cmosew) 0: write to bytes 00h-1fh of the extended ram is allowed. 1: not allowed. writes are ignored. 4 r/w 0b block extended ram read (cmoser) 0: read from bytes 00h-1fh of the extended ram is allowed. 1: not allowed. reads return ffh. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 55 host domain functions bit r/w default description 3 r/w 0b block extended ram r/w (cmoserw) 0: r/w to the extended ram 128 bytes is allowed. 1: not allowed. writes are ignored and reads return ffh 2-0 - 0h reserved 6.2.8.9 date of month alarm register offset (domao) index: f1h bit r/w default description 7 - 0b reserved 6-0 r/w 49h date of month alarm register offset (domao) it contains the index offset of ?date of month alarm?. 6.2.8.10 month alarm register offset (monao) index: f2h bit r/w default description 7 - 0b reserved 6-0 r/w 4ah month alarm register offset (monao) it contains the index offset of ?month alarm?. 6.2.8.11 p80l begin index (p80lb) index: f3h bit r/w default description 7 - - reserved 6-0 r/w - p80l begin index (p80lbi) it indicates the p80l queue begins in rtc sram bank 1. refer to section 6.8.3.4 p80l on page 119. 6.2.8.12 p80l end index (p80le) index: f4h bit r/w default description 7 - - reserved 6-0 r/w - p80l end index (p80lei) it indicates the p80l queue ends in rtc sram bank 1. refer to section 6.8.3.4 p80l on page 119. 6.2.8.13 p80l current index (p80lc) index: f5h bit r/w default description 7 - - reserved 6-0 r/w - p80l current index (p80lc) it indicates the p80l queue current in rtc sram bank 1. refer to section 6.8.3.4 p80l on page 119. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 56 it8511 e /te/ g 6.2.9 power management i/f channel 1 configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-12. host view register map via index-data i/o, pm1 logical device 7 0 index register name super i/o control reg logical device number (ldn = 11h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 62h i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 63h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=11h interrupt request type select (irqtp) 71h 6.2.9.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. 6.2.9.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) it contains data register base address register. index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. bits 7-3 (iobad0[15:11]) are forc ed to 00000b and can?t be written. 6.2.9.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) it contains data register base address register. index: 61h bit r/w default description 7-0 r/w 62h refer to section 6.2.3.3 on page 45. 6.2.9.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) it contains command/status register base address register. index: 62h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.4 on page 46. bits 7-3 (iobad1[15:11]) are forc ed to 00000b and can?t be written. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 57 host domain functions 6.2.9.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) it contains command/status register base address register. index: 63h bit r/w default description 7-0 r/w 66h refer to section 6.2.3.5 on page 46. 6.2.9.6 interrupt request number a nd wake-up on irq enable (irqnumx) index: 70h bit r/w default description 3-0 r/w 01h refer to section 6.2.3.6 on page 46. 6.2.9.7 interrupt request type select (irqtp) index: 71h bit r/w default description 7-2 r/w 03h refer to section 6.2.3.7 on page 46. 6.2.10 power management i/f channel 2 configuration registers this section lists default values for each register and more detailed information for this logical device. some register bits will be read-only if unused. table 6-13. host view register map via index-data i/o, pm2 logical device 7 0 index register name super i/o control reg logical device number (ldn = 12h) 07h logical device activate register (lda) 30h logical device control i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 60h and configuration i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 61h registers i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 62h i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 63h i/o port base address bits [15:8] for descriptor 2 (iobad2[15:8]) 64h i/o port base address bits [7:0 ] for descriptor 2 (iobad2[7:0]) 65h selected if interrupt request number and wake-up on irq enabled (irqnumx) 70h ldn register=12h interrupt request type select (irqtp) 71h 6.2.10.1 logical device activate register (lda) index: 30h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.1 on page 45. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 58 it8511 e /te/ g 6.2.10.2 i/o port base address bits [1 5:8] for descriptor 0 (iobad0[15:8]) it contains data register base address register. index: 60h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.2 on page 45. bits 7-3 (iobad0[15:11]) are forc ed to 00000b and can?t be written. 6.2.10.3 i/o port base address bits [7:0] for descriptor 0 (iobad0[7:0]) it contains data register base address register. index: 61h bit r/w default description 7-0 r/w 68h refer to section 6.2.3.3 on page 45. 6.2.10.4 i/o port base address bits [1 5:8] for descriptor 1 (iobad1[15:8]) it contains command/status register base address register. index: 62h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.4 on page 46. bits 7-3 (iobad1[15:11]) are forc ed to 00000b and can?t be written. 6.2.10.5 i/o port base address bits [7:0] for descriptor 1 (iobad1[7:0]) it contains command/status register base address register. index: 63h bit r/w default description 7-0 r/w 6ch refer to section 6.2.3.5 on page 46. 6.2.10.6 i/o port base address bits [1 5:8] for descriptor 2 (iobad2[15:8]) it contains command/status register base address register. index: 64h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.4 on page 46. 6.2.10.7 i/o port base address bits [7:0] for descriptor 2 (iobad2[7:0]) it contains command/status register base address register. index: 65h bit r/w default description 7-0 r/w 00h refer to section 6.2.3.5 on page 46. bits 3-0 (iobad2[3:0]) are forced to 0000b and can?t be written. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 59 host domain functions 6.2.10.8 interrupt request number and wake-up on irq enable (irqnumx) index: 70h bit r/w default description 7-0 r/w 01h refer to section 6.2.3.6 on page 46. 6.2.10.9 interrupt request type select (irqtp) index: 71h bit r/w default description 7-0 r/w 03h refer to section 6.2.3.7 on page 46. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 60 it8511 e /te/ g 6.2.11 programming guide host side to read or write the target register (tr) at target address(ta) of pnpcfg approach 1 hw strap baddr=00 write ta to io port 2eh by lpc io cycle read or write tr at io port 2fh by lpc io cycle host side to read or write the target register (tr) at target address(ta) of pnpcfg approach 2 hw strap baddr=01 write ta to io port 4eh by lpc io cycle read or write tr at io port 4fh by lpc io cycle host side to read or write the target register (tr) at target address(ta) of pnpcfg approach 3 hw strap baddr=03 write ta to io port (swcbahr,swxbalr) by lpc io cycle read or write tr at (swcbahr,swxbalr+1) by lpc io cycle host side to read or write the target register (tr) at target index (ti) of pnpcfg ti = 00h~2eh (assume baddr=00) write ti to io port 2eh by lpc io cycle read or write tr at io port 2fh by lpc io cycle host side to read or write the target register (tr) at target index(ti) of pnpcfg ti=30h~feh, belongs to target logical device (tld) (assume baddr=00) write 07h to io port 2eh by lpc io cycle write tld to io port 2fh by lpc io cycle write ti to io port 2eh by lpc io cycle read or write tr at io port 2fh by lpc io cycle free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 61 host domain functions figure 6-2. program flow chart for pnpcfg to active the target l ogical device (tld) of pnpcfg write 07h to io port 2eh by lpc io cycle write tld to io port 2fh by lpc io cycle write 60h to io port 2eh write a new value to io port 2fh if the default value is not wanted rtc and smfi logical device have more special registers to be filled note: to enable an interrupt to host side through serirq, the firmware enables it in registers at pnpcfg and relative registers in ec side. write 62h to io port 2eh write a new value to io port 2fh if the default value is not wanted write 70h to io port 2eh write a new value to io port 2fh if the default value is not wanted write 61h to io port 2eh write a new value to io port 2fh if the default value is not wanted write 63h to io port 2eh write a new value to io port 2fh if the default value is not wanted write 71h to io port 2eh write a new value to io port 2fh if the default value is not wanted write 30h to io port 2eh write 01h to io port 2fh to active this logical device iobad0 iobad0 iobad1 iobad0 irqnumx iobad1 lda see also section 7.12.5 on page 252 for accessing pnpcfg through ec2i. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 62 it8511 e /te/ g 6.3 shared memory flash interface bridge (smfi) 6.3.1 overview the bridge provides the host to access the shared memo ry. it also provides ec code address space mapped into host domain address space, and locking mechanism for read/write protection. 6.3.2 features ? supports memory mapping between host domain and ec domain ? supports read/write/erase flash operations and locking mechanism ? supports two shared memory access paths: host and ec ? supports parallel flash and up to 4m bytes 6.3.3 function description 6.3.3.1 supported flash it8511 ? parallel flash: requirement: the first instruction of the firmware must be ?ljmp/ajmp/sjmp?. requirement: ?read cycle time? and ?write cycle time? of the flash/eprom have to be faster than or equal to t frdd (refer to table 10-9. flash read cycle ac table). 6.3.3.2 host to m bus translation the smfi provides an interface between the host bus a nd the m bus. the flash is mapped into the host memory address space for host accesses. the flash is also mapped into the ec memory address space for ec accesses. an m bus transaction is generated by the host bus translations and has the following three types: x 8-bit lpc memory read/write x 8-bit fwh read/write x 8-bit host-indirect memory read/write after the lpc address translation is done, the host memory tr ansaction is forwarded to m- bus (flash interface) if it is accessing an unprotected region. the host side can?t issue a write transaction until the firmware write 1 to hostwa bit smeccs register. see also table 3-3 on page 8. 6.3.3.3 memory mapping the host memory addresses are mapped into the follow ing regions shown in the following table. some regions are always mapped and some are mapped only when the corresponding register is active. and these regions may be mapped into the same range in the flash space. see also table 3-1 on page 7. table 6-14. mapped host memory address memory address range (byte) region description ffc0_0000h-ffff_ffffh 386 mode bios range this is the memory space whose maximum value is up to 4m bytes. if the flash size defined in fmssr register is smaller than 4m bytes, the remaining space is treated as ?out of range? free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 63 host domain functions memory address range (byte) region description 000f_0000h-000f_ffffh legacy bios range the total is 64k inside lower 1m legacy bios range. 000e_0000h-000e_ffffh extended legacy bios range the total is 64k inside lower 1m legacy bios range. the following memory transactions are based on lp c, fwh or i/o cycles which are valid only when corresponding lpcmen/fwhen bit in shmc register is enabled. legacy bios range always handle. extended legacy bios range handle only when biosexts bit in sh mc register is active. otherwis e, transactions are ignored. 386 mode bios range always handle. host-indirect memory address host-indirect memory cycles are memory transactions based on lpc i/o cycles. this address specified in sm imar3-0 is used as follows: translated 32-bit host address = { smimar3[7: 0], smimar2[7:0], smimar1[7;0], smimar0[7:0]} 6.3.3.4 host-indirect memory read/write transaction the following i/o mapped registers can be used to perform an m bus transaction using an lpc i/o transaction: ? host-indirect memory address registers (smimar 3-0) stand for host address bit 31 to 0. ? host-indirect memory data register (smimdr) stand for read or write data bit 7 to 0. when lpc i/o writes to imd register, smfi begins a flash read with smimar3-0 as the addresses. it8511 responses long-waits until the transaction on m-bus (flash interface) is completed. when lpc i/o read cycle from smimdr register begins a flash write with using the smimar3-0 as the address. the data back from smimdr register is us ed to complete the lpc i/o read cycle. host-indirect memory read/write transactions use t he same memory mapping and locking mechanism as the lpc memory read/write transactions. 6.3.3.5 ec-indirect memory read/write transaction r8032tt in it8511 can access a full flash address range via "movx" instruction. this kind of access is useful to 1. read flash id for ec bios 2. customize user-defined flash programming interface 3. put extra bios data outside ec 64k ? ec-indirect memory address registers (ecindar3-0) stand for flash address bit 31 to 0. ? ec-indirect memory data register (ecinddr) stand for read or write data bit 7 to 0. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 64 it8511 e /te/ g 6.3.3.6 locking between host and ec domains a hardware arbiter handles flash read/write translation between the host and ec side. normally the grant is parked on the ec side and switches to the host si de when the memory transaction is on lpc bus. if the ec side is code fetching, any host access will be deferred or aborted depending on heres bit in smeccs register. if the host side is accessing, the ec side is pending to code fetch. when the host wants to erase or program the flash, the signaling interface (semaphore write or kbc/pmc extended command) notifies the firmware to write 1 to host wa bit in smeccs register and relative register listed in table 3-3 on page 8. ec 8032 should fail to code fetch due to flash busying with erasing/programming and scratch rom should be applied (see also section 6.3.3.9). once the host accessing to the flash is completed, the host should indicate this to the ec, allowing ec to clear hostwa bit and resume normal operation. the ec can clear hostwa bit at any time, and prevent the host from issuing any erase or program operations. 6.3.3.7 host access protection the software can use a set of registers in ec side to control the host read/write protection functionality. the ec can override the host settings and prevent host fr om accessing to certain regi ons of the shared memory. the override may be set individuality for read and write. after reset, all memory ranges are allowed host read but inhibited to write (erase/program). 6.3.3.8 response to a forbidden access a forbidden access is generated by a tran slated host address which is protected. the ec responds to a forbidden access by generati ng an interrupt int23 (if enabled by herrien bit in smeccs register). hwerr and hrerr in the smeccs register indicate t he forbidden access to write or read respectively .the response on the host bus is according to heres field in smecss register. heres field 00b: drive long wait for read; ignore write 01b: read back 00h; ignore write 10b: drive error sync for both read and write 11b: read back long sync; write back error sync 6.3.3.9 scratch sram there are five internal scratch sram no 0-4 whic h are always mapped into da ta space and may be mapped into code space if their corresponding code space mappi ng registers are enabled. it also means that scratch sram may be mapped into data and code space at the same time and the firmware on scratch rom can access the same scratch ram. it is called scratch ram when being located at data space (default after reset) and called scratch rom when being located at code space. each of these five scratch sram can be mapped into code space with any base addresses without the boundary limit. more than one scratch sram no. can be mapped into code space with an overlay range. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 65 host domain functions figure 6-3. scratch sram in data space scratch sram no 1. (1024 bytes) scratch sram no 2. ( 512 bytes) scratch sram no 3. ( 256 bytes) scratch sram no 4. ( 256 bytes) 0000h 0800h 0c00h 0e00h 1000h 0f00h scar0h/scar0/scar0l code space mapping register set scratch sram no. scratch ram data space address scar4h/scar4/scar4l scar3h/scar3/scar3l scar2h/scar2/scar2l scar1h/scar1/scar1l scratch rom code space address scratch sram no 1. (1024 bytes) scratch sram no 0. (2048 bytes) 00_0000h 02_8000h 02_7fffh scratch sram no 1. (1024 bytes) scratch sram no 2. ( 512 bytes) scratch sram no 3. ( 256 bytes) scratch sram no 4. ( 256 bytes) scratch sram no 0. (2048 bytes) scratch sram no 0. (2048 bytes) each scratch sram no. has three corresponding code space mapping registers in figure 6-3. scratch sram in data space. to enable a scratch sram to be mapped into code space, refer to the following steps with code space mapping registers. for scratch sram no. 0: sc0a17-0 field (18-bit) is the base address of scratch sram no. 0 and has been translated according to ?mapped flash address range? field in table 3-2. ec/flash mapping on page 8. also refer to ecbb field in fecbsr register on page 69. the base address in sc0a17-0 field is only valid if it is between 00_0000h and 02_7fffh. to enable the code space mapping of scratch no. 0: make sc0a17-0 field between 00_0000h and 02_7fffh. to disable the code space mapping of scratch no. 0: write 11b to sc0a17-16 field. scratch sram no.0 is always located in data space regardless of mapping into code space. so is scratch sram no. 1-4. this ssmc bit in fbcfg register is ob solete. this register bit is only used to be compatible with old it8510 firmware and should not be used in new firmware. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 66 it8511 e /te/ g 6.3.3.10 dma for scratch sram dma (direct memory access) is used to shadow flash content of a specified addr ess range inside code space to scratch sram. the performance of dma is much better than ?movc-movx? steps. to enable dma operation to scratch sram no. 0, please follow the steps below: 1. write data to scarh register with wanted sc0a17-16 field and 1 to nsdma bit. 2. write data to scar0l register with wanted sc0a7-0 field. 3. write data to scar0m register with wanted sc0a15-8 field. 4. write data to scarh register with wanted sc0a17-16 field and 0 to nsdma bit. dma operation is started and code space mapping is enabled after dma operation is finished. if the firmware wants to modify the mapped base addre ss in code space, more steps below should be taken: 5. write data to scar0h register with 11b to sc0a17-16 field. disable code space mapping first since sc0a17-0 are modified in three writings and may be invalid before writing is completed. 6. write data to scar0m/scar0l regi ster with wanted sc0a15-0 field. 7. write data to scar0h register with wanted sc0a17-16 field. enable code space mapping after this step. so is scratch sram no. 1-4. see also 7.1.10.3 code snippet of copying flash content to scratch rom (dma) on page 156. 6.3.3.11 trusted rom/ram trusted rom and ram are dedicated for tmbkc firmware. trusted rom is where tm kbc firmware locates. if tmkbcen bit in cnf register is asserted, tm kbc, ps/2 and kbs modules can not be accessed by the firmware unless the firmware is executing from trusted rom. the firmware is treated as trusted rom if 1. it is located inside the trusted rom range defined in tromr register. 2. it is fetched from the flash, or scratch rom is shadowed by dma without modifying its mapped base address. trusted ram is scratch ram that has asserted trust flag. only trus ted rom can access trusted ram. 6.3.3.12 flash programming via host lpc interface with scratch sram when programming flash is processing, the flash will be busy and code fetch from flash by 8032 and will be invalid and cause 8032 fail to execute instructions. it mean s the firmware must copy nec essary instructions from code space to scratch sram, enable mapping scratch sram to scratch rom, and jump to scratch rom before programming flash. flash programming steps: (a) the host side communicates to the ec side via kbc/pmc extended or semaphore registers (b) ec side: write 1 to hostwa bit in smeccs register (c) ec side: write 0 to smecowpr0-9 (for example, 4-m bytes range) (refer to table 3-3. flash read/write protection controlled by ec side on page 8) (d) ec side: copy necessary code to sc ratch ram (by movc-movx steps or dma) (e) ec side: enable code space mapping of scratch sram (f) ec side: make the host processor enter smm mode if necessary (g) ec side: jump instruction to scratch rom free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 67 host domain functions (h) host side: set relative memory-write registers in south-bridge (i) host side: start flash programming (j) end flash programming and reset ec domain if necessary. (refer to section 5.5 on page 29) note: do not let ec enter the idle/doze/sleep mode while processing flash programming flow. 6.3.4 ec interface registers the registers of smfi can be divided into two parts: host interface regi sters and ec interface registers and this section lists the ec interface. the ec interface can only be accessed by the internal 8032 processor. the base address for smfi is 1000h. these registers are listed below. table 6-15. ec view register map, smfi 7 0 offset fbiu configuration (fbcfg) 00h flash programming configuration register (fpcfg) 01h flash ec code banking select register (fecbsr) 05h flash memory size select register (fmssr) 07h shared memory ec control and status (smeccs) 20h shared memory host semaphore (smhsr) 22h shared memory ec override re ad protect 0-1 (smecorpr0-1) 23h-24h shared memory ec override wr ite protect 0-1 (smecowpr0-1) 29h-2ah reversed 30h reversed 31h reversed 32h reserved 33h reserved 34h host control 2 register (hctrl2r) 36h trusted rom register (tromr) 37h ec-indirect memory address register 0 (ecindar0) 3bh ec-indirect memory address register 1 (ecindar1) 3ch ec-indirect memory address register 2 (ecindar2) 3dh ec-indirect memory address register 3 (ecindar3) 3eh ec-indirect memory data register (ecinddr) 3fh scratch sram 0 address low byte register (scar0l) 40h scratch sram 0 address middle byte register (scar0m) 41h scratch sram 0 address high byte register (scar0h) 42h scratch sram 1 address low byte register (scar1l) 43h scratch sram 1 address middle byte register (scar1m) 44h scratch sram 1 address high byte register (scar1h) 45h scratch sram 2 address low byte register (scar2l) 46h scratch sram 2 address middle byte register (scar2m) 47h scratch sram 2 address high byte register (scar2h) 48h scratch sram 3 address low byte register (scar3l) 49h scratch sram 3 address middle byte register (scar3m) 4ah scratch sram 3 address high byte register (scar3h) 4bh scratch sram 4 address low byte register (scar4l) 4ch scratch sram 4 address middle byte register (scar4m) 4dh scratch sram 4 address high byte register (scar4h) 4eh free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 68 it8511 e /te/ g 6.3.4.1 fbiu configuration register (fbcfg) the fbiu (flash bus interface unit) directly interfaces with the flash device. the fb iu also defines the access time to the flash base address from 00_0000h to 3f_ ffffh (4m bytes). ewr bit controls memory cycles on m-bus (flash interface). address offset: 00h bit r/w default description 7 r/w 0b scratch sram map control (ssmc) 0: normal 1: scratch sram no. 0, whose size is 2k bytes, is mapped into f800h-ffffh in code space and overrides the settings in scar0h/scar0m/scar0l register. this bit is obsolete and only used to be compatible with old it8510 firmware and should not be used in new firmware. note that the following is the definition of this register field in it8510. 0: scratch ram (data space). 1: scratch rom (code space). 6 w 0h override hardware strap shbm (ovrshbm) override hardware strap shbm and always treat its result as 1. 5 r/w 0h override hardware strap baddr1-0 (ovrbaddr) override hardware strap baddr1-0 an d always treat its result as 10b. 4-2 - 0h reserved 1 - - reserved 0 - - reserved 6.3.4.2 flash programming configuration register (fpcfg) this register provides general control on banking and flash standby. address offset: 01h bit r/w default description 7 r/w 1b banking source option (bso) 0: use 8032 p1[0] and p1[1] as code banking source. 1: use ecbb[1:0] in fecbsr register as code banking source. using p1 as banking source has less instruction count since only ?mov? is invoked rather than ?movx? although t2 and t2ex are used in other bits in p2. 6 r/w 1b auto flash standby (afstby) reserved 5 r/w 1b reserved 4 - - reserved 3-0 r/w 11111b reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 69 host domain functions 6.3.4.3 flash ec code banking select register (fecbsr) the register is used to select ec banking area bank 0~3 when bso =1 in fpcfg register. address offset: 05h bit r/w default description 7-2 - 0h reserved 1-0 r/w 00b ec banking block (ecbb) when ecbb is set to 00, ec code uses conventional code area (maximum 64k) as code memory. common bank 32k-byte flash mapping range is from 00_0000h to 00_7fffh. bank 0 32k-byte flash mapping range is from 00_8000h to 00_ffffh. bank 1 32k-byte flash mapping range is from 01_0000h to 01_7fffh. bank 2 32k-byte flash mapping range is from 01_8000h to 01_ffffh. bank 3 32k-byte flash mapping range is from 02_0000h to 02_7fffh. see also figure 3-1 on page 6. bits 1-0: 00: select common bank + bank 0 01: select common bank + bank 1 10: select common bank + bank 2 11: select common bank + bank 3 if a15 of 8032 code memory equals to 0, select common bank, otherwise select bank 0, 1, 2 or 3. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 70 it8511 e /te/ g 6.3.4.4 flash memory size select register (fmssr) the register provides the selection for the external flash memory size. address offset: 07h bit r/w default description 7-6 - 0h reserved 5-0 r/w 111111b flash memory size select (fmss) these bits select the external flash memory size. these bits only affect the host memory size ?seen? by southbridge and don?t affect address decoder in ec side. see also table 3-1. host/flash mapping on page 7. if southbridge issues lpc memory cycles as memory transaction, this field must be selected not to conflict with other memory devices on lpc bus. if southbridge issues fwh cycles as memo ry transaction, there is no conflict issue since each fwh id has its dedicated 4g memory space. bits 543210 memory size (bytes) 111111b: 4m 011111b: 2m 001111b: 1m 000111b: 512k 000011b: 256k 000001b: 128k or 00h: 128k (2^17) 02h: 256k (2^18) 04h: 512k (2^19) 06h: 1m (2^20) 08h: 2m (2^21) 0ah: 4m (2^22) 0ch: 8m (2^23) 0eh: 16m (2^24) 10h: 32m (2^25) 12h: 64m (2^26) 14h: 128m (2^27) 16h: 256m (2^28) otherwise: reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 71 host domain functions 6.3.4.5 shared memory ec control and status register (smeccs) the following set of registers is accessible only by the ec. the registers are applied to vstby. this register provides the flash cont rol and status of a restricted access. address offset: 20h bit r/w default description 7 r/w 0b host semaphore interrupt enable (hsemie) it enables interrupt to 8030 via int22 of intc. 0: disable the host semaphore (write) interrupt to the ec. 1: the interrupt is set (level high) if hsemw bit is set. 6 r/wc 0b host semaphore write (hsemw) 0: host has not written to hsem3-0 field in smhsr register. 1: host has written to hsem3-0 field in smhsr register. writing 1 to this bit to clear itself and clear internal detect logic. writing 0 has no effect. 5 r/w 0b host write allow (hostwa) 0: the smfi does not generate write transactions on m-bus. 1: the smfi can generate write transactions on m-bus. the read performance on m-bus will be very poor for host lpc if this bit is set. 4-3 r/w 00b host error response (heres) these bits control response types on read/write translation from/to a protected address. 1-0 number 00: drive long wait for read; ignore write 01: read back 00h; ignore write 10: drive error sync for both read and write 11: read back long sync; write back error sync 2 r/w 0b host error interrupt enable (herrien) it enables interrupt to 8030 via int23 of intc. 0: disable 1: the interrupt is set (level high) if hrerr or hwerr bit is set. 1 r/wc 0b host write error (hwerr) 0: no error is detected du ring a host-initiated write. 1: it represents the host write to a writ e-protected address. writing 1 to this bit clears it to 0. writing 0 has no effect. 0 r/wc 0b host read error (hrerr) 0: no error is detected during a host-initiated read. 1: it represents the host reads to a read-protected address. writing 1 to this bit clears it to 0. writing 0 has no effect. 6.3.4.6 shared memory host semaphore register (smhsr) this register provides eight semaphore bits between the ec and the host. bits 3-0 may be set by the host and bits 7-4 may be set by the ec. the regist er is reset on host domain hardware reset. this is the register the same as the one in section 6.3.5.6 but they are in different views. address offset: 22h bit r/w default description 7-4 r/w 0h ec semaphore (csem3-0) these four bits may be written by t he ec and read by both the host and the ec free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 72 it8511 e /te/ g bit r/w default description 3-0 r 0h host semaphore (hsem3-0) these four bits may be written by the host and read by both the host and the ec. 6.3.4.7 shared memory ec override re ad protect registers 0-1 (smecorpr0-1) refer to table 3-3. flash read/write protection controlled by ec side on page 8. address offset: 23h bit r/w default description 7-0 r/w 00h override read protect low address (orpla7-0) the default values make all the flash ranges readable. address offset: 24h bit r/w default description 7-1 - - reserved 0 r/w 0b override read protect (orla8) the default values make all the flash ranges readable. 6.3.4.8 shared memory ec override wr ite protect registers 0-1 (smecowpr0-1) refer to table 3-3. flash read/write protection controlled by ec side on page 8. address offset: 29h bit r/w default description 7-0 r/w 1b override write protect low address (owpla7-0) the default values make all the flash ranges write-protected. address offset: 2ah bit r/w default description 7-1 - - reserved 0 r/w 1b override write protect (owp8) the default values make all the flash ranges write-protected. 6.3.4.9 host control 2 register (hctrl2r) address offset: 36h bit r/w default description 7 r/w 1b host bridge enable (hbren) 1: the host memory cycle is decoded 0: otherwise only modify this bit before vcc power is supplied. 6 r/w 0b safe host bridge (shbr) 1: host pci clock is less than 33mhz. 0: otherwise it has the same affection as slwpci bit in mbctrl register in the host side. 5-3 - - reserved 2-0 - - reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 73 host domain functions 6.3.4.10 trusted rom register (tromr) address offset: 37h bit r/w default description 7-1 r/w 0h trusted rom range (tromrng-1) this field defines the address range that belongs to trusted rom and can be modified only inside trusted rom range. refer to table 3-4. trusted rom range on page 8 for the detail. 0 - - reserved 6.3.4.11 ec-indirect memory address register 0 (ecindar0) address offset: 3bh bit r/w default description 7-0 r/w 00h ec-indirect memory address (ecinda7-0) define the ec-indirect memory address when asserting a read/write cycle to ec-indirect memory data register (ecinddr). 6.3.4.12 ec-indirect memory address register 1 (ecindar1) address offset: 3ch bit r/w default description 7-0 r/w 00h ec-indirect memory address (ecinda15-8) define the ec-indirect memory address when asserting a read/write cycle to ec-indirect memory data register (ecinddr). 6.3.4.13 ec-indirect memory address register 2 (ecindar2) address offset: 3dh bit r/w default description 7-0 r/w 00h ec-indirect memory address (ecinda23-16) define the ec-indirect memory address when asserting a read/write cycle to ec-indirect memory data register (ecinddr). 6.3.4.14 ec-indirect memory address register 3 (ecindar3) address offset: 3eh bit r/w default description 7-4 r 0000b ec-indirect memory address (ecinda31-28) read only. 3-0 r/w 0h ec-indirect memory address (ecinda27-24) define the ec-indirect memory address when asserting a read/write cycle to ec-indirect memory data register (ecinddr). 6.3.4.15 ec-indirect memory data register (ecinddr) address offset: 3fh bit r/w default description 7-0 r/w - ec-indirect memory data (ecindd7-0) read/write to this register will access one byte on the flash with the 32-bit flash address defined in ecindar3-0. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 74 it8511 e /te/ g 6.3.4.16 scratch sram 0 address low byte register (scar0l) address offset: 40h bit r/w default description 7-0 r/w 00h scratch sram 0 address (sc0a7-0) 6.3.4.17 scratch sram 0 address middle byte register (scar0m) address offset: 41h bit r/w default description 7-0 r/w 00h scratch sram 0 address (sc0a15-8) 6.3.4.18 scratch sram 0 address high byte register (scar0h) address offset: 42h bit r/w default description 7 r/w 0b next start dma (nsdma) if 1 is written to this bit, dma will be started at the next writing. 6 r/w 0b trust flag (trsf) this bit indicates that scratch ram no. 0 can be only accessed by code inside trusted rom range. 5-2 r/w 0h reserved 1-0 r/w 11b scratch sram 0 address (sc0a17-16) the default value makes this scratch sram not be a scratch rom. 6.3.4.19 scratch sram 1 address low byte register (scar1l) address offset: 43h bit r/w default description 7-0 r/w 00h scratch sram 1 address (sc1a7-0) 6.3.4.20 scratch sram 1 address middle byte register (scar1m) address offset: 44h bit r/w default description 7-0 r/w 00h scratch sram 1 address (sc1a15-8) 6.3.4.21 scratch sram 1 address high byte register (scar1h) address offset: 45h bit r/w default description 7 r/w 0b next start dma (nsdma) if 1 is written to this bit, dma will be started at the next writing. 6 r/w 0b trust flag (trsf) this bit indicates that scratch ram no.1 can be only accessed by code inside trusted rom range. 5-2 r/w 0h reserved 1-0 r/w 11b scratch sram 1 address (sc2a17-16) the default value makes this scratch sram not be a scratch rom. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 75 host domain functions 6.3.4.22 scratch sram 2 address low byte register (scar2l) address offset: 46h bit r/w default description 7-0 r/w 00h scratch sram 2 address (sc2a7-0) 6.3.4.23 scratch sram 2 address middle byte register (scar2m) address offset: 47h bit r/w default description 7-0 r/w 00h scratch sram 2 address (sc2a15-8) 6.3.4.24 scratch sram 2 address high byte register (scar2h) address offset: 48h bit r/w default description 7 r/w 0b next start dma (nsdma) if 1 is written to this bit, dma will be started at the next writing. 6 r/w 0b trust flag (trsf) this bit indicates that scratch ram no.2 can be only accessed by code inside trusted rom range. 5-2 r/w 0h reserved 1-0 r/w 11b scratch sram 2 address (sc2a17-16) the default value makes this scratch sram not be a scratch rom. 6.3.4.25 scratch sram 3 address low byte register (scar3l) address offset: 49h bit r/w default description 7-0 r/w 00h scratch sram 3 address (sc3a7-0) 6.3.4.26 scratch sram 3 address middle byte register (scar3m) address offset: 4ah bit r/w default description 7-0 r/w 00h scratch sram 3 address (sc3a15-8) 6.3.4.27 scratch sram 3 address high byte register (scar3h) address offset: 4bh bit r/w default description 7 r/w 0b next start dma (nsdma) if 1 is written to this bit, dma will be started at the next writing. 6 r/w 0b trust flag (trsf) this bit indicates that scratch ram no. 3 can be only accessed by code inside trusted rom range. 5-2 r/w 0h reserved 1-0 r/w 11b scratch sram 3 address (sc3a17-16) the default value makes this scratch sram not be a scratch rom. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 76 it8511 e /te/ g 6.3.4.28 scratch sram 4 address low byte register (scar4l) address offset: 4ch bit r/w default description 7-0 r/w 00h scratch sram 4 address (sc4a7-0) 6.3.4.29 scratch sram 4 address middle byte register (scar4m) address offset: 4dh bit r/w default description 7-0 r/w 00h scratch sram 4 address (sc4a15-8) 6.3.4.30 scratch sram 4 address high byte register (scar4h) address offset: 4eh bit r/w default description 7 r/w 0b next start dma (nsdma) if 1 is written to this bit, dma will be started at the next writing. 6 r/w 0b trust flag (trsf) this bit indicates that scratch ram no. 4 can be only accessed by code inside trusted rom range. 5-2 r/w 0h reserved 1-0 r/w 11b scratch sram 4 address (sc4a17-16) the default value makes this scratch sram not be a scratch rom. 6.3.5 host interface registers the registers of smfi can be divided into two parts: host interface regi sters and ec interface registers and this section lists the host interface. the host interf ace registers can only be accessed by the host processor. the smfi resides at lpc i/o space and the base addr ess can be configured through lpc pnpcfg registers. the smfi logical device number is 0fh (ldn=0fh). these registers are listed below table 6-16. host view register map, smfi 7 0 offset shared memory indirect memory address (smimar0-3) 00h-03h shared memory indirect memory data (smimdr) 04h shared memory host semaphore (smhsr) 0ch m-bus control register (mbctrl) 0fh 6.3.5.1 shared memory indirect memory address register 0 (smimar0) the following set of registers is accessible onl y by the host. the registers are applied to vcc. this register defines the addr esses 7-0 for a read or write transaction to the memory. address offset: 00h bit r/w default description 7-0 r/w - indirect memory address (imadr7-0) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 77 host domain functions 6.3.5.2 shared memory indirect memory address register 1 (smimar1) this register defines the addresses 15-8 for a read or write transaction to the memory. address offset: 01h bit r/w default description 7-0 r/w - indirect memory address (imadr15-8) 6.3.5.3 shared memory indirect memory address register 2 (smimar2) this register defines the addr esses 23-16 for a read or write transaction to the memory. address offset: 02h bit r/w default description 7-0 r/w - indirect memory address (imadr23-16) 6.3.5.4 shared memory indirect memory address register 3 (smimar3) this register defines the addr esses 31-24 for a read or write transaction to the memory. address offset: 03h bit r/w default description 7-0 r/w - indirect memory address (imadr31-24) 6.3.5.5 shared memory indirect memory data register (smimdr) this register defines the data bits 7-0 for a read or write transaction to the memory. address offset: 04h bit r/w default description 7-0 r/w - indirect memory data (imda7-0) 6.3.5.6 shared memory host semaphore register (smhsr) this register provides eight semaphore bits between the ec and the host. bits 3-0 may be set by the host and bits 7-4 may be set by the ec. the register reset on host domain hardware reset. this is the register the same as the one in section 6.3.4.9 on page 72 but they are in different views. address offset: 0ch bit r/w default description 7-4 r 0h ec semaphore (csem3-0) four bits that may be updated by the ec and read by both the host and the ec. 3-0 r/w 0b host semaphore (hsem3-0) four bits that may be updated by the host and read by both the host and the ec. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 78 it8511 e /te/ g 6.3.5.7 m-bus control register (mbctrl) address offset: 0fh bit r/w default description 7-1 - - reserved 3-0 r/w 0b slow pci clock register (slwpci) 1: host pci clock is less than 33mhz. 0: otherwise it has the same affection as shbr bi t in hctrl2r register in ec side. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 79 host domain functions 6.4 system wake-up control (swuc) 6.4.1 overview swuc detects wakeup events and generate sci#, smi# and pwureq# signals to the host side, or alert ec by interrupts to wuc. 6.4.2 features ? supports programmable wake-up events so urce from the host controlled modules. ? generates smi# or pwureq# inte rrupt to host to wake-up system. 6.4.3 functional description the wakeup event and gathering scheme is shown below. figure 6-4. wakeup event and gathering scheme swchier event detection wker swchstr wkstr (host side) wksmier wkirqer event routing event routing event routing event routing smi# from pm1 smi# from pm2 pmureq# check wker for its source list smi# check wksmier for its source list irq to lpc/serirq check wkirqer for its source list host event interrupt enable (ec side) wake-up events to ec 8032 through wu26 check swchier for its source list 6.4.3.1 wake-up status when the wake up event is detected, the relative status bit is set to 1 in both host and ec status registers, no matter whether any event enable bits are se t or not. a status bit is cleared by wr iting 1 to it. writing 0 to a status bit does not change its value. clearing the event enable bit does not affect t he status bit, but prevents it from issuing an event to output. the host uses a mask regist er (wksmier) to decide what the status bits will respond to. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 80 it8511 e /te/ g 6.4.3.2 wake-up events when a wake up event is detected, it is recorded on a status bit in wkstr (host view) register and swchstr register (ec view), regardless of the enabled bit. each event behavior is determined by a wake up control logic controlled by a set of dedicated registers. input events are detected by the swuc shown as follows: ? module irq wake up event ? modem ring (ri1 and ri2) ? telephone ring (ring input) ? rtc alarm ? software event ? legacy off event ? acpi state change event module irq wake-up event a module irq wake-up event from each logical device is asserted when the leading edge of the module irq is detected. the relative enable bit (wkirqen) must be set to 1 to enable and trigger a wake-up event. refer to the irqnum and wkirqen fields in irqnumx register. when the event is detected, mirq bit in wkstr register is set to 1. if mirqe in wker regist er is also set to 1, the pwureq# out put is still asserted and until the status bit is cleared. modem ring if transitions form high to low on ri1# (or ri2#) is detect ed on the serial port 1 (or serial port 2) connected to a modem, and then when the signal goes high on ri1#(or ri2#), it will cause a ring wake-up event asserted if the ri1#(or ri2#) event enable bit is set 1 in the wker register (bit0 for ri1#, and bit1 for ri2#). telephone ring if transitions form high to low on the ring input pin, and then when the signal goes high on ring input pin. it will cause a ring wake-up event asserted when the ring event enable bit is set 1 in the wker register (bit3). rtc alarm an alarm signal can be generated by rtc module and us ed as wake up event. after an alarm event is detected in the rtc, the rtc alarm status bit is set and rtcal bit in swctl3 register is set to response it to enable rtc alarm as a wake-up event to ec, the softw are need to follow the sequence listed below: 1.set the alarm conditions in the rtc module. 2.set eirtca bit in swcier register to enable alarm status interrupt masking. 3.make sure that the rtca bit in swctl3 register is cleared. 4.enable the wake-up on swuc event in the wuc and intc modules. software event this bit may trigger a wake event by software control. when the sirqs (software irq event status bit) in wkstr register is set, a software event to the host is ac tive. when the sirqs bit in swchstr register is set, a software event to the ec is active. the software event may be activated by the ec via access to the host controlled module bridge regardless of the vcc status. the sirqs bit in swchstr may be set when the respec tive bit toggles in wkstr from 0 to 1 and when hsecm=0 is in swctl1 register. when hsecm =1 t, the sirqs bit in swchstr is set on a write of a 1 to the respective bit in wkstr. the sirqs bit in swchstr is cleared by writing 1 to it. legacy off events the host supports either legacy or acpi mode. the o peration mode is assigned on pwrbtn bit in the super i/o power mode register (siopwr). when eiscrdpbm bit in swcier register is set, any change in this bit will generate an interrupt to the ec. the ec may read this bit, usi ng scrdpbm bit in swctl2 register, to determine the other power state. in the legacy mode, t he pwrsly bit in siopwr r egister represents a turn power off request. when this bit is se t and scrdpso bit in swctl2 register is set, an interrupt is generated to ec if eiscrdpso bit in swci er register is also set. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 81 host domain functions acpi state change events the bits (s1-s5) in wkacpir register are used to prov ide a set of ?system power state change request?. the host uses these bits to issue an acpi state change request. a write of 1 to any of these bits represents a state change request to the ec, the request may be also read out in swctl2 register even s0 is represented when all bits in wkacpi is cleared to 0. when any of s0-s 5 bits in swctl2 is set and the respective mask bit in swcier register is set, an interrupt is generated to ec . all interrupt outputs may be cleared either writing 1 to the status bit or clearing the masking interrupt enable register. 6.4.3.3 wake-up output events the swuc output four types of wake up events: irq interrupt through serirq to host side, whic h is activated by swuc logical device of pnpcfg. pwureq# routing as an sci event. smi# routing as an smi event. wu26 an interrupt to the wuc module in the ec domain which is handled by ec firmware. output events are generated to host when their status bit is set (1 in wkstr). output event to the ec through the wuc is generated when their ec status bit is se t (1 in swchstr). the host can program three event routing control registers (wkstr, wksmier and wkirqer) to handle each of the host events to be asserted. this allows selective routing of these events output to pwureq#, smi# and/or swuc interrupt request (irq). after an output event is asserted, it can be cleared either by clearing its status bit or being masked. the current status of the event may be read out at the wake-up event status register(wkstr), and wake-up signals monitor register (wksmr). the swuc also handles the wake up event coming from the pmc 1 and 2 for smi# event. in the ec domain, wake-u p event interrupt enable r egister (swchier) holds an enable bit to allow selective routing of the event to out put the ec wake-up interrupt (wu26) to the wuc. 6.4.3.4 other swuc controlled options additionally, the swuc handles the follo wing system control signals: host keyboard reset (kbrst#) ga20 signal host configuration address option ? host keyboard reset (kbrst#) the host keyboard reset output (kbrst#) can be asserted either by software or hardware: software: kbrst# will be asserted when the ec firmware issues a reset command by writing 1 to hrst in swctl1 register. clear this bit to de-assert the kbrst#. hardware: kbrst# will be as serted during vstby power-up reset if hrapu bit in sw ctl3 register is set and an lpc transaction is started. the kbrst# signal will be active in the following conditions: (1) hrsta bit in the swuc is enabled and lpc cycle is active when the vstby is power-on. (2) lpcpf bit in the swuc is enabled and lpcpd# signal is active. (3) hrst bit in the swuc is enabled. (4) bit 0 of kbhikdor in the kbc is enabled if krstga20r is set. the kbrst# output scheme is shown in figure 6-5 on page 82. note it is another way to use gpio output function to send kbrst# signal. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 82 it8511 e /te/ g figure 6-5. kbrst# output scheme lpcpf@swctl3 lpcpd#=0 hrst@swctl1 hrsta@swctl3 vstby power-up reset accepted lpc cycle detected kbhikdor bit-0 krstga20r@swctl1 kbrst# kbrst#/gpb6 ? ga20 signal in the chip, the ga20 is connected to a gpio signal that is configured as output. port gpb5 is recommended to be used as ga20 since its initial state is output driving high. ec can assert the ga20 signal state by 1. modifying gpb5 in gpio register 2. writing 1 to lpcpf in swctl3 register and ga20 si gnal will be asserted while lpcpd# signal is active. the ga20 signal will be active in the following conditions: (1) lpcpf bit in the swuc is enabled and lpcpd# signal is active. (2) bit-1 of kbhikdor in the kbc is enabled if krstga20r is set. the ga20 output scheme is shown in figure 6-6 on page 82. note it is another way to use gpio output function to send ga20 signal. figure 6-6. ga20 output scheme lpcpf@swctl3 lpcpd#=0 kbhikdor bit-1 krstga20r@swctl1 ga20 ga20/gpb5 ? host configuration address option the contents of swcbahr and swcbalr change only during vstby power -up reset. to update the base address of the pnpcfg registers, refer to the followings: 1. clear hcav bit in swctl1 register by writing 1 to it. 2. write the lower byte of the address to swcbalr (lsb must be cleared). 3. write the higher byte of the address to swcbahr. 4. set hcal bit to prevent the unintended change in the swcbalr and swcbahr register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 83 host domain functions 6.4.4 host interface registers the registers of swuc can be divided into two parts: host interface registers and ec interface registers and this section lists the host interface. the host interf ace registers can only be accessed by the host processor. swuc resides at lpc i/o space and the base address c an be configured through lpc pnpcfg registers. the swuc logical device number is 04h (ldn=04h). swuc host interface registers are battery -backed. these registers are listed below. table 6-17. host view register map, swuc 7 0 offset wake-up event status register (wkstr) 00h wake-up enable r egister (wker) 02h wake-up signals monitor register (wksmr) 06h wake-up acpi status register (wkacpir) 07h wake-up smi enable register (wksmier) 13h wake-up interrupt enable register (wkirqer) 15h 6.4.4.1 wake-up event status register (wkstr) the register is used to monitor the status of wake-u p events. the register will be cleared when the vstby power is power-up, or the host domain software reset occurs. address offset: 00h bit r/w default description 7 r/wc 0 module irq event status (mirqs) 0: event is not active. 1: event is active. 6 r/wc 0 software irq event status (sirqs) the function of this bit can be changed by programming the hsecm bit in swuc control status register (swctl1). when hsecm=0 and writing 1 to this bit, the value of this bit will be inverted. when hsecm=1 and writing 1 to this bi t, the bit is set to 1. the bit will be cleared when the sirqs bit in sw uc host event status register (swchstr) is written to 1. 0: event is not active. 1: event is active. 5-4 r 00 reserved 3 r/wc 0 ring# event status (rings) if the ring detection mode is disabled, the bit is always 0. 0: event is not active. 1: event is active. 2 r 00 reserved 1 r/wc 0 ri2# event status (ri2s) 0: event is not active. 1: event is active. 0 r/wc 0 ri1# event status (ri1s) 0: event is not active. 1: event is active. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 84 it8511 e /te/ g 6.4.4.2 wake-up event enable register (wker) the register is used to enable the individual wake-up events to generate pwureq# in terrupt. the register will be cleared when the vstby power is power-up, or the host domain software reset occurs. address offset: 02h bit r/w default description 7 r/w 0 module irq event enable (mirqe) 0: disable. 1: enable. 6 r/w 0 software irq event enable (sirqe) 0: disable. 1: enable. 5-4 r 00 reserved 3 r/w 0 ring# event enable (ringe) 0: disable. 1: enable. 2 r 00 reserved 1 r/w 0 ri2# event enable (ri2e) 0: disable. 1: enable. 0 r/w 0 ri1# event enable (ri1e) 0: disable. 1: enable. 6.4.4.3 wake-up signals monitor register (wksmr) the register is used to monitor the value of the sm i# and pwureq# signals and identify the generated source. this register is a read-only register. address offset: 06h bit r/w default description 7-6 r 00 reserved 5 r 0 pwureq# output from swuc (pwureqos) 0: pwureq# output from swuc is low. 1: pwureq# output from swuc is high. 4 r 0 pwureq# signal status (pwureqs) 0: pwureq# signal is low. 1: pwureq# signal is high. 3 r 0 smi# output from pm2 (pm2smi) 0: smi# output from pm channel 2 is low. 1: smi# output from pm channel 2 is high. 2 r 0 smi# output from pm1 (pm1smi) 0: smi# output from pm channel 1 is low. 1: smi# output from pm channel 1 is high. 1 r 0 smi# output from swuc (swcsmi) 0: smi# output from swuc is low. 1: smi# output from swuc is high. 0 r 0 smi# signal status (smis) 0: smi# signal is low. 1: smi# signal is high. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 85 host domain functions 6.4.4.4 wake-up acpi stat us register (wkacpir) the register is used to monitor the status of acpi. when this register is read, its value always returns 00h. address offset: 07h bit r/w default description 7-6 r 00 reserved 5 r/w 0 change to s5 state (s5) the host uses this bit to request the ec to change the acpi s5 state. 0: not request to change s5 state. 1: request to change s5 state. 4 r/w 0 change to s4 state (s4) the host uses this bit to request the ec to change the acpi s4 state. 0: not request to change s4 state. 1: request to change s4 state. 3 r/w 0 change to s3 state (s3) the host uses this bit to request the ec to change the acpi s3 state. 0: not request to change s3 state. 1: request to change s3 state. 2 r/w 0 change to s2 state (s2) the host uses this bit to request the ec to change the acpi s2 state. 0: not request to change s2 state. 1: request to change s2 state. 1 r/w 0 change to s1 state (s1) the host uses this bit to request the ec to change the acpi s1 state. 0: not request to change s1 state. 1: request to change s1 state. 0 r 0 reserved 6.4.4.5 wake-up smi enable register (wksmier) the register is used to enable the individual wake-up ev ents to generate smi# interrupt. the register will be cleared when the vstby power is power-up, or the host domain software reset occurs. address offset: 13h bit r/w default description 7 r/w 0 reserved 6 r/w 0 software irq event to smi enable (ssmie) 0: disable. 1: enable. 5-4 r 00 reserved 3 r/w 0 ring# event to smi enable (ringsmie) 0: disable. 1: enable. 2 r 00 reserved 1 r/w 0 ri2# event to smi enable (ri2smie) 0: disable. 1: enable. 0 r/w 0 ri1# event to smi enable (ri1smie) 0: disable. 1: enable. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 86 it8511 e /te/ g 6.4.4.6 wake-up irq enable register (wkirqer) the register is used to enable the indi vidual wake-up events to generate the interrupt signal that is assigned by swuc. the register will be cleared wh en the vstby power is power-up, or the host domain software reset occurs. address offset: 15h bit r/w default description 7 r/w 0 reserved 6 r/w 0 software irq event to irq enable (sirqe) 0: disable. 1: enable. 5-4 r 00 reserved 3 r/w 0 ring# event to irq enable (ringirqe) 0: disable. 1: enable. 2 r 00 reserved 1 r/w 0 ri2# event to irq enable (ri2irqe) 0: disable. 1: enable. 0 r/w 0 ri1# event to irq enable (ri1irqe) 0: disable. 1: enable. 6.4.5 ec interface registers the registers of swuc can be divided into two parts, host interface registers and ec interface registers. this section lists the ec interface. the ec interface can only be accessed by t he internal 8032 processor. the base address for swuc is 1400h. these registers are listed below. table 6-18. ec view register map, swuc 7 0 offset swuc control status 1 register (swctl1) 00h swuc control status 2 register (swctl2) 02h swuc control status 3 register (swctl3) 04h swuc host configuration base address low byte register (swcbalr) 08h swuc host configuration base addr ess high byte register (swcbahr) 0ah swuc interrupt enable register (swcier) 0ch swuc host event status register (swchstr) 0eh swuc host event interrupt enable register (swchier) 10h 6.4.5.1 swuc control status 1 register (swctl1) the register is used to control the individual wake-u p action on swuc. the register will be cleared when the vstby power is power-up. bit 0 is only cleared when the warm reset occurs. address offset: 00h bit r/w default description 7 r/w 1 kb reset/ga20 routing (krstga20r) 0: enable routing bit-0 of kbhikdor as kbrst# source enable routing bit-1 of kbh ikdor as ga20 source 1: disable above free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 87 host domain functions bit r/w default description 6 r/w 0 reserved 5 r/w 0 host software event clear mode (hsecm) this bit is used to control the clea r mode of sirqs bit at the wake-up event status register (wkstr). 4 r/w 0 host configuration address lock (hcal) when the bit is written to 1, the host configuration address and the bit will be locked. the bit is only cleared at the following condition: vstby power-up or watchdog reset. 3 r/wc 0 host configuration address valid (hcav) this bit is set after writing swcbahr register. 1: indicate host configuration base address stored in swcbalr and swcbahr registers are valid. 0: swcbalr and swcbahr registers are not valid. the bit can be cleared by writing to 1. 2 r 0 lpc reset active (lpcrst) 0: lpcrst# is inactive. 1: lpcrst# is active. 1 r - vcc power on (vccpo) 0: vcc is power-off. 1: vcc is power-on. see also vccdo bit in rsts register in 7.14.4.5 on page 260. 0 r/w - host reset active (hrst) when this bit is 1, the kbrst# is active to generate one host software reset. 6.4.5.2 swuc control status 2 register (swctl2) the register is used to control the individual wake-u p action on swuc. the register will be cleared when the vstby power is power-up and lpcrst# is active. address offset: 02h bit r/w default description 7 r/wc 0 super i/o configuration siopwr power supply off (scrdpso) the bit is used to monitor the power supply off (pwrsly) bit in siopwr register of pnpcfg. when the bit is written to 1, clear the bit and the interrupt signal caused by the value change in this bit. a write of 0 to this bit is ignored. 6 r/wc 0 super i/o configuration siopwr power button mode (scrdpbm) the bit is used to monitor the power button mode (pwrbtn) bit in siopwr register of pnpcfg. when t he bit is written to 1, clear the interrupt signal caused by the value change in this bit. a write of 0 to this bit is ignored. 5-1 r/wc 0000 acpi request s5-1 (acpirs5-1) these bits are used to monitor the s5-1 bit at the wake-up acpi status register (wkacpir). when the bit is written to 1, clear the bit and the interrupt signal caused by acpi. a write of 0 to this bit is ignored. 0 r/wc 0000 acpi request s0 (acpirs0) if all s5-1 bits at the wkacpir are wri tten to 0, the bit will be set to 1. the bit will be cleared if the bit is written to 1. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 88 it8511 e /te/ g 6.4.5.3 swuc control status 3 register (swctl3) the register is used to control the individual wake-up action on swuc. the register will only be cleared when the vstby powers up. address offset: 04h bit r/w default description 7-3 r 00h reserved 2 r/wc 0 rtc alarm active (rtcal) when the rtc alarm is active, the bi t will be set to 1. the bit can be cleared by writing to 1. 1 r/w 0 lpc power fail turn off kbrst# and ga20 (lpcpf) if the bit is set to 1, the kbrst# and ga20 will be forced to low when the lpcpd# signal is active. 0 r/w 1 host reset active during vstby power-up (hrsta) if the bit is set to 1, the kbrst# signal will be active when the lpc cycle is active until vstby power-up reset is finished. writing to this bit is ignored if hcal bit is set. 6.4.5.4 swuc host configuration base address low byte register (swcbalr) the register is used to program the base add ress of the swuc host interface registers. see also table 6-2 on page 40 and hcal/hcav bit in swctl1 register. address offset: 08h bit r/w default description 7-0 r/w 00h base address low byte (balb) 6.4.5.5 swuc host configuration base address high byte register (swcbahr) the register is used to program the base add ress of the swuc host interface registers. see also table 6-2 on page 40 and hcal/hcav bit in swctl1 register. address offset: 0ah bit r/w default description 7-0 r/w 00h base address high byte (bahb) 6.4.5.6 swuc interrupt en able register (swcier) the register is used to enable the individual interrupt source on swuc. the interr upt can be cleared by clearing the status bit or masking the source . on the other hand, the register will be cleared when the warm reset is active. address offset: 0ch bit r/w default description 7 r/w 0 enable interrupt from super i/o configuration siopwr power supply off (eiscrdpso) 1: generate high-level interrupt when the scrdpso bit in swuc control status 2 register (swctl2) is changed. 0: disable the interrupt source. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 89 host domain functions bit r/w default description 6 r/w 0 enable interrupt from super i/o configuration siopwr power button mode (eiscrdpbm) 1: generate high-level interrupt when the scrdpbm bit in swuc control status 2 register (swctl2) is changed. 0: disable the interrupt source. 5-1 r/w 0000 enable interrupt from acpi request s5-1 (eiacpirs5-1) 1: generate high-level interrupt when the acpirs5-1 bit in swuc control status 2 register (swctl2) is changed. 0: disable the interrupt source. 0 r/w 0 enable interrupt from rt c alarm active (eirtca) 1: generate on high-level interrupt when the rtcal bit in swuc control status 3 register (swctl3) is changed to 1. 0: disable the interrupt source. 6.4.5.7 swuc host event st atus register (swchstr) the information of this register is mirror as the wake -up event status register (wkstr). the status bits can be cleared by writing to the corresponding bit in the tw o registers. the register will be cleared when the vstby power is power-up, or the host software reset occurs. address offset: 0eh bit r/w default description 7 r/wc 0 module irq event status (mirqs) 0: event is not active. 1: event is active. 6 r/wc 0 software irq event status (sirqs) the function of this bit can be changed by programming hsecm bit in swuc control status register (swctl1). when hsecm=0, this bit is set to 1 when sirqs toggles to 1 in wkstr register. when hsecm=1 and this bit is set to 1 while writing 1 to sirqs in wkstr register. this bit will be cleare d by writing 1 to it. 0: event is not active. 1: event is active. 5-4 r 00 reserved 3 r/wc 0 ring# event status (rings) if the ring detection mode is disabled, the bit is always 0. 0: event is not active. 1: event is active. 2 r 00 reserved 1 r/wc 0 ri2# event status (ri2s) 0: event is not active. 1: event is active. 0 r/wc 0 ri1# event status (ri1s) 0: event is not active. 1: event is active. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 90 it8511 e /te/ g 6.4.5.8 swuc host event interrupt enable register (swchier) the register is used to enable the individual wake-up events to generate one interrupt to the ec 8032 via wu26 of wuc. the register will be cl eared when t he warm reset occurs. address offset: 10h bit r/w default description 7 r/w 0 module irq event enable (mirqee) 0: disable. 1: enable. 6 r/w 0 software irq event enable (sirqee) 0: disable. 1: enable. 5-4 r 00 reserved 3 r/w 0 ring# event enable (ringee) 0: disable. 1: enable. 2 r 00 reserved 1 r/w 0 ri2# event enable (ri2ee) 0: disable. 1: enable. 0 r/w 0 ri1# event enable (ri1ee) 0: disable. 1: enable. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 91 host domain functions 6.5 keyboard controller (kbc) 6.5.1 overview this keyboard controller supports a standard keyboard and mouse controller interface. 6.5.2 features ? compatible with the legacy 8042 interface keyboard controller. ? supports two standard registers for programming: command/data register and status register. ? automatically generates interrupts to the host side and ec side when the kbc status is changed. 6.5.3 functional description this keyboard controller is compatible with the legacy 8042 interface keyboard controller. figure 6-7. kbc host interface block diagram i bus ec bus kbstr (legacy 64h) kbdor (legacy 60h) kbdir (legacy 60h) output buffer empty input buffer full irq interrupt to the host via serirq/lpc interrupt to the intc status the host processor can read the status of kbc from the kbc status register. the internal 8032 can read the status of kbc from the kbc host inte rface keyboard/mouse status register. host write data to kbc interface when writing to address 60h or 64h (programmable), the ibf bit in the kbc status register is set and a2 bit in the kbc status register indicates 8032 whose address wa s written. when writing to address 60h, a2 bit is 0. when writing to address 64h, a2 bit is 1. ec 8032 can identify that the input buffer is full by either polling ibf bit in the status register or detecting an interrupt (int24) if the interrupt is enabled. ec 8032 can read the data from the kbc host interface keyboard/mouse data input register (kbhidir), and the ibf bit in the status register is cleared. ec 8032 write data to kbc interface ec 8032 can write data to the kbc when it needs to send data to the host. when ec 8032 writes data to the kbc host interface keyboard data output register (kbh ikdor), the obf bit in the status register is set. if the irq1 interrupt is enabled, the irq1 will be sent to the host. the host can read t he data output register when it detects the output buffer full condition. when ec 8032 writes data to the kbc host interface mouse free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 92 it8511 e /te/ g data output register (kbhimdor), the obf bit in the stat us register is set. if the irq12 interrupt is enabled, the irq12 will be sent to the host. the host can read the da ta output register when it detects the output buffer full condition. when the output buffer empty interrupt to in tc (int2) is enabled, the interrupt signal is set high if the output buffer is empty. interrupts there are two interrupts (input bu ffer full interrupt and output buffer empty) connected to the intc. there are two interrupts (i rq1 and irq12) connected to the host side (serirq). the irq numbers of kbc are programmable and use irq1 and irq12 as abbreviations in this section. figure 6-8. irq control in kbc module hw level/edge control 0 1 irq1b@kbirqr or irq12b@kbirqr 1 0 obfkie@kbhicr or obfmie@kbhicr irqnp@kbirqr irqm@kbirqr read irq1b@kbirqr or irq12b@kbirqr write obf serirq irq routing controlled by pnpcfg ga20 and kbrst# refer to section 6.4.3.4 on page 81. 6.5.4 host interface registers the registers of kbc can be divided into two parts: host interface registers and ec interface registers and this section lists the host interface. the host interface registers can only be accessed by the host processor. the kbc resides at lpc i/o space and the base addr ess can be configured through lpc pnpcfg registers. the kbc/keyboard logical device number is 06h (ldn=06h) and the kbc/mouse logical device number is 05h (ldn=05h). for comp atibility issue, the two i/o port base ad dresses of kbc /keyboard are suggested to configure at 60h and 64h. these registers are listed below. table 6-19. host view register map, kbc 7 0 offset kbc data input register (kbdir) legacy 60h kbc data output register (kbdor) legacy 60h kbc command register (kbcmdr) legacy 64h kbc status register (kbstr) legacy 64h legacy 60h represents (i/o port ba se address 0) + (offset 0h) legacy 64h represents (i/o port ba se address 1) + (offset 0h) see also table 6-3 on page 40. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 93 host domain functions 6.5.4.1 kbc data input register (kbdir) when the host processor is writing th is register, the ibf bit in kbc stat us register (kbstr) will be set and the a2 bit will be cleared. if the ibfcie bit in kbc host in terface control register (kbh icr) is enabled, the write action will cause one interrupt to 8032 processor via int24 of intc. address offset: 00h for i/o port base address 0, legacy 60h bit r/w default description 7-0 w - kbc data input (kbdi) the data is used to output for keyboard/mouse. 6.5.4.2 kbc data output register (kbdor) when the host processor is reading th is register, the obf bit in kbc stat us register (kbstr) will be cleared. the reading access will also clear the interrupt for host processor when the irqm bits of kbc interrupt control register (kbirqr) are programmed to be at level mode. if the obecie bit in kbc host interface control register (kbhicr) is enabled, the read action will ca use one interrupt to 8032 processor via int2 of intc. address offset: 00h for i/o port base address 0, legacy 60h bit r/w default description 7-0 r - kbc data output (kbdo) the data comes from the keyboard/mouse source. 6.5.4.3 kbc command register (kbcmdr) when the register is written, the ibf bit in kbc stat us register (kbstr) will be set and the a2 bit will be set. address offset: 00h for i/o port base address 1, legacy 64h bit r/w default description 7-0 w - kbc command (kbcmd) the command data is used to output for keyboard/mouse. 6.5.4.4 kbc status register (kbstr) the host processor uses the register to monitor the stat us of kbc. the same information is similar to the kbc host interface keyboard/mouse st atus register (kbhisr). it is used by the internal 8032. address offset: 01h for i/o port base address 0, legacy 64h bit r/w default description 7-4 r 0h programming data 3-0 (pd3-0) the data is used by the 8032 firmware to be the general-purpose setting. 3 r 0 a2 address (a2) the bit is used to keep the a2 address information of the last write operation that the host processor accessed the kbc. 2 r 0 programming data ii (pdii) the function is the same as the pd3-0. 1 r 0 input buffer full (ibf) when the host processor is writing dat a to kbdir or kbcmdr, the bit is set. on the other hand, the bit will be clea red when the kbdir or kbcmdr is read by the 8032 firmware. 0 r 0 output buffer full (obf) when the ec 8032 is writing data to kbdor , the bit is set. on the other hand, the bit will be cleared wh en the kbdor is read by the host processor. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 94 it8511 e /te/ g 6.5.5 ec interface registers the registers of kbc can be divided into two parts, host interface registers and ec interface registers. this section lists the ec interface. the ec interface can only be accessed by t he internal 8032 processor. the base address for kbc is 1300h. these registers are listed below. table 6-20. ec view register map, kbc 7 0 offset kbc host interface control register (kbhicr) 00h kbc interrupt control register (kbirqr) 02h kbc host interface keyboard/mou se status register (kbhisr) 04h kbc host interface keyboard data output register (kbhikdor) 06h kbc host interface mouse data output register (kbhimdor) 08h kbc host interface keyboard/mouse data input register (kbhidir) 0ah . 6.5.5.1 kbc host interface control register (kbhicr) address offset: 00h bit r/w default description 7 r 0 reserved 6 r/w 0 pm channel 1 input buffer full 8032 interrupt enable (pm1icie) the bit is used to enable the interrupt to 8032 for pm channel 1 when the input buffer is full via int25 of intc. 5 r/w 0 pm channel 1 output buffer empty 8032 interrupt enable (pm1ocie) the bit is used to enable the interrupt to 8032 for pm channel 1 when the output buffer is empty via int3 of intc. 4 r/w 0 pm channel 1 host interface interrupt enable (pm1hie) 0: the irq11 is controlled by the irq11b bit in kbc interrupt control register (kbirqr). 1: enables the interrupt to the host side via serirq for pm channel 1 when the output buffer is full. the interrupt type is controlled by the irqm and irqnp bit in kbirqr. 3 r/w 0 input buffer full 8032 interrupt enable (ibfcie) the bit is used to enable the interrupt to 8032 for keyboard/mouse when the input buffer is full via int24 of intc. 2 r/w 0 output buffer empty 8032 interrupt enable (obecie) the bit is used to enable the interrupt to 8032 for keyboard/mouse when the output buffer is empty via int2 of intc. 1 r/w 0 output buffer full mouse interrupt enable (obfmie) 0: the irq12 is controlled by the irq12b bit in kbirqr. 1: enables the interrupt to mouse driver in the host processor via serirq when the output buffer is full. the interr upt type is controlled by the irqm and irqnp bit in kbirqr. 0 r/w 0 output buffer full keyboard interrupt enable (obfkie) 0: the irq1 is controlled by the irq1b bit in kbirqr. 1: enables the interrupt to mouse driver in the host processor via serirq when the output buffer is full. the interr upt type is controlled by the irqm and irqnp bit in kbirqr. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 95 host domain functions 6.5.5.2 kbc interrupt control register (kbirqr) address offset: 02h bit r/w default description 7 r 0 reserved 6 r/w 0 interrupt negative polarity (irqnp) the bit is enabled, and then the interrupt level is inverted. 5-3 r/w 0 interrupt mode (irqm) these bits are used to control the in terrupt type to be level-triggered or edge-triggered (pulse) mode. in level-triggered mode, the default value of irq1/11/12 to serirq via routing logic is low and will be set to high when the interrupt condition occurs. in edge-triggered mode, the default value of irq1/11/12 to serirq via routing logic is high and a negative pulse will be generated when the interrupt condition occurs. note that the polarity definition in edge- triggered is different from scipm field in pmctl register and smipm field in pmic register. 000: level-triggered mode. 001: edge-triggered mode with 1-cycle pulse width. 010: edge-triggered mode with 2-cycle pulse width. 011: edge-triggered mode with 4-cycle pulse width. 100: edge-triggered mode with 8-cycle pulse width. 101: edge-triggered mode wi th 16-cycle pulse width. other: reserved. 2 r/w 1 irq11 control bit (irq11b) when the pmhie bit in kbc host interf ace control register (kbhicr) is 0, the bit directly controls the irq11 signal. the bit can be used to monitor the status of irq11 signal. 1 r/w 1 irq12 control bit (irq12b) when the obfmie bit in kbc host interf ace control register (kbhicr) is 0, the bit directly controls the irq12 signal. the bit can be used to monitor the status of irq12 signal. 0 r/w 1 irq1 control bit (irq1b) when the obfkie bit in kbc host interf ace control register (kbhicr) is 0, the bit directly controls the irq1 signal. the bit can be used to monitor the status of irq1 signal. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 96 it8511 e /te/ g 6.5.5.3 kbc host interface keyboa rd/mouse status register (kbhisr) the 8032 firmware uses the register to monitor the st atus of kbc. it can use bit 7-4 and bit 2 to send the information to the host processor. the data of this regi ster is the same as the dat a of kbc status register (kbstr). address offset: 04h bit r/w default description 7-4 r/w 0h programming data 3-0 (pd3-0) the data is used by the 8032 firmware to be the general-purpose setting. 3 r 0 a2 address (a2) the bit is used to keep the a2 address in formation of the write operation while the host processor accesses the kbc. 2 r/w 0 programming data ii (pdii) the function is the same as pd3-0. 1 r 0 input buffer full (ibf) when the host processor is writing dat a to kbdir or kbcmdr, the bit is set. on the other hand, the bit will be cleared when kbhidir is read by the 8032 firmware. 0 r 0 output buffer full (obf) when 8032 is writing data to kbhikdor and kbhimdor, the bit is set. on the other hand, the bit will be cleared when the kbdor is read by the host. 6.5.5.4 kbc host interface keyboard data output register (kbhikdor) the 8032 firmware can write the register to send the da ta of the kbc data output register (kbdor). besides, the action will set the obf bit in the kbc status regi ster (kbstr). if the obecie bit in the kbc interrupt control register (kbirqr) is enabled, the action will clear the interrupt. address offset: 06h bit r/w default description 7-0 w - kbc keyboard data output (kbkdo) the data output to the kbc data output register (kbdor). 6.5.5.5 kbc host interface mouse data output register (kbhimdor) the 8032 firmware can write the register to send the da ta of the kbc data output register (kbdor). besides, the action will set the obf bit in the kbc status regi ster (kbstr). if the obecie bit in the kbc interrupt control register (kbirqr) is enabled, the action will clear the interrupt. address offset: 08h bit r/w default description 7-0 w - kbc mouse data output (kbkdo) the data output to the kbc data output register (kbdor). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 97 host domain functions 6.5.5.6 kbc host interface keyboard/m ouse data input register (kbhidir) the 8032 firmware can read the register to get the data of the kbc data input register (kbdir). besides, the action will clear the ibf bit in the kbc status register (kbstr). if the ibfcie bit in the kbc interrupt control register (kbirqr) is enabled, t he action will clear the interrupt. address offset: 0ah bit r/w default description 7-0 r - kbc keyboard/mouse data input (kbkmdi) the data is the same as the data of kbc data input register (kbdir). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 98 it8511 e /te/ g 6.6 power management channel (pmc) 6.6.1 overview the power management channel is defined in acpi specification and used as a communication channel between the host processor and embedded controller. 6.6.2 features ? supports two pm channels ? supports compatible mode and enhanced mode (both channels) ? supports shared and private interface ? supports command/status and data ports ? supports irq/smi/sci generation 6.6.3 functional description to generate the sci and smi interrupts to the host 6.6.3.1 general description the pm channel supports two operation modes: one is called compatible mode that is available for channel 1 only. the other is called enhanced mode. pmc is avail able for both channels. the pm channel provides four registers: pmdir, pmdor, pmcmdr and pmstr for communication between the ec and host side. the pmdir register can be written to by the host and read by the ec. the pmdor register can be written to by the ec and read by the host. the pmcmdr/pmstr register can be read by both the ec and host side. the pmc host interface block diagram is shown below. figure 6-9. pmc host interface block diagram i bus ec bus pmstr pmdor (legacy 62h) pmdir output buffer empty input buffer full irq/smi#/sci# (legacy 62h) (legacy 66h) ec interrupts two interrupts (ibf and obf) are connected to intc. these interrupts are enabled by obeie and ibfie in pmctln register respectively. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 99 host domain functions the diagram of pmc interrupt to ec 8032 via int3/int25 of intc is shown below. figure 6-10. ec interrupt request for pmc obf@pmsts obeie@pmctl ibfie@pmctl ibf@pmsts ibf interrupt to 8032 via int25 obe interrupt from pm1 obe interrupt from pm2 ibf interrupt from pm1 ibf interrupt from pm2 obe interrupt to 8032 via int3 host interrupt the ec can select to access to different address space to generate irq, smi or sci interrupt when either ibf or obf is set. the irq numbers of pmc are programmable and use irq11 as the abbreviation in the following section. the abbreviation, n, represents channel 1 and/or channel 2 of this register. 6.6.3.2 compatible mode when irq numbers in host configuration register ar e assigned by host software, and the interrupt can be generated either by hardware via pm1hie in kbhicr regi ster or by programming kbirqr register. in normal polarity mode (irqnp in kbirqr register is cleared), it8511 supports legacy level for pm compatible mode interrupt. when a level interrupt is selected (irqm in kbirqr register is cleared), the interrupt signal is asserted when the obf flag has been set, which is still asserted until the output buffer is read (i.e.,obf flag is cleared). the ec can control the interrupts gene rated by the pm channel to the one as follows: irq signal to lpc/serirq, when irqen bit in pmien register is set. smi# output to swuc, when smien bit in pmien register is set. sci# signal, using the sciec output, when scien bit in pmien register is set. the irq/sci#/smi# control diagram in pmc compatible mode is shown below. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 100 it8511 e /te/ g figure 6-11. irq/sci#/smi# cont rol in pmc compatible mode hw level/edge control 0 1 irq11b@kbirqr 1 0 irq routing controlled by pnpcfg serirq smien@pmie scien@pmie 0 1 0 1 smi# to swuc sci# to pin sminp@pmic scinp@pmctl irqen@pmie pm1hie@kbhicr irqnp@kbirqr irqm@kbirqr read irq11b@kbirqr write o b f hw path sw path read irqb@pmic 6.6.3.3 enhanced pm mode enhanced pm mode is activated when apm is set to 1 in pmctln register. irq, smi or sci interrupts generated can be selected to output via software control or hardware. which channel will be output an irq is decided by programming irqen bit in pmien register. sci and smi are generated when ec writes to the data output buffer. sci is generated when ec reads the data input buffer. different data register generates different interrupt. the obf flag in pmstsn register is se t and both smi and sci interrupts are deasserted when pmdon register is written into data. the obf_smi interr upt is generated when pmdosmin register is written into data. the obf_smi flag is cleared when obf flag is cleared. the obf_sci interrupt is generated when pmdoscin register is written into data.obf_sc i which is cleared when obf is cleared. the ibf flag is cleared and sci interrupt is generated when pmdiscin register is read out data. the ibf flag is cleared and sci interrupt is not asserted when pmdin register is read out data. the irq/sci/smi control diagram in pmc enhanced mode is shown below. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 101 host domain functions figure 6-12. irq/sci#/smi# control in pmc enhanced mode obf hw level/edge control write pmdo write pmdosmi write pmdosci irqnp@kbirqr 1 0 serirq irqb hwirqen@pmie irqen@pmie irqm@kbirqr read irqb@pmic set obf for smi set obf for sci level/edge smib@pmic 0 1 0 1 set ibf for sci clear ibf@pmsts level/edge scib@pmic 1 0 1 0 0 1 write irqb@pmic smipm@pmic hwsmien@pmie read smib@pmic smien@pmie sminp@pmic smi# to swuc read scib@pmic scien@pmie scinp@pmctl sci# of other channel hwscien@pmie scipm@pmctl read pmdisci read pmdi sci# to pin read irq11b@kbirqr hw path sw path irq routing controlled by pnpcfg 6.6.3.4 pmc2ex there is a channel 2 extended (pmc2ex) mailbox (mbx) function based on pmc channel 2, which is constructed by a 16-byte mailbox shared with bram. see also figure 7-34. bram mapping diagram on page 265. this 16-byte mailbox can be accessed from both the ec side (nam ed mbxec0-15) and host side (mbxh0-15). in the ec side, mbxec0-15 is always located in pmc module offset f0h-ffh. in the host side, mbxh0-15 address is based on the des criptor 2 of power management i/f channel 2 logic device inside lpc i/o space. (refer to section 6.2.10.6 and 6.2.10.7 on page 58) the pmc2ex (channel 2 extended) shares the same inte rrupt generation resource and registers (offset 10h-18h). for registers, pmc2ex shares the same registers (o ffset 10h-18h) and has its dedicated mbxctrl register (offset 19h). for interrupt generation, pmc2ex shares the same interrupt logic with c hannel 2. if mbxen is set, ibf/obf interrupt source of pmc2ex is ored with channel 2. the ec/host side should check whether to get the gr ant from the internal arbiter after writing to mbxec0/mbxh0 (respectively). the typical pmc2ex mailbox operation is described below. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 102 it8511 e /te/ g figure 6-13. typical pmc2ex mailbox operation ec check whether getting the grant by reading status register ec write mbxec15 host read mbxh0 host read mbxh15 pmc2ex mailbox is granted to ec pmc2ex obf set pmc2ex obf cleared pmc2ex mailbox is free 1..14 1..14 ec write mbxec0 yes host check whether getting the grant by reading status register host write mbxh15 ec read mbxec0 ec read mbxec15 pmc2ex mailbox is granted to host pmc2ex ibf set pmc2ex ibf cleared pmc2ex mailbox is free 1..14 1..14 host write mbxh0 yes 6.6.4 host interface registers the registers of pmc can be divided into two parts: ho st interface registers and ec interface registers and this section lists the host interface. the host interf ace registers can only be acce ssed by the host processor. the pmc channel 1 and 2 reside at lpc i/o space and the base address can be configured through lpc pnpcfg registers. the channel 1 logical device number is 11h (ldn=11h) and the channel 2 logical device number is 12h (ldn=12h). for compatibility issue, the tw o i/o port base addresses of channel 1 are suggested to configure at 62h and 66h. these registers are listed below. table 6-21. host view register map, pmc 7 0 offset pmc data input register (pmdir) legacy 62h pmc data output register (pmdor) legacy 62h pmc command register (pmcmdr) legacy 66h pmc status register (pmstr) legacy 66h legacy 62h represents (i/o port ba se address 0) + (offset 0h) legacy 66h represents (i/o port ba se address 1) + (offset 0h) see also table 6-3 on page 40. 6.6.4.1 pmc data input register (pmdir) address offset: 00h for i/o port base address 0, legacy 62h for channel 1 bit r/w default description 7-0 w 0h data input register bit [7:0] (dirb) this is the data input register for power management channel data communication between the host and ec side. when the host writes this port, data is written to pmdir register and ec 8032 can read it. notice that when the command/status register is wr itten, the data is also stored into pmdir register. users must read a2 to decide whether the pmdir data is data or command. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 103 host domain functions 6.6.4.2 pmc data output register (pmdor) address offset: 00h for i/o port base address 0, legacy 62h for channel 1 bit r/w default description 7-0 r 0h data output register bit [7:0] (dorb) this is the data output register for power management channel data communication between the host and ec. when the host reads this port, data is read from pmdor register and ec 8032 can write it. 6.6.4.3 pmc command register (pmcmdr) address offset: 00h for i/o port base address 1, legacy 66h for channel 1 bit r/w default description 7-0 w 0h command register bit [7:0] (crb) the port is written by the host when a2 = 1 in pmstr register. 6.6.4.4 status register (pmstr) address offset: 00h for i/o port base address 1, legacy 66h for channel 1 bit r/w default description 7-4 r/w 0h status register (sts) for channel 1 and channel 2 with mbxen cleared: this is a general purpose flag used for signaling between the host and ec side. when used as acpi pm channel, the predefined meaning is burst, sci event and smi event. for channel 2 with mbxen set: bit 7: ibf of pmc channel 2 extended (pmc2ex) bit 6: obf of pmc channel 2 extended (pmc2ex) bits 5-4: 00b: pmc2ex mailbox is not granted to both sides. 01b: pmc2ex mailbox is granted to the ec side. 10b: pmc2ex mailbox is granted to the host side. 11b: reserved 3 r 0h a2 (a2) this bit is used to indicate the last write (by host) address bit a2. if the bit is 0, it represents that the data written by the host is data. if this bit is 1, it represents that the data wri tten by the host is command. 2 r/w 0h general purpose flag (gpf) this bit is used as a general-purpose flag. 1 r 0h input buffer full (ibf) this bit is used to indicate that the pmdir of the pm channel has been written by the host. this bit is set wh en the host writes data input register or command register and is cleared when the ec 8032 reads the data input register. notice that the write to data input register or command register by the host all trigger this fl ag and ec must use a2 to distinguish whether the write is a command or data. 0 r 0h output buffer full (obf) this bit is used to indicate that the pmdor of the pm channel has been written by the ec. this bit is set wh en ec writes the data output port and is cleared when the host reads the data out buffer. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 104 it8511 e /te/ g 6.6.5 ec interface registers the registers of pmc can be divided in to two parts, host interface register s and ec interface registers. this section lists the ec interface. the ec interface can only be accessed by t he internal 8032 processor. the base address is 1500h. these registers are listed below. table 6-22. ec view register map, pmc 7 0 offset host interface pm channel 1 status (pm1sts) 00h host interface pm channel 1 data out port (pm1do) 01h host interface pm channel 1 data out port with sci (pm1dosci) 02h host interface pm channel 1 data out port with smi (pm1dosmi) 03h host interface pm channel 1 data in port (pm1di) 04h host interface pm channel 1 data in port with sci (pm1disci) 05h host interface pm channel 1 control (pm1ctl) 06h host interface pm channel 1 interrupt control (pm1ic) 07h host interface pm channel 1 interrupt enable (pm1ie) 08h host interface pm channel 2 status (pm2sts) 10h host interface pm channel 2 data out port (pm2do) 11h host interface pm channel 2 data out port with sci (pm2dosci) 12h host interface pm channel 2 data out port with smi (pm2dosmi) 13h host interface pm channel 2 data in port (pm2di) 14h host interface pm channel 2 data in port with sci (pm2disci) 15h host interface pm channel 2 control (pm2ctl) 16h host interface pm channel 2 interrupt control (pm2ic) 17h host interface pm channel 2 interrupt enable (pm2ie) 18h mailbox control (mbxctrl) 19h 16-byte pmc2ex mailbox 0 (mbxec0) f0h ? ? 16-byte pmc2ex mailbox 15 (mbxec15) ffh 6.6.5.1 pm status register (pmsts) this register is the same as the status regi ster in host side but reside in the ec side. address offset: 00h/10h bit r/w default description 7-4 r/w 0h status register (sts) for channel 1 and channel 2 with mbxen cleared: this is a general-purpose flag used for signaling between the host and ec. when used as acpi pm channel, the predefined meaning is burst, sci event and smi event. for channel 2 with mbxen set: bit 7: ibf of pmc channel 2 extended (pmc2ex) bit 6: obf of pmc channel 2 extended (pmc2ex) bits 5-4: 00b: pmc2ex mailbox is not granted to both sides. 01b: pmc2ex mailbox is granted to the ec side. 10b: pmc2ex mailbox is granted to the host side. 11b: reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 105 host domain functions bit r/w default description 3 r 0h a2 (a2) this bit is used to indicate the last wr ite (by host) address bit a2. if the bit is 0, it represents that the data written to th e data port is data. if this bit is 1, it represents that the data writt en to the data port is command. 2 r/w 0h general purpose flag (gpf) this bit is used as a general-purpose flag. 1 r 0h input buffer full (ibf) this bit is used to indicate that the pmdir of the pm channel has been written by the host. this bit is se t when host write data port or command port and is cleared when the ec read the data in the buffer. 0 r 0h output buffer full (obf) this bit is used to indicate that the pmdor of the pm channel has been written by the ec. this bit is set w hen ec writes data port and is cleared when the host reads the data output buffer. 6.6.5.2 pm data out port (pmdo) this register is the pmdor buffer. the data wr itten to this register is stored in pmdor. address offset: 01h/11h bit r/w default description 7-0 w 0h pm data out (pmdo[7:0]) this is the data output buffer. 6.6.5.3 pm data out port with sci (pmdosci) this register is the pmdor buffer with sci. the data wr itten to this register is stored in pmdor. sci is generated upon write. address offset: 02h/12h bit r/w default description 7-0 w 0h pm data out with sci (pmdosci[7:0]) this is the data output buffer with sc i. writing to this port will generate hardware sci if enabled. 6.6.5.4 pm data out port with smi (pmdosmi) this register is the pmdor buffer with smi. the data wr itten to this register is stored in pmdor. smi is generated upon write. address offset: 03h/13h bit r/w default description 7-0 w 0h pm data out with smi (pmdosmi[7:0]) this is the data output buffer with sm i. writing to this port will generate hardware smi if enabled. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 106 it8511 e /te/ g 6.6.5.5 pm data in port (pmdi) this register is the pmdir buffer. host writt en data or command is stored in this buffer. address offset: 04h/14h bit r/w default description 7-0 r 0h pm data in (pmdi[7:0]) this is the data input buffer. 6.6.5.6 pm data in port with sci (pmdisci) this register is the pmdir buffer. ho st written data or command is stored in this buffer. reading this register (ec) generates sci. address offset: 05h/15h bit r/w default description 7-0 r 0h pm data in with sci (pmdisci[7:0]) this is the data input buffer with sci. reading this port will generate sci when enabled. 6.6.5.7 pm control (pmctl) address offset: 06h/16h bit r/w default description 7 r/w 0h enhance pm mode (apm) setting this bit to ?1? enables the enhance pm mode. the interrupts (irq, sci or smi) are automatically generated by hardware operations if enabled. 6 r/w 1h sci negative polarity (scinp) setting this bit to ?1? causes the sci polarity inversed (low active). 5-3 r/w 0h sci pulse mode (scipm[2:0]) these bits are used to control the in terrupt type to be level-triggered or edge-triggered (pulse) mode. in level-triggered mode, the default value of irq1/11/12 to serirq via routing logic is low and will be set to high when the interrupt condition occurs. in edge-triggered mode, the default value of irq1/11/12 to serirq via routing logic is low and a positi ve pulse will be ge nerated when the interrupt condition occurs. note that the polarity definition in edge-triggered is different from irqm field in kbirqr register. 000: level-triggered mode. 001: edge-triggered mode with 1-cycle pulse width. 010: edge-triggered mode with 2-cycle pulse width. 011: edge-triggered mode with 4-cycle pulse width. 100: edge-triggered mode with 8-cycle pulse width. 101: edge-triggered mode wi th 16-cycle pulse width. other: reserved. 2 - 0h reserved 1 r/w 0h output buffer empty interrupt enable (obeie) setting this bit to ?1? enables the ec interrupt generation when the output buffer full flag is cleared (by host reading the data port). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 107 host domain functions bit r/w default description 0 r/w 0h input buffer full interrupt enable (ibfie) setting this bit to ?1? enables the ec interrupt generation when the input buffer full flag is set (by host writing the data port or command port). 6.6.5.8 pm interrupt control (pmic) address offset: 07h/17h bit r/w default description 7 - 0b reserved 6 r/w 1b smi negative polarity (sminp) setting this bit to ?1? causes the smi polarity inversed. 5-3 r/w 0h smi pulse mode (smipm[2:0]) these bits are used to control the in terrupt type to be level-triggered or edge-triggered (pulse) mode. in level-triggered mode, the default value of irq1/11/12 to serirq via routing logic is low and will be set to high when the interrupt condition occurs. in edge-triggered mode, the default value of irq1/11/12 to serirq via routing logic is low and a positi ve pulse will be ge nerated when the interrupt condition occurs. note that the polarity definition in edge-triggered is different from irqm field in kbirqr register. 000: level-triggered mode. 001: edge-triggered mode with 1-cycle pulse width. 010: edge-triggered mode with 2-cycle pulse width. 011: edge-triggered mode with 4-cycle pulse width. 100: edge-triggered mode with 8-cycle pulse width. 101: edge-triggered mode wi th 16-cycle pulse width. other: reserved. 2 r/w 0b host sci control bit (scib) this bit is the sci generation bit when hardware sci is disabled. read always returns the current value of sci. 1 r/w 0b host smi control bit (smib) this bit is the smi generation bit when hardware smi is disabled. read always returns the current value of smi. 0 r/w 1b host irq control bit (irqb) this bit is the irq generation bit when hardware irq is disabled. read always returns the current value of irq. 6.6.5.9 pm interrupt enable (pmie) address offset: 08h/18h bit r/w default description 7-6 - 0h reserved 5 r/w 0h hardware smi enable (hwsmien) setting this bit to ?1? enables the smi generated by hardware control. writing to the smib bit generates the smi if this bit is set to ?0?. 4 r/w 0h hardware sci enable (hwscien) setting this bit to ?1? enables the sc i generated by hardware control. writing to the scib bit generates the sci if this bit is set to ?0?. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 108 it8511 e /te/ g bit r/w default description 3 r/w 0h hardware irq enable (hwirqen) setting this bit to ?1? enables the irq generated by hardware control. writing to the irqb bit generates the irq if this bit is set to ?0?. 2 r/w 0h smi enable (smien) setting this bit to ?1? enables the smi generated by this module. 1 r/w 0h sci enable (scien) setting this bit to ?1? enables the sci generated by this module. 0 r/w 0h irq enable (irqen) setting this bit to ?1? enables the irq generated by this module. 6.6.5.10 pm interrupt enable (pmie) address offset: 19h bit r/w default description 7 r/w 0b mailbox enable (mbxen) 1b: enable 16-byte pmc2ex mailbox 0b: otherwise 6-0 - - reserved 6.6.5.11 16-byte pmc2ex mailbox 0-15 (mbxec0-15) address offset: f0h-ffh bit r/w default description 7-0 r/w - mailbox byte content this byte is the 16-byte pmc2ex mailbox in the ec side. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 109 host domain functions 6.7 trusted mobile kbc (tmkbc) 6.7.1 overview this trusted mobile kbc supports the functions in an lt (lagrande technology) compatible platform associated with trusted input and output for mobile keyboard controller (tmkbc) devices. 6.7.2 features ? compatible with the lt trusted mob ile kbc specification (revision 0.95). ? automatically generates interrupts to the host side and ec side when the status is changed. 6.7.3 functional description 6.7.4 host interface registers the registers of tmkbc can be divided into two parts: ho st interface registers and ec interface registers. the host interface registers only can be ac cessed by the host processor. the following host interface registers are in the lt private register space, st arting at base address b000h and accessed via lpc trusted port cycles. table 6-23. host view register map, tmkbc 7 0 offset tmkbc vendor id register (tvendid) 01h-00h tmkbc device id r egister (tdevid) 03h-02h tmkbc version register (tver) 05h-04h generic capabilities repor ting register (cap) 06h tmkbc revision id register (trevid) 07h configuration register (cnf) 09h-08h control register (cnt) 0bh-0ah irq capabilities reporting register (irqcap) 0dh-0ch reserved 0fh-0eh status register (sts) 11h-10h reserved 12h extended status register (extsts) 13h reserved 16h-14h interrupt trigger enable register (inttrig) 17h tmkbc data input register (tdatain) 1bh-18h reserved 1fh-1ch tmkbc data output register (tdataout) 23h-20h 6.7.4.1 tmkbc vendor id register (tvendid) this register reports the vendor id of the tmkbc. address offset: 01h-00h bit r/w default description 15-0 r - vendor id (vendid) vendor?s id value. it is the same as pci vendor?s id. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 110 it8511 e /te/ g 6.7.4.2 tmkbc device id register (tdevid) this register reports the device id of the tmkbc. address offset: 03h-02h bit r/w default description 15-0 r - device id (devid) device id value. 6.7.4.3 tmkbc versi on register (tver) this register reports the version number of the tmkbc. address offset: 05h-04h bit r/w default description 15-0 r - version number (ver) version number of the tmkbc logic. 6.7.4.4 generic capabilities reporting register (cap) this register reports t he capabilities of the tmkbc. address offset: 06h bit r/w default description 7-4 r - reserved 3 r 0b msi interrupt capability (msi) this bit will be one if the tmkbc supports the optional msi delivery method for interrupts. 2 r 0b led capability (led) this bit will be one if the tmkbc supports the optional led. 1-0 r 00b poll rate (poll) this field indicates the rate at which the tmkbc must be polled if the tsw operates the tmkbc in a poll mode. 00: 6ms 01: 8ms 10: 10ms 11: 12ms 6.7.4.5 tmkbc revision id register (trevid) this register reports the revision id of the tmkbc. address offset: 07h bit r/w default description 7-0 r - revision id (revid) revision id of the tmkbc. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 111 host domain functions 6.7.4.6 configuration register (cnf) this register is used to configure the tmkbc. address offset: 09h-08h bit r/w default description 15-13 - - reserved 12-9 r/w 0000b tmkbc irq selection (irqsel) software configures this field to sele ct which interrupt to be used. values must be programmed to it indicated in the irq capabilities reporting register. 8 r/w 0b tmkbc force irq (firq) software sets this bit to one to force irq to be activated. this bit is used for testing the interrupt path. 7-2 - - reserved 1 r/w 0b tmkbc reset (tmkbcrst) software sets this bit to 1 and then to 0 to reset the tmkbc logic. 0 r/w 0b tmkbc enable (tmkbcen) software sets this bit to put the tmkbc into the trust mode. 1: trust mode 0: legacy mode 6.7.4.7 control register (cnt) this register is used to control the tmkbc. address offset: 0bh-0ah bit r/w default description 15-9 - - reserved 8 r/w 0b kana led enable (led) software sets this bit to one to turn on the kana led. 7 r/w 0b compose led enable (comled) software sets this bit to one to turn on the compose led. 6 r/w 0b scroll lock led enable (scrled) software sets this bit to one to turn on the scroll lock led. 5 r/w 0b cap lock led enable (capled) software sets this bit to one to turn on the cap lock led. 4 r/w 0b num lock led enable (numled) software sets this bit to one to turn on the num lock led. 3-1 - - reserved 0 r/w 0b tmkbc command control (cmdcnt) software sets this bit to one to te ll the tmkbc to execute the command that has been written to the data input register. this bit will be cleared after the tmkbc completes the command and then places the result in the data output register. software must not perform a subsequent command until the current command has been completed. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 112 it8511 e /te/ g 6.7.4.8 irq capabilities re porting register (irqcap) this register is used to report the irq capabilities. address offset: 0dh-0ch bit r/w default description 15-0 r dffeh irq capabilities (irqcap) the respective bit will be one if t he tmkbc can be conf igured to select that interrupt. for example, if the tmkbc can be configured to generate irq1 and irq14, bits 1 and 14 will be set in this register. 6.7.4.9 status register (sts) this register reports t he status of the tmkbc. address offset: 11h-10h bit r/w default description 15 r 0b tmkbc operating mode (mode) 1: in the trust mode. 0: not in the trust mode. 14 r 0b extended error (exterr) 1: some types of errors or other event occurs. see the extended status register for further details. 0: no error occurs. 13-12 - - reserved 11-8 r/w 1000b write buffer status (wbufsts) 0: data input (write) buffer is full. any value other than 0 indicates the number of bytes that can be written to the data input (write) buffer. 7-6 r 00b read buffer data type (rbuftyp) 00: command response 01: first generation hid device 5-4 - - reserved 3-0 r 0000b read buffer status (rbufsts) 0: data output (re ad) buffer is empty. any value other than 0 indicates the number of bytes that can be read from the data output (read) buffer. 6.7.4.10 extended status register (extsts) this register is used to report erro rs and other details of the status. address offset: 13h bit r/w default description 7-4 - - reserved 3 r 0b force irq sts (firqs) this bit is set to indicate that irq is asserted due to the tmkbc force irq bit being set. this bit is cleared when the tmkbc force irq bit is cleared. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 113 host domain functions bit r/w default description 2 r/w1c 0b command error status (cerrs) this bit is set when an error occurs in the command unit this bit is cleared by writing a one to the position of this bit. 1 r/w1c 0b mouse overrun status (mos) this bit is set when the mouse over run occurs. this bit is cleared by writing a one to the position of this bit. 0 r/w1c 0b keyboard overrun status (kos) this bit is set when the keyboard overrun occurs. this bit is cleared by writing a one to the position of this bit. 6.7.4.11 interrupt trigger enable register (inttrig) this register is used to enable the interrupt. address offset: 17h bit r/w default description 7-1 - - reserved 0 r/w 0b interrupt enable (inten) software writes this bit to one to enable the interrupt. once the tmkbc has sent an interrupt, this bit (inten ) will be reset to a 0 and the tmkbc must not send another interrupt until it is set to 1 by software. 6.7.4.12 tmkbc data input register (tdatin) this register is used to write data and commands to the tmkbc. address offset: 1bh-18h bit r/w default description 7-0 w 00h data input (datin) data written to this register will be stored in the tmkbc?s input buffer. 6.7.4.13 tmkbc data output register (tdatout) this register is used to read data from the tmkbc. address offset: 23h-20h bit r/w default description 7-0 r 00h data output (datout) read this register will get data from the tmkbc?s output buffer. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 114 it8511 e /te/ g 6.7.5 ec interface registers the registers of the tmkbc can be divided into two parts: host interface registers and ec interface registers. the ec interface registers can only be accessed by the internal 8032 processor. t he base address of the ec interface register is 2400h. table 6-24. ec view register map, tmkbc 7 0 offset ec side configuration register (eccon) 00h status control register (stscon) 01h ec data input register (edatin) 02h ec data output register (edatout) 03h ec buffer status register (ebufsts) 04h ec status register (ests) 05h ec vendor id low register (evenl) 06h ec vendor id high register (evenh) 07h ec device id low register (edevl) 08h ec device id high register (edevh) 09h ec version low register (everl) 0ah ec version high register (everh) 0bh ec revision id register (erevid) 0ch 6.7.5.1 ec side configuration register (eccon) address offset: 00h bit r/w default description 7-6 - - reserved 5 r/w 0b ec read buffer inte rrupt enable (erbie) this bit is used to enable the interrupt when the read buffer has the 8-byte data package. 4 r/w 0b operating mode interrupt enable (mie) this bit is used to enable the interrupt when the operating mode is changed (the tmkbcen bit is enabled or disabled). 3-0 r/w 0h ec irq selection (eirqs) software configures this field to pr ogram the tmkbc irq selection bits in the configuration register. 6.7.5.2 status control register (stscon) address offset: 01h bit r/w default description 7-4 - - reserved 3 w 0b clear tmkbc command control (ctc) this bit is used to clear the tmkbc command control bit in the control register. 2 w 0b set command error status (sces) this bit is used to set the command error status bit in the extended status register to 1. 1 w 0b set mouse overrun status (smos) this bit is used to set the mouse overrun status bit in the extended status register to 1. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 115 host domain functions bit r/w default description 0 w 0b set keyboard overrun status (skos) this bit is used to set the keyboa rd overrun status bit in the extended status register to 1. 6.7.5.3 ec data input register (edatin) address offset: 02h bit r/w default description 7-0 r 00h ec data input (edatin) reading this register will get data from the tmkbc?s input buffer. 6.7.5.4 ec data output register (edatout) this register is used to write data to the host side. address offset: 03h bit r/w default description 7-0 w 00h ec data output (edatout) data written to this register will be stored in the tmkbc?s output buffer. 6.7.5.5 ec buffer status register (ebufsts) address offset: 04h bit r/w default description 7-4 r 1000b ec write buffer status (ewbsts) 0: write buffer is full. any value other than 0 indicates the number of bytes that can be written to the write buffer. 3-0 r 0000b ec read buffer status (erbsts) 0: read buffer is empty. any value other than 0 indicates the number of bytes that can be read from the read buffer. 6.7.5.6 ec status register (ests) address offset: 05h bit r/w default description 7 r 0b tmkbc enable status this bit will mirror the value of the tmkbcen bit in the cnf register. the ec firmware can read this bit to get the value of the tmkbcen bit in the cnf register. 2-6 - - reserved 1 r/w1c 0b ec read buffer status (erbs) this bit is set when the read buffer has the 8-byte data package. 0 r/w1c 0b trust mode change status (tmcs) this bit is set when the operating mode is changed. this bit is cleared by writing a one to the position of this bit. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 116 it8511 e /te/ g 6.7.5.7 ec vendor id low register (evenl) this register is used to define the vendor id of bits [7:0]. address offset: 06h bit r/w default description 7-0 r/w 00h ec vendor id low bits (evidl) ec firmware can use these bits to define the vendor id of bits [7:0]. 6.7.5.8 ec vendor id high register (evenh) this register is used to define the vendor id of bits [15:8]. address offset: 07h bit r/w default description 7-0 r/w 00h ec vendor id high bits (evidh) ec firmware can use these bits to define the vendor id of bits [15:8]. 6.7.5.9 ec device id low register (edevl) this register is used to define the device id of bits [7:0]. address offset: 08h bit r/w default description 7-0 r/w 00h ec device id low bits (edevl) ec firmware can use these bits to define the device id of bits [7:0]. 6.7.5.10 ec device id high register (edevh) this register is used to define the device id of bits [15:18]. address offset: 09h bit r/w default description 7-0 r/w 00h ec device id high bits (edevh) ec firmware can use these bits to def ine the device id of bits [15:18]. 6.7.5.11 ec version low register (everl) this register is used to define t he version register of bits [7:0]. address offset: 0ah bit r/w default description 7-0 r/w 00h ec version register low bits (evrl) ec firmware can use these bits to define the version register of bits [7:0]. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 117 host domain functions 6.7.5.12 ec version high register (everh) this register is used to define the version register of bits [15:8]. address offset: 0bh bit r/w default description 7-0 r/w 00h ec version register high bits (evrh) ec firmware can use these bits to define the version register of bits [15:8]. 6.7.5.13 ec revision id register (erevid) this register is used to define t he version register of bits [7:0]. address offset: 0ch bit r/w default description 7-0 r/w 00h ec revision id register (erevid) ec firmware can use these bits to define the revision id register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 118 it8511 e /te/ g 6.8 real-time clock (rtc) 6.8.1 overview the rtc module provides timekeeping and calendar managem ent capabilities. the alarm function is available ranging from once a second to once a month. 6.8.2 feature ? timekeeping and calendar management. ? supports two-bank sram. ? time of day alarm ranging from once a second to once a month. ? four interrupt features are ava ilable: periodic interrupt, alarm 1 interrupt, alarm 2 interrupt, and update ended interrupt. ? valid timekeeping during power-down. ? supports bcd or binary format to represent the time. ? supports daylight saving compensation function. ? supports automatic leap year compensation function. ? latches lpc i/o port 80h written data into sram of rtc bank 1 (p80l function) 6.8.3 functional description 6.8.3.1 timekeeping the rtc includes two sram with 128 bytes for each bank, and provides the function of timekeeping and calendar. it uses a 32.768khz clock signal for timeke eping. the 32.768 khz clock can be supplied by the internal rtc oscillator circuit. the rtc update cycle occurs once a second if the set mode bit in the rtc control register b is programmed to 0 and the divider chain control fiel d in the rtc control register a is programmed to 010. time is kept in bcd or binary format, as determined by data mode field in the rtc control register b, and in either 12 or 24-hour format, as determined by hour mode field in the rtc control register b. the daylight saving time function is enabled by settling the daylight savings (ds) bit in the rtc control register b. 6.8.3.2 update cycles because the time and calendar registers are updated seri ally, unpredictable results may occur if they are accessed during the update. ther efore, we need to ensure that reading or writing to the time registers does not coincide with a system update of these locations. ther e are two methods to avoid this contention. the first method is using the update-ended interrupt to avoid t he update cycle period. when the update-ended interrupt is enabled, the interrupt will be generated immediately fo llowing the end of the update cy cle. when the interrupt is received, this implies that an update has just been completed, and 999 ms remain until the next update. the second method uses the ?update in progress? (uip) bit in the rtc control register a to determine whether the update cycle is in progress or not. if the uip bit is 0, it is committed that the update cycle will not start for at least 244 p s. 6.8.3.3 interrupts the rtc has three interrupt lines, one (irq) is connected to serirq and handles the three interrupt conditions: periodic interrupt, alarm 1 interrupt, and update end in terrupt the others are alarm1 interrupt and alarm2 interrupt which are connected to swuc and intc (int 29) respectively. the interrupts are generated if the respective enable bits in rtc control register b are se t prior to an interrupt event occurrence. the periodic interrupt rate select (pirsel) field in rtc control regi ster a controls the rate of the periodic interrupt. the alarm 1 interrupt and alarm 2 interrupt will be generated when the current time reaches a stored alarm time. any alarm registers may be set to ?unconditional match? by setting bits 7 and 6 in the alarm register. the update ended interrupt is generated in the end of the update cycle. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 119 host domain functions 6.8.3.4 p80l if this function is enabled by p80len bit in spctrl1 regi ster, lpc i/o port 80h written data will be latched into sram of rtc bank 1. the data may fail to latch data if there is a transaction cy cle to bram or ec2i->rtc in the ec side at the same time unless acp80 bit in spctrl1 register is set, wh ich guarantees written data is latched into sram by issuing long wait sync on host lpc bus. the 7-bit destination address range in rtc bank 1 is determined by p80lb, p80le regi ster in the host side, which constructs a queue. p80lb: it indicates the start index of the queue. readable/writable. p80le: it indicates the end index of the queue. readable/writable. p80lc: it indicates the current index of the queue. read-only. these three registers are supplied by vbs power and not affected by vcc status. whenever written data is latched, p 80lc increases one. if it reaches p80le (queue end), it will wrap back to p80lb (queue begin). 6.8.4 host interface registers the rtc resides at lpc i/o space and the base addr ess can be configured through lpc pnpcfg registers. the rtc logical device number is 10h (ldn=10h). for com patibility issue, the two i/o port base addresses of channel are suggested to configure at 70h and 72h and it make two index/data pairs mapped into 70h-73h. these registers are listed below. table 6-25. host view register map, rtc 7 0 offset rtc index register of bank 0 (rirb0) legacy 70h rtc data register of bank 0 (rdrb0) legacy 71h rtc index register of bank 1 (rirb1) legacy 72h rtc data register of bank 1 (rdrb1) legacy 73h legacy 70h represents (i/o port ba se address 0) + (offset 0h) legacy 71h represents (i/o port ba se address 0) + (offset 1h) legacy 72h represents (i/o port ba se address 1) + (offset 0h) legacy 73h represents (i/o port ba se address 1) + (offset 1h) see also table 6-3 on page 40. the rtc has two banks of sram, which are bank 0 sram and bank 1 sram. all rtc time, alarm data, and control registers are acce ssed by the rtc index and da ta registers. note rtc registers are not allowed to be access ed if lkrtc bit in lsioha register of ec2i module is set. the index register points to the register location being access ed, and the data register contains the data to be transferred to or from the location. the bank 0 sram is accessed via the first pair of the index and data registers (legacy index 70h, 71h). the bank 1 sram is accessed via the second pair of the index and data registers (legacy index 72h, 73h). the first 14 byte s and two programmable bytes of the bank 0 sram are rtc time, alarm 1 data and control registers. the firs t 5 bytes of the bank 1 sram are rtc alarm 2 data registers. access to the rtc sram may be locked. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 120 it8511 e /te/ g figure 6-14. register map of rtc rtc address index index 00h 01h 70h index 00h rtc 02h register registers 03h 71h data 0dh 04h register 0eh general 05h purpose 06h sram 07h 08h 09h 0ah 7fh 0bh 0ch 0dh programmed programmed bank 0 register rtc address index index 72h index 00h rtc 00h seconds alarm 2 register alarm2 01h minutes alarm 2 73h data 04h registers 02h hours alarm 2 register 05h general 03h date of month alarm 2 purpose 04h month alarm 2 sram 7fh bank 1 register date of month alarm 1 month alarm 1 register c register d seconds seconds alarm 1 minutes minutes alarm 1 register b hours hours alarm 1 day of week date of month month year register a free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 121 host domain functions table 6-26. host view register map via index-data i/o pair, rtc bank 0 index seconds register (secreg) 00h seconds alarm 1 register (seca1reg) 01h minutes register (minreg) 02h minutes alarm 1 register (mina1reg) 03h hours register (hrreg) 04h hours alarm 1 register (hra1reg) 05h day of week register (dowreg) 06h date of month register (domreg) 07h month register (monreg) 08h year register (yrreg) 09h rtc control register a (ctlrega) 0ah rtc control register b (ctlregb) 0bh rtc control register c (ctlregc) 0ch rtc control register d (ctlregd) 0dh date of month alarm 1 register (doma1reg) programmed month alarm 1 register (mona1reg) programmed table 6-27. host view register map via index-data i/o pair, rtc bank 1 index seconds alarm 2 register (seca2reg) 00h minutes alarm 2 register (mina2reg) 01h hours alarm 2 register (hra2reg) 02h date of month alarm 2 register (doma2reg) 03h month alarm 2 register (mona2reg) 04h 6.8.4.1 rtc bank 0 register 6.8.4.1.1 seconds register (secreg) index: 00h bit r/w default description 7-0 r/w 00h seconds data (secdat) 00 to 59 in bcd format. 00 to 3b in binary format. 6.8.4.1.2 seconds alarm 1 register (seca1reg) index: 01h bit r/w default description 7-0 r/w 00h seconds alarm 1 data (seca1dat) 00 to 59 in bcd format. 00 to 3b in binary format. unconditional match is selected when bit 7 and 6 are ?11?. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 122 it8511 e /te/ g 6.8.4.1.3 minutes register (minreg) index: 02h bit r/w default description 7-0 r/w 00h minutes data (mindat) 00 to 59 in bcd format. 00 to 3b in binary format. 6.8.4.1.4 minutes alarm 1 register (mina1reg) index: 03h bit r/w default description 7-0 r/w 00h minutes alarm 1 data (mina1dat) 00 to 59 in bcd format. 00 to 3b in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.1.5 hours register (hrreg) index: 04h bit r/w default description 7-0 r/w 00h hours data (hrdat) in 12-hour mode: 01 to 12 (am) and 81 to 92 (pm) in bcd format. 01 to 0c (am) and 81 to 8c (pm) in binary format. in 24-hour mode: 00 to 23 in bcd format. 00 to 17 in binary format. 6.8.4.1.6 hours alarm 1 register (hra1reg) index: 05h bit r/w default description 7-0 r/w 00h hours alarm 1 data (hra1dat) 1 . in 12-hour mode: 01 to 12 (am) and 81 to 92 (pm) in bcd format. 01 to 0c (am) and 81 to 8c (pm) in binary format. 2 . in 24-hour mode: 00 to 23 in bcd format. 00 to 17 in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.1.7 day of week register (dowreg) index: 06h bit r/w default description 7-0 r/w 00h day of week data (dowdat) 01 to 07 in bcd format. 01 to 07 in binary format. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 123 host domain functions 6.8.4.1.8 date of month register (domreg) index: 07h bit r/w default description 7-0 r/w 00h date of month data (domdat) 01 to 31 in bcd format. 01 to 1f in binary format. 6.8.4.1.9 month register (monreg) index: 08h bit r/w default description 7-0 r/w 00h month data (mondat) 01 to 12 in bcd format. 01 to 0c in binary format. 6.8.4.1.10 year register (yrreg) index: 09h bit r/w default description 7-0 r/w 00h year data (yrdat) 00 to 99 in bcd format. 00 to 63 in binary format. 6.8.4.1.11 rtc control register a (ctlrega) index: 0ah bit r/w default description 7 r - update in progress (uip) it is 0 when bit 7 of ctlregb register is 1. 0: timing registers will not be updated within 244 s 1: timing registers will be updated within 244 s 6-4 r/w 010b divider chain control (dicctl) control the divider chain for timing generation. the following is the table of the divi der chain control and test selection: ctlrega[6:4] configuration 000 reserved 010 normal operation 11x divider chain reset others test mode free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 124 it8511 e /te/ g bit r/w default description 3-0 r/w 0000b periodic interrupt rate select (pirsel) control the rate of the periodic interrupt. the following is the table of the periodic interrupt rate encoding: rate select periodic interrupt ra te (ms) divider chain output 0000 no interrupts --- 0001 3.906250 7 0010 7.812500 8 0011 0.122070 2 0100 0.244141 3 0101 0.488281 4 0110 0.976562 5 0111 1.953125 6 1000 3.906250 7 1001 7.812500 8 1010 15.625000 9 1011 31.250000 10 1100 62.500000 11 1101 125.000000 12 1110 250.000000 13 1111 500.000000 14 6.8.4.1.12 rtc control register b (ctlregb) index: 0bh bit r/w default description 7 r/w 00h set mode (sm) 0: timing updates occur normally. 1: update cycles will not occur until this bit is 0. 6 r/w 00h periodic interrupt enable (pie) enable the periodic interrupt. the rate is determined by ctlrega[3:0]. it is cleared to 0 on rtc reset or at the time when rtc is disabled. 0: disabled 1: enabled 5 r/w 00h alarm 1 interrupt enable (a1ie) this interrupt is generated when the alarm1 condition matches the current data time. it is cleared to 0 when bit7 of ctlregd register is 0. 0: disabled 1: enabled 4 r/w 00h update ended interrupt enable (ueie) this interrupt is generated when an update occurs. it is cleared to 0 on rtc reset or at the time when the rtc is disabled. 0: disabled 1: enabled 3 r/w- 00h alarm 2 interrupt enable (a2ie) this interrupt is generated when the alarm 2 condition matches the current data time. it is cleared to 0 when bit7 of ctlregd register is 0. 0: disabled 1: enabled 2 r/w 00h data mode (dam) 0: enable bcd format 1: enable binary format free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 125 host domain functions bit r/w default description 1 r/w 00h hour mode (hrm) 0: enable 12-hour format 1: enable 24-hour format 0 r/w 00h daylight savings (ds) in spring, time advances from 1: 59:59 am to 3:00:00 am on the first sunday in april. in fall, time returns from 1:59:59 am to 1:00:00 am on the last sunday in october. 0: disabled 1: enabled 6.8.4.1.13 rtc control register c (ctlregc) index: 0ch bit r/w default description 7 r 00h irq flag (irqf) this flag will be set and an interrupt will be generated when one of the following conditions occurs: pif=1 and pie=1 a1if=1 and a1ie=1 ueif=1 and ueie=1 this bit is cleared to 0 on rtc reset or at the time when the rtc is disabled. this bit is also cleared to 0 when this register is read. 6 r 00h pe r iodic interrupt flag (pif) this bit is cleared to 0 on rtc reset or at the time when the rtc is disabled. this bit is also cleared to 0 when this register is read. when the ctlrega [3:0] bits are not 0000b, the interrupt will be generated and this bit is set to 1 once the period is specified. 5 r 00h alarm 1 interrupt flag (a1if) this bit is cleared to 0 when bit 7 of ctlregd register is 0. this bit is also cleared to 0 when this register is read. 0: no alarm condition occurred 1: alarm 1 condition occurred 4 r 00h update ended interrupt flag (ueif) this bit is cleared to 0 on rtc reset or at the time when the rtc is disabled. this bit is also cleared to 0 when this register is read. 0: no update occurred. 1: updated cycle is ended 3 r 00h alarm 2 interrupt flag (a2if) this bit is cleared to 0 when bit 7 of ctlregd register is 0. this bit is also cleared to 0 when this register is read. 0: no alarm condition occurred 1: alarm 2 condition occurred 2-0 - 00h reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 126 it8511 e /te/ g 6.8.4.1.14 rtc control register d (ctlregd) index: 0dh bit r/w default description 7 r 00h valid ram and time (vrat) this bit responses whether the voltage that feeds the rtc is too low or not. 0: rtc contents are not valid. 1: rtc contents are valid. 6-0 - 00h reserved 6.8.4.1.15 date of month alarm 1 register (doma1reg) the index of this register is programmable. please see the ?rtc logical device? for details. index: programmed bit r/w default description 7-0 r/w c0h date of month alarm 1 data (doma1dat) 01 to 31 in bcd format. 01 to 1f in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.1.16 month alarm 1 register (mona1reg) the index of this register is programmable. please see the ?rtc logical device? for details. index: programmed bit r/w default description 7-0 r/w c0h month alarm 1 data (mona1dat) 01 to 12 in bcd format. 01 to 0c in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.2 rtc bank 1 register 6.8.4.2.1 seconds alarm 2 register (seca2reg) index: 00h bit r/w default description 7-0 r/w 00h seconds alarm 2 data (seca2dat) 00 to 59 in bcd format. 00 to 3b in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.2.2 minutes alarm 2 register (mina2reg) index: 01h bit r/w default description 7-0 r/w 00h minutes alarm 2 data (mina2dat) 00 to 59 in bcd format. 00 to 3b in binary format. unconditional match is selected when bit 7 and 6 are ?11?. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 127 host domain functions 6.8.4.2.3 hours alarm 2 register (hra2reg) index: 02h bit r/w default description 7-0 r/w 00h hours alarm 2 data (hra2dat) 1. in 12-hour mode: 01 to 12 (am) and 81 to 92 (pm) in bcd format. 01 to 0c (am) and 81 to 8c (pm) in binary format. 2. in 24-hour mode: 00 to 23 in bcd format. 00 to 17 in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.2.4 date of month alarm 2 register (doma2reg) index: 03h bit r/w default description 7-0 r/w c0h date of month alarm 2 data (doma2dat) 01 to 31 in bcd format. 01 to 1f in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.2.5 month alarm 2 register (mona2reg) index: 04h bit r/w default description 7-0 r/w c0h month alarm 2 data (mona2dat) 01 to 12 in bcd format. 01 to 0c in binary format. unconditional match is selected when bit 7 and 6 are ?11?. 6.8.4.3 rtc i/o register 6.8.4.3.1 rtc index register of bank 0 (rirb0) address offset: 70h bit r/w default description 7-0 r/w - rtc index register of bank 0(rirb0) this register is used to locate the data on bank 0, and is a read/write access register. it must be paired with rtc data register of bank 0 to program or read the indexed registers. 6.8.4.3.2 rtc data register of bank 0 (rdrb0) address offset: 71h bit r/w default description 7-0 r/w - rtc data register of bank 0 (rdrb0) this register is used to preserve the data that are to program or to read from the bank 0, and is a read/write ac cess register. it must be paired with rtc index register of bank 0 to pr ogram or read the indexed registers. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 128 it8511 e /te/ g 6.8.4.3.3 rtc index register of bank 1 (rirb1) address offset: 72h bit r/w default description 7-0 r/w - rtc index register of bank 1(rirb1) this register is used to locate the data on bank 1, and is a read/write access register. it must be paired with rtc data register of bank 1 to program or read the indexed registers. 6.8.4.3.4 rtc data register of bank 1 (rdrb1) address offset: 73h bit r/w default description 7-0 r/w - rtc data register of bank 1 (rdrb1) this register is used to preserve the data that are to program or to read from the bank 1, and is a read/write ac cess register. it must be paired with rtc index register of bank 1 to pr ogram or read the indexed registers. free datasheet http:/// free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 130 it8511 e /te/ g this page is intentionally left blank. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 131 ec domain functions 7. ec domain functions 7.1 8032 embedded controller (ec) 7.1.1 overview the embedded controller is an 8032 micro-controller which is an 8051-compatible micro-controller. 7.1.2 features ? supports sleep (a.k.a. power-down) and idle mode ? supports two external interr upts and one power fail interrupt ? supports 64k code/data space ? supports 256 bytes internal(w.r.t. 8032) ram, with 128 bytes specia l function register ? supports 3x16-bit timer/counter from gpe5, tmri0 and tmri1 ? supports 1xwatch dog timer ? supports full duplex uart ? memory mapped i/o configuration 7.1.3 general description the 8032tt is a high-performance 8051 family compat ible micro-controller bas ed on risc architecture & pipeline design. this ip specification of interface timi ng, external data memory read / write timing and external program memory read timing are different from that of the standard 80c52. but instruction-set is fully compatible with standard 8051 family. table 7-1. 8032 port usage signal port note 8032 external data bus p0[7:0], p2[7 :0], p3[7:6] ec bus movx instruction int0# p3[2] driven by intc int1# p3[3] driven by intc txd p3[1] txd signal on pin rxd p3[0] rxd signal on pin t0 timer p3[4] driven by gpe5 t1 timer p3[5] driven by tmri0 pin t2 timer p1[0] note: t2 and t2ex should be taken care of if 8032 banks are switched by p1. see also section 0 driven by tmri1 pin t2ex timer p1[1] unused 7.1.4 functional description memory the 8032 manipulates operands in four memory sp aces. there are 64k-byte program memory space, 64k-byte external data memory space, 256-byte intern al data memory, and with a 16-bit program counter space. the internal data memory address space is furt her divided into the 256-byte internal data ram and 128-byte special function register address space. the up 128-bytes ram can be reached by indirect addressing. four register banks, 128 addressable bits, and the stack resi de in the internal data ram. i/o ports the 8032 has 8-bit i/o ports. the four ports provide 32 i/o li nes to interface to the external world. all four ports are both byte and bit addressable. port 0 is used as an address/data bus and port 2 is used as the upper 8-bits address when external memory/device is accessed. port 3 contains specia l control signals such as the read free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 132 it8511 e /te/ g and write strobes. port 1 is used for both i/o and external interrupts. interrupts in the 8032 there are six hardware resources that generat e an interrupt request. the starting addresses of the interrupt service program for each interrupt source are like standard 8052. the external interrupt request inputs ( int0# , int1# ) can be programmed for either negative edge or low level-activated operation. timers / counters the 8032 has three 16-bit timers/counters that are t he same as the timers of the standard 8051 family. the 8032 has two additional watchdog timers for system failure monitor. serial i/o ports the 8032 has one programmable, full-duplex serial i/o por t whose function is the same as that of 8051 family and dependent on the requirement. power management the 8032 supports idle and doze/sleep modes of operati on. in the idle mode, the ec 8032 is stopped operation while the peripherals continue operating. in the doze/s leep mode, all the clocks are stopped. the doze/sleep mode can be waked up by int0# or int1# external interrupt with level trigger. dual data pointer the 8032 has two data pointers (dtpr, dtpr1). these tw o data pointers can help users enhance lots of block data memory moving. using dual data pointers to move block data almost saves half of the time spent by original 8051 codes. watch dog timers interrupt / reset the 8032 creates one programmable watchdog timers to monitor system failure. that is maximum 2^26. hardware multiply 8032 includes a hardware multiplier to enhance calculating speed. 8032 can finish one mu ltiply instruction at 1 machine cycle. 7.1.5 memory organization in 8032, the memory is organized as three address spaces and the program counter. the memory spaces are shown in ec memory map. - 16-bit program counter - 64k-byte program memory address space - 64k-byte external data memory address space - 256-byte internal data memory address the 16-bit program counter register provides 8032 with its 64k addressi ng capabilities. the program counter allows users to execute calls and branches to any lo cation within the program memory space. there are no instructions that permit program execution to move from the program memory space to any of the data memory spaces. the 64k-byte program memory address space is loca ted by dedicated address bu s. the 64k-byte external data memory address space is automatically accessed w hen the movx instruction is executed. the internal data memory space is subdivided into a 256-byte in ternal data ram address space and a 128-byte special function register address space as shown in the sfrs map. the internal data ram address space is 0 to 255. four 8-register banks occupy locations 0 through 31. the stack can be located anywhere in the internal data ram address space. in addition, 128 bit location ns of the on-chip ram are accessible through direct addressing. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 133 ec domain functions 7.1.6 on-chip peripherals table 7-2. system interrupt table interrupt source request fl ag priority flag enabl e flag vector address prior ity- within-level fl cleared by hardw are? external request ie0/tcon.1 px0/ip.0 ex0/ie.0 0003h 1 edge-yes level-no int ernal timer0/count er0 tf0/tcon.5 pt0/ip.1 et0/ie.1 000bh 2 yes external request ie1/tcon.3 px1/ip.2 ex1/ie.2 0013h 3 edge-yes level-no int ernal timer1/count er1 tf1/tcon.7 pt1/ip.3 et1/ie.3 001bh 4 yes xmit t /scon.1 internal serial port rcvr ri/scon.0 ps/ip.4 es/ie.4 0023h 5 no tf2/t2con.7 int ernal timer2/count er2 exf2/tscon.6 pt2/ip.5 et2/ie.5 002bh 6 no ag i figure 7-1. interrupt control system configuration 0 1 tf0 0 1 ie0 timer 0 ea ex0 et0 ex1 interrupt enable ip priorit y enable highes prior ity in te r r u p i n t e r r u p t p o l l i n g s q u e n c e int1 int0 it0 it1 ie1 timer 1 tf1 et1 ri ti receive t ransmit es et2 exf2 tf2 timer 2 t2ex px0 pt0 px1 pt1 ps pt2 note : t2ex is tied to logic high and is not available in it8511. external interrupt external interrupt int0# and int1# input signal ma y each be programmed to be level-triggered or edge triggered depending upon bits it0 and it1 in the tcon regist er. if it0 or it1 = 0, int0# or int1# is triggered by detected low at the input signal. if it0 or it1 = 1, int0# or int1# is negative-edge triggered. external interrupts are enabled with bits ex0 and ex1in the ie register. ev ens on the external interrupt input signals set the free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 134 it8511 e /te/ g interrupt flags ie0 or ie1 in tcon. these request bits ar e cleared by hardware vectors to service routines only if the interrupt is negative-edge triggere d. if the interrupt is level triggered, the interrupt service routine must clear the request bit. external hardware must release in t0# or int1# before the service routine completes, or an additional interrupt is requested. external interrupt input signals are sampled once every oscillator clock's rising edge. a level-triggered interrupt input signal held low or high for at least three clocks guarantees detection. edge-t riggered external interrupts only the request input signal for one clo/ck time. this ensures edge recognition and sets interrupt request bit ex0 or ex1. the 8032 clears ex0 or ex1 automatically during service routine fetch cycles for edge-triggered interrupts. timer interrupts sources of timer 0, timer 1 and timer 2 are gpe5, tmri 0 and tmri1 from pins. three timer-interrupt request bits tf0, tf1 and tf2 are set by timer 0, timer 1 and timer 2 overflow. when timer 0 and timer 1 interrupts are generated, the bits tf0 and tf1 are cleared by an on-chip hardware vector to an interrupt service routine. timer 2 is different from timer 0 or timer 1. timer 2 has to clear tf2 bit by software writing when timer 2 interrupt is generated. timer interrupts are enabled by bits et0, et1, and et2 in the ie register. timer 2 interrupts are generated by a logical or of bits tf2 and exf2 in register t2con. neither flag is cleared by a hardware vector to a service routine. in fact, the interrupt service routine must determine if tf2 or exef2 generates the interrupt, and then clear the bit. timer 2 interrupt is enabled by et2 in register ie. serial port interrupt serial port interrupts are generated by the logical or of bits ri and ti in the scon register. neither flag is cleared by a hardware vector to the service routine. the service routine resolves ri and ti interrupt generation and clears the serial port request flag. the serial port inte rrupt is enabled by bit es in t he ie register in the same way by using serial port 1. interrupt priority 8032 has 2 level priorities. setting / clearing a bit in the interru pt priority register (ip) or extent interrupt priority register (eip) establish its as sociated interrupt request as a high / low prio rity. if a low-priority level interrupt is being serviced, a high-priority level interrupt will interr upt it. however, an interrupt source cannot interrupt a service program of the same or higher level. the in terrupt priority is shown on interrupt control system configuration. interrupt response time the figure of interrupt response time shows the response time is between the interrupt request being active and the interrupt service routing being ex ecuted. the minimum interrupt response time is eight clocks that when an interrupt request asserts after t he ending instruction execution complete s. the maximum interrupt response time is 24 clocks when an interrupt request asserts duri ng the ending instruction, djnz direct, rel or other instruction sets whose operation period is 16 clocks and is decoded ok. however, a high priority interrupt asserts while a low priority interru pt service program is executing. the minimum and the maximum interrupt response time is 8 clocks and 24 clocks respectively. figure 7-2. interrupt response time call isr push pc ending instructions interrupt vector address interrupt response ti me int0 or int1 clk free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 135 ec domain functions 7.1.7 timer / counter timer 0 timer 0 functions as either a timer or event counter in f our modes of operation. timer 0 is controlled by the four low-order bits of the tmod register and bits 5, 4, 1 and 0 of the tcon regi ster. the tmod register selects the method of timer gating (gate), timer or counter operati on (c/t), and mode of operation (m1, m0). the tcon register provides timer 0 control functions: overflag ( tf0), run control (tr0), inte rrupt flag (ie0), and interrupt type control (it0). for normal timer operation (gate = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate and tr0 allows int0# to control timer operation. timer0/mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is se t up as an 8-bit timer (th0 register) with a module 32 prescaler implemented with the lower five bits of the tl0 register. the upper three bits of tl0 register are indeterminate and should be ignored. prescale r overflow increments the th0 register. timer 0/ mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 connected in cascade. the selected input increments tl0. figure 7-3. timer 0/1 in mode 0 and mode 1 12 0 1 xtal 1 tx thx (8 bits) tlx ( 8 bits ) overflow in te r r u p t request tfx gatex tr x x = 0 or 1 mode 0: 13-bit time/counter mode 1: 16-bit time/counter c/ tx in tx timer 0/ mode 2 (8-bit timer with auto-reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from the th0 register. tl0 overflow sets the timer overflow flag (tf0) in the tc on register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 136 it8511 e /te/ g figure 7-4. timer 0/1 in mode 2, auto-reload 12 0 1 xtal1 tx tlx (8 bits) overflow inter r u pt request tfx gatex trx x = 0 or 1 thx (8 bits) reload c/ tx in tx timer 0/ mode 3(two 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers. this mode is provided for application requiring an additional 8-bit time r or counter. tl0 uses the timer 0 control bits c/t and gate in tmod, and tr0 in tcon in the normal manner . th0 is locked into a timer function (counting 8032_freq/12) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. note: 8032_freq equals to ec clock frequency (listed in table 10-1 on page 297). figure 7-5. timer 0 in mode 3 two 8-bit timers 12 0 1 xtal1 t0 tl0 (8 bits) overflow inter r u pt request gate0 tr0 1/12 fosc th0 ( 8 bits ) tf0 tf1 1/12 fosc tr1 inte r r up t request overflow c/t0 in t0 timer 1 timer 1 functions as either a timer or event counter in three modes of operation. the logical configuration for modes 0, 1 and 2 is the same as that of time r 0. mode 3 of timer 1 is a hold-count mode. timer 1 is controlled by the four high-or der bits of the tmod register and bits 7, 6, 3 and 2 of the tcon register. the tmod register selects the method of timer gating (gate), timer or counter operation (c/ t), and mode of operation (m1 and m0). the tcon register provides timer 1 control functions: overfl ow flag (tf1), run control (tr1), interrupt flag(ie1), and interrupt type control (it1). for normal timer operation (gate = 0), setting tr1 allows timer register tl1 to be incremented by the selected input. setting gate and tr1 allows external input signal int1# to control timer operation. this setup can be used to make pulse width measurements. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 137 ec domain functions timer 1/ mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer, which is se t up as an 8-bit timer (th1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 r egister. the upper 3 bits of the tl1 register are ignored. prescaler overflow increment the th1 register. timer1/ mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 connected in cascade. the selected input increments tl1. timer 1/ mode 2 (8-bit timer) mode 2 configures timer 1 as an 8-bit timer (tl1 regist er) with automatic reload from the th1 register on overflow. overflow from tl1 sets overflow flag tf1 in t he tcon register and reloads tl1 with the contents of th1, which is preprogrammed by softw are. the reload leaves th1 unchanged. timer 1/ mode3 (halt) placing timer in mode 3 causes it to halt and its count. this can be used to halt timer 1 when the tr1 run control bit is not available, i.e., when timer 0 is in mode 3. timer 2 timer 2 is a 16-bt timer/count maintained by two eight-bit timer registers, th2 and tl2, which are connected in cascade. the timer/counter 2 mode control register t2 mod and the timer /counter control register t2con control the operation of timer 2. timer 2 provides the following operating modes: capt ure mode, auto-reload mode, baud rate generator mode, and programmable clock-out mode. select the operating mo de with t2mod and tcon register bits as shown in table of timer 2 modes of operat ion. auto-reload is the default mode. setting rclk and/or tclk selects the baud rate generator mode. timer 2 operation is similar to timer 0 and timer 1. c/ 2 t selects 8032_freq/12 (timer operation) or external input signal t2 (counter operation) as the timer regist er input. setting tf2 to be incremented by the selected input. timer 2/ capture mode in the capture mode, timer 2 functions as a 16-bit timer or counter. an overflow condition sets bit tf2, which you can use to request an interrupt. setting the external enable bit exen 2 allows the rcap2hand rcap2l registers to capture the current value in timer registers th2 and tl2 in response to a l-to-0 transition at external input t2ex. the transition at t2ex also sets bit exf2 on t2con. the exf2 bit, like tf2, can generate an interrupt. tr2 must be enabled when this mode is run. note : t2ex is tied to logic high and is not available in it8511. figure 7-6. timer 2: capture mode 12 0 1 xtal 1 t2 tl2 ( 8 bits ) overflow in te r r u p t request th 2 (8 bits) tf2 rcap2h rcap2l t2ex exf2 exen 2 tr 2 capture c/ t2 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 138 it8511 e /te/ g note: t2ex is tied to logic high and is not available in it8511. timer 2/ auto-reload mode the auto-reload mode configures timer 2 as a 16-bit time r or event counter with automatic reload. the timer operates as an up counter or up/down counter, as determined by the down counter enable bit (dcen). at device reset, dcen is cleared, so in the auto-reload mode, timer 2 defaults to operation as an up counter. tr2 must be enabled when this mode is run. up counter operation when dcen = 0, timer 2 operates as an up counter. if exen = 0, timer 2 counts up to ffffh and sets the tf2 overflow flag. the overflow condition loads the 16-bit value in the reload/capture registers (rcap2h, rcap2l) into the timer registers (th2, tl2). the values in rcap2h and rcap2l are preset by software. if exen2 = 1, the timer registers are rel oaded by either a timer overflow or a high-to-low transi tion at external input t2ex. this transition also sets the exf2 bit in t he t2con register. either tf2 or exf2 bit can generate a timer 2 interrupt request. tr2 must be enabled when its mode is run. up/down counter operation when dcen = 1, timer 2 operates as an up/down counter. external input signal t2ex controls the direction of the count. when t2ex is high, timer 2 counts up. the ti mer overflow occurs at ffffh, which sets the timer 2 overflow flag (tf2) and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers (th2, tl2) equals the value stored in rcap2h and rcap2l. the underflow sets the tf2 bit and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflo ws changing the direction of the count. when timer 2 operates as an up/down counter, exf2 does not generate an interrupt. this bit can be used to provide 17-bit resolution. tr2 must be enabled when his mode is run. figure 7-7. timer 2: auto reload (decn = 0) 12 0 1 xtal1 t2 tl2 (8 bits) overflow interrupt request th2 (8 bits) rcap2h rcap2l t2ex exf2 exen2 tr2 tf2 reload c/ t 2 note: t2ex is tied to logic high and is not available in it8511. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 139 ec domain functions figure 7-8. timer 2: auto reload mode (decn = 1) t2ex tr 2 tl2 (8 bits) overflow th2 (8 bits) rcap2h rcap2l ffh ffh 12 xtal 1 t2 0 1 count d ir e c tio n 1 = up 0 = d o w n in te r r u p t request tf2 exf2 (down counting reload va lu e ) (up counting reload value) c/ t2 note: t2ex is tied to logic high and is not available in it8511. timer 2/ baud rate generator mode this mode configures timer 2 as a baud rate generator fo r use with the serial port. select this mode by setting the rclk and/or tclk bits in t2con. timer 2/ clock-out mode in the clock-out mode, timer 2 functions as a 50%-dut y-cycle, variable-frequency clock. the input clock increments tl0 at frequency 8032_freq/2. the timer rep eatedly counts to overflow from a preloaded value. at overflow, the contents of the rcap2h and rcap2l regist ers are loaded into th2/tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers: clock-out frequency = 8032_freq / {4x(65536 - rcap2h, rcap2l)} note : 8032_freq equals to ec clock frequency (listed in table 10-1 on page 297). table 7-3. timer 2 modes of operation mode auto-reload m ode capture m ode baud rate generator m ode prog rammable c lock-out rclk or t clk (in t2coon) cp/rl2# (i n t 2mod) t2oe (i n t 2mod) 0 0 1 x 0 1 x 0 0 0 x 1 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 140 it8511 e /te/ g figure 7-9. timer 2: clock out mode t2oe xtal 1 tr 2 t2 0 1 tl2 (8 bits) overflow th2 (8 bits) rcap2h rcap2l 2 2 interrupt request exf2 exen 2 t2ex c/ t2 note: t2ex is tied to logic high and is not available in it8511. watchdog timer the watchdog timer has system reset functions. users can set wd1-1, wd1-0 (in register ckcon, 8eh) to choose 2^17, 2^20, (56/63)*2^23 or 2^26 counter for watchdog timer. after the watchdog timer counts the specific counter and an overflow occurs, set wdtrst flag (in register wdtcon, d8h) and finally reset the 8032. if 8032 has been reset by watchdog timer, wdten flag remains one. figure 7-10. watchdog timer reset rwt ewt xtal 1 overflow counter wd1-1 wd1-0 counting 0 0 1 1 17 2 20 2 23 (56/63)*2 26 2 wdtrst flag 0000000h 00 1 1 serial i/o port the serial i/o port provides both asynchronous communi cation modes. it operates as a universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2, and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates. mode 1 and 3 operate over a wide range of baud rates, which are generated by timer 1 and timer 2. the serial port signals are defined in table of serial po rt signals, and the serial port special function registers (sbuf, scon) are described in the section of special function registers. for the three asynchronous modes, the uart transm its on the txd pin and receiv es on the rxd pin. the free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 141 ec domain functions sbuf register, which holds received bytes and bytes to be transmitted, actually consists of two physically different registers. to send, software writes a byte to sbuf; to receive, software reads sbuf. the receive shift register allows reception of a second byte before the byte has been read from sbuf. however, if software has not read the first byte by the time the second byte is re ceived, the second byte will overwrite the first. the uart sets interrupt bits ti and ri on transmission and recepti on respectively. these two bits share a single interrupt request and interrupt vector. figure 7-11. serial port block diagram subf (t ransmi t) scon write sbuf read sbuf subf (recei ve) recei ve shift register mo d e 0 transmit load sbuf interrupt request ti ri serin i/o control txd rxd transmit shift register table 7-4. serial port signals func tion name type description mult ip lexed wit h txd o tr ansmit data. in mode 0,txd transmits the clock signal. in modes1, 2,and 3,txd transmits serial data. p3.1 rxd i/o receive data. in mode 0, r xd tran smits and receives serial data. in mode 1, 2,and 3, rxd receiv es serial data. p3.0 asynchronous modes (modes 1, 2, and 3) the serial port has three asynchronous modes of operation. mode 1 mode 1 is a full-duplex and asynchronous mode. the data fr ame consists of 10 bits: one start bit, eight data bits, and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a message is received, the stop bit is read in the rb8 bit in the scon register. the baud rate is generated by overflow of timer 1 or timer 2. mode 2 and 3 mode 2 and 3 are full-duplex and asynchronous modes. the data frame consists of 11 bits: one start bit, eight data bits (transmitted and received lsb first), one pr ogrammable ninth data bit, and one stop bit which is read from the rb8 bit in the scon register. on transmit, t he ninth data bit is written to the tb8 bit in the scon register. alternatively, you can use the ninth bit as a command/data flag. - in mode 2, the baud rate is programmable to 1/32 or 1/64 of the oscillator frequency. - in mode 3, the baud rate is generated by overflow of timer 1 or timer 2. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 142 it8511 e /te/ g figure 7-12. data frame (mode 1, 2 and 3) d0 d1 d2 d3 d4 d5 d6 d7 d8 start bit dat a byt e nint h dat a bit (modes 2 and 3 only) stop bit transmission (mode 1, 2, 3) follow these steps below to initiate a transmission: 1. write to the scon register. select the mode with the sm0 and sm1 bits, and clear the ren bit. for mode 2 and 3, write the ninth bit to the tb8 bit. 2. write the byte to be transmitted to the sbuf register. this write starts the transmission. reception (mode 1, 2, 3) to prepare for a reception, set the ren bit in the scon register. the actual recept ion is then initiated by a detected high-to-low transition on the rxd pin. baud rates baud rates for mode 2 mode 2 has a two-baud rate, which is selected by the smod bit in the pcon register. the following expression defines the baud rate: serial i/o mode 2 baud rate = (2 ^ smod) x (8032_freq / 64) 8032_freq equals to ec clock frequency (listed in table 10-1 on page 297). baud rates for mode 1 and 3 in mode 1 and 3, the baud rate is generated by overflow of timer (default) and/or timer 2. you may select either or both timers to generate the baud rate(s) for the transmitter and/or the receiver. timer 1 generated baud rates (mode 1 and 3) timer 1 is the default baud rate generator for the transmi tter and the receiver in mode 1 and 3. the baud rate is determined by the timer 1 overflow rate and the value of smod, as shown in the following formula: serial i/o mode 1 and 3 baud rate = (2 ^ smod) x (timer 1 overflow rate) / 32 selecting timer 1 as the baud rate generator to select timer 1 as the baud rate generator: ? disable the timer interrupt by clearing the ie0 register. ? configure timer 1 as a timer or an event counter (s et or clear the c/t bit in the tmod register). serial i/o mode 1 and 3 baud rate = (2 ^ smod) x 8032_freq / (32 x 12 x (256 ? th1) ) note : 8032_freq equals to ec clock frequency (listed in table 10-1 on page 297). ? select timer mode 0-3 by programming the m1 and m0 bits in the tmod register. in most applications, timer 1 is configured as a timer in auto-reload mode (high nibble of tmod = 0010b). the resulting baud rate is defin ed by the following expression: timer 1 can generate very low baud rates by the following setups: ? enable the timer 1 interrupt by setting the et1 bit in the ie register. ? configure timer 1 to run as a 16-bit timer (high nibble of tmod = 0001b). ? use the timer 1 interrupt to in itiate a 16-bit software reload. timer 2 generated baud rates (mode 1 and 3) timer 2 may be selected as the baud rate generator for the transmitter and/or receiver. the baud rate generator mode of timer 2 is similar to the auto-reload mode. a ro llover in the th2 register reloads registers th2 and tl2 with the 16-bit value on registers rcap2h and rcap2l, which are presented by software. the baud rate of timer 2 is expressed by the following formula: serial i/o mode 1 and 3 baud rate = (timer 2 overflow rate) / 16 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 143 ec domain functions selecting timer 2 as the baud rate generator to select timer 2 as the baud rate generator for t he transmitter and/or receiver, program the rclck and tclck bits in the t2con register. setting rclk and/or tc lk puts timer 2 into its baud rate generator mode. in this mode, a rollover in the th2 register does not set t he tf2 bit in the t2con register. besides, a high-to-low transition at the t2ex input signal sets the exf2 bit in the t2con register but does not cause a reload from (rcap2h, rcap2l) to (th2, tl2). you can use the t2ex input signal as an additional external interrupt by setting the exen2 bit in t2con. note: t2ex is tied to logic high and is not available in it8511. note: turn off the timer (clear the tr2 bit in the t2con register) before accessing registers th2, tl2, cap2h and rcap2l. you may configure timer 2 as a timer or a coun ter. in most applications, it is configured for timer operation (i.e., the c/t2 bit is cleared in the t2con register). table 7-5. selecting the baud rate generator(s) rclk bit tclck bit receiv er baud ra te generator tr ans mit ter baud ra te generator 00 timer 1 timer 1 01 timer 1 timer 2 10 timer 2 timer 1 11 timer 2 timer 2 figure 7-13. timer 2 in baud rate generator mode xtal1 tr2 t2 0 1 2 c/ t2 tl2 (8 bits) th2 (8 bits) rcap2h rcap2l 2 0 1 timer 1 overflow smod 0 1 tclck interrupt request exf2 exen2 t2ex 16 tx clock note: oscillator frequency is divided by 2, not 12. note availability of additional external interrupt 0 1 rclck 16 rx clock 0 1 smod1 16 tx1 clock 16 rx1 clock note: t2ex is tied to logic high and is not available in it8511. note that timer 2 increments every state time (2tosc) when it is in the baud rate generator mode. in the baud rate formula that follows, ?rcap2h, rcap2l? denoti ng the contents of rcap2h and rcap2l is taken as a 16-bit unsigned integer: serial i/o mode 1 and 3 baud rate = 8032_freq x (32 x [65536 - (rcap2h,racap2l)]) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 144 it8511 e /te/ g note: 8032_freq equals to ec clock frequency (listed in table 10-1 on page 297). when timer 2 is configured as a timer and is in baud rate generator mode, do not read or write the th2 or tl2 registers. the timer is being incremented every state time , and the result of a read or write may not be accurate. in addition, you may read but not write to the rcap2 r egisters; a write may overlap a reload and cause write and/or reload errors. 7.1.8 idle and doze/sleep mode idle mode when set idl bit in pcon(87h), the 8032 will enter an idle mode. in the idle mode, the 8032 is idle while all the on-chip peripherals remain active. the internal ram and sfrs registers remain unchanged during this mode. the idle mode can be terminated by any enabled in ternal/external interrupt or by a hardware reset. doze/sleep mode when pd bit is set in pcon(87h), the 8032 will enter a doze/sleep mode. in the doze/sleep mode, the 8032 clock is stopped, and pll may be alive or stopped depending on pllctrl. the doze/sleep mode can be waked up by the hardware reset or by th e external enabled interrupt with level trigger activation (itx in register tcon is set to 0). the program counter, internal ram and sfrs registers retain their values and will not be changed after the exiting do ze/sleep mode by external in terrupt. the reset will restar t the 8032, while the sfrs with initial values and the internal ram retain their values. 7.1.9 ec internal register description the embedded 8032 internal memory space and specia l function registers (f0h-80h) are listed below. table 7-6. internal ram map 7 0 index bank 0 7h-0h bank 1 fh-8h bank 2 17h-10h bank 3 1fh-18h addressable bits 2fh-20h general purpose ram 7fh-2fh indirect addressing register ffh-80h 7 0 sfr index pcon dps dph1 dpl1 dph dpl sp p0 80h ckcon th1 th0 tl1 tl0 tmod tcon 88h p1 90h sbuf scon 98h p2 a0h ie a8h p3 b0h ip b8h status c0h th2 tl2 rcap2h rcap2l t2mod t2con c8h psw d0h wdtcon d8h acc e0h e8h b f0h f8h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 145 ec domain functions 7.1.9.1 port 0 register (p0r) address: 80h bit r/w default description 7-0 r/w ffh p0 register bit [7:0] (p0) this is the 8-bit 8032 port 0. 7.1.9.2 stack pointer register (spr) address: 81h bit r/w default description 7-0 r/w 07h stack pointer bit [7:0] (sp) this is the 8-bit stack pointer. 7.1.9.3 data pointer low register (dplr) address: 82h bit r/w default description 7-0 r/w 0h data pointer low bit [7:0] (dpl) this is the 8-bit data pointer low byte. 7.1.9.4 data pointer high register (dphr) address: 83h bit r/w default description 7-0 r/w 0h data pointer high bit [7:0] (dph) this is the 8-bit data pointer high byte. 7.1.9.5 data pointer 1 low register (dp1lr) address: 84h bit r/w default description 7-0 r/w 0h data pointer 1 low bit [7:0] (dpl1) this is the 8-bit data pointer 1 low byte. 7.1.9.6 data pointer 1 high register (dp1hr) address: 85h bit r/w default description 7-0 r/w 0h data pointer 1 high bit [7:0] (dph1) this is the 8-bit data pointer 1 high byte. 7.1.9.7 data pointer select register (dpsr) address: 86h bit r/w default description 7-1 - 0h reserved 0 r/w 0h data pointer select (dps) setting ?1? selects the data pointer 1 (dpl1, dph1) while setting ?0? selects the data pointer (dpl, dph). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 146 it8511 e /te/ g 7.1.9.8 power control register (pcon) address: 87h bit r/w default description 7 r/w 0h serial port double baud rate (smod1) setting ?1? doubles the baud rate when timer 1 is used and mode 1, 2, or 3 is selected in scon register. 6 - 0h reserved 5-2 - 0h reserved 1 r/w 0h power down mode (pd) set ?1? to enter a sleep (a.k.a power-down) or doze mode immediately. the sleep or doze mode is controlled by ppdc bit. exit sleep or doze mode and clear this bit by external interrupt or hardware reset. 0 r/w 0h idle mode (idl) set ?1? to enter idle mode immediately. exit idle mode and clear this bit by inte rnal interrupt and external interrupt or hardware reset. 7.1.9.9 timer control register (tcon) address: 88h bit r/w default description 7 r/w 0h timer 1 overflow (tf1) this bit is set by hardware when time r 1 register overflows. this bit is cleared by hardware when the processo r vectors to the interrupt service routine. 6 r/w 0h timer 1 run control (tr1) setting ?1? enables timer 1 operation and setting ?0? disables timer 1. 5 r/w 0h timer 0 overflow (tf0) this bit is set by hardware when time r 0 register overflows. this bit is cleared by hardware when the processo r vectors to the interrupt service routine. 4 r/w 0h timer 0 run control (tr0) setting ?1? enables timer 0 operation and setting ?0? disables the timer 0. 3 r/w 0h interrupt 1 edge detect (ie1) this bit is set by hardware when an edge or a level is detected on external int1 (depends on the setting of it1 ). this bit is cleared by hardware when the interrupt service routine is pr ocessed if an edge trigger is selected. 2 r/w 0h interrupt 1 type select (it1) setting ?1? selects the edge-triggered for int1. setting ?0? selects a level-triggered. don't write 1 to this bit because inte rrupt triggered type is considered in intc module and needs it0 and it1 to be set as level-low triggered. 1 r/w 0h interrupt 0 edge detect (ie0) set by hardware when an edge or a level is detected on external int0 (depends on the setting of it0 ). cleared by hardware when the interrupt service routine is processed if an edge trigger is selected. 0 r/w 0h interrupt 0 type select (it0) setting ?1? selects the edge-triggered for int0. setting ?0? selects a level-triggered. don't write 1 to this bit because inte rrupt triggered type is considered in intc module and needs it0 and it1 to be set as level-low triggered. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 147 ec domain functions 7.1.9.10 timer mode register (tmod) address: 89h bit r/w default description 7 r/w 0h timer 1 gate (gate1) 0: timer 1 will clock when tr1 =1, regardless of the state of int1. 1: timer 1 will clock only when tr1 =1 and int1 is deasserted. 6 r/w 0h timer 1 source (src1) 0: timer 1 counts the divided-down ec clock. 1: timer 1 counts negative transitions on t1 input of 8032 from tmri0 pin. 5-4 r/w 0h timer 1 mode (mode1) 0h: 8-bit timer/counter (th1) with 5-bit prescaler (tl1) 1h: 16-bit timer/counter 2h: 8-bit auto-reload timer/counter (tl1). reload from th1 at overflow. 3h: timer 1 halted. retains count. 3 r/w 0h timer 0 gate (gate0) 0: timer 0 will clock when tr0=1, regardless of the state of int0. 1: timer 0 will clock only when tr0=1 and int0 is deasserted. 2 r/w 0h timer 0 source (src0) 0: timer 0 counts the divided-down ec clock. 1: timer 0 counts negative transitions on t0 input of 8032 from gpe5. 1-0 r/w 0h timer 0 mode (mode0) 0h: 8-bit timer/counter (th0) with 5-bit prescaler (tl0) 1h: 16-bit timer/counter 2h: 8-bit auto-reload timer/counter (tl0). reload from th0 at overflow. 3h: timer 0 halted. retains count. 7.1.9.11 timer 0 low byte register (tl0r) address: 8ah bit r/w default description 7-0 r/w 0h timer 0 low byte bit [7:0] (tl0) timer 0 low byte register. 7.1.9.12 timer 1 low byte register (tl1r) address: 8bh bit r/w default description 7-0 r/w 0h timer 1 low byte bit [7:0] (tl1) timer 1 low byte register. 7.1.9.13 timer 0 high byte register (th0r) address: 8ch bit r/w default description 7-0 r/w 0h timer 0 high byte bit [7:0] (th0) timer 0 high byte register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 148 it8511 e /te/ g 7.1.9.14 timer 1 low byte register (th1r) address: 8dh bit r/w default description 7-0 r/w 0h timer 1 high byte bit [7:0] (th1) timer 1 high byte register. 7.1.9.15 clock control register (ckcon) address: 8eh bit r/w default description 7-6 r/w 0h watch dog time out counter select (wd[1:0]) 0h: 17-bit counter 1h: 20-bit counter 2h: (56/63)*2 23 counter 3h: 26-bit counter 5 r/w 0h timer 2 clock (t2m) 0: timer 2 clock is ec clock / 12. 1: timer 2 clock is ec clock / 4. 4 r/w 0h timer 1 clock (t1m) 0: timer 1 clock is ec clock / 12. 1: timer 1 clock is ec clock / 4. 3 r/w 0h timer 0 clock (t0m) 0: timer 0 clock is ec clock / 12. 1: timer 0 clock is ec clock / 4. 2-0 - - reserved 7.1.9.16 port 1 register (p1r) address: 90h bit r/w default description 7-0 r/w ffh p1 register bit [7:0] (p1) this is the 8-bit 8032 port 1. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 149 ec domain functions 7.1.9.17 serial port control register (scon) address: 98h bit r/w default description 7 r/w 0h serial port mode 0 (sm0_0) serial port mode control is set/cleared by software. modes 1-3 are supported. 6 r/w 0h serial port mode 1 (sm1_0) serial port mode control is set/cleared by software. modes 1-3 are supported. 5 - 0h reserved 4 r/w 0h receive enable (ren) receiver enable bit. setting ?1? enables the serial data reception. setting ?0? disables the serial data reception. 3 r/w 0h transmit bit 8 (tb8) transmit bit 8, set/cleared by hardwar e to determine the state of the ninth data bit transmitted in 9-bit uart mode. 2 r/w 0h receive bit 8 (rb8) receive bit 8, set/cleared by hardware to determine the state of the ninth data bit received in 9-bit uart mode. 1 r/w 0h transmit interrupt (ti) transmit interrupt, set by hardware when the byte is transmitted and cleared by software after serving. 0 r/w 0h receive interrupt (ri) receive interrupt, set by hardware when the byte is received and cleared by software when data is processed. 7.1.9.18 serial port bu ffer register (sbufr) address: 99h bit r/w default description 7-0 r/w 0h serial port buffer bit [7:0] (sbuf) this is the 8-bit 8032 serial port data buffer. writing to sbuf loads the transmit buffer to the serial i/o port. reading sbuf reads the receive buffer of the serial port. 7.1.9.19 port 2 register (p2r) address: a0h bit r/w default description 7-0 r/w ffh p2 register bit [7:0] (p2) this is the 8-bit 8032 port 2. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 150 it8511 e /te/ g 7.1.9.20 interrupt enable register (ie) address: a8h bit r/w default description 7 r/w 0h global interrupt enable (ea) setting this bit enables all interrupts that are individually enabled by bit 0-6. clearing this bit disables all interrupts. 6 r/w 0h serial port 1 interrupt enable (es1) setting this bit enables the serial port 1 interrupt. 5 r/w 0h timer 2 overflow interrupt enable (et2) setting this bit enables the timer 2 overflow interrupt. 4 r/w 0h serial port 0 interrupt enable (es0) setting this bit enables the serial port 0 interrupt. 3 r/w 0h timer 1 overflow interrupt enable (et1) setting this bit enables the timer 1 overflow interrupt. 2 r/w 0h external interrupt 1 enable (ex1) setting this bit enables the external interrupt 1. 1 r/w 0h timer01 overflow interrupt enable (et0) setting this bit enables the timer 0 overflow interrupt. 0 r/w 0h external interrupt 0 enable (ex0) setting this bit enables the external interrupt 0. 7.1.9.21 port 3 register (p3r) address: b0h bit r/w default description 7-0 r/w ffh p3 register bit [7:0] (p3) this is the 8-bit 8032 port 3. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 151 ec domain functions 7.1.9.22 interrupt priority register (ip) address: b8h bit r/w default description 7 - 0h reserved 6 - - reserved 5 r/w 0h timer 2 overflow interrupt priority (pt2) setting this bit enables the timer 2 overflow interrupt. 4 r/w 0h serial port 0 interrupt priority (ps0) setting this bit enables the serial port 0 interrupt. 3 r/w 0h timer 1 overflow interrupt priority (pt1) setting this bit enables the timer 1 overflow interrupt. 2 r/w 0h external interrupt 1 priority (px1) setting this bit enables the external interrupt 1. 1 r/w 0h timer01 overflow interrupt priority (pt0) setting this bit enables the timer 0 overflow interrupt. 0 r/w 0h external interrupt 0 priority (px0) setting this bit enables the external interrupt 0. 7.1.9.23 status register (status) address: c5h bit r/w default description 7 - 0b reserved 6 r/w 0b high priority interrupt status (hip) 5 r/w 0b low priority interrupt status (lip) 4-2 - 0h reserved 1 r/w 0b serial port 0 transmit activity monitor (spta0) 0 r/w 0b serial port 0 receive activity monitor (spra0) 7.1.9.24 timer 2 control register (t2con) address: c8h bit r/w default description 7 r/w 0h timer 2 overflow (tf2) set by hardware when the timer 2 overflows. it must be cleared by software. tf2 is not set if rclk=1 or tclk=1. 6 r/w 0h timer 2 external flag (exf2) if exen2=1, a capture or reload is caused by a negat ive transition on t2ex sets efx2. efx2 dose not cause an interrupt in up/down counter mode (dcen=1). 5 r/w 0h receive clock (rclk) selects timer 2 overflow pulses (rclk=1) or timer 1 overflow pulses (rclk=0) as the baud rate generator for port mode 1 and 3. 4 r/w 0h receive clock (rclk) selects timer 2 overflow pulses (tclk=1) or timer 1 overflow pulses (tclk=0) as the baud rate generator for port mode 1 and 3. 3 r/w 0h timer 2 external enable (exen2) setting exen2 causes a capture or reload to occur as a result of a negative transition on t2ex unless timer 2 is being used as the baud rate generator for the serial port. clearing exen2 causes timer 2 to ignore events at t2ex. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 152 it8511 e /te/ g bit r/w default description 2 r/w 0h timer 2 run control (tr2) setting this bit starts the timer. 1 r/w 0h timer/counter 2 select (ct2) 0: timer 2 counts the divided-down ec clock. 1: timer 2 counts negative transitions on t2 input of 8032 from tmri1 pin. 0 r/w 0h capture/reload (cprl2) when this bit is set, captures occur on negative transitions at t2ex if exen2=1. when reloads occur o if exen 2=1, the cp/ 2 rl bit is ignored and timer 2 is forced to auto-reload on timer 2 overflow if rclk =1 or tclk = 1. 7.1.9.25 timer mode register (t2mod) address: c9h bit r/w default description 7-2 - 0h reserved 1 r/w 0h timer 2 output enable (t2oe) in the timer 2 clock-out mode, this bit connects the programmable clock output to external signal t2. 0 r/w 0h down count enable (dcen) this bit configures timer 2 as an up/down counter. 7.1.9.26 timer 2 capture low byte register (rcap2lr) address: cah bit r/w default description 7-0 r/w 0h timer 2 capture low byte bit [7:0] (rcap2l) low byte of the timer2 reload/recapture register. this register stores 8-bit value to be loaded into or captured from the timer register tl2 in timer 2. 7.1.9.27 timer 2 capture high byte register (rcap2hr) address: cbh bit r/w default description 7-0 r/w 0h timer 2 capture high byte bit [7:0] (rcap2h) high byte of the timer2 reload/recapture register. this register stores 8-bit value to be loaded into or captured from the timer register th2 in timer 2. 7.1.9.28 timer 2 low byte register (tl2r) address: cch bit r/w default description 7-0 r/w 0h timer 2 low byte bit [7:0] (tl2) timer 2 low byte register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 153 ec domain functions 7.1.9.29 timer 2 high byte register (th2r) address: cdh bit r/w default description 7-0 r/w 0h timer 2 high byte bit [7:0] (th2) timer 2 high byte register. 7.1.9.30 program status word register (psw) address: d0h bit r/w default description 7 r/w 0h carry flag (cf) cy is set if the operation result in a carry out of (during addition) or a borrow into (during subtraction) the hi gh-order bit of the result; otherwise cy is cleared. 6 r/w 0h auxilary carry flag (ac) ac is set if the operation result in a carry out of the low-order 4 bits of the result (during addition) or a borrow form the high-order bits into the low-order 4 bits (during subtraction); otherwise ac is cleared. 5 r/w 0h user flag 0 (f0) general-purpose flag. 4-3 r/w 0h register bank select bit [1:0](rs1:0) 0h: bank 0, 00h-07h 1h: bank 1, 08h-0fh 2h: bank 2, 10h-17h 3h: bank 3, 18h-1fh 2 r/w 0h overflow flag (ov) this bit is set if an addition or signed variables result in an overflow error (i.e., if the magnitude of the sum or difference is too great for the seven lsbs in 2?s ? complement representatio n). the overflow flag is also set if the multiplication product overflows one byte or if a division by zero is attempted. 1 r/w 0h user defined flag (ud) general-purpose flag. 0 r/w 0h parity flag (p) this bit indicates the parity of the accumulator. it is set if an odd number of bits in the accumulator is set. otherwise , it is cleared. not all instructions update the parity bit. the parity bit is se t or cleared by instructions that change the contents to the accumulator. 7.1.9.31 watch dog timer control register (wdtcon) address: d8h bit r/w default description 7 - 0h reserved 6-2 - 0h reserved 1 r/w 0h watch dog timer enable (wdten) setting ?1? enables the watchdog timer. 0 r/w 0h watch dog timer reset (wdtrst) setting ?1? resets the watchdog timer. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 154 it8511 e /te/ g 7.1.9.32 accumulator register (acc) address: e0h bit r/w default description 7-0 r/w 0h accumulator bit [7:0] (acc[7:0]) the instruction uses the accumulator as both source and destination for calculations and moves. 7.1.9.33 b register (br) address: f0h bit r/w default description 7-0 - 0h b register (b[7:0]) the b register is used as both a source and destination in multiply and divide operations. 7.1.10 programming guide 7.1.10.1 code snippet of entering idle/doze/sleep mode ; power-down adc/dac analog circuit ; enter no-wait mode before entering power saving mode ; disable unnecessary channel of intc/wuc mov dptr, #1e03h ; pllctrl register mov a, #01h ; 00h for doze mode ; 01h for sleep mode movx @dptr, a nop ; reserved orl pcon, #01h ; #01h for idle mode ; #02h for doze/sleep mode ; repeat "nop" eight times immediately ; for internal bus turn-around nop ; 1st nop ; 2nd nop ; 3rd nop ; 4th nop ; 5th nop ; 6th nop ; 7th nop ; 8th free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 155 ec domain functions 7.1.10.2 code snippet of copying flash content to scratch rom 4 (movc-movx by pio) ; first copy data from code space to scratch ram in data space, ; then enable code space mapping of scratch rom ; copy 256 bytes from code space to scratch ram ; code space: ff00h ~ ffffh (byte) ; data space: 0700h ~ 07ffh (byte) mov r6, #00h copy_loop: mov dptr, #0ff00h ; read from code space from ff00h (byte) mov a, r6 movc a, @a+dptr mov dph, #07h ; write to data space from 0700h (byte) mov dpl, r6 movx @dptr, a inc r6 cjne r6, #00h, copy_loop ; copy 256 bytes ; enable mapping scratch sram to scratch rom mov dptr, #104eh ; scar4h register mov a, #03h ; disable code space mapping first movx @dptr, a mov dptr, #104ch ; scar4l register mov a, #00h ; movx @dptr, a mov dptr, #104dh ; scar4 register mov a, #0ffh ; movx @dptr, a mov dptr, #104eh ; scar4h register mov a, #00h ; movx @dptr, a ; enable code space mapping free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 156 it8511 e /te/ g 7.1.10.3 code snippet of copying flash content to scratch rom (dma) ; dma copies 256 bytes from code space to scratch ram then ; enable code space mapping ; ; code space: ff00h ~ ffffh (byte) ; data space: 0700h ~ 07ffh (byte) mov dptr, #104eh ; scar4h register mov a, #80h ; movx @dptr, a mov dptr, #104ch ; scar4l register mov a, #00h ; movx @dptr, a mov dptr, #104dh ; scar4 register mov a, #0ffh ; movx @dptr, a mov dptr, #104eh ; scar4h register mov a, #00h ; movx @dptr, a ; start dma then enable code space mapping free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 157 ec domain functions 7.2 interrupt controller (intc) 7.2.1 overview intc mainly collects several interru pts from modules. using interrupt driven design has a better performance than polling-driven. it traps pwrfail#, rom match interrupt and samples 31 interrupt channels, then outputs to the int0# and int1# of 8032. both interrupts int0# and int1# to 8032 are generated by intc, and don't write 1 to it0 and it1 bit in tcon because interrupt triggered type is considered in intc and needs it0 and it1 to be set as level-low triggered. note int0# and int1# are external interrupts of 8032 and they are controlled by ea, ex0 and ex1 in ie register. external interrupts can wakeup 8032 from idle/doze/sleep mode, but internal interrupts can wakeup 8032 from idle mode only. 7.2.2 features ? configurable level-triggered and edge-triggered mode ? configurable interrupt polarity of triggered mode ? clear registers for edge-triggered interrupts ? each interrupt source can be enabled/masked individually ? special handler for power-fail (int0# of 8032) 7.2.3 functional description 7.2.3.1 power fail interrupt the intc collects interrupts sources from internal and external (through wuc) and provides two interrupt requests int0# and int1# to 8032. 8032 treats int0# as a higher priority interrupt request than int1#. intc uses int0# as a power-fail interrupt and int1# as a maskable interrupt. the firmware should enable the ie0 and ie1 bit in tcon before all. to implement a power-fail application, connect gpb7 to external circuit. fi rmware puts the gpb7 in alternative function, enables the smitter trigger of gpb7 to receiv e an asynchronous external input, and provides relative int0# interrupt routine. there are two methods to trap a power-fail event: ?tra p enabled? and ?trap enabled and locked?. users select ?trap enabled? by setting tren bit in pfailr and select ?trap enabled and locked? by setting trenl bit in pfailr. if both bits are selected, tren bit is ignored. if ?trap enabled? is used, power-fail event is detected by falling edge transition of pwrfail#, and int0# to 8032 is asserted. after int0# is set, tren bit is cleared. ?trap enabled and locked? method is similar to ?tr ap enabled? method but trenl will not be cleared after int0# is set. 7.2.3.2 rom match interrupt refer to section 7.17 debugger (dbgr) on page 280. 7.2.3.3 programmable interrupts intc also collects 31 maskable interrupt sources and make a request on int1 # of 8032 if triggered. each channel can be individually enabled or masked by ierx . if an interrupt channel is masked and one interrupt request is triggered, the request is masked (inhibited, not canceled), and will be asserted the request on int1# if it is enabled. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 158 it8511 e /te/ g the isrx indicates the status of inte rrupt regardless of ierx. in the level- triggered mode, isrx is affected by corresponding interrupt sources, and fi rmware should clear the interrupt st atus on interrupt sources after its request is handled. in edge-triggered mode, isrx is se t by selected edge transition (determined by ielmrx) of corresponding interrupts sources, and firm ware should write 1 to clear to isrx after this request is handled. firmware may use the ivect to determine which channel is to be serviced first or have its priority rule by reading isrx and ierx. ivect treats int1 as the lowest priority interrupt and int31 as the highest priority interrupt. the 8032 always wakes up from idle/doze/sleep mode when it detects an enabled external interrupt and it wakes up from idle mode by intern al interrupt, too. firmware should disable unwanted interrupt sources to prevent from waking up unexpectedly. note that interrupts from wuc are not always level-tri ggered interrupts since they may be just throughout wuc if the corresponding channels at wuc are disabled (bypassed). if an edge-triggered passes through wuc and intc with wuc corresponding channel is disabled and intc corresponding channel is level-trig mode, it may cause 8032 interrupt routine called but finds no interrupt source to service, or it may cause 8032 to wake up from idle/doze/sleep mode and enters interrupt routi ne but finds no interrupt source to service. 7.2.4 ec interface registers the ec interface registers are listed below. the base address for intc is 1100h. table 7-7. ec view register map, intc 7 0 offset interrupt status register 0 (isr0) 00h interrupt status register 1 (isr1) 01h interrupt status register 2 (isr2) 02h interrupt status register 3 (isr3) 03h interrupt enable register 0 (ier0) 04h interrupt enable register 1 (ier1) 05h interrupt enable register 2 (ier2) 06h interrupt enable register 3 (ier3) 07h interrupt edge/level-triggered mode register 0 (ielmr0) 08h interrupt edge/level-triggered mode register 1 (ielmr1) 09h interrupt edge/level-triggered mode register 2 (ielmr2) 0ah interrupt edge/level-triggered mode register 3 (ielmr3) 0bh interrupt polarity register 0 (ipolr0) 0ch interrupt polarity register 1 (ipolr1) 0dh interrupt polarity register 2 (ipolr2) 0eh interrupt polarity register 3 (ipolr3) 0fh interrupt vector register (ivect) 10h int0# status (int0st) 11h power fail register (pfailr) 12h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 159 ec domain functions 7.2.4.1 interrupt status register 0 (isr0) this register indicates which maskable interrupts are pendi ng regardless of the state of the corresponding ierx bits. address offset: 00h bit r/w default description 7-1 r/wc or r - interrupt status (is7-1) it indicates the interrupt input status of intx. intst7 to intst1 correspond to int7 to int1 respectively. each bit is r/wc if the correspondi ng bit in ielmrx register indicates edge-triggered mode, and is r if it indicates level-triggered mode. for each bit: read 0: interrupt input to intc is not pending. read 1: interrupt input to intc is pending. for each bit: write 0: no action write 1: clear this bit when it is in the edge-triggered mode, and writing 1 is ignored when it is in the level-triggered mode. 0 r 0b reserved 7.2.4.2 interrupt status register 1 (isr1) this register indicates which maskable interrupts are pendi ng regardless of the state of the corresponding ierx bits. address offset: 01h bit r/w default description 7-0 r/wc or r - interrupt status (is15-8) it indicates the interrupt input status of intx. intst15 to intst8 correspond to int15 to int8 respectively. each bit is r/wc if the correspondi ng bit in ielmrx register indicates edge-triggered mode, and is r if it indicates level-triggered mode. for each bit: read 0: interrupt input to intc is not pending. read 1: interrupt input to intc is pending. for each bit: write 0: no action write 1: clear this bit when it is in the edge-triggered mode, and writing 1 is ignored when it is in the level-triggered mode. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 160 it8511 e /te/ g 7.2.4.3 interrupt status register 2 (isr2) this register indicates which maskable interrupts are pendi ng regardless of the state of the corresponding ierx bits. address offset: 02h bit r/w default description 7-0 r/wc or r - interrupt status (is23-16) it indicates the interrupt input status of intx. intst23 to intst16 correspond to int23 to int16 respectively. each bit is r/wc if the correspondi ng bit in ielmrx register indicates edge-triggered mode, and is r if it indicates level-triggered mode. for each bit: read 0: interrupt input to intc is not pending. read 1: interrupt input to intc is pending. for each bit: write 0: no action write 1: clear this bit when it is in the edge-triggered mode, and writing 1 is ignored when it is in the level-triggered mode. 7.2.4.4 interrupt status register 3 (isr3) this register indicates which maskable interrupts are pendi ng regardless of the state of the corresponding ierx bits. address offset: 03h bit r/w default description 7-0 r/wc or r - interrupt status (is31-24) it indicates the interrupt input status of intx. intst31 to intst24 correspond to int31 to int24 respectively. each bit is r/wc if the correspondi ng bit in ielmrx register indicates edge-triggered mode, and is r if it indicates level-triggered mode. for each bit: read 0: interrupt input to intc is not pending. read 1: interrupt input to intc is pending. for each bit: write 0: no action write 1: clear this bit when it is in the edge-triggered mode, and writing 1 is ignored when it is in the level-triggered mode. 7.2.4.5 interrupt enable register 0 (ier0) address offset: 04h bit r/w default description 7-1 r/w 0h interrupt enable (ie7-0) each bit determines the corresponding interrupt channel (int7-0) is masked or enabled. note that it has no effect on int0 0: masked 1: enabled 0 - 0b reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 161 ec domain functions 7.2.4.6 interrupt enable register 1 (ier1) address offset: 05h bit r/w default description 7-0 r/w 0h interrupt enable (ie15-8) each bit determines the corresponding interrupt channel (int15-8) is masked or enabled. 0: masked 1: enabled. 7.2.4.7 interrupt enable register 2 (ier2) address offset: 06h bit r/w default description 7-0 r/w 0h interrupt enable (ie23-16) each bit determines the corresponding interrupt channel (int23-16) is masked or enabled. 0: masked 1: enabled 7.2.4.8 interrupt enable register 3 (ier3) address offset: 07h bit r/w default description 7-0 r/w 0h interrupt enable (ie31-24) each bit determines the corresponding interrupt channel (int31-24) is masked or enabled. 0: masked 1: enabled 7.2.4.9 interrupt edge/level-triggered mode register 0 (ielmr0) it determines the corresponding interrupt channel is level-triggered or edge-triggered. address offset: 08h bit r/w default description 7-0 r/w 0h interrupt edge/level-triggered mode (ielm7-0) each bit determines the triggered mode of the corresponding interrupt channel (int7-0). 0: level-triggered 1: edge-triggered free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 162 it8511 e /te/ g 7.2.4.10 interrupt edge/level-triggered mode register 1 (ielmr1) it determines the corresponding interrupt channel is level triggered or edge-triggered. address offset: 09h bit r/w default description 7-0 r/w 0h interrupt edge/level-triggered mode (ielm15-8) each bit determines the triggered mode of the corresponding interrupt channel (int15-8). 0: level-triggered 1: edge-triggered 7.2.4.11 interrupt edge/level-triggered mode register 2 (ielmr2) it determines the corresponding interrupt channel is level-triggered or edge-triggered. address offset: 0ah bit r/w default description 7-0 r/w 00011101b interrupt edge/level-triggered mode (ielm23-16) each bit determines the triggered mode of the corresponding interrupt channel (int23-16). 0: level-triggered 1: edge-triggered 7.2.4.12 interrupt edge/level-triggered mode register 3 (ielmr3) it determines the corresponding interrupt channel is level-triggered or edge-triggered. address offset: 0bh bit r/w default description 7-0 r/w 01001100b interrupt edge/level-triggered mode (ielm31-24) each bit determines the triggered mode of the corresponding interrupt channel (int31-24). 0: level-triggered 1: edge-triggered 7.2.4.13 interrupt polarity register 0 (ipolr0) for level-triggered interrupt, it determines this interr upt is level-high- triggered or level-low-triggered. for edge-triggered interrupt, it determines this interrupt is rising- edge-triggered or fa lling-edge-triggered. address offset: 0ch bit r/w default description 7-0 r/w 0h interrupt polarity (ipol7-0) each bit determines the active high/low of the corresponding interrupt channel (int7-0). 0: level-high-triggered or rising-edge-triggered 1: level-low-triggered or falling-edge-triggered free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 163 ec domain functions 7.2.4.14 interrupt polarity register 1 (ipolr1) for level-triggered interrupt, it determines this interr upt is level-high- triggered or level-low-triggered. for edge-triggered interrupt, it determines this interrupt is rising- edge-triggered or fa lling-edge-triggered. address offset: 0dh bit r/w default description 7-0 r/w 0h interrupt polarity (ipol15-8) each bit determines the active high/low of the corresponding interrupt channel (int15-8). 0: level-high-triggered or rising-edge-triggered 1: level-low-triggered or falling-edge-triggered 7.2.4.15 interrupt polarity register 2 (ipolr2) for level-triggered interrupt, it determines this interr upt is level-high- triggered or level-low-triggered. for edge-triggered interrupt, it determines this interrupt is rising- edge-triggered or fa lling-edge-triggered. address offset: 0eh bit r/w default description 7-0 r/w 0h interrupt polarity (ipol23-16) each bit determines the active high/low of the corresponding interrupt channel (int23-16 0: level-high-triggered or rising-edge-triggered 1: level-low-triggered or falling-edge-triggered 7.2.4.16 interrupt polarity register 3 (ipolr3) for level-triggered interrupt, it determines this interr upt is level-high- triggered or level-low-triggered. for edge-triggered interrupt, it determines this interrupt is rising- edge-triggered or fa lling-edge-triggered. address offset: 0fh bit r/w default description 7-0 r/w 0h interrupt polarity (ipol31-24) each bit determines the active high/low of the corresponding interrupt channel (int31-24). 0: level-high-triggered or rising-edge-triggered 1: level-low-triggered or falling-edge-triggered 7.2.4.17 interrupt vector register (ivct) address offset: 10h bit r/w default description 7-6 r 00b reserved 5-0 r 10000b interrupt vector (ivect) it contains the interrupt number, which is the highest priority, enabled and pending interrupt. the valid values range from 10h to 2fh. note that int1 has the lowest priority and int31 has the highest priority. if no enabled interrupt is pending, it returns 10h. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 164 it8511 e /te/ g 7.2.4.18 8032 int0# status (int0st) int0pf is set when falling edge transition of pwrfail# with tren or trenl bit in pfailr is set, and it is clear when being reset or read its content. int0rm is set when the trigger address matches the 8032 program counter. address offset: 11h bit r/w default description 7-1 - 00h reserved 1 r - int0# from rom match status (int0rm) 0: int0# is deasserted by an 8032 rom match. 1: int0# is asserted by an 8032 rom match. 0 r - int0# from pwrfail# status (int0pf) 0: int0# is deassert ed by a power-fail. 1: int0# is asserted by a power-fail. 7.2.4.19 power fail register (pfailr) it provides two methods to trap the pwrfail# event. this register can?t be reset by wdt reset. address offset: 12h bit r/w default description 7-3 - 00h reserved 2 r/w 0b pwrfail# trap enabled and locked (trenl) firmware sets this bit to enable pwrfail# trap. when trap is enabled, int0 bit in int0st will be set if the falling edge transition of pwrfail# is detected. this bit can?t be cleared by writing 0 to it until reset. 0: no pwrfail# trap 1: pwrfail# trap 1 r - pwrfail# status (pfailst) 0: pwrfail# is low (asserted) 1: pwrfail# is high (deasserted) 0 r/w 0b pwrfail# trap enabled (tren) firmware sets this bit to enable pwrfail# trap. when trap is enabled, int0 bit in int0st will be set if the falling edge transition of pwrfail# is detected, and tren will be cleared. this bit is ignored when trenl bit is set. 0: no pwrfail# trap 1: pwrfail# trap free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 165 ec domain functions 7.2.5 intc interrupt assignments table 7-8. intc interrupt assignments interrupt source default type(adjustable) description reference int0 reserved - - - int1 external/wuc high-level trig wko[20] figure 7-16, p 173 int2 internal high-level trig kbc output buffer empty interrupt section 6.5.3, p 91 int3 internal high-level trig pmc output buffer empty interrupt section 6.6.3.1, p 98 int4 internal rising-edge trig tmkbc interrupt section 6.7.5.1, p 114 int5 external/wuc high-level trig wkintad (wkinta or wkintd) figure 7-16, p 173 int6 external/wuc high-level trig wko[23] figure 7-16, p 173 int7 internal high-level trig pwm interrupt section 7.11.4.29, p 241 int8 internal high-level trig adc interrupt section 7.10.3.1, p 209 int9 internal high-level trig smbus0 interrupt section 7.7.3.1, p 191 int10 internal high-level trig smbus1 interrupt section 7.7.3.1, p 191 int11 internal high-level trig kb matrix scan interrupt section 7.4.2, p 174 int12 external/wuc high-level trig wko[26] figure 7-16, p 173 int13 external/wuc high-level trig wkintc figure 7-16, p 173 int14 external/wuc high-level trig wko[25] figure 7-16, p 173 int15 internal high-level trig cir interrupt section 7.16.4.3, p 270 int16 internal rising-edge trig ps/2 interrupt 3 section 7.8.2, p 202 int17 external/wuc high-level trig wko[24] figure 7-16, p 173 int18 internal rising-edge trig ps/2 interrupt 2 section 7.8.2, p 202 int19 internal rising-edge trig ps/2 interrupt 1 section 7.8.2, p 202 int20 internal rising-edge trig ps/2 interrupt 0 section 7.8.2, p 202 int21 external/wuc high-level trig wko[22] figure 7-16, p 173 int22 internal high-level trig smfi semaphore interrupt section 6.3.4.5, p 71 int23 internal high-level trig smfi lock error interrupt section 6.3.3.8, p 64 int24 internal high-level trig kbc input buffer full interrupt section 6.5.3, p 91 int25 internal high-level trig pmc input buffer full interrupt section 6.6.3.1, p 98 int26 - - - - int27 - - - - int28 external high-level trig gint from function 1 of gpd5 table 5-11, p 20 int29 internal high-level trig rtc alarm 2 section 6.8.3, p 118 int30 internal rising-edge trig external timer interrupt section 7.13.3, p 254 int31 external/wuc high-level trig wko[21] figure 7-16, p 173 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 166 it8511 e /te/ g figure 7-14. intc simplified diagram ring#/pwrfail#/lpcrst#/gpb7 to int0# of 8032 trap handler int0pf dbgr int0rm ier[0] intc input sources 0 int0 ielmr[0] isr[0] 0 ipolr[0] 1 from grp1 int1 ? int2 ? ::: int7 ? to int1# of 8032 grp1 from grp2 from grp3 from grp4 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 167 ec domain functions 7.2.6 programming guide figure 7-15. program flow chart for intc flow of level-triggered interrupt channel of intc modify the corresponding bit in ielmr and ipolr if the default value is not wanted write 1 to the corresponding bit in ier to enable it interrupt triggered on int1# of 8032 and run the service routine the routine determines which channel is triggered by reading ivct write 1 to clear the corresponding status in isr flow of edge-triggered interrupt channel of intc clear this interrupt event at its source modify the corresponding bit in ielmr and ipolr if the default value is not wanted clear this interrupt event by writing 1 to the corresponding bit in isr write 1 to the corresponding bit in ier to enable it interrupt triggered on int1# of 8032 and run the service routine the routine determines which channel is triggered by reading ivct note: the routine may has its own interrupt priority by reading isr register. note: if this channel source comes from wuc, the corresponding bit of wuesr needs to be cleared, too free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 168 it8511 e /te/ g 7.3 wake-up control (wuc) 7.3.1 overview wuc groups internal and external inputs, and asserts wake-up signals to intc that allows 8232 to exit an idle/doze/sleep mode. 7.3.2 features ? supports up to 32 wake-up, internal and external interrupt inputs. ? supports both the rising-edge and falling-edge triggered mode. ? input can be connected to intc directly. 7.3.3 functional description input sources of wuc are external inputs such as pi ns about ps/2, gpio and kb matrix scan, or inputs from internal module such as swuc, lpc and smbus that handle external inputs. each channel can be selected to be rising or falling ed ge triggered mode. if one channel is disabled, the input bypasses wuc pending logic and is connected directly to intc. 7.3.4 ec interface registers the ec interface registers are listed bel ow. the base address for wuc is 1b00h. table 7-9. ec view register map, wuc 7 0 offset wake-up edge mode register (wuemr1) 00h wake-up edge mode register (wuemr2) 01h wake-up edge mode register (wuemr3) 02h wake-up edge mode register (wuemr4) 03h wake-up edge sense register (wuesr1) 04h wake-up edge sense register (wuesr2) 05h wake-up edge sense register (wuesr3) 06h wake-up edge sense register (wuesr4) 07h wake-up enable r egister (wuenr1) 08h wake-up enable r egister (wuenr2) 09h wake-up enable r egister (wuenr3) 0ah wake-up enable r egister (wuenr4) 0bh 7.3.4.1 wake-up edge mode register (wuemr1) this register configures the trigger mode of input signals wu10 to wu17. address offset: 00h bit r/w default description 7-0 r/w 0h wake-up edge mode (wuem17-10) 0: rising-edge triggered is selected. 1: falling-edge triggered is selected. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 169 ec domain functions 7.3.4.2 wake-up edge mode register (wuemr2) this register configures the trigger mode of input signals wu20 to wu27. address offset: 01h bit r/w default description 7-0 r/w 0h wake-up edge mode (wuem27-20) 0: rising-edge triggered is selected. 1: falling-edge triggered is selected. 7.3.4.3 wake-up edge mode register (wuemr3) this register configures the trigger mode of input signals wu30 to wu37. address offset: 02h bit r/w default description 7-0 r/w 0h wake-up edge mode (wuem37-30) 0: rising-edge triggered is selected. 1: falling-edge triggered is selected. 7.3.4.4 wake-up edge mode register (wuemr4) this register configures the trigger mode of input signals wu40 to wu47. address offset: 03h bit r/w default description 7-0 r/w 0h wake-up edge mode (wuem47-40) 0: rising-edge triggered is selected. 1: falling-edge triggered is selected. 7.3.4.5 wake-up edge sense register (wuesr1) this register indicates the occurrenc e of a selected trigger condition and is associated with input signals wu10 to wu17. note : each bit cannot be set by software. writing a 1 c an clear these bits and writing a 0 has no effect. address offset: 04h bit r/w default description 7-0 r/wc - wake-up sense (wues17-10) for each bit: read 1: it indicates a trigger condition occurs on the corresponding input. read 0: otherwise for each bit: write 1: clear this bit write 0: no action free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 170 it8511 e /te/ g 7.3.4.6 wake-up edge sense register (wuesr2) this register indicates the occurrenc e of a selected trigger condition and is associated with input signals wu20 to wu27. note : each bit cannot be set by software. writing a 1 c an clear these bits and writing a 0 has no effect. address offset: 05h bit r/w default description 7-0 r/wc - wake-up sense (wues27-20) for each bit: read 1: it indicates a trigger condition occurs on the corresponding input. read 0: otherwise for each bit: write 1: clear this bit write 0: no action 7.3.4.7 wake-up edge sense register (wuesr3) this register indicates the occurrenc e of a selected trigger condition and is associated with input signals wu30 to wu37. note : each bit cannot be set by software. writing a 1 c an clear these bits and writing a 0 has no effect. address offset: 06h bit r/w default description 7-0 r/wc - wake-up sense (wues37-30) for each bit: read 1: it indicates a trigger condition occurs on the corresponding input. read 0: otherwise for each bit: write 1: clear this bit write 0: no action 7.3.4.8 wake-up edge sense register (wuesr4) this register indicates the occurrenc e of a selected trigger condition and is associated with input signals wu40 to wu47. note: each bit cannot be set by software. writing a 1 can clear these bits and writing a 0 has no effect. address offset: 07h bit r/w default description 7-0 r/wc - wake-up sense (wues47-40) for each bit: read 1: it indicates a trigger condition occurs on the corresponding input. read 0: otherwise for each bit: write 1: clear this bit write 0: no action free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 171 ec domain functions 7.3.4.9 wake-up enable register (wuenr1) this register enables a wake-up function of the corresponding input signal wu10 to wu17. address offset: 08h bit r/w default description 7-0 r/w 0h wake-up enable (wuen17-10) 1: a trigger condition on the corresponding input generates a wake-up signal to the power management control of ec. 0: a trigger condition on the corresponding input doesn?t assert the wake-up signal; it is canceled but not pending. 7.3.4.10 wake-up enable register (wuenr2) this register enables a wake-up function of the corresponding input signal wu20 to wu27. address offset: 09h bit r/w default description 7-0 r/w 0h wake-up enable (wuen27-20) 1: a trigger condition on the corresponding input generates a wake-up signal to the power management control of ec, and the wuo27-20 from wui27-20 is processed by wuemr2 and wuesr2. 0: a trigger condition on the corresponding input doesn?t assert the wake-up signal and the wuo27-20 is connected to the intc directly. 7.3.4.11 wake-up enable register (wuenr3) this register enables a wake-up function of the corresponding input signal wu30 to wu37. address offset: 0ah bit r/w default description 7-0 r/w 0h wake-up enable (wuen37-30) 1: a trigger condition on the corresponding input generates a wake-up signal to the power management control of ec. 0: a trigger condition on the corresponding input doesn?t assert the wake-up signal; it is canceled, not pending. 7.3.4.12 wake-up enable register (wuenr4) this register enables a wake-up function of the corresponding input signal wu40 to wu47. address offset: 0bh bit r/w default description 7-0 r/w 0h wake-up enable (wuen47-40) 1: a trigger condition on the corresponding input generates a wake-up signal to the power management control of ec. 0: a trigger condition on the corresponding input doesn?t assert the wake-up signal; it is canceled but not pending. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 172 it8511 e /te/ g 7.3.5 wuc input assignments table 7-10. wuc i nput assignments wuc input source description output to intc default type (adjustable) wu10 ps2clk0 external source from pin rising edge trig wu11 ps2dat0 external source from pin rising edge trig wu12 ps2clk1 external source from pin rising edge trig wu13 ps2dat1 external source from pin wkinta, to int5 rising edge trig wu14 ps2clk2 external source from pin rising edge trig wu15 ps2dat2 external source from pin rising edge trig wu16 ps2clk3 external source from pin rising edge trig wu17 ps2dat3 external source from pin rising edge trig wu20 wui0 external source from pin wko[20], to int1 rising edge trig wu21 wui1 external source from pin wko[21], to int31 rising edge trig wu22 wui2 external source from pin wko[22], to int21 rising edge trig wu23 wui3 external source from pin wko[23], to int6 rising edge trig wu24 wui4 external source from pin wko[24], to int17 rising edge trig wu25 pwrsw external source from pin wko[25], to int14 rising edge trig wu26 swuc wake up from swuc module wko[26], to int12 rising edge trig wu27 reserved wu30 ksi[0] external source from pin rising edge trig wu31 ksi[1] external source from pin rising edge trig wu32 ksi[2] external source from pin rising edge trig wu33 ksi[3] external source from pin wkintc, to int13 rising edge trig wu34 ksi[4] external source from pin rising edge trig wu35 ksi[5] external source from pin rising edge trig wu36 ksi[6] external source from pin rising edge trig wu37 ksi[7] external source from pin rising edge trig wu40 wui5 external source from pin rising edge trig wu41 crx external source from pin wu42 lpc access lpc cycle with address recognized see also section 6.1.6, p 39 rising edge trig wu43 smdat0 external source from pin wkintd, to int5 wu44 smdat1 external source from pin wu45 wui6 external source from pin rising edge trig wu46 wui7 external source from pin rising edge trig wu47 reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 173 ec domain functions figure 7-16. wuc simplified diagram wuenr[0] wuc input sources wu20 wuemr[0] wuesr[0] 1 wko[0] wko[20] to intc 0 wkintb ? wu21 ?? wko[21] to intc ? wu22 ?? wko[22] to intc ::: ::: ? wu27 ?? wko[27] to intc grp2 from grp1 wkinta to intc from grp3 wkintc to intc note: only wko[ ] from grp2 are connected to intc, and from grp4 wkintd to intc others are dis-connected 7.3.6 programming guide if the wuc source is from gpio port, the firmware sh ould not enable the corresponding channel when this gpio is not in alternate function. figure 7-17. program flow chart for wuc write 1 to clear the corresponding status in wuesr flow of edge triggered interrupt channel of wuc modify the corresponding bit in wuemr if default value is not wanted the interrupt routine has handled this event at clear this bit in wuesr corresponding bit in wuenr to enable it interrupt triggered to intc write 1 to the free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 174 it8511 e /te/ g 7.4 keyboard matrix scan controller 7.4.1 overview the module provides control for keyboard matrix scan. 7.4.2 features ? supports 18 x scan output ? supports 8 x scan input ? supports schmitt trigger input pin ? supports programmable pull-up on all output/input pins ? supports one interrupt (connected to int11 of intc) for any ksi inputs to go low to wake up the system 7.4.3 ec interface registers the keyboard matrix scan registers are li sted below. the base address is 1d00h. table 7-11. ec view register map, kb scan 7 0 offset keyboard scan out [7:0] (ksol) 00h keyboard scan out [15:8] (ksoh1) 01h keyboard scan out control (ksoctrl) 02h keyboard scan out [17:16] (ksoh2) 03h keyboard scan in [7:0] (ksi) 04h keyboard scan in control (ksictrl) 05h 7.4.3.1 keyboard scan out low byte data register (ksol) address offset: 00h bit r/w default description 7-0 r/w 0h keyboard scan out low data [7:0] (ksol) this is the 8-bit keyboard scan output register which controls the kso[7:0] pins. 7.4.3.2 keyboard scan out high byte data 1 register (ksoh1) address offset: 01h bit r/w default description 7-0 r/w 0h keyboard scan out high data 1 [7:0] (ksoh1) this is the 8-bit keyboard scan output register which controls the kso[15:8] pins. 7.4.3.3 keyboard scan out control register (ksoctrl) address offset: 02h bit r/w default description 7-6 - - reserved 5-3 - - reserved 2 r/w 0h kso pull up (ksopu) setting 1 enables the internal pull up of the kso[15:0] pins. to pull up kso[17:16], set the gpcr re gisters of their corresponding gpio ports. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 175 ec domain functions bit r/w default description 1 - - reserved 0 r/w 0h kso open drain (ksood) setting 1 enables the open-drain mode of the kso[17:0] pins. setting 0 selects the push-pull mode. 7.4.3.4 keyboard scan out high byte data 2 register (ksoh2) address offset: 03h bit r/w default description 7-2 - - reserved 1-0 r/w 0h keyboard scan out high data 2 [1:0] (ksoh2) this is the 2-bit keyboard scan output register which controls the kso[17:16] pins. 7.4.3.5 keyboard scan in data register (ksir) address offset: 04h bit r/w default description 7-0 r 0h keyboard scan in high data [7:0] (ksi) this is the 8-bit keyboard scan input register which shows the value of the ksi[7:0] pins. 7.4.3.6 keyboard scan in control register (ksictrlr) address offset: 05h bit r/w default description 7-5 - 0h reserved 4 r/w 0h override pp from kbs (ovrppk) this bit overrides pp function which is enabled by hardware strap in kbs interface and disables it. 3 r/w 0h override pp from ppen (ovrppen) this bit overrides pp function which is enabled by hardware strap ppen and disables it. 2 r/w 0h ksi pull up (ksipu) setting 1 enables the internal pull up of the ksi[7:0] pins. 1 - - reserved 0 - - reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 176 it8511 e /te/ g 7.5 general purpose i/o port (gpio) 7.5.1 overview the general purpose i/o port is composed of independent i/o pins controlled by registers. there is also other available general pur pose i/o such as hardware strap id7-0. 7.5.2 features ? i/o pins individually configured as input, output or alternate function ? supports 98-port gpio ? configurable internal pull-up resistors ? configurable internal pull-down resistors ? supports schmitt-trigger input on all ports 7.5.3 ec interface registers the ec interface registers are listed bel ow. the base address for gpio is 1600h. table 7-12. ec view register map, gpio 7 0 offset general control register (gcr) 00h port data register (gpdra) 01h port data register (gpdrb) 02h ? ? port data register (gpdri) 09h port control n registers (gpcra0) 10h port control n registers (gpcra1) 11h ? ? port control n registers (gpcrj5) 5dh port data mirror register (gpdmra) 61h port data mirror register (gpdmrb) 62h ? ? port data mirror register (gpdmrm) a5h output type register (gpota) 71h ? ? output type register (gpoti) 79h 7.5.3.1 general control register (gcr) this register individually controls the bus state of ea ch port. the input gating and output floating control signals can be used to reduce power consumption in various system conditions. address offset: 00h bit r/w default description 7 r/w 0h gpb5 follow lpcrst# enable (gfle) 1: gpdrb bit 5 will be set immediately if there is a high-to-low transition on wui4. 0: otherwise note that ga20 is function 1 of gpb5, lpcrst# is function 1 of gpd2 and wui4 is function 2 of gpd2. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 177 ec domain functions bit r/w default description 6 r/w 0b wui7 enabled (wui7en) when set, wui7 is on input from gpe7. it is valid only when gpmd is input or output mode. 5 r/w 0b wui6 enabled (wui6en) when set, wui6 is on input from gpe6. it is valid only when gpmd is input or output mode. 4-3 - 00b reserved 2-1 r/w 10b lpc reset enabled (lpcrsten) 00: reserved 01: lpc reset is enabled on gpb7. 10: lpc reset is enabled on gpd2. 11: lpc reset is disabled. 0 - - reserved 7.5.3.2 port data regi sters a-m (gpdra-gpdrm) the port data register (gpdr) is an 8-bit register. t he pin function is controlled by port control register (gpcrn). when the pin function is set to be a general output pin, the value of the gpdrx bit is directly output to its corresponding pin. when the pin function is set to be a general input pin, the pin level status can be detected by reading the corresponding register bit. each register contains one group which has eight ports at most. address offset: 01h-0dh bit r/w default description 7-0 r/w gpdrb: port data register (gpdrn[7:0]) 20h otherwise: 00h when the pin function is set to be a gener al output pin, the value of this bit is directly output to its corresponding pin. in the output mode, reading this regist er returns the last written data to gpdrn. in other modes, reading this register returns the pin level status. for group k/j and gpe0-3, the return data may have no meaning in the function 1 mode. 7.5.3.3 port data mirror re gisters a-m (gpdmra-gpdmrm) address offset: 61h-6dh bit r/w default description 7-0 r - port data mirror register (gpdmrn[7:0]) reading this register returns the pin level status. for group k/j and gpe0-3, the return data may have no meaning in the function 1 mode. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 178 it8511 e /te/ g 7.5.3.4 port control n registers (gpcrn, n = a0-i7) these registers are used to control the functions of each i/o port pin. each register is responsible for the settings of one pin in the port. if operation mode is ?alternate function?, function 1 and/or function 2 will be enabled. refer to table 7-13. gpio alternate function on page 181 for details. address offset: 10h-17h for gpcra0- gpcra7, respectively (group a) address offset: 18h-1fh for gpcrb0- gpcrb7, respectively (group b) address offset: 20h-27h for gpcrc0- gpcrc7, respectively (group c) address offset: 28h-2fh for gpcrd0- gpcrd7, respectively (group d) address offset: 30h-37h for gpcre0- gpcre7, respectively (group e) address offset: 38h-3fh for gpcrf0- gpcrf7, respectively (group f) address offset: 40h-47h for gpcrg0- gpcrg7, respectively (group g) address offset: 48h-4fh for gpcrh0- gpcrh7, respectively (group h) address offset: 50h-57h for gpcri0- gpcri7, respectively (group i) address offset: 58h-5dh for gpcrj0- gpcrj5, respectively (group j) address offset: 90h-95h for gpcrk0- gpcrk5, respectively (group k) address offset: 98h-9fh for gpcrl0- gpcrl7, respectively (group l) address offset: a0h-a5h for gpcrm0-gpc rm5, respectively (group m) bit r/w default description port pin mode (gpmd[1:0]) these bits are used to select the gpio operation mode. note that gpeo-gpe3/group k doesn?t have the output mode and the corresponding gpmd cannot be assigned as 01. gpmd[1:0] pin status read gpdrn write gpdrn 00b alternate function pin status gpdr is writable but it has no effects on the pin status. 01b output pin status the value written to gpdr is output to pin. 10b input pin status gpdr is writable but it has no effects on the pin status. 7-6 r/w - 11b reserved - - 5-3 r/w - reserved 2 r/w refer to table 7-13 on page 181 port pin pull up (gppu) this bit is used to pull the port. this bit is always valid regardless of gpmd, input or output. enable this bi t will increase power consumption. note that if one port is operated in output mode, it should not enable this bit unless its output type is open-drain. for example, clear this bit when fa16/gpg0 is switched to alternative function. for gpg0-g7 (to be compatible with it8510) 0: disable the pull down function. 1: enable the pull down function. for others: 0: disable the pull up function. 1: enable the pull up function. 1 r/w refer to table 7-13 port pin pull down (gppd) this bit is used to pull the port. it is always valid regardless of gpmd, free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 179 ec domain functions on page 181 input or output. never enable pull up/down of a port at the same time or it forms a dc path and has unnecessary leakage current. this pull down control bit is only available for group j, l and m. 0 r/w 0 reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 180 it8511 e /te/ g 7.5.3.5 output type registers a-i (gpota-gpoti) the output type register (gpot) is an 8-bit register. these registers control the output type of gpio. each register contains one group which has eight ports. note that these bits are valid only when corresponding gpmd equals to 01 (output mode). address offset: 71h-79h bit r/w default description 7-0 r/w 00h output type register (gpotn[7:0]) for each bit: 0: push-pull output 1: open-drain output this register is not available for group j-m. free datasheet http:/// www.ite.com.tw 181 it8511e/te/g v0.4.1 ec domain functions 7.5.4 alternate function selection the following lists function 1 and function 2 of each gpio port. no tice that the ga20 function can be implemented by gpo or fun ction 1 which is implemented at kbc module. function 1 of gpb6 is kbrst# from kbc module through swuc mode. lpcrst# is recommended to input from gpd2 port. table 7-13. gpio alternate function group addr pin loc. function 1 condition function 2 condition output driving (ma) schmitt trigger pull cap. default pull default mode gpioa 0 1610h 32 pwm0 gpcra0[7:6]=00 8 y up up gpi 1 1611h 33 pwm1 gpcra1[7:6]=00 8 y up up gpi 2 1612h 36 pwm2 gpcra2[7:6]=00 8 y up up gpi 3 1613h 37 pwm3 gpcra3[7:6]=00 8 y up up gpi 4 1614h 38 pwm4 gpcra4[7:6]=00 8 y up up gpi 5 1615h 39 pwm5 gpcra5[7:6]=00 8 y up up gpi 6 1616h 40 pwm6 gpcra6[7:6]=00 8 y up up gpi 7 1617h 43 pwm7 gpcra7[7:6]=00 8 y up up gpi gpiob 0 1618h 153 rxd gpcrb0[7:6]=00 2 y up up gpi 1 1619h 154 txd gpcrb1[7:6]=00 2 y up up gpi 2 161ah 162 2 y up gpi 3 161bh 163 smclk0 gpcrb3[7:6]=00 4 y up gpi 4 161ch 164 smdat0 gpcrb4[7:6]=00 4 y up gpi 5 161dh 5 ga20 gpcrb5[7:6]=00 2 y up gpo 6 161eh 6 kbrst# gpcrb6[7:6]=00 2 y up up func1 7 161fh 165 ring# gpcrb7[7:6]=00 pwrfail#/ lpcrst# gpcrb7[7:6]=00 /lpcrsten=01 2 y up gpi free datasheet http:/// www.ite.com.tw 182 it8511e/te/g v0.4.1 it8511 e /te/ g group addr pin loc. function 1 condition function 2 condition output driving (ma) schmitt trigger pull cap. default pull default mode gpioc 0 1620h 47 clkout gpcrc0[7:6]=00 2 y up gpi 1 1621h 169 smclk1 gpcrc1[7:6]=00 4 y up gpi 2 1622h 170 smdat1 gpcrc2[7:6]=00 4 y up gpi 3 1623h 171 2 y up gpi 4 1624h 172 tmri0 gpcrc4[7:6]=00 wui2 gpcrc4[7:6]=00 2 y up gpi 5 1625h 175 2 y up gpi 6 1626h 176 tmri1 gpcrc6[7:6]=00 wui3 gpcrc6[7:6]=00 2 y up gpi 7 1627h 1 ck32kout gpcrc7[7:6]=00 4 y up up gpi gpiod 0 1628h 26 ri1# gpcrd0[7:6]=00 wui0 gpcrd0[7:6]=00 4 y up up gpi 1 1629h 29 ri2# gpcrd1[7:6]=00 wui1 gpcrd1[7:6]=00 4 y up up gpi 2 162ah 30 lpcrst# lpcrsten=10 wui4 gpcrd2[7:6]=00 8 y up up func1 3 162bh 31 ecsci# gpcrd3[7:6]=00 8 y up up gpi 4 162ch 41 8 y up up gpi 5 162dh 42 gint gpcrd5[7:6]=00 8 y up up gpi 6 162eh 62 tach0 gpcrd6[7:6]=00 2 y up gpi 7 162fh 63 tach1 gpcrd7[7:6]=00 2 y up gpi gpioe 0 1630h 87 adc4 gpcre0[7:6]=00 n/a gpi 1 1631h 88 adc5 gpcre1[7:6]=00 n/a gpi 2 1632h 89 adc6 gpcre2[7:6]=00 n/a gpi 3 1633h 90 adc7 gpcre3[7:6]=00 n/a gpi 4 1634h 2 pwrsw gpcre4[7:6]=00 2 y up up gpi 5 1635h 44 wui5 gpcre5[7:6]=00 2 y up gpi 6 1636h 24 lpcpd# gpcre6[7:6]=00 wui6 wui6en bit gcr register 2 y up gpi 7 1637h 25 clkrun# gpcre7[7:6]=00 wui7 wui7en bit gcr register 4 y up up gpi free datasheet http:/// www.ite.com.tw 183 it8511e/te/g v0.4.1 ec domain functions group addr pin loc. function 1 condition function 2 condition output driving (ma) schmitt trigger pull cap. default pull default mode gpiof 0 1638h 110 ps2clk0 gpcrf0[7:6]=00 8 y up up gpi 1 1639h 111 ps2dat0 gpcrf1[7:6]=00 8 y up up gpi 2 163ah 114 ps2clk1 gpcrf2[7:6]=00 8 y up up gpi 3 163bh 115 ps2dat1 gpcrf3[7:6]=00 8 y up up gpi 4 163ch 116 ps2clk2 gpcrf4[7:6]=00 8 y up up gpi 5 163dh 117 ps2dat2 gpcrf5[7:6]=00 8 y up up gpi 6 163eh 118 ps2clk3 gpcrf6[7:6]=00 8 y up up gpi 7 163fh 119 ps2dat3 gpcrf7[7:6]=00 8 y up up gpi gpiog 0 1640h 113 fa16 gpcrg0[7:6]=00 4 y dn dn gpi 1 1641h 112 fa17 gpcrg1[7:6]=00 4 y dn dn gpi 2 1642h 104 fa18 gpcrg2[7:6]=00 4 y dn dn gpi 3 1643h 103 fa19 gpcrg3[7:6]=00 4 y dn dn gpi 4 1644h 3 fa20 gpcrg4[7:6]=00 4 y dn dn gpi 5 1645h 4 fa21 gpcrg5[7:6]=00 4 y dn dn gpi 6 1646h 27 lpc80hl gpcrg6[7:6]=00 4 y dn gpi 7 1647h 28 lpc80ll gpcrg7[7:6]=00 4 y dn gpi gpioh 0 1648h 48 2 y up gpi 1 1649h 54 8 y up up gpi 2 164ah 55 8 y up up gpi 3 164bh 69 8 y up gpi 4 164ch 70 8 y up gpi 5 164dh 75 2 y up gpi 6 164eh 76 2 y up gpi 7 164fh 105 4 y up gpi gpioi 0 1650h 148 2/12 y up gpi 1 1651h 149 2/12 y up gpi 2 1652h 152 2/12 y up gpi 3 1653h 155 2/12 y up gpi 4 1654h 156 2/12 y up gpi 5 1655h 168 2/12 y up gpi 6 1656h 174 2/12 y up gpi 7 1657h 109 2/12 y up up gpi free datasheet http:/// www.ite.com.tw 184 it8511e/te/g v0.4.1 it8511 e /te/ g group addr pin loc. function 1 condition function 2 condition output driving (ma) schmitt trigger pull cap. default pull default mode gpioj 0 1658h 99 dac0 gpcrj0[7:6]=00 4 y up/dn func1 1 1659h 100 dac1 gpcrj1[7:6]=00 4 y up/dn func1 2 165ah 101 dac2 gpcrj2[7:6]=00 4 y up/dn func1 3 165bh 102 dac3 gpcrj3[7:6]=00 4 y up/dn func1 4 165ch 97 4 y up/dn dn gpi 5 165dh 98 4 y up/dn dn gpi gpiok 0 1690h 81 adc0 gpcrj0[7:6]=00 n/a func1 1 1691h 82 adc1 gpcrk1[7:6]=00 n/a func1 2 1692h 83 adc2 gpcrk2[7:6]=00 n/a func1 3 1693h 84 adc3 gpcrk3[7:6]=00 n/a func1 4 1694h 93 adc8 gpcrk4[7:6]=00 n/a func1 5 1695h 94 adc9 gpcrk5[7:6]=00 n/a func1 gpiol 0 1698h 8 gpcrl0[7:6]=00 4 y up/dn dn gpi 1 1699h 11 gpcrl1[7:6]=00 4 y up/dn dn gpi 2 169ah 12 gpcrl2[7:6]=00 4 y up/dn dn gpi 3 169bh 20 gpcrl3[7:6]=00 4 y up/dn dn gpi 4 169ch 21 gpcrl4[7:6]=00 4 y up/dn dn gpi 5 169dh 106 gpcrl5[7:6]=00 4 y up/dn dn gpi 6 169eh 107 gpcrl6[7:6]=00 4 y up/dn dn gpi 7 169fh 108 gpcrl7[7:6]=00 4 y up/dn dn gpi gpiom 0 16a0h 22 ecsmi# gpcrm0[7:6]=00 8 y up/dn func1 1 16a1h 23 pwureq# gpcrm1[7:6]=00 2 y up/dn func1 2 16a2h 85 gpcrm2[7:6]=00 2 y up/dn dn gpi 3 16a3h 86 gpcrm3[7:6]=00 2 y up/dn dn gpi 4 16a4h 91 gpcrm4[7:6]=00 8 y up/dn dn gpi 5 16a5h 92 gpcrm5[7:6]=00 2 y up/dn dn gpi free datasheet http:/// www.ite.com.tw 185 it8511e/te/g v0.4.1 ec domain functions note: since all gpio belong to vstby power plane, and there are some special considerations below: (1) if it is output to external vcc derived power plane circuit, this signal should be isolated by a diode such as kbrst# and g a20. (2) if it is input from external vcc derived power plane circuit, this external circuit must consider not to float the gpio inp ut. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 186 it8511 e /te/ g figure 7-18. gpio simplified diagram 0 1 0 1 pad flip-flop data register data mirror register 0 1 to input of altfunc circuit from output of altfunc circuit hardware wired input gating value gpmd = 00 (altfunc) gpmd = 00 (altfunc) ec-bus gpmd = 01 (gpo) port0 port1 port7 ... grpa grpb ... for each port (bit) in each group 7.5.5 programming guide the firmware should modify lpcrsten and enable fa 16-fa21 alternative function when it boots up if necessary. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 187 ec domain functions 7.6 ec clock and power management controller (ecpm) 7.6.1 overview the ec clock and power management module provide the ec clock control and power management. 7.6.2 features ? supports programmable ec clock frequency ? supported by module power-down mode control ? supports pll power-down when 8032 enters a sleep mode 7.6.3 ec interface registers the clock generation and power ma nagement registers are listed belo w. the base address is 1e00h. table 7-14. ec view register map, ecpm 7 0 offset clock frequency select (cfselr) 00h clock gating control 1 (cgctrl1r) 01h clock gating control 2 (cgctrl2r) 02h clock gating control 3 (cgctrl3r) 05h pll control (pllctrl) 03h auto clock gating (autocg) 04h 7.6.3.1 clock frequency select register (cfselr) address offset: 00h bit r/w default description 7-5 - - reserved 4 r/w 0b clock frequency select (cfsel) 0: uc clock is divided and it depends on cdnum (bit 3-0). 1: no divided 3-0 r/w 0h clock div number (cdnum) the frequency of uc is divided by (cdnum + 1) * 2 and that is 2~32. 7.6.3.2 clock gating control 1 register (cgctrl1r) this register is reset by vstby power-up reset only. address offset: 01h bit r/w default description 7 r/w 0b gpio clock gating (gpiocg) 0: operation 1: clock to this module is gated 6 r/w 0b etwd clock gating (etwdcg) 0: operation 1: clock to this module is gated 5 r/w 0b smb clock gating (smbcg) 0: operation 1: clock to this module is gated 4 r/w 0b keyboard scan clock gating (kbscg) 0: operation 1: clock to this module is gated free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 188 it8511 e /te/ g bit r/w default description 3 r/w 0b ps/2 clock gating (ps2cg) 0: operation 1: clock to this module is gated 2 r/w 0b pwm clock gating (pwmcg) 0: operation 1: clock to this module is gated 1 r/w 0b dac clock gating (daccg) 0: operation 1: clock to this module is gated 0 r/w 0b adc clock gating (adccg) 0: operation 1: clock to this module is gated 7.6.3.3 clock gating control 2 register (cgctrl2r) this register is reset by vstby power-up reset only. address offset: 02h bit r/w default description 7 r/w 0b tmkbc clock gating (tmkcg) 0: operation 1: clock to this module is gated 6 r/w 0b egpc clock gating (exgcg) 0: operation 1: clock to this module is gated 5 r/w 0b cir clock gating (circg) 0: operation 1: clock to this module is gated 4 r/w 0b swuc clock gating (swuccg) 0: operation 1: clock to this module is gated 3 r/w 0b pmc clock gating (pmccg) 0: operation 1: clock to this module is gated 2 r/w 0b kbc clock gating (kbccg) 0: operation 1: clock to this module is gated 1 r/w 0b ec2i clock gating (ec2icg) 0: operation 1: clock to this module is gated 0 r/w 0b smfi clock gating (smficg) 0: operation 1: clock to this module is gated free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 189 ec domain functions 7.6.3.4 clock gating control 3 register (cgctrl3r) this register is reset by vstby power-up reset only. address offset: 05h bit r/w default description 7 w 0b r8030tt uart clock gating(uartcg) 0: operation 1: clock to this function is gated 6 w 1b reserved always write 1 to this bit. 5-1 - - reserved 0 r/w 1b dbgr clock gating (dbgrcg) 0: operation 1: clock to this module is gated. 7.6.3.5 pll control (pllctrl) this register is reset by vstby power-up reset only. address offset: 03h bit r/w default description 7-1 - - reserved 0 r/w 1b pll power down control (ppdc) 0: pll will not be power-down by soft ware until vstby is not supplied. setting pd bit in pcon will enter an ec doze mode. 1: pll will be power down after setti ng pd bit in pcon and enter an ec power-down mode. 7.6.3.6 auto clock gating (autocg) this register is reset by vstby power-up reset only. for the ps/2 module, normally it can not be accomplishe d to gate the clock of ps/2 module in the idle/doze mode if it?s clock-gated by ps2cg bi t since the clock of ps/2 module should be released immediately after an activity on ps/2 interface. however, it can be acco mplished by setting aps2cg bit wi th enabling its interrupt path. aps2cg required interrupt pat h: (corresponding wu10~15 ) -> int5 -> 8032 int1# for smb and cir modules, they are similar. asmbcg required interrupt path: (correspo nding wu43,44,47) -> int5 -> 8032 int1# cir required interrupt path: wu41 -> int5 -> 8032 int1# address offset: 04h bit r/w default description 7-4 - - reserved 3 r/w 0b auto tmkbc clock gating (tmkcg) 1: automatically gating clock of tm kbc if tm hardware strap is not enabled or the chip is in the idle/doze/sleep mode. it also overrides tmkcg bit in cgctrl2r register. 0: tmkbc clock is gated by tmkcg bit in cgctrl2r register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 190 it8511 e /te/ g bit r/w default description 2 r/w 0b auto cir clock gating (acircg) 1: automatically gating clock of cir if the corresponding port of gpio is not in its alternative function or the chip is in the idle/doze/sleep mode. it also overrides circg bit in cgctrl2r register. 0: cir clock is gated by circg bit in cgctrl2r register. 1 r/w 0b auto ps/2 clock gating (aps2cg) 1: automatically gating clock of ps2 by channel if the corresponding port of gpio is not in its alternative function or the chip is in the idle/doze/sleep mode. it also ov errides ps2cg bit in cgctrl1r register. 0: ps/2 clock is gated by ps2cg bit in cgctrl1r register. 0 r/w 0b auto smb clock gating (asmbcg) 1: automatically gating clock of smb by channel if the corresponding port of gpio is not in its alternative function or the chip is in the idle/doze/sleep mode. it also ov errides smbcg bit in cgctrl1r register. 0: smb clock is gated by smbcg bit in cgctrl1r register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 191 ec domain functions 7.7 sm bus interface (smb) 7.7.1 overview the smbus interface includes two smbus channels. the module can maintain bi-directional communication with the external device through smclk0/smdat0 (cha nnel a) and smclk1/smdat1 (channel b) pins. it is compatible with access bus and i2c bus. 7.7.2 features ? supports smbus 2.0. ? supports two smbus channels. ? performs smbus messages with packet error checking (pec) either enabled or disabled. 7.7.3 functional description this smbus interface provides an smbus master fo r each channel. the master supports seven command protocols of the smbus (see system management bus specification): quick command, send byte, receive byte, write byte/word, read byte/word, process call, and block read/write. 7.7.3.1 smbus master interface when an interrupt to intc (int9 and int10 for channel a and b respectively) is detected, software can read the host status register to know t he interrupt source. there are 5 interrupt conditions: byte done, failed, bus error, device error, and finish. quick command: in the quick command, the transmit slave address register is sent. so ftware should force the pec_en bit in host control register and i2c_en bit in host cont rol 2 register to 0 when this command is run. send byte/ receive byte: in the send byte command, the transmit slave address and host command registers are sent. in the receive byte command, the tran smit slave address register is sen t. the received data is stored in the host data 0 register. software must force the i2c_en bit in host control 2 register to 0 when this command is run. write byte/ write word in the write byte command, the transmit slave addre ss register, host command register, and host data 0 registers are sent. in the write word command, the transmit slave addre ss register, host command r egister, host data 0, and host data 1 registers are sent. in these commands, software must force the i2c_ en bit in host control 2 register to 0. read byte/ read word in the read byte command, the transmit slave addre ss register and host command register are sent. data is received into the host data 0 register. in the read word command, the transmit slave addres s register and host command register are sent. the returned 2 bytes of data are received into the ho st data 0 register and host data 1 register. in these commands, software must force the i2c_ en bit in host control 2 register to 0. process call in the process call command, the tr ansmit slave address register, ho st command register, host data 0 register, and host data1 registers are sent. the return ed 2 bytes of data are receiv ed into the host data 0 register and host data 1 register. when the i2c_en bit in host control 2 register is set to 1, the host command register will not be sent. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 192 it8511 e /te/ g note: the process call command with i2c_en bit set and the pec_en bit set produce undefined results. block write/ block read in the block write command, the transmit slave addres s register, host command register, and host data 0 (byte count) register are sent. data is then se nt from the host block data byte register. in the block read commands, the transmit slave addr ess register, and host command register are sent. the first byte (byte count) received is stored in the ho st data 0 register, and the re maining bytes are stored in the host block data byte register. the byte done status bit in the host status register will be set 1 when t he master has received a byte (for block read commands) or if it has completed tran smission of a byte (for block write commands). note: on the block read command, software shall write 1 to last byte bit in host control register when the next byte will be the last byte to be received. i2c block read this command allows the smbus logic to perform bl ock reads to i2c devices in a 10-bit addressing mode. in i2c block read command, the transmit slave addr ess register, host command register, host data 0 register, and host data 1 register are sent. bit 0 of the transmit slave address register must be 0. the received data is stored in the ho st block data byte register. 7.7.3.2 smbus porting guide (1).smbus master interface: the smbus controller requires that various data and co mmand registers be setup for the message to be sent. when the start bit in the host control register is set, the smbus controller will perform the requested transaction. any register values needed for computat ion purposes should be saved prior to issuing of a new command. the ?timing registers?(22h~28h) should be programm ed before the transaction starts. besides the 25ms register, all of the other count numbers are based on ec clock. for example, write 28h (40 / freqec ~= 4.0 s) into the 4.0 s register. (freqec is listed in table 10-1 on page 297 and this example has assumed freqec = 10 mhz.) the it8511 smbus interface can perform smbus messages with either packet error checking (pec) enabled or disabled (pec_en bit =1 or 0 in host control registe r). the actual pec calculation and checking is performed in software. here is the steps the software shall follow to program the registers for various command. 1. quick command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in quick command, the transmit slave address register is sent (software shall write data to the transmit slave address register). (3). start the transaction (write 41h to the host c ontrol register, which will se lect the ?quick command?, enable the interrupts, and start the transaction). (4). when the data transmission was completed, an interrupt is generated. software c an read the host status register to know the source of the interrupt. note: after reading the status register, the software must write 1 to clear it. 2. send byte command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 193 ec domain functions (2). in send byte command, the transmit slave addr ess register and host command register are sent (software shall write data to the transmit slave addr ess register and host command register). bit 0 of the transmit slave addres s register must be 0. (3). start the transaction ( write 45h to the host cont rol register, which will sele ct the ?send byte/receive byte command?, enable the interrupts, and start the transaction). (4). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. 3. receive byte command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in receive byte command, the tr ansmit slave address register is se nt (software shall write data to the transmit slave address register). bit 0 of t he transmit slave address register must be 1. (3). start the transaction ( write 45h to the host cont rol register, which will sele ct the ?send byte/receive byte command?, enable the interrupts, and start the transaction). (4). when the data transmission was completed, an in terrupt was generated. software can read the host status register to know the source of the interrupt. (5). in receive byte command, the received data is stored in the host data 0 register. software can read this register to get the data. 4. write byte command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in write byte command, the transmit slave a ddress register, host command register, and host data 0 register are sent (software shall write data to th ese registers). bit 0 of t he transmit slave address register must be 0. if the packet error checking(pec) is enabled , software shall write the pec value to the packet error check register and this re gister will be sent, too. (3). start the transaction (write 49 h to the host control register, which will select the ?write byte/read byte command?, enable the interrupts, and start the transaction). (4). when the data transmission was completed, an in terrupt was generated. software can read the host status register to know the source of the interrupt. 5. write word command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in write word command, the transmit slave a ddress register, host comm and register, host data 0 register, and host data 1 register are sent (softwar e shall write data to these registers). bit 0 of the transmit slave address register must be 0. if the packet error checking (pec) is enabled, softwar e shall write the pec value to the packet error check register. and this register will be sent, too. (3). start the transaction (write 4dh to the host control register, which w ill select the ?write word/read word command?, enable the interrupts, and start the transaction). (4). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. 6. read byte command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in read byte command, the transmit slave a ddress register and host command register are sent (software shall write data to these registers). bit 0 of the transmit slave addr ess register must be 1. (3). start the transaction (write 49 h to the host control register, which will select the ?write byte/read byte free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 194 it8511 e /te/ g command?, enable the interrupts, and start the transaction). (4). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. (5). in read byte command, the data re ceived is stored in the host data 0 register. software can read this register to get the data. if the packet error checking (pec) is enabled, softw are can read the pec value from the packet error check register. 7. read word command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in read word command, the transmit slave a ddress register and host co mmand register are sent (software shall write data to these registers). the bit 0 of the transmit slave a ddress register must be 1. (3). start the transaction (write 4dh to the host control register, which w ill select the ?write word/read word command?, enable the interrupts, and start the transaction). (4). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. (5). in read word command, the received data is stor ed in the host data 0 register and host data 1 register. software can read t hese registers to get the data. if the packet error checking(pec) is enabled, so ftware can read the pec val ue from the packet error check register. 8. process call command (1). enable the smbus host controller (smbus host enable bit in host control register 2 is set to 1). (2). set the i2c_en bit (in host control register 2) to 1 or force it to 0. when the i2c_en bit is set, the smbus logic will instead be set to communicate with i2c device. the process call command will skip the command code. (3). in process call command, the transmit slave addr ess register, host command register (if i2c_en = 0), host data 0 register, and host data 1 register ar e sent (software shall write data to these registers). bit 0 of the transmit slave address register must be 0. (4). start the transaction (write 51h to the host c ontrol register, which will select the ?process call command?, enable the interrupts, and start the transaction). (5). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. (6). in process call command, the received data is stor ed in the host data 0 register and host data 1 register. software can read thes e registers to get the data. if the packet error checking (pec) is enabled, so ftware can read the pec val ue from the packet error check register. note: the i2c_en bit and pec_en bit can?t be set high at the same time. it will produce the undefined results. 9. block write command (1). enable the smbus host controller (smbus host enable bit in host control register 2 is set to 1). (2). set the i2c_en bit (in host control register 2) to 1 or force it to 0. when the i2c_en bit is set, the smbus logic will instead be set to communicate with i2c device. the block write command will skip sending the byte count (host data 0 register). (3). in block write command, the transmit slave a ddress register, host command register, and host data 0 register (byte count, if i2c_en = 0) are sent (softw are shall write data to these registers). bit 0 of the transmit slave address register must be 0. the dat a is then sent from the host block data byte register (software shall write data to this register). (4). start the transaction (w rite 55h to the host contro l register, which will select the ?block read/block write command?, enable the interrupts, and start the transaction). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 195 ec domain functions (5). when the data in host block data byte register is sent, an interrupt will be generated. software can read the host status register to know the source of the interr upt (byte done status is 1). (6). software writes the data to the ho st block data byte register, then the data is sent from this register by smbus logic. (7). repeat step (5) and (6) for the other dat a byte until all of the data were sent. if the packet error checking(pec) is enabled, softwar e shall write the pec value to the packet error check register and this re gister will be sent, too. (8). when the data transmission is completed, an in terrupt will be generated. so ftware can read the host status register to know the source of the interrupt. note: the i2c_en bit and pec_en bit can?t be set high at the same time. it will produce the undefined results. 10. block read command (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in block read command, the transmit slave a ddress register and host co mmand register are sent (software shall write data to these registers). bit 0 of the transmit slave addr ess register must be 1. (3). start the transaction (w rite 55h to the host contro l register, which will select the ?block read/block write command?, enable the interrupts, and start the transaction). (4). when the byte count and the fi rst byte data are received, an interrupt will be gener ated. software can read the host status register to know the source of the interr upt (byte done status is 1). (5). software read the data from the host data 0 regi ster to get the byte count, and read the data from the host block data byte register to get the first data byte. (6). when the next data is received, an interrupt will be generated. software can read the host status register to know the source of t he interrupt (byte done status is 1). (7). software read the data from the host bl ock data byte register to get the data. (8). repeat step (6) and (7) until the last byte. (9). set the last byte bit in the host control register to indicate that the next byte will be the last byte to be received. (10). get an interrupt and receive the last byte. if the packet error checking (pec) is enabled, softw are can read the pec value from the packet error check register. 11. i2c block read command this command allows the smbus logic to perform blo ck reads to i2c devices in a 10-bit addressing mode. (1). enable the smbus host controller (smbus host e nable bit in host control register 2 is set to 1). i2c_en bit must be 0 in this command. (2). in i2c block read command, the transmit slave a ddress register, host command register, host data 0 register, and host data 1 register are sent (softw are shall write data to these registers). bit 0 of the transmit slave address register must be 0. (3). start the transaction (write 5 9h to the host control register, whic h will select the ?i2c block read command?, enable the interrupts, and start the transaction). (4). when the data is received, an interrupt will be gener ated. software can read the host status register to know the source of the interrupt (byte done status is 1). (5). software can read the data from the host block data byte register to get the data. (6). repeat step (4) and (5) until the last byte. (7). set the last byte bit in the host control register to indicate that the next byte will be the last byte to be received. (8). get an interrupt and receive the last byte. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 196 it8511 e /te/ g 7.7.4 ec interface registers the smbus i/o registers are listed below. the base address for smbus is 1c00h. a and b are for channel a and b respectively. table 7-15. ec view register map, smbus 7 0 offset host status (hosta)(a,b) 00h,11h host control (hoctl)(a,b) 01h,12h host command (hocmd)(a,b) 02h,13h transmit slave address (trasla)(a,b) 03h,14h host data 0 (d0reg)(a,b) 04h,15h host data 1 (d1reg)(a,b) 05h,16h host block data byte (hobdb)(a,b) 06h,17h packet error check (pecerc)(a,b) 07h,18h smbus pin control (smbpctl)(a,b) 0ah,1bh host control2 (hoctl2)(a,b) 10h,21h 4.7 s low register (4p7usl) 22h 4.0 s high register (4p0ush) 23h 300 ns register (300ns) 24h 250 ns register (250ns) 25h 25 ms register (25ms) 26h 45.3 s low register (45p3usl) 27h 45.3 s high register (45p3ush) 28h 4.7 s and 4.0 s high register (4p7a4p0h) 33h 7.7.4.1 host status register (hosta) all status bits are set by hardware and cleared by writing a one to the parti cular bit position by the software. software can read this register to know the source of the interrupt (master interface). address offset: channel a: 00h channel b: 11h bit r/w default description 7 r/wc 00h byte done status (bds) this bit will be set 1 when the host co ntroller has received a byte (for block read commands) or if it has complete d the transmission of a byte (for block write commands). 6-5 - 00h reserved 4 r/wc 00h failed (fail) 0: this bit is cleared by writing a 1 to the bit position. 1: this bit is set when kill is set. 3 r/wc 00h bus error (bser) 0: this bit is cleared by writing a 1 to the bit position. 1: the source of the interrupt is t hat the smbus has lost arbitration. 2 r/wc 00h device error (dver) 0: this bit is cleared by writing a 1 to this bit?s position. 1: this bit is set in one of the following conditions: (1)illegal command field. (2)25ms time-out error. (3)not response ack. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 197 ec domain functions bit r/w default description 1 r/wc 00h finish interrupt (fintr) this bit will be set by termination of a command. 0: this bit is cleared by writing 1 to this position. 1: the source of the interrupt is the stop condition detected. 0 r 00h host busy (hoby) 0: this bit is cleared when the cu rrent transaction is completed. 1: this bit is set while the command is in operation. 7.7.4.2 host control register (hoctl) address offset: channel a: 01h channel b: 12h bit r/w default description 7 r/w 00h pec enable (pec_en) 0: the transaction without the pec (packet error checking) phase appended 1: the transaction with the pec phase appended. 6 w 00h start (srt) 0: this bit will always return 0 on reads. 1: when this bit is set, the smbu s host controller will perform the requested transaction. 5 w 00h last byte (laby) this bit is used for block read command. 0: this bit will always return 0 on reads. 1: software shall write 1 to this bit wh en the next byte will be the last byte to be received for the block read command. 4-2 r/w 00h smbus command (smcd) these bits indicate which command will be performed. bit 0 of the transmit slave address register deter mines if this is a read or write command. 000:quick command 001:send byte/ receive byte 010:write byte/ read byte 011:write word/ read word 100:process call 101:block read/ block write 110:i2c block read 111:reserved 1 r/w 00h kill (kill) 0: normal smbus host controller functionality. 1: when this bit is set, kill the current host transaction. this bit, once set, must be cleared by software to allow the smbus host controller to function normally. 0 r/w 00h host interrupt enable (intren) 0: disable. 1: enable the generation of an inte rrupt for the master interface free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 198 it8511 e /te/ g 7.7.4.3 host command register (hocmd) address offset: channel a: 02h channel b: 13h bit r/w default description 7-0 r/w 00h host command register (hcreg) these bits are transmitted in the command field of the smbus protocol. 7.7.4.4 transmit slave address register (trasla) address offset: channel a: 03h channel b: 14h bit r/w default description 7-1 r/w 00h address (adr) address of the targeted slave. 0 r/w 00h direction (dir) direction of the host transfer. 0: write 1: read 7.7.4.5 data 0 register (d0reg) address offset: channel a: 04h channel b: 15h bit r/w default description 7-0 r/w 00h data 0 (d0) these bits contain the data sent in the data0 field of the smbus protocol. for block write commands, this register reflects the number (from 1 to 32) of bytes to transfer. 7.7.4.6 data 1 register (d1reg) address offset: channel a: 05h channel b: 16h bit r/w default description 7-0 r/w 00h data 1 (d1) these bits contain the data sent in the data1 field of the smbus protocol. 7.7.4.7 host block data byte register (hobdb) address offset: channel a: 06h channel b: 17h bit r/w default description 7-0 r/w 00h block data (bldt) for a block write command, data is sent from this register. on block read command, the received data is stored in this register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 199 ec domain functions 7.7.4.8 packet error check register (pecerc) address offset: channel a: 07h channel b: 18h bit r/w default description 7-0 r/w 00h pec data (pecd) these bits are written with the 8-bit crc value that is used as the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this re gister and is then read by software. 7.7.4.9 smbus pin control register (smbpctl) address offset: channel a: 0ah channel b: 1bh bit r/w default description 7-3 - 00h reserved 2 r/w 1b smclk control (smbc) 0: smclk0/1/2 pin will be driven low regardless of what the other smb logic will be. 1: the smclk0/1/2 pin will not be driven low. the other smbus logic controls this pin. 1 r - smdat current state (smbdcs) this bit returns the value of the smdat0/1/2 pin. 0: low 1: high 0 r - smclk current state (smbcs) this bit returns the value of the smclk0/1/2 pin. 0: low 1: high 7.7.4.10 host control register 2 (hoctl2) address offset: channel a: 10h channel b: 21h bit r/w default description 7-2 - 00h reserved 1 r/w 00h i2c enable (i2c_en) 0: sm bus behavior. 1: enable to communicate with i2c device. when this bit is set, the smbus logic will instead be set to communicate with i2c devices. this forces the following changes: (1) the process call command will skip the command code. (2) the block write command will skip sending the byte count. 0 r/w 00h smbus host enable (smhen) 0: disable the smbus host controller. 1: the smb host interface is enabled to execute commands. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 200 it8511 e /te/ g 7.7.4.11 4.7 s low register (4p7usl) the following registers (22h-28h,33h) define the smclk0/1/2 and smdat0/1/2 timing. address offset: 22h bit r/w default description 7-0 r/w 00h 4.7 s low register (4p7usl) this 4.7 s low register and 4.7 s high bit (in the 4.7 s and 4.0 s high register) define the count number for the 4.7 s counter. the 4.7 s is (count number / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.12 4.0 s low register (4p0usl) address offset: 23h bit r/w default description 7-0 r/w 00h 4.0 s low register (4p0usl) this 4.0 s low register and 4.0 s high bit (in the 4.7 s and 4.0 s high register) define the count number for the 4.0 s counter. 4.0 s is (count number / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.13 300 ns register (300nsreg) address offset: 24h bit r/w default description 7-0 r/w 00h 300ns register (300ns) this field defines the smdat0/1/2 hold time. this byte is the count number of the counter for 300 ns. the 300 ns is calculated by (count number / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.14 250 ns register (250nsreg) address offset: 25h bit r/w default description 7-0 r/w 00h 250ns register (250ns) this field defines the smdat0/1/2 setup time. this byte is the count number of the counter for 250 ns. the 250 ns is calculated by (count number / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.15 25 ms register (25msreg) address offset: 26h bit r/w default description 7-0 r/w 00h 25 ms register (25ms) this field defines the smclk0/1/2 clock low timeout. this byte is the count number of the counter for 25 ms. the 25 ms is calculated by (count number *1.024 khz). free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 201 ec domain functions 7.7.4.16 45.3 s low register (45p3uslreg) address offset: 27h bit r/w default description 7-0 r/w 00h 45.3 s low register (45p3uslow) this 45.3 s low register, 45.3 s high register, 4.7 s low register and 4.7 s high bit (in the 4.7 s and 4.0 s high register) define the smclk0/1/2 high periodic (maximal). (45.3 s + 4.7 s=50 s) this byte is the count number bits [7:0] of the counter for 45.3 s. the 45.3 s is calculated by (count number[15:0] / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.17 45.3 s high register (45p3ushreg) address offset: 28h bit r/w default description 7-0 r/w 00h 45.3 s high register (45p3ushgh) this 45.3 s low register, 45.3 s high register, 4.7 s low register and 4.7 s high bit (in the 4.7 s and 4.0 s high register) define the smclk0/1/2 high periodic (maximal). (45.3 s + 4.7 s=50 s). this byte is the count number bits [15:8] of the counter for 45.3 s. the 45.3 s is calculated by (count number[15:0] / freqec). (freqec is listed in table 10-1 on page 297) 7.7.4.18 4.7 s and 4.0 s high register (4p7a4p0h) address offset: 33h bit r/w default description 7-2 - - reserved 1 r/w 00h 4.0 s high bit (4p0ush) this bit is bit 8 of the count number for the 4.0 s counter. this 4.0 s low register and 4.0 s high bit define the count number for the 4.0 s counter. 0 r/w 00h 4.7 s high bit (4p7ush) this bit is bit 8 of the count number for the 4.7 s counter. this 4.7 s low register and 4.7 s high bit define the count number for the 4.7 s counter. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 202 it8511 e /te/ g 7.8 ps/2 interface 7.8.1 overview the ps/2 device uses a two-wire bi-directional interface for data transmission. the device consists of four identical channels. each of the four channels provides two signals (clk and data line) to communicate with the auxiliary device. th e ps/2 interface also connects the clk line and data line to the wuc (wu10-wu17) to wake-up the 8032 when these lines are toggled. clk line and data line are the same as ps2clkn and ps2datn (n=0,1 or 2) pins. refer to table 5-5 on page 18 for the details. 7.8.2 features ? supports four ps/2 channels. ? supports hardware/software mode selection. ? three interrupt features are available: start in terrupt, transaction done interrupt, and software mode interrupt (int16, int18, int19 and int20). 7.8.3 functional description the ps/2 interface has two operation methods: hardware mode and software mode. when the hardware mode is enabled, the ps/2 interface can perform automatic re ception or transmission depending on the trms bit in the psctl register. when the hardware mode is disabled (software mode is enabled), the ps/2 clk line and data line are controlled by the firmware via the cclk bit and cdat bit in the psctl register. the following sections will describe how to use the ps/2 interface. 7.8.3.1 hardware mode selected receive mode: here are the steps the host shall follo w to receive data from a ps/2 device. 1. enable the hardware mode, select the receive mo de, and release the clk line and data line (write 07h to the ps/2 control register). 2. enable the interrupts. (tdie bit in ps/2 interrupt control register must be se t to 1 because when the data transmission is completed, the data in ps/2 data register needs to be read.) after these steps, the ps/2 interface is ready to rece ive data. when the data transm ission is completed, an interrupt signal is set high (transaction done interrupt). the status (transaction done status) can be read from ps/2 status register and the received data can be read from the ps/2 data register. the ps/2 clk line will be held low until the ps/2 data register is read. transmit mode: here are the steps the host shall fo llow to send data to a ps/2 device. 1. enable the hardware mode, select the transmit mode, and pull the clk line low and data line high (write 0dh to the ps/2 control register). 2. enable the interrupts. (tdie bit in ps/2 interrupt control register must be se t to 1 because when the data transmission is completed, the data in ps/2 status register needs to be read.) 3. write the data to be transmi tted to the ps/2 data register. 4. pull the data line low (write 0c h to the ps/2 control register). 5. pull the clk line high (write 0e h to the ps/2 control register). after these steps, the ps/2 interface is ready to transmit data. when the data transmission is completed, an interrupt signal is set high (transaction done interrupt). the status (transaction done status) can be read from ps/2 status register. the clk line will be held lo w until the ps/2 status register is read. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 203 ec domain functions input signal debounce this ps/2 interface performs a debounce operation on the clk input signal before determining its logical value. when this operation is enabled (dcen bit in the ps/2 cont rol register is set to 1), the clk input signal must be stable for at least 4 clock cycles. 7.8.3.2 software mode selected software control ps/2 clk line and data line when the software mode is selected (pshe=0 in ps/2 control register), the software can control the ps/2 clk line and data line. the cclk bit and cdat bit in the ps/2 control register control the clk line and data line. when one of these bits is cleared, the relevant pin is held low. when one of these bits is set, the relevant pin is pulled high. software control the interrupt when the ps/2 hardware enable bit is cleared (psh e=0 in ps/2 control register) and the software mode interrupt enable bit is set (smie=1 in ps/2 interrupt control register), the so ftware can control the ps/2 interrupt. the interrupt is set high when the cclk bit in ps/ 2 control register is set high. if such an interrupt is not desired, clear the software mode interrupt enable bit (smie=0 in ps/2 interrupt control register). 7.8.4 ec interface registers the ps/2 interface registers are listed belo w. the base address for ps/2 is 1700h. table 7-16. ec view register map, ps/2 7 0 offset ps/2 control register 1 (psctl1) 00h ps/2 control register 2 (psctl2) 01h ps/2 control register 3 (psctl3) 02h ps/2 control register 4 (psctl4) 03h ps/2 interrupt control register 1 (psint1) 04h ps/2 interrupt control register 2 (psint2) 05h ps/2 interrupt control register 3 (psint3) 06h ps/2 interrupt control register 4 (psint4) 07h ps/2 status register 1 (pssts1) 08h ps/2 status register 2 (pssts2) 09h ps/2 status register 3 (pssts3) 0ah ps/2 status register 4 (pssts4) 0bh ps/2 data register 1 (psdat1) 0ch ps/2 data register 2 (psdat2) 0dh ps/2 data register 3 (psdat3) 0eh ps/2 data register 4 (psdat4) 0fh 7.8.4.1 ps/2 control register 1-4 (psctl1-4) this register controls the operation of the ps/2 inte rface. ps/2 control register 1-4 are for channel 1-4 respectively. address offset: 00h~03h bit r/w default description 7-5 - 000b reserved 4 r/w 0b debounce circuit enable (dcen) 0: the debounce circuit is disabled. 1: the debounce circuit is enabled. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 204 it8511 e /te/ g bit r/w default description 3 r/w 0b transmit / receive mode selection (trms) 0: receive mode is selected. 1: transmit mode is selected. 2 r/w 0b ps/2 hardware enable (pshe) when this bit is set to 1, the ps/2 channel can perform automatic reception or transmission. when this bit is 0, the channel?s clk and data lines are controlled by the cclk and cdat bits in this register. 0: ps/2 hardware mode is disabled (software mode is enabled). 1: ps/2 hardware mode is enabled. 1 r/w 0b control clk line (cclk) this bit can control the clk line. 0: the clk line is held low. 1: the clk line is pulled high. 0 r/w 1b control data line (cdat) this bit can control the data line. 0: the data line is held low. 1: the data line is pulled high. 7.8.4.2 ps/2 interrupt control register 1-4 (psint1-4) this register enables or disables various interrupts sour ces. ps/2 interrupt control register 1-4 are for channel 1-4 respectively. address offset: 04h~07h bit r/w default description 7-3 - 00000b reserved 2 r/w 0b transaction done interrupt enable (tdie) enable or disable the interrupt gene ration when the transaction done status occurs. 0: disable the interrupt. 1: enable the interrupt. 1 r/w 0b start interrupt enable (sie) enable or disable the interrupt generation when the start status occurs. 0: disable the interrupt. 1: enable the interrupt. 0 r/w 0b software mode interrupt enable (smie) enable or disable the interrupt generation when the ps/2 hardware is disabled. the cclk bit in psctl regist er can control the interrupt output when this bit is set to 1 and ps/2 hardware is disabled. 0: disable the interrupt. 1: enable the interrupt. 7.8.4.3 ps/2 status re gister 1-4 (pssts1-4) this register contains the status information on the data transfer on the ps/2. status register 1-4 are for channel 1-4 respectively. address offset: 08h~0bh bit r/w default description 7-6 - 00b reserved 5 r 0b frame error (fer) this bit is 1 when the stop bit in a received frame was detected low. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 205 ec domain functions bit r/w default description 4 r 0b parity error (per) this bit is 1 when a parity error condition occurs. 3 r 0b transaction done status (tds) this bit is 1 when a ps/2 data transfer was done. 2 r 0b start status (ss) this bit is 1 when a start bit was detected. 1 r - clk line status (cls) reading this bit returns the current status of the ps/2 clk line. 0 r - data line status (dls) reading this bit returns the current status of the ps/2 data line. 7.8.4.4 ps/2 data register 1-4 (psdat1-4) in receive mode, this register holds the data received fr om the ps/2 device. in transmit mode, the data in this register is transmitted to the ps/2 device. data register 1-4 are for channel 1-4 respectively. address offset: 0ch~0fh bit r/w default description 7-0 r/w 00h data (dat) holds the data received from the ps/2 device in the receive mode or the data which will be transmitted in the transmit mode. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 206 it8511 e /te/ g 7.9 digital to analog converter (dac) 7.9.1 overview the dac interface is used as a communication inte rface between the embedded controller and dac. 7.9.2 feature ? supports 4-channel d/a converter ? 8-bit resolution ? independent enable signals for each channel ? power-down function 7.9.3 functional description the dac interface has four channels. each channel generates an output in the range of 0v to avcc with eight-bit resolution. when a dac channel is enabled, it s output is defined by the value written to its dacdat register. dacdat 0-3 control channel 0-3 respectively . the 0v output is obtained for a value of 00h in the dacdat register. the avcc output is obtained for a va lue of ffh in the dacdat register. in power-down mode (powdn=1 in dacctrl regi ster), the dac output is 0v. dac analog circuit has less power consumption if it is power-down. powdn bit in da cctrl register controls this and it?s cleared when ec domain reset. the firmware should clear powdn bit before entering idle/doze/sleep mode. 7.9.4 ec interface registers the dac interface registers are listed belo w. the base address for dac is 1a00h. table 7-17. ec view register map, dac 7 0 offset dac control (dacctrl) 00h dac data channel 0 (dacdat0) 01h dac data channel 1 (dacdat1) 02h dac data channel 2 (dacdat2) 03h dac data channel 3 (dacdat3) 04h dac power down register (dacpdreg) 05h 7.9.4.1 dac control register (dacctrl) this register controls the operation of the dac module. address offset: 00h bit r/w default description 7-5 - 0h reserved 4 r/w 1b power down (powdn) 0: the dac is not power-down. 1: the dac is power-down. 3 r/w 0h dac channel 3 enable (dacen3) this bit is used to enable the dac channel 3. 0: disable 1: enable free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 207 ec domain functions bit r/w default description 2 r/w 0h dac channel 2 enable (dacen2) this bit is used to enable the dac channel 2. 0: disable 1: enable 1 r/w 0h dac channel 1 enable (dacen1) this bit is used to enable the dac channel 1. 0: disable 1: enable 0 r/w 0h dac channel 0 enable (dacen0) this bit is used to enable the dac channel 0. 0: disable 1: enable 7.9.4.2 dac data channel 0~3 register (dacdat0~3) the data in these registers will be loaded into channel 0~3. address offset:channel 0: 01h channel 1: 02h channel 2: 03h channel 3: 04h bit r/w default description 7-0 r/w - dac data register (dacdat) 8 bit data will be loaded to the dac for d/a operation. 7.9.4.3 dac power down register (dacpdreg) when the bit in this register is set, the respective dac channels will be power-down. address offset: 05h bit r/w default description 7-4 - - reserved 3 r/w 1b dac channel 3 power down (powdn3) 0: the dac channel 3 is not power-down. 1: the dac channel 3 is power-down. 2 r/w 1b dac channel 2 power down (powdn2) 0: the dac channel 2 is not power-down. 1: the dac channel 2 is power-down. 1 r/w 1b dac channel 1 power down (powdn1) 0: the dac channel 1 is not power-down. 1: the dac channel 1 is power-down. 0 r/w 1b dac channel 0 power down (powdn0) 0: the dac channel 0 is not power-down. 1: the dac channel 0 is power-down. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 208 it8511 e /te/ g 7.10 analog to digital converter (adc) 7.10.1 overview the adc(analog to digital converter) provides an accura te method for measuring slow changing voltages. the module can measure the channel up to f ourteen-voltage with 10-bit resolution. 7.10.2 features ? supports 10-bit resolution after software calibration and 0 to 3v input voltage range ? supports an digital low pass filter for spike smoothing ? supports four-voltage buffer ? supports fast ad conversion of 16 channels within 100 ms ? supports programmable conversion-start delay to guarantee input setting time ? polling or interrupt-driven interface 7.10.3 functional description figure 7-19. adc channels control diagram adc1 adc2 adc3 adc4 adc5 adc6 adc7 vcc vstby avcc vbs adc0 0 1 2 3 4 5 6 7 10 11 12 13 m u x 14 : 1 volt c h0,1,2,3 adc tim ing control ec bus analog input 2 2 2 adc7 adc7 9 8 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 209 ec domain functions 7.10.3.1 adc general description inputs the adc has 14 inputs (adc0-9, adc10~13) divided into two groups described as the following: ? external voltage (adc0-9): these are for dc voltage sources. ? internal voltage (adc10-13): these are connected to the internal supply vo ltages of the device (vcc, vstby avcc and vbat). the input voltages of adc10-12 are divided by 2 before being input to analog multiplexer while adc13 is not divided by 2. a/d converter the sigma-delta high-resolution a/d converter receives the selected input with a 16 to 1 analog multiplier and converts it. the result of the conversion is 14-bit si gned integer (2's complement) and it is a 10-bit, unsigned integer for voltage inputs after software calibration process. for the software calibration flow, refer to section 7.10.5 adc programming guide. adc cycle the adc has four output buffers: these are for the voltage channel. the buffer for voltage measurement channels holds the current data until the next same volt channel measurement is completed after one adc cycle is finished. an adc cycle includes measurements of all four channels. the first measurement is a voltage channel 0 and followed by voltage channel 1, 2, 3. afte r an a/d conversion is comple ted for a certain channel, its relative bit of the data valid (datval bit in v ch0ctl, vch1ctl, vch2ctl and vch3ctl register) flag is set that represents the channel of data is available and ec can read out. channel conversion time if channel delay uses a default value, which means voldly is delayed 256 k units, sclkdiv factor in adcctl register is also set by default, and dfilen is set to 1, the one channel conversion time is about 3.6msec. if dfilen is set to 0, the one channel conversion time is about 780usec. interrupt to intc adc interrupt (int8) will be active if end-of-cycle, voltage channel 0 data valid, voltage channel 1 data valid, voltage channel 2 data valid or voltage channel 3 data valid is true. see also intecen, intdven0, intdven1, intdven2 and intdven3. 7.10.3.2 voltage measurement and automatic hardware calibration the adc converts the un-calibrated input voltage signal into a 14-bit singed integer (2's complement) in data buffer vchdiatl and vchdiatm when ahce(automatic ha rdware calibration enable) is cleared(default), and converted into a 10-bit unsigned integer in data buffer vchdiatl and vchdiatm when ahce(automatic hardware calibration enable) is set. the automatic har dware calibration is used for the alternative of the software calibration flow. the input signal should be applied relative to the agnd pin and should range from 0v to 3v. the following should explain the input voltage based on the reading from the voltage/channel data result (vchidatl field in vchidatm register for voltage). example (refer to the bottom of figure 7-20 on page 220 for the details: the un-calibrated input data is 14-bit singed in teger (2's complement) in data buffer vchidatx. an input signal equal to 3.0v is about 0fffh. an input signal equal to 1.5v is about 0000h. an input signal equal to 0.0v is about 3000h. after software calibration flow, it is a 10-bit unsigned integer: 3.0v (about 0fffh) is calibrated as 3ffh. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 210 it8511 e /te/ g 1.5v (about 0000h) is calibrated as 200h. 0.0v (about 3000h) is calibrated as 000h. changing the input selection for a new measurement channel (voltage), the software needs to set a delay time to prevent the result of an unint ended adc operation. the adc waits fo r a programmable delay time between the selection of the input to be measured and the beginning of the a/d conversion. 7.10.3.3 adc operation reset the adc is disabled, and all interrupt is masked and a ll event status bits reset. the selected input for all four-voltage channels is disabled (bit4-0 of the vchictl register is set to fh). adc clock the adc clock is generated by dividing the ec clock by a factor defined in sclkdiv in aclkctl register. the adc clock must be at a frequency of 0.5 mhz. sc lkdiv must be programmed before enabling the adc. initializing the adc the adc must be initialized before adc is enabled (adcen in the adccfg register is set to 1). the followings need to be done before the adc is enabled. 1. set ainitb@adcsts = 1 then clear it (only once after vstby power on) 2. adcen bit in adccnf register is cleared. 3. programming (sclkdiv factor in adcctl register). 4. voltage channel delay. 5. channel select in vchictl register 6. hardware voltage calibration information g and o needs to be done by setting calibration active via kdctl register. enabling the adc after the adc is enabled, the voltage channel is measured as long as the adcen is set 1 and when the voltage channel is selected. the measurement operat ions may be enabled or disabled individually. disabling the adc adc analog circuit has less power consumption if it is di sabled. adcen bit in adccfg register controls this and it?s cleared at ec domain reset. the firmware should clear adcen bit before entering idle/doze/sleep mode. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 211 ec domain functions 7.10.4 ec interface registers the adc control/status and data out r egisters set interfaces with the ec through the ec dedicated bus. these registers are mapped in the address space of the ec. t he registers are listed below and the base address is 1900h. table 7-18. ec view register map, adc 7 0 offset adc status (adcsts) 00h adc configuration (adccfg) 01h adc clock control (adcctl) 02h voltage channel 0 channel control (vch0ctl) 04h calibration data control register (kdctl) 05h voltage channel 1 control (vch1ctl) 06h voltage channel 1 data buffer lsb (vch1datl) 07h voltage channel 1 data buffer msb (vch1datm) 08h voltage channel 2 control (vch2ctl) 09h voltage channel 2 data buffer lsb (vch2datl) 0ah voltage channel 2 data buffer msb (vch2datm) 0bh voltage channel 3 control (vch3ctl) 0ch voltage channel 3 data buffer lsb (vch3datl) 0dh voltage channel 3 data buffer msb (vch3datm) 0eh voltage high scale calibration data buffer lsb (vhscdbl) 14h voltage high scale calibration data buffer msb (vhscdbm) 15h voltage channel 0 data buffer lsb (vch0datl) 18h voltage channel 0 data buffer msb (vch0datm) 19h voltage high scale gain-error calibration data buffer lsb (vhsgcdbl) 1ch voltage high scale gain-error calibration data buffer msb (vhsgcdbm) 1dh for a summary of the abbreviations used for register type, see ?register abbreviations and access rules? 7.10.4.1 adc status register (adcsts) this register indicates the global status of the ad c module. adcsts is cleared (00h) on vstby power-up reset; on other resets, bit 2 is unchanged and other bits are cleared. address offset: 00h bit r/w default description 7 r/w 1b filter high accuracy (firhiacc) 0: digital filter operation at low accuracy 1: digital filter operation at high accuracy 6 - 0b reserved 5-4 r/w 00b decimation filter ratio (dfr) these bits determine the down-sampling rate to remove the quantization noise. bits 5 4 0 0: 32 others: reserved 3 r/w 0b analog accuracy initialization bit (ainitb) write 1 to this bit and write 0 to this bit immediately once and only once during the firmware initialization and do not write 1 again after initialization since it8511 takes much power consumption if this bit is set as 1. writing steps about this bit should be done before adcen bit is set in adccfg register. 1: start adc accura cy initialization. 0: stop adc accura cy initialization. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 212 it8511 e /te/ g bit r/w default description 2 r/w 0b adc power statement (adcps) this bit remains zero when adc power is in a normal state. when adc power shuts down or failure occurs, the software must program this bit to one. the program must be waited at least 20 0usec for adc internal initialization after power on. 0: indicate the adc power in a normal state. 1: indicate the adc power in a shut down or failure state. 1 r/wc 0b data overflow event (dove) measurement data from the previous cycle was overwritten with data from the current cycle before being read . in the event of a data overflow, the datval bit remains set and new data is placed in channel data buffer register. this bit is cleared by writing 1 to it; writing 0 is ignored. 0: no overflow (default) 1: overflow 0 r/wc 0b end-of-cycle event (eoce) end of adc cycle; all enabled measurements (up to four) are completed. for each of the enabled channels, the datval bit is set to 1 and the data stored in channel data buffer register respectively. 0: cycle in progress (default) 1: end of adc cycle 7.10.4.2 adc configurati on register (adccfg) this register controls the operation an d global configuration of the adc module. address offset: 01h bit r/w default description 7-6 10b reserved 5 r/w 0b digital filter enable (dfilen) enables the digital filter operation fo r spike smoothing on adc output signal. setting this bit to 1 enables the digital low pass filter to prevent unwanted signal changes based on the adc conv ersion and the smoothing data is read on the vchxdat register. when this digi tal filter is enable, the ec clock division factor (sclkdiv) must be set to a value which is larger than 15 (decimal), then digital filter will work fine. 0: disabled digital filter operation(default) 1: enabled digital filter operation on adc output signal when adcen is set 1. if adcen is cleared, this bit can be ignored. 4-3 - - reserved 2 r/w 0b interrupt from end-of-cycle event enable (intecen) enables an adc interrupt generated by end-of adc-cycle event (eocev in adcsts register). 0: disabled (default) 1: enabled interrupt by eocev event 1 r/w 0b reserved 0 r/w 0b adc module enable (adcen) controls adc operation or not 0: adc disabled (default), power-down 1: adc enabled free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 213 ec domain functions 7.10.4.3 adc clock control register (adcctl) this register controls the ec clock to adc clock division. address offset: 02h bit r/w default description 7-6 - 0h reserved 5-0 r/w 15h ec clock division factor (sclkdiv) divide the ec clock into the adc clock. the ec clock is different from the adc clock. adc clock frequency = (ec clock frequency) / (sclkdiv + 1) ec clock frequency is listed in table 10-1 on page 297. the resulting adc clock frequency should be less than 0.5 mhz when dfilen is cleared, and sclkdiv needs to be larger than 20(decimal) when dfilen is set. it is recommended to use the default sclkdiv value for a good performance. range: 4 to 63; if values 0 to 3 are set and may result in undetermined adc behavior. 7.10.4.4 voltage channel 0 control register (vch0ctl) this register both controls the operation and indicates the status of the voltage channel. address offset: 04h bit r/w default description 7 r/wc 0b data valid (datval) the vch0datx is available for reading when dataval is set. this bit is cleared when the adc module is disabled (adcen in adccfg register is cleared) or by writing 1 to it. 0: no valid data in vch0datx register (default) 1: end of conversion ? new dat a is available in vch0datx 6 r/w 0b reserved 5 r/w 0b interrupt from data valid enable (intdven) enabled to the adc interrupt generated by data valid event of voltage channel 0. 0: disabled (default) 1: enabled ? adc interrupt from local datval 4-0 r/w 11111b selected input (selin) indicates which volt channel input is selected for measurement. the channel selection must be programmed before the channel is measured. bits 43210 description 00000: channel 0 00001: channel 1 .... 01010: channel 10 .... 01101: channel 13 others: reserved 11111: channel disabled (default) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 214 it8511 e /te/ g 7.10.4.5 calibration data co ntrol register (kdctl) this register both controls the operation and indi cates the status of the calibration channel. address offset: 05h b it r/w default description 7 r/w 0b automatic hardware calibration enable(ahce) 0: disable automatic hardware calibration, and the un-calibrated data(14bits signed) is stored in vchidatx (default). 1: enable automatic hardware calibra tion, and the calibrated data(10bits unsigned) is stored in vchidatx . 6 r/wc 0b reserved 5 r/wc 0b high-scaler calibration da ta valid (hcdatval) the data may be read when this bit is set 1. this bit is cleared when the adc module is disabled (adcen in adccfg regi ster is cleared) or by writing 1 to it. if gain error calibration is selected, the va lid data is for gain error calibration; otherwise, it is for offset calibration. 0: no new valid data in volt calibration data register (default). 1: end of volt calibration ? new data is available in data buffer. 4 r/wc 0b gain_error calibration data valid (gcdatval) the data may be read when this bit is set 1. this bit is cleared when the adc module is disabled (adcen in adccfg regi ster is cleared) or by writing 1 to it. when this bit is set, the valid data is for gain error calibration. 0: no new valid data in high-scaler calibration data register (default). 1: end of high-scaler calibration ? new data is available in data buffer. 3 r/w 0b reserved 2 r/w 0b reserved 1 r/w 0b volt high scale calibration enable (vhscke) when gecke is cleared to 0, set this bit to 1 to enable the volt high scale (3volts) calibration operation for volt adc channel (ahce bit must be cleared.) to initialize one adc calibration oper ation, calibration data will be stored on voltage high scale calibration data buffer when adc calibration data has been done (datval=1), and this bit will be cleared to zero automatically. 0: disabled calibration operation(default) 1: enabled calibration operation only when gecke is cleared to 0. 0 r/w 0b gain_error calibration enable (gecke) enables the gain_error calibration oper ation for volt adc channel (ahce bit must be clear). set this bit to 1 to initialize one adc gain_error calibration operation, and calibration data will be stored on voltag e gain_error calibra tion data buffer when adc calibration data has been done(gcdatval=1), and this bit will be cleared to zero automatically. 0: disabled calibration operation(default) 1: enabled gain error calibration operation free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 215 ec domain functions 7.10.4.6 voltage channel 1 control register (vch1ctl) this register both controls the operation and indicates the status of voltage channel 1. address offset: 06h bit r/w default description 7 r/wc 0b data valid (datval) the data may be read immediately when this bit is set 1. this bit is cleared when the adc module is disabled or by writing 1 to it. 0: no valid data in vch1datx register (default) 1: end of conversion ? new data is available. 6 r/w 0b reserved 5 r/w 0b interrupt from data valid enable (intdven) enabled to the adc interrupt for data valid event of volt channel 1. 0: disabled (default) 1: enabled ? adc interrupt from local datval 4-0 r/w 11111b selected input (selin) indicates which volt channel input is selected for measurement. channel selected must be done before beginning to measure channel. bits 4 3 2 1 0 description 0 0 0 0 0: channel 0 0 0 0 0 1: channel 1 .... 0 1 0 1 0: channel 10 .... 0 1 1 0 1: channel 13 others: reserved 1 1 1 1 1: channel disabled (default) 7.10.4.7 volt channel 1 data buffer lsb (vch1datl) this register (buffer) holds the data(lsb 8bits) measured by the volt channel 1. address offset: 07h bit r/w default description 7-0 r - volt channel data (vchdat7-0) volt channel data is measured by the volt channel 1. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.8 volt channel 1 data buffer msb (vch1datm) this register (buffer) holds the data(msb 6bits) measured by the volt channel 1. address offset: 08h bit r/w default description 7-6 - reserved 5-0 r - volt channel data (vchdat13-8) volt channel data is measured by the volt channel 1. the data may be available only when datval is set. datval must be cleared after read data. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 216 it8511 e /te/ g 7.10.4.9 voltage channel 2 control register (vch2ctl) this register both controls the operation and indicates the status of voltage channel 2. address offset: 09h bit r/w default description 7 r/wc 0b data valid (datval) the same as volt channel 1. 6 r/w 0b reserved the same as volt channel 1. 5 r/w 0b interrupt from data valid enable (intdven) the same as volt channel 1. 4-0 r/w 11111b selected input (selin) the same as volt channel 1. 7.10.4.10 volt channel 2 data buffer lsb (vch2datl) this register (buffer) holds the data(lsb 8bits) measured by the volt channel 2. address offset: 0ah bit r/w default description 7-0 r - volt channel data (vchdat7-0 ) volt channel data is measured by the volt channel 2. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.11 volt channel 2 data buffer msb (vch2datm) this register (buffer) holds the data(msb 6bits) measured by the volt channel 2. address offset: 0bh bit r/w default description 7-6 - reserved 5-0 r - volt channel data (vchdat13-8) volt channel data is measured by the volt channel 2. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.12 voltage channel 3 control register (vchn3ctl) this register both controls the operation and indicates the status of voltage channel 3. address offset: 0ch bit r/w default description 7 r/wc 0b data valid (datval) the same as volt channel 1. 6 r/w 0b reserved the same as volt channel 1. 5 r/w 0b interrupt from data valid enable (intdven) the same as volt channel 1. 4-0 r/w 11111b selected input (selin) the same as volt channel 1. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 217 ec domain functions 7.10.4.13 volt channel 3 data buffer lsb (vch3datl) this register (buffer) holds the data(lsb 8bits) measured by the volt channel 3. address offset: 0dh bit r/w default description 7-0 r - volt channel data (vchdat7-0) volt channel data is measured by the volt channel 3. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.14 volt channel 3 data buffer msb (vch3datm) this register (buffer) holds the data(msb 6bits) measured by the volt channel 3. address offset: 0eh bit r/w default description 7-6 - reserved 5-0 r - volt channel data (vchdat13-8) volt channel data is measured by the volt channel 3. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.15 volt high scale calibra tion data buffer lsb (vhscdbl) this register (buffer) holds the calibration data(lsb 8bits) measured by the internal voltage channel. address offset: 14h bit r/w default description 7-0 r - volt calibration data (vckd7-0) volt calibration data is measured by the internal voltage channel. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.16 volt high scale calibra tion data buffer msb (vhscdbm) this register (buffer) holds the calibration data(msb 4bits) measured by the internal voltage channel. address offset: 15h bit r/w default description 7-6 - 00h reserved 5-0 r - volt calibration data (vckd13-8) volt calibration data is measured by the internal voltage channel. the data may be available only when datval is set. datval must be cleared after read data. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 218 it8511 e /te/ g 7.10.4.17 voltage channel 0 data buffer lsb (vch0datl) this register (buffer) holds the data (lsb 7-0) measured by the voltage channel 0. address offset: 18h bit r/w default description 7-0 r - voltage channel data (vchdat7-0) volt channel data is measured by the volt channel 0. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.18 voltage channel 0 data buffer msb (vch0datm) this register (buffer) holds the data (msb 6 bits) measured by the temperature channel. address offset: 19h bit r/w default description 7-6 - 00h reserved 5-0 r - voltage channel data (vchdat13-8) volt channel data is measured by the volt channel 0. the data may be available only when datval is set. datval must be cleared after read data. 7.10.4.19 volt high scale gain-error ca libration data buffer lsb (vhsgcdbl) this register (buffer) holds the gain-error calibration data(lsb 8bits) measured by the internal voltage channel. address offset: 1ch bit r/w default description 7-0 r - volt gain-error data (vged7-0) volt gain-error data is measured by the internal voltage channel. the data may be read only when the datval is set. 7.10.4.20 volt high scale gain-error ca libration data buffer msb (vhsgcdbm) this register (buffer) holds the gain-error calibration da ta(msb 6bits) measured by the internal voltage channel. address offset: 1dh bit r/w default description 7-4 - 00h reserved 5-0 r - volt gain-error data (vged13-8) volt gain-error data is measured by the internal voltage channel. the data may be read only when the datval is set. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 219 ec domain functions 7.10.5 adc programming guide table 7-19. detail step of adc channel conversion action step description 1 set ainitb@adcsts = 1 then clear it (only once after vstby power on) case1: ahce = 0 (hardware calibration disable, use software calibration) clear ahce@kdctl reg goto step 2 case2: ahce = 1 (hardware calibration enable) set ahce@kdctl reg , dfilen =1 go to step 9 (skip step 3 to 8) 2 enable digital filter by setting dfilen@adccfg = 1 3 set high scale offset calibration bit by setting vhscke@kdctl = 1 4 start adc conversion by setting adcen@adccfg = 1 5 waiting for hcdatval@kdctl = 1 if true, get offset data o by reading vhscdbm and vhscdbl o [13:0] = {vhscdbm[5:0], vhscdbl[7:0]} 6 start gain_error calibration by setting gecke@kdctl = 1 7 waiting for gcdatval@kdctl = 1 if true, get gain_error data g by reading vhsgcdbm and vhsgcdbl g [13:0] = {vhsgcdbm[5:0], vhsgcdbl[7:0]} determine offset and gain_error during initialization 8 disable adc to reduce power consumption by setting adcen@adccfg = 0 9 enable vchnctl for measuring desired channels; n = 0,1, 2, or 3 10 for example; to measure adc0 voltage on voltage buffer 1 set selin@vch1ctl = 0 11 start adc channel conversion by setting adcen@adccfg =1 12 waiting for datval@vch1ctl = 1 case1 : ahce =0 (disable) if true, get adc0 output data r by reading vch1datm and vch1datal r [13:0] = {vch1dtm[5 :0], vch1datl[7:0]} case1 : ahce =1 (enable) if true, get adc0 output data d by reading vch1datm and vch1datal d [9:0] = {vch1dtm[1:0 ], vch1datl[7:0]} 13 disable adc to reduce power consumption by setting adcen@adccfg = 0 adc channel conversion 14 follow to make a software calibration then go to step 8 next time. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 220 it8511 e /te/ g figure 7-20. adc software calibration flow r = uncalibrated adc output data (14-bit singed integer) it is a variable at every calibration offset calibration o = offset data (14-bit singed integer) it is a constant at every calibration gain_error calibration g = gain_error data (14-bit singed integer) it is a constant at every calibration adc channel conversion r b = uncalibrated adc output data (15-bit unsinged integer) o b = offset data (15-bit unsinged integer) g b = gain_error data (15-bit unsinged integer) d (10-bit unsigned integer) = ( g b - o b ) > 0 is guaranteed check r b range if ( r b >= g b ), overflow if ( r b <= o b ), underflow otherwise (14-bit signed integer) 1fffh 1000h 0fffh 0000h 3fffh 3000h 2fffh 2000h 5fffh 5000h 4fffh 4000h 3fffh 3000h 2fffh 2000h + 4000h (15-bit unsigned integer) (13-bit unsigned integer) (10-bit unsigned integer) 2fffh 2000h 1fffh 1000h 0fffh 0000h 2fffh 2000h 1fffh 1000h 0fffh 0000h g, o, r possible range g b , o b , r b possible range y possible range calibrated d possible range start d = 3ffh (10-bit unsigned integer) 3.0v d = 000h (10bit unsigned integer) 0.0v ( r b - o b ) ,( g b - o b ) is 14-bit range 03ffh [] r b - o b ) 14-bit * (1fffh << 13) 26-bit ( g b - o b ) 14-bit >> 16 [] r b - o b ) > 0 ( g b - o b ) > 0 ( g b - o b ) > ( r b - o b ) calculate at every calibration calculate at every calibration only calculate once during initialization discard the remainder 3.0v 0.0v 0.0v 3.0v 3.0v 3.0v 0.0v 0.0v treat 14-bit signed g, o, r as 14-bit unsigned let g b = 0ffbh + 4000h o b = o - 0012h g b , o b , r b are linear and easy for 8032 unsigned addition/subtration free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 221 ec domain functions figure 7-21. adc software calibration flow in a special case another quick way in a special case: if d is used to be compared with a threshold value, th is threshold can be calculated first to be mapped into the data space of g b , o b , r b during initialization, and the multiplication and division operation invoked to calibrate r b can be omitted. there are only one multip lication and one division to calculate r bl during initialization . [] ( g b - o b ) 14-bit * ( d << 3) 13-bit 1fffh 13-bit + o b 14-bit r bl = 15-bit 15-bit r bh = 15-bit r bl + (2 << 3 ) - 1 = r bl + 7 threshold low boundary threshold high boundary example: g b = 5020h o b = 3010h threshold voltage = 2.0v, target d = 3ffh * 2.0 / 3.0 = 2aah then r bl = final [] (5020h - 3020h)* (2aah << 3) 1fffh + 3010h = 456bh r bh = r bl + 7 calibrated adc output < 2.0v if r b < 456bh calibrated adc output > 2.0v if r b > (456bh + 7) calibrated adc output <= 2.0v if r b <= (456bh + 7) calibrated adc output > = 2.0v if r b >= 456bh then uncalibrated r b which satisfies r bl <= r b <= r bl should be mapped into calibrated d that is, normally 8 possible r b values will be mapped into calibrated d free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 222 it8511 e /te/ g 7.11 pwm and smartauto fan control (pwm) 7.11.1 overview the pwm module generates eight 8-bit pwm outputs; eac h pwm output may have a different duty cycle. the fan speed may be controlled by software or automatically controlled by the smartauto fan control module. in smartauto fan mode, the smartauto fan control logic mo nitors the temperature and automatically adjusts the pwm output for driving the fan speed. 7.11.2 features ? supports eight pwm outputs ? supports two fan tachometer inputs ? supports programmable automatic smartaut o fan control based on the temperature ? supports exchangeable pwm outpu t for smartauto fan control ? supports fan temperatur e limit configuration ? supports interrupt for temperature limit exceeded 7.11.3 functional description 7.11.3.1 general description figure 7-22. pwm & smartauto fan block group 3 group 2 group 1 pwm output stage pwm channel output ec clock ctr down counter pcfs0-3@pcsgr for corresponding group 32.768 khz pcs0-7@pcssgl/h for corresponding channel dcri (i=0~7) comparatori (i=0~7) smartautofan control 1,2 smartautofan pwm ch select f1trr, f2trr reg. tachometer measure unit 1,2 tach0/1 from pin clock prescaler group 0 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 223 ec domain functions figure 7-23. pwm clock tree div by 128 ec clock pwmtm@ztier fs tachmetor sampling clock frequency = freqec/128 ec clock 32.768 khz pcfs0@pcsgr c0cprs clock prescaler group 0 c4mcprs, c4cprs clock prescaler group 1 c7mcprs, c7cprs clock prescaler group 3 c6mcprs, c6cprs clock prescaler group 2 ec clock 32.768 khz pcfs1@pcsgr ec clock 32.768 khz pcfs2@pcsgr ec clock 32.768 khz pcfs3@pcsgr the pwm uses the 32.768 khz clock or ec clock as a reference for its pwm output. the prescaler divider values in cicrps register which divides the pwm input clock into its working clock respectively. each channel can select their prescaler divider by {pcssgh,pcssgl} register. the prescaler di vider c0crps register has 8-bit counter value; and the {cimcrps, cicrps}(i=4,6,7) has 16-bit counter value. the pwm provides eight 8-bit pwm outputs, which are pwm0 to pwm7. each pw m output is controlled by its duty cycle registers (dcri, i =0 to 7). all pwm output is cont rolled by a cycle time register (ctr). when pwm working clock is enabled, the pwm cycle output is high when the value in the dcri register is larger than the value in ctr down-counter. when the value of dcri register is not larger than the value in ctr down-counter, the pwmi cycl e output is on low and pwmi cycle out put polarity can be inversed by invpi register. when the value in ctr counter down-counter reaches 0, the value in ctr counter will be reloaded then start down-counter until the pwm work ing clock is disabled. cycle time and duty cycle the pwm module supports duty cycles ranging from 0% to 100%. the pwmi output signal cycle time is: n(cicprs + 1) x (ctr + 1) x t clk where: ? t clk is the period of pwm input clock = (1 / 32.768 khz) or (1 / freqec), which is selected by pcfs3-0 in pcsgr regiser. (freqec is listed in table 10-1 on page 297) ? the pwmi output signal duty cycle (in %, when invpi is 0) is: (dcri) / (ctr + 1) x 100. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 224 it8511 e /te/ g in the following cases, the pwmi output is hold at a state(low or high): ?pwmi output is still low when the content of dcri is larger than the ctr value. ?pwmi output is still high when the content of dcri is equal to the ctr value. ? pwmi output is still low when t he content of dcri =0 & invpi = 0 is in pwmpol register. pwm inhibit mode the pwm is in an inhibit mode when pcce in ztier regi ster is 0. in this mode, the pwm input clock is disabled (stopped). the pwmi signal is 0 when invpi bit is 0; it is 1 when invpi bit is 1. it is recommended the prsc and ctr registers should be updated in a pwm inhibit mode. 7.11.3.2 cr256 description figure 7-24. cr256 pwm block diagram pwm output stage pwm channel ouput dcr0~7 additional pulse gen. base pulse gen. cr256pcs cr256pos0 2 4 cr256pos0 additional pulse gen. cr256pos1 4 base pulse gen. cr256pos1 dcr0~7 group 3 group 2 group 1 clock prescaler group 0 cr256 operation principle the cr256 block is composed of clock pre-scaler, pulse generators, output stage. it is shown in figure 7-24 on page 224. each pulse generator is divided into the base pulse generator and additional pulse generator. there are two pulse generators for two channels of cr256. one pwm cycle of cr256 is composed of 16 base pul se cycles, which are produced by the base pulse generator and additional pulse generator. one base pulse cycle has 16 resolutions, and one resolution equals to one clock period of clock prescaler output. so , one pwm cycle of cr256 has 256(16*16) resolutions. one base pulse cycle is composed of 16 clocks of prescaler output. it is shown in table 7-20 on page 225. 7.11.3.3 how to decide cr256 duty time the duty time of cr256 is determined by the value of dc ri, which is also used by the traditional pwm channel. when dcri is assigned to cr256 pwm, the values of bits 7-4 of dcri are all represen ted by h. the values of bits 3-0 are all represented by l. the duty time of one pwm cycle is ca lculated by the following formula: duty cycle = (16*h + l) / 256 the minimum of duty cycle of cr256 is 0 as h = 0, l =0, and maximum is 255 as h=15, l=15. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 225 ec domain functions 7.11.3.4 how to program cr256 pwm for complete resolution 256 pwm output, the programmer can set cr256pos0, 1 (cr256 pwm is disabled in default.). cr256 pwm channel0 is active when cr256pos0 is se t to 0~7, and cr256 pwm channel1 is active when cr256pos1 is set to 0~7. dcri is assigned to cr256 channel0 when cr256pos0 =i, dcri is assigned to cr256 channel1 when cr256pos1 =i. cr256 uses the upper 4 bits of dc ri to generate the base pulse cycle whose duty cycle range is from 0/16 to 15/16, and uses the lower 4 bits of dcri to generate additional pulses that are added into the base pulse cycle. the additional pulse is added into the leading portion of the base pulse cycle shown in table 7-21 on page 226, and the symbol ?v? den otes that the base pulse cycle needs to be added by one additional pulse. for exam ple, if dcri of cr256 is 01h, the 15 th base pulse cycle is added by one additional pulse, and other base pulse cycles are zero and have no any additional pulse added. so, the duty cycle of cr256 pwm output is 1/256. whether one base pulse cycle is added by one additional pulse or not is showed in figure 7-25 on page 226 and cr256 pwm programming guide is showed in figure 7-29 on page 246. table 7-20. cr256 waveform dcri one base pulse cycle bit7-4 0123456789101112131415 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b one resolution free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 226 it8511 e /te/ g table 7-21. cr256 added a dditional pulse position dcri additional pulse position base pulse cycle number bit3-0 0123456789101112131415 0000b 0001b v 0010b v v 0011b v v v 0100b v v v v 0101b v v v v v 0110b v v v v v v 0111b vvvvvvv 1000b vvvvvvvv 1001b vvvvvvvvv 1010b v v vvv v v vvv 1011b v v vvv vvv vvv 1100b vvv vvv vvv vvv 1101b vvv vvv vvvvvvv 1110b vvvvvvv vvvvvvv 1111b vvvvvvvvvvvvvvv one base pulse cycle figure 7-25. cr256 base pulse vs. additional pulse no additional pulse a dditional pulse one base pulse cycle 7.11.3.5 smartauto fan control mode fan pwm channel select the ec chip provides 2 types of fan control operat ion mode using pmw output. a mode select can be set in fancnf in the fani configuration register (fanicnf). when in a smartauto fan mode, the fan will be as signed for a zone and its pwm duty cycle will be automatically adjusted according to the temperature of that zone. its pwm duty cycle register can be read/written by softw are to control the pwm duty cycle output in a manual fan mode. in a fan control mode, it is necessa ry to select which pwm channel output s for driving fan. the fpwmcs in fanicnf register is set from 000b~111b to select ch0~7 pwm output as driving source for fani respectively. smartauto fan control operation when operating in smartauto fan control mode, the hardware controls the fans based on monitoring the free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 227 ec domain functions temperature and speed. the following initialization needs to be done: 1. set the minimum temperature that will turn on/off the fans in fani temperature limit register(fitlimitr). 2. set the hysteresis value for the minimum tem perature. the fan keeps in the on state until the temperature is below a certain amount which is set in fitlimitr register. the hysteresis value can be set in zhysr register. 3. in smartauto fan mode 0, t he duty cycle for the minimum fan speed needs to be set in fimpdcr register. the actual temperature increase/decreas e decides a linear function based on the fan speed range in the afisrr register. 4. in smartauto fan mode 1, t he duty cycle for the minimum fan speed needs to be set in fimpdcr register. the actual temperat ure increase/decrease decides pwm output for fan based on the temperature criterion, pwm duty cycle criterion in the fitci register and fipdci regsiter. 5. set the absolute temperature for fani in the fiat limitr register. if the ac tual temperature is equal to or exceeds the absolute temperat ure value set in fiatlimitr, fani will be set to the entire on state. figure 7-26. smartauto mode 0 fan pwm output vs. temperature reading pwm duty output 100%(full) 50%(half) zhysr fimpdcr 0%(stop) temperature reading (fitlimitr) (fiatlimitr) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 228 it8511 e /te/ g figure 7-27. smartauto mode 1 fan pwm output vs. temperature reading pwm duty output 100%(full) fipdc3 fipdc2 fipdc1 zhysr fimpdcr temperature reading 0%(stop) (fitlimitr) fitc2 (fiatlimitr) fitc1 fitc3 the following is smartauto fan linear calculation formula: linear autofan output duty cycle = p_fipdc + [(t - t_limit ) / trange * p_fipdcr] p_fipdcr denotes the fan minimum pwm duty cylce of region, e.g minimum region=f1mpdcr , 1st region = fipdc1, ... t denotes the input temperature t_limit denotes the fan temperature criteri on, set by f1tlimitr, f1tc1~3, . .. trange denotes the speed range set by afmisrr, afmasrr [ ] denotes to take the integer result 7.11.3.6 manual fan control mode in manual mode, the software may monitor either the fan tachometer reading r egisters or temperature reading register to control the fan speed by prog ramming the duty cycle of the driving pwm (fimpdcr) register. the contents of the tachometer read ing register is still updated according to the sampling counter that samples the tachometer input (tach0 pin for fan1 of the local sensor zone and tach1 pin for fan2 of the remote sensor zone). the sampling rate (fs) is freqec / 128. (freqec is listed in table 10-1 on page 297) fan speed (r.p.m.) = 60 / ( 1/fs sec * {fntmrr, fntlrr} * p) n denotes 1 or 2 p denotes the numbers of square pulses per revolution. and {fntmrr, fntlrr} = 0000h denotes fan speed is zero. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 229 ec domain functions 7.11.4 ec interface registers these registers are mapped in the address space of ec. the registers are listed below and the base address is 1800h. table 7-22. ec view register map, pwm 7 0 offset channel 0 clock prescaler register (c0cprs) 00h cycle time (ctr) 01h pwm duty cycle (dcr0-7) 02h-09h pwm polarity (pwmpol) 0ah prescaler clock frequency select register (pcfsr) 0bh prescaler clock source select group low (pcssgl) 0ch prescaler clock source select group high (pcssgh) 0dh cr256 prescaler clock source select group (cr256pcssg) 0eh prescaler clock source gating register (pcsgr) 0fh fan 1 configuration (fan1cnf) 10h fan 2 configuration (fan2cnf) 11h smartauto fan minimum-region speed range register (afmisrr) 12h smartauto fan maximum-region speed range register (afmasrr) 13h min/off pwm limit (mopl) 14h fan 1 minimum pwm duty (f1mpdcr) 15h fan 2 minimum pwm duty (f2mpdcr) 16h fan 1 temperature limit (f1tlimitr) 17h fan 2 temperature limit (f2tlimitr) 18h fan 1 absolute temperature limit (f1atlimitr) 19h fan 2 absolute temperature limit (f2atlimitr) 1ah zone hysteresis (zhysr) 1bh fan 1 temperature record (f1trr) 1ch fan 2 temperature record (f2trr) 1dh fan 1 tachometer lsb reading (f1tlrr) 1eh fan 1 tachometer msb reading (f1tmrr) 1fh fan 2 tachometer lsb reading (f2tlrr) 20h fan 2 tachometer msb reading (f2tmrr) 21h zone interrupt status control (zintscr) 22h zone temperature interrupt enable (ztier) 23h channel 4 clock prescaler register (c4cprs) 27h channel 4 clock prescaler msb register (c4mcprs) 28h channel 6 clock prescaler register (c6cprs) 2bh channel 6 clock prescaler msb register (c6mcprs) 2ch channel 7 clock prescaler register (c7cprs) 2dh channel 7 clock prescaler msb register (c7mcprs) 2eh fan 1 temperature criterion(f1tc1-3) 30h-32h fan 2 temperature criterion(f2tc1-3) 34h-36h fan 1 pwm duty criterion (f1pdc1-3) 38h-3ah fan 2 pwm duty criterion (f2pdc1-3) 3ch-3eh for a summary of the abbreviations used for register types, see ?register abbrevia tions and access rules? 7.11.4.1 channel 0 clock prescaler register (c0cprs) this register controls the cycle time and the minimal pulse width of channel 0~3. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 230 it8511 e /te/ g address offset: 00h bit r/w default description 7-0 r/w 00b prescaler divider value (psdv) pwm input clock is divided by the number of (c0cprs+ 1). for example, the value of 01h results in a divide by 2. the value of ffh results in a divide by 256. the contents of this register may be changed only when the pwm module is in the pwm inhibit mode. 7.11.4.2 cycle time register (ctr) this register controls the cycle time and duty cycle steps. address offset: 01h bit r/w default description 7-0 r/w ffh cycle time value (ctv) the prescaler output clock is divided by the number of (ctr + 1). for example, the value of 00h results in a divide by 1. the value of ffh results in a divide by 256. the contents of this register may be changed only when the pwm module is in the pwm inhibit mode. 7.11.4.3 pwm duty cycle register 0 to 7(dcri) this register (dcri; i=0 to 7) contro ls the duty cycle of pwmi output signal. address offset: 02h(ch0), 03h(ch1), 04h(ch2), 05 h(ch3), 06h(ch4), 07h(ch5), 08h(ch6), 09h(ch7); bit r/w default description 7-0 r/w 00h duty cycle value (dcv) dcri register decides t he number of clocks for which pwmi is high when invpi bit is 0 in pwmpol register. the pwmi duty cycle output = (dcri)/(ctr+1) if the dcri value > ctr value, pwmi signal is still low. if dcri value = ctr value, pwmi signal is still high. when inverse pwmi bit is 1, t he value of pwmi is inversed. 7.11.4.4 pwm polarity register (pwmpol) this register controls the polarity of pwm0 to pwm7. address offset: 0ah bit r/w default description 7-0 r/w 00h inverse pwm outputs (invp7-0) bit 7 to 0 control the polarity of pwm7 to pwm0 respectively. 0: non-inverting. 1: inverting. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 231 ec domain functions 7.11.4.5 prescaler clock frequency select register (pcfsr) this register bit3~0 is used to select prescaler cl ock frequency for four channel groups3~0. each of them includes 1 set prescaler regist ers. see the following table. channel group prescaler channels 0 c0cprs 1 c4mcprs,c4cprs 2 c6mcprs,c6cprs 3 c7mcprs,c7cprs this register bit7~4 is used to select one pwm outpu t from eight channels for cr256 pwm channel 1, and the dcri of the selected channels is used as dcr of cr256 pwm channel 1. address offset: 0bh bit r/w default description 7-4 r/w 1000b cr256 pwm output select 1 (cr256pos1) the bits select cr256 pwm output channel 0000: select pwm channel 0 as output of cr256 pwm channel 1 0001: select pwm channel 1 as output of cr256 pwm channel 1 0010: select pwm channel 2 as output of cr256 pwm channel 1 0011: select pwm channel 3 as output of cr256 pwm channel 1 0100: select pwm channel 4 as output of cr256 pwm channel 1 0101: select pwm channel 5 as output of cr256 pwm channel 1 0110: select pwm channel 6 as output of cr256 pwm channel 1 0111: select pwm channel 7 as output of cr256 pwm channel 1 1000: disable cr256 channel 1 output. 3-0 r/w 0h prescaler clock frequency select (pcfs3-0) bit 3 to 0 select prescaler clock frequency for channel group 3 to 0 respectively. 0: select 32.768 khz 1: select ec clock frequency (listed in table 10-1 on page 297) 7.11.4.6 prescaler clock source select group low (pcssgl) this register is used to select prescaler clock source fo r four channels. each channel uses 2 bits to select one from four prescaler clock sources. address offset: 0ch bit r/w default description 7-6 r/w 0h prescaler clock select 3 (pcs3) the bits select prescaler clock for channel 3. the bits 7-6 are the same as bit 1-0. 5-4 r/w 0h prescaler clock select 2 (pcs2) the bits select prescaler clock for channel 2. the bits 5-4 are the same as bit 1-0. 3-2 r/w 0h prescaler clock select 1 (pcs1) the bits select prescaler clock for channel 1. the bits 3-2 are the same as bit 1-0. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 232 it8511 e /te/ g bit r/w default description 1-0 r/w 0h prescaler clock select 0 (pcs0) the bits select prescaler clock for channel 0. 00: select prescaler clock divided by c0cprs 01: select prescaler clock divided by {c4mcprs,c4cprs} 10: select prescaler clock divided by {c6mcprs,c6cprs} 11: select prescaler clock divided by {c7mcprs,c7cprs} 7.11.4.7 prescaler clock source select group high (pcssgh) this register is used to select prescaler clock source fo r four channels. each channel uses 2 bits to select one from four prescaler clock sources. address offset: 0dh bit r/w default description 7-6 r/w 1h prescaler clock select 7(pcs7) the bits select prescaler clock for channel 7. the bits 7-6 are the same as bit 1-0. 5-4 r/w 1h prescaler clock select 6(pcs6) the bits select prescaler clock for channel 6. the bits 5-4 are the same as bit 1-0. 3-2 r/w 1h prescaler clock select 5(pcs5) the bits select prescaler clock for channel 5. the bits 3-2 are the same as bit 1-0. 1-0 r/w 1h prescaler clock select 4 (pcs4) the bits select prescaler clock for channel 4 00: select prescaler clock divided by c0cprs 01: select prescaler clock divided by {c4mcprs,c4cprs} 10: select prescaler clock divided by {c6mcprs,c6cprs} 11: select prescaler clock divided by {c7mcprs,c7cprs} 7.11.4.8 cr256 prescaler clock source select group (cr256pcssg) bits 7-6 of this register are used to select presca ler clock source for cr256(complete resolution 256) pwm channels. bits 3-0 of this register are used to select one pw m output from eight channels for cr256 pwm channel 0, and the dcri of the selected channels is used as dcr of cr256 pwm channel 0. address offset: 0eh bit r/w default description 7-6 r/w 00b cr256 prescaler clock select 7(cr256pcs) the bits select prescaler clock for cr256 pwm channel. 00: select prescaler cl ock divided by c0cprs 01: select prescaler clock divided by {c4mcprs,c4cprs} 10: select prescaler clock divided by {c6mcprs,c6cprs} 11: select prescaler clock divided by {c7mcprs,c7cprs} 5-4 r/w 0h reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 233 ec domain functions bit r/w default description 3-0 r/w 1000b cr256 pwm output select 0 (cr256pos0) the bits select cr256 pwm output to pad channel 0000: select pwm channel 0 as output of cr256 pwm channel 0 0001: select pwm channel 1 as output of cr256 pwm channel 0 0010: select pwm channel 2 as output of cr256 pwm channel 0 0011: select pwm channel 3 as output of cr256 pwm channel 0 0100: select pwm channel 4 as output of cr256 pwm channel 0 0101: select pwm channel 5 as output of cr256 pwm channel 0 0110: select pwm channel 6 as output of cr256 pwm channel 0 0111: select pwm channel 7 as output of cr256 pwm channel 0 1000: disable cr256 channel 0 output 7.11.4.9 prescaler clock source gating register (pcsgr) address offset: 0fh bit r/w default description 7-0 r/w 0h prescaler clock source gating (pcsg) bits 7-0 are used to gate prescaler clock source for pwm channels 7-0 respectively. 0: no gating clock source 1: gating clock source; pwm channel output is 0 when invp bit is set to 0 respectively 7.11.4.10 fan 1 configuration register (fan1cnf) this register controls the fan 1 operation mode, which is associated with its temperature sensor. address offset: 10h bit r/w default description 7-6 r/w 00b fan configuration (fancnf) when the fan is in the smartauto fan mode 0, it will be assigned to a zone and its pwm duty cycle will be automat ically adjusted according to the temperature of that zone. when the fan is in the smartauto fan mode 1, it will be assigned to a zone and its pwm duty cycle will be automatica lly adjusted according to the setting value on f1tci and f1dpci register when the fan is in the manual fan mode, its pwm duty cycle register can be read/written by software to control the pwm duty cycle output. bit config. 00 fan on zone smartauto mode 0 01 fan on zone smartauto mode 1 10 fan manually controlled others reserved 5 - 0h reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 234 it8511 e /te/ g bit r/w default description 4-2 r/w 0h fan pwm channel se lect (fpwmcs) bits 4-2 select pwm duty cycle output for driving fan. in smartauto fan mode, the value of the pwm duty cycl e register selected for fan will be updated according to the smartauto fan algorithm, so software may not write these pwm duty cycle register for fan. bit pwm ch for fan 000 pwm channel 0 001 pwm channel 1 010 pwm channel 2 011 pwm channel 3 100 pwm channel 4 101 pwm channel 5 110 pwm channel 6 111 pwm channel 7 1-0 r/w 0h fan spin up time (fansupt) bits 1-0 select the time for the fan to spin up. when the fan spins up after fan has stopped for more than 31ms, the pwm output is held at 100% duty cycle during time specified. bit time 00 zero sec 01 250m sec (+- 30msec) 10 500m sec (+- 30msec) 11 1000m sec (+- 30msec) 7.11.4.11 fan 2 configuration register (fan2cnf) this register controls the fan 2 operation mode, which is associated with its temperature sensor. address offset: 11h bit r/w default description 7-6 r/w 00b fan configuration (fancnf) the same as the fan1cnf register 5 - 0h reserved 4-2 r/w 0h fan pwm channel se lect (fpwmcs) the same as the fan1cnf register 1-0 r/w 0h fan spin up time (fansupt) the same as the fan1cnf register free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 235 ec domain functions 7.11.4.12 smartauto fan minimum-regi on speed range register (afmisrr) this register controls the minimum region of the spe ed activity for fan 1 and 2 in the smartauto fan mode. address offset: 12h bit r/w default description 7 - - reserved 6-4 r/w 4h fan speed range 1 (fsr1) in the smartauto fan mode, when the temperature drops within the range of the temperature limit(tlimit register) and the absolute temperature limit(atlimit register in mode 0), or first region temperature (fitc1 in mode 1), ), the speed of the fan is increa sed linearly according to the increment range of the temperature. bits 6-4 decide the temperature range. bit temperature range (degree c) 001h 2 degree c 010h 4 degree c 011h 8 degree c 100h 16 degree c 101h 32 degree c 110h 64 degree c others reserved 3 - - reserved 2-0 r/w 5h fan speed range 2 (fsr2) in the smartauto fan mode 1, when the temperature drops within the range of the first region temperature (fitc1 in mode 1) and the second region temperature (fitc2 in mode 1), the speed of the fan is increased linearly according to the increment range of the temperature. bits 6-4 decide the temperature range. bit temperature range (degree c) 001h 2 degree c 010h 4 degree c 011h 8 degree c 100h 16 degree c 101h 32 degree c 110h 64 degree c others reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 236 it8511 e /te/ g 7.11.4.13 smartauto fan maximum-regi on speed range register (afmasrr) this register controls the maximum region of the spe ed activity for fan 1 and 2 in the smartauto fan mode. address offset: 13h bit r/w default description 7 - - reserved 6-4 r/w 5h fan speed range 3 (fsr3) in the smartauto fan mode, when the temperature drops within the range of the second region temperature (fitc2 in mode 1), and the third region temperature (fitc3 in mode 1), the speed of the fan is increased linearly according to the increment range of the temperature. bits 6-4 decide the temperature range. bit temperature range (degree c) 001h 2 degree c 010h 4 degree c 011h 8 degree c 100h 16 degree c 101h 32 degree c 110h 64 degree c others reserved 3 - - reserved 2-0 r/w 0h fan speed range 4 (fsr4) in the smartauto fan mode 1, when the temperature drops within the range of the third region temperature (fitc3 in mode 1) and the absolute temperature limit(atlimit register in mode 1), the speed of the fan is increased linearly according to he increment range of the temperature. bits 6-4 decide the temperature range. bit temperature range (degree c) 001h 2 degree c 010h 4 degree c 011h 8 degree c 100h 16 degree c 101h 32 degree c 110h 64 degree c others reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 237 ec domain functions 7.11.4.14 min/off pwm li mit register (mopl) this register specifies whether duty cycle will be 0% or minimun fan duty when the measured termperature is below the temperature limit register setting. bit 7(o ff2) applies to fan2 and bit 6 (off1) applies to fan1. address offset: 14h bit r/w default description 7 r/w 0b off2/min limit (o2mlimit) 0: pwm actions at 0% duty when the temperature is not larger than limit. 1: pwm actions at pwm minimum duty when the temperature is below limit. 6 r/w 0b off1/min limit (o1mlimit) 0: pwm actions at 0% duty when the temperature is not larger than limit. 1: pwm actions at pwm minimum duty when the temperature is below limit. 5-0 - 0h reserved 7.11.4.15 fan 1 minimum pwm du ty cycle register (f1mpdcr) this register specifies the minimun fan duty that pwm will output when the measured termperature reaches the temperature limit register settting. address offset: 15h bit r/w default description 7-0 r/w 80h minimum pwm duty cycle value ( mpwmdcv) the value of this register is the same as the dcri register, which defines the number of clocks for which pwmi is high (from the full cycle of the pwmi cycle) when invpi bit is 0 in pwmpol register. 7.11.4.16 fan 2 minimum pwm du ty cycle register (f2mpdcr) this register specifies the minimun fan duty that pwm will output when the measured termperature reaches the temperature limit register settting.. address offset: 16h bit r/w default description 7-0 r/w 80h minimum pwm duty cycle value ( mpwmdcv) this register is the same as the f1mpdcr register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 238 it8511 e /te/ g 7.11.4.17 fan 1 temperature limit register (f1tlimitr) this register specifies the temperature limi t value for fan 1 assigned to the zone 1. address offset: 17h bit r/w default description 7-0 r/w 5ah temperature limit value (tlimitv) when the temperature exceeds this limit, the fan will be turned on and speed increased according to the smartauto fan algorithm based on the setting in bits 6-4 of the smartauto fan minimum-region speed range register(afmsrr). bit minimum pwm duty 80h -128 degree c ? ? ceh -50 degree c ? ? 00h 0 degree c ? ? 32h 50 degree c ? ? 7fh 127 degree c 7.11.4.18 fan 2 temperature limit register (f2tlimitr) this register specifies the temperature limi t value for fan 2 assigned to the zone 2. address offset: 18h bit r/w default description 7-0 r/w 5ah temperature limit value (tlimitv) this register is the same as the f1tlimitr register. 7.11.4.19 fan 1 absolute temperature limit register (f1atlimitr) this register specifeis the abs olute temperature limit value for fan 1 assigned to zone 1. address offset: 19h bit r/w default description 7-0 r/w 64h absolute temperature limit value (atlimitv) in a smartauto fan mode, when the cu rrent temperature exceeds this limit, the fan will be running on pwm dut y 100% except th ose disable by fanxcnf register. bits temperature 80h -128 degree c ? ? ceh -50 degree c ? ? 00h 0 degree c ? ? 32h 50 degree c ? ? 7fh 127 degree c free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 239 ec domain functions 7.11.4.20 fan 2 absolute temperature limit register (f2atlimitr) this register specifies the abs olute temperature limit value for fan 2 assigned to zone 2. address offset: 1ah bit r/w default description 7-0 r/w 64h absolute temperature limit value (atlimitv) the same as the f1atlimitr register. 7.11.4.21 zone hysteresis register (zhysr) this register controls the amount that the fan will turn off when the temperature is less than the temperatur limit value. address offset: 1bh bit r/w default description 7-4 r/w 4h zone hysteresis value (zhysv) used in smartauto fan mode. bits 7-4 are assigned to fan 2 and bit 3-0 are assigned to fan 1. bits hys value 0h 0 degree c ? ? 5h 5 degree c ? ? fh 15 degree c 3-0 4h zone hysteresis value (zhysv) bits 3-0 are assigned to fan 1 and others are the same as bit7-0. 7.11.4.22 fan 1 temperature record register (f1trr) in a smartauto fan 1 enabled operation, the register is uesd to input the temperature to smartautofan fan1 controller, and the programmer needs to update the register value when zone 1 temperature is changed . address offset: 1ch bit r/w default description 7-0 r/w 5ah current temperature value (ctempv) the value of the current temperat ure is represented as follows: bits 7-0 current temperature 80h -128 degree c ? ? ceh -50 degree c ? ? 00h 0 degree c ? ? 32h 50 degree c ? ? 7fh 127 degree c free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 240 it8511 e /te/ g 7.11.4.23 fan 2 temperature record register (f2trr) in a smartauto fan 2 enabled operation, the register is uesd to input the temperatur e to smartautofan fan2 controller, and the programmer needs to update the register value when zone 2 temperature is changed . address offset: 1dh bit r/w default description 7-0 r/w 5ah current temperature value (ctempv) this register is the same as the f1trr register. 7.11.4.24 fan 1 tachometer lsb reading register (f1tlrr) this register reflects the lsb value of the current tachom eter of the fan. the value is represented for each fan in a 16 bits. fan 1 corresponds to tach0 (tachometer input of fan1). address offset: 1eh bit r/w default description 7-0 r - current tachometer lsb value (ctachlv) the value of bit 7-0 denotes lsb tachometer speed. 7.11.4.25 fan 1 tachometer msb reading register (f1tmrr) this register reflects the msb value of the current tachom eter of the fan. the value is represented for each fan in a 16 bits. fan 1 corresponds to tach0. address offset: 1fh bit r/w default description 7-0 r - current tachometer msb value (ctachmv) the value of bits 7-0 denotes msb tachometer speed. 7.11.4.26 fan 2 tachometer lsb reading register (f2tlrr) this register reflects the lsb value of the current tachom eter of the fan. the value is represented for each fan in a 16 bits. fan 2 corresponds to tach1 (tachometer input of fan2).. address offset: 20h bit r/w default description 7-0 r - current tachometer lsb value (ctachlv) the value of bits 7-0 denotes the lsb tachometer speed. 7.11.4.27 fan 2 tachometer msb reading register (f2tmrr) this register reflects the msb value of the current tachom eter of the fan. the value is represented for each fan in a 16-bit binary digits. fan 2 corresponds to tach1. address offset: 21h bit r/w default description 7-0 r - current tachometer msb value (ctachmv) the value of bits 7-0 denotes msb tachometer speed. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 241 ec domain functions 7.11.4.28 zone interrupt status control register (zintscr) the zone bits of the register indicate the temperatur e violation when the measured temperature violates the limit in temperature limit register se t for any of the two thermal zones. address offset: 22h bit r/w default description 7 r 0b zone 2 limit exceeded (z2le) set 1 when the temperature measured by zone 2(remote) is larger than the limit set in temperature limit register. 6 r 0b zone 1 limit exceeded (z1le) set 1 when the temperature measured by zone 1(internal) is larger than the limit set in temperature limit register. 5 r/w 0b tach1 data-valid interrupt enable(t1die) 1: enable interrupt to r8032 when the fan1 tachometer data is valid. 0: disable interrupt to r8032 when the fan1 tachometer data is valid. 4 r/wc 0b tach1 data-valid interrupt clear(t1dic) write one to clear the interrupt status, which is caused when fan 1 tachometer data is valid; writing zero is ignored. 3 r 0b tach1 data-valid inte rrupt status(t1dis) 1: fan1 tachometer data-valid event occurs 0: no fan1 tachometer data-valid event occurs. 2 r/w 0b tach2 data-valid interrupt enable(t2die) 1: enable interrupt to r8032 when the fan 2 tachometer data is valid. 0: disable interrupt to r8032 when t he fan 2 tachometer data is valid. 1 r/wc 0b tach2 data-valid interrupt clear(t2dic) write one to clear interrupt status, which is caused when fan 2 tachometer data is valid; writing zero is ignored. 0 r 0b tach2 data-valid inte rrupt status(t2dis) 1: fan2 tachometer data-valid event occurs 0: no fan2 tachometer data-valid event occurs. 7.11.4.29 zone temperature interrupt enable register (ztier) the register is used to enable the interrupt to the ec 8032 via int7 when the zone temperature event occurs, either zone 1 limit exceeded or zone 2 limit exceeded. address offset: 23h bit r/w default description 7 r/w 0b zone temperature event enable (ztee) this bit enables interrupt (int7) to intc if z1le and z2le bit in zintscr register is set. 0: disable 1: enable 6 - - reserved 5-2 - 0b reserved 1 r/w 0b pwm clock counter enable (pcce) 1: enable pwms clock counter. set this bit to 1 after all other registers have been set. 0: disable pwms clock counter free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 242 it8511 e /te/ g bit r/w default description 0 r/w 0b pwm test mode (pwmtm) 1: pwm switches to a test mode 0: pwm works on a normal mode 7.11.4.30 channel 4 clock prescaler register (c4cprs) this register controls the cycle time and the minimal pulse width of channel 4-7. address offset: 27h bit r/w default description 7-0 r/w 00b prescaler divider value (psdv7-0) pwm input clock is divided by the num ber of psdv15-0 + 1 except 0 value. for example, the value of 0001h result s in a divide by 2 and the value of ffffh results in a divide by 65536 except 0 value. set value 0 to disable clock prescaler divider. the contents of this register may be changed only when the pwm module is in a pwm inhibit mode. this register defines the low byte and the next register c4mcprs defines the high byte. 7.11.4.31 channel 4 clock prescaler msb register (c4mcprs) this register controls the cycle time and the minimal pulse width of channel 4-7. address offset: 28h bit r/w default description 7-0 r/w 00b prescaler divider value (psdv15-8) refer to the previous register for the details. 7.11.4.32 channel 6 clock prescaler register (c6cprs) this register controls the cycle time and the minimal pulse width of channel 6. address offset: 2bh bit r/w default description 7-0 r/w 00b prescaler divider value (psdv7-0) pwm input clock is divided by the num ber of psdv15-0 + 1 except 0 value. for example, the value of 0001h result s in a divide by 2 and the value of ffffh results in a divide by 65536 except 0 value. set value 0 to disable clock prescaler divider. the contents of this register may be changed only when the pwm module is in a pwm inhibit mode. this register defines the low byte and the next register c6mcprs defines the high byte. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 243 ec domain functions 7.11.4.33 channel 6 clock prescaler msb register (c6mcprs) this register controls the cycle time and the minimal pulse width of channel 6. address offset: 2ch bit r/w default description 7-0 r/w 00b prescaler divider value (psdv15-8) refer to the previous register for the details. 7.11.4.34 channel 7 clock prescaler register (c7cprs) this register controls the cycle time and the minimal pulse width of channel 7. address offset: 2dh bit r/w default description 7-0 r/w 00b prescaler divider value (psdv7-0) pwm input clock is divided by the num ber of psdv15-0 + 1 except 0 value. for example, the value of 0001h result s in a divide by 2 and the value of ffffh results in a divide by 65536 except 0 value. set value 0 to disable clock prescaler divider. the contents of this register may be changed only when the pwm module is in a pwm inhibit mode. this register defines the low byte and the next register c7mcprs defines the high byte. 7.11.4.35 channel 7 clock prescaler msb register (c7mcprs) this register controls the cycle time and the minimal pulse width of channel 7. address offset: 2eh bit r/w default description 7-0 r/w 00b prescaler divider value (psdv15-8) refer to the previous register for the details. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 244 it8511 e /te/ g 7.11.4.36 fan 1 temperature criterion register 1-3 (f1tc1-3) in a smartauto fan mode1, this register is set by software, and used to change the fan1 pwm output according to the relational pwm duty cyle value of f1pdc1-3 register. address offset: 30h-32h (default : 3ch, 46h, 50h) bit r/w default description 7-0 r/w -- criterion temperature setting (ctemps) the value of the criterion temperature is represented as follows: bits 7-0 current temperature 80h -128 degree c ? ? ceh -50 degree c ? ? 00h 0 degree c ? ? 32h 50 degree c ? ? 7fh 127 degree c 7.11.4.37 fan 2 temperature criterion register 1-3(f2tc1-3) in a smartauto fan mode1, this register is set by software, and is used to change the fan2 pwm output according to the relational pwm duty cyle value of f2pdc1-3 register. address offset: 34h-36h (default : 3ch, 46h, 50h) bit r/w default description 7-0 r/w -- criterion temperature setting (ctemps) the same as the f1tc1-3 register 7.11.4.38 fan 1 pwm duty cycle criterion register 1-3(f1pdc1-3) in a smartauto fan mode1, the regist ers specify the fan 1 duty cycle t hat pwm will output when the measured termperature reaches the settting value of the relational f1tc1-3 register. address offset: 38h-3ah (default : 3ch, 46h, 50h) bit r/w default description 7-0 r/w -- pwm duty cycle value ( pwmdcv) the same as the f2pdc1-3 register 7.11.4.39 fan 2 pwm duty cycle criterion register 1-3(f2pdc1-3) in a smartauto fan mode1, the regist ers specify the fan 2 duty cycle t hat pwm will output when the measured termperature reaches the settting value of the relational f2tc1-3 register. address offset: 3ch-3eh (default : 3ch, 46h, 50h) bit r/w default description 7-0 r/w -- pwm duty cycle value ( pwmdcv) the value of this register is the same as that of the dcri register, which defines the number of the clock. the number determines the high period of one pwmi cycle when invpi bit is 0 in pwmpol register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 245 ec domain functions 7.11.5 pwm programming guide figure 7-28. program flow chart for pwm channel output start program cicprs reg. (set prescaler clock for channel 0 ~7) program ctr reg. (set pwm cycle time ) pwm channel output completed program dcri reg (set duty cyle time for ch* ) program invpi@ pwmpol(polarity) i denotes 0 to 7 i denotes 0 to 7 program gpcrai to enable pwm output on gpio pins i denotes 0 to 7 write 1 to pcce@ztier to enable pwm clock i denotes 0 to 7 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 246 it8511 e /te/ g figure 7-29. program flow chart for cr256 pwm channel output start program cicprs reg. (set prescaler clock for channel 0 ~7) program ctr reg. (set pwm cycle time ) pwm channel output completed program dcri reg (set duty cyle time for ch* ) write i into cr256posj (set cr256 pwm chj to pwmi) i denotes 0 to 7 i denotes 0 to 7 program gpcrai to enable pwm output on gpio pins i denotes 0 to 7 write 1 to pcce@ztier to enable pwm clock i denotes 0 to 7 j denotes 0 to 1 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 247 ec domain functions figure 7-30. program flow chart for smartauto fan channel output start program fanicnf to selet a pwm channel as smartauto fan channel (default ch0) complete pwm output procedure (it is same as pwm channel output program chart) smartauto fan set completed write afmisrr, afmaisrr reg (set smartauto fan speed range ) program oimlimit@mopl reg (off or minimum duty cycle) i denotes 1 to 2 y i denotes 1 to 2 program fimpdcr to set minimum pwm duty cyle for fani (same as dcr reg) i denotes 1 to 2 program fipdc1,2,3 to desired pwm duty cycle in mode 1 i denotes 1 to 2 program fitlimitr to set temperature limit program fiatlimitr to set absolute temperature limit write 00 to fancnf@fanicnf (to start smartauto fan control) write current temperatre value into fitrr polling i denotes 1 to 2 one fan temp updated the temperature must be updated during several millisecond according to the measured value of the temperature with adc. i denotes 1 to 2 program fitc1,2,3 to desired temperture in mode 1 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 248 it8511 e /te/ g 7.12 ec access to host controlled modules (ec2i bridge) 7.12.1 overview the module enables ec access to pnpcfg, rtc and sw uc modules. it can access the host domain modules with host on alternate usage or take control of it and prevent any host from accessing that module. 7.12.2 features ? supports lock bit to prevent conf licts in host-controlled module. ? supports super i/o i-bus arbitration ? supports super i/o access lock violation indication 7.12.3 functional description the ec2i bridge enables the ec to access the host controlled module registers (e.g., host configuration module(pnpcfg), rtc and swuc), using the i-bus which is arbitrated by i- bus arbiter to prevent i-bus grant from fighting between ec and the host side. the bridge prov ides a lock bit to control the access of the host controlled modules. when the relative lock bit is cleared, the host is allowed to access to the host controlled modules registers. when the relative lock bit is set, the host is not allowed to access to the host controlled module registers (i.e., write operations are ignored and read operations return the unknown). whenever the host accesses to the locked register, a violation flag is set on the respective bit in the siolv register. ec should access the host controlled modules only after preventing host accessing to the module (using lock bits). the ib arbiter arbitrates ib usage between the hos t and ec. if an lpc transaction has started prior to the beginning of ec transaction, ec waiting for the completion of the lpc transaction. if ec transaction starts prior to lpc transaction, the lpc translation needs to wait for the completion of ec transaction. ec firmware may access the host controlled modules only when vstby is on and vcc is on and lpcclk is active. ec read operation from a host controlled module register, refer to the followings: 1. set csae bit in ibctl register. 2. make sure that both crib and cwib bits in ibctl register are cleared. 3. setting its enable bit in ibmae register for acce ss module, only one module can enable at a time. 4. assign the offset of the regist er in the device in ihioa register. 5. write 1 to crib bit in ibctl register. 6. read the crib bit in ibctl until it returns 0. 7. read the data from ihd register. ec write operation from a host controlled module register, refer to the followings: 1. set csae bit in ibctl register. 2. make sure that both crib and cwib bits in ibctl register are cleared. 3. setting its enable bit in ibmae register for ac cess module, only one module can enable at a time. 4. assign the offset of the regist er in the device in ihioa register. 5. write the data to ihd register, which begins a write transaction. 6. read the cwib bit in ibctl until it returns 0, whic h represents that a write tr ansaction has been finished. for minimal conflict between host and ec in the use of host controlled modules, refer to the followings. notice for read/write operation 1. the host is allowed to access the host controll ed module only when the corresponding lock bit is cleared. 2. the firmware should not read any of the rtc read-vol atile registers to prevent from host software access. 7.12.4 ec interface registers the following set of registers is accessible only by the ec. the registers are maintained by vstby. the registers are listed below and the base address is 1200h. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 249 ec domain functions table 7-23. ec view register map, ec2i 7 0 offset indirect host i/o address.(ihioa) 00h indirect host data (ihd) 01h lock super i/o host access (lsioha) 02h super i/o access lock violation (siolv) 03h ec to i-bus modules access enable (ibmae) 04h i-bus control (ibctl) 05h for a summary of the abbreviations us ed for the register type, see ?register abbreviations and access rules?. 7.12.4.1 indirect host i/o address register (ihioa) this register defines the host i/o address for read or write transactions initiated by ec from/to the host controlled modules. the i/o address is an offset from the lsb bits of the address of the host controlled module. the accessed module is selected using ec to ib modules access enable register (ibmae). address offset: 00h bit r/w default description 7-0 r/w 00b indirect host i/o offset (ihioo) these bits indicate the offsets within the device range are allowed. 7.12.4.2 indirect host data register (ihd) this register holds host data for read or write transact ions initiated by ec from/to the host controlled modules. address offset: 01h bit r/w default description 7-0 r/w 00b indirect host data (ihda) 7.12.4.3 lock super i/o host access register (lsioha) this register controls locking of host access to the host controlled modules. address offset: 02h bit r/w default description 7-2 - 0h reserved 1 r/w 0b lock real-time clock (rtc) host access (lkrtcha) 0: host access to the rtc registers is enabled 1: host access to the rtc registers is disabled 0 r/w 0b lock pnpcfg registers host access (lkcfg) 0: host access to the pnpcfg registers is enabled 1: host access to the pnpcfg registers is disabled free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 250 it8511 e /te/ g 7.12.4.4 super i/o access lock vi olation register (siolv) this register provides an error indication when a host lo ck violation occurs on host controlled modules access. address offset: 03h bit r/w default description 7-2 - 0h reserved 1 r/wc 0b real-time clock (rtc) lock violation (rtclv) 0: there is no lock violation when the host accesses rtc registers. 1: when the host accesses the rtc but lkrtcha bit in lsioha register is set, this bit is set to indicate a violation and can be write-1-clear. 0 r/wc 0b pnpcfg register lock violation (cfglv) 0: there is no lock violation when t he host accesses pnpcfg registers. 1: when the host accesses pnpcfg register but lkcfg bit in lsioha register is set, this bit is set to indi cate a violation and can be write-1-clear. 7.12.4.5 ec to i-bus modules access enable register (ibmae) this register enables ec access to the host controlled modu les. only one of the bits in this register may be set at a time. address offset: 04h bit r/w default description 7-3 - 0h reserved 2 r/w 0b mobile system wake-up control (swuc) access enable (swucae) 0: ec access to the swuc registers is disabled. 1: ec access to the sw uc registers is enabled. 1 r/w 0b real-time clock (rtc) ec access enable (rtcae) the rtc has two selection signals defined in its configuration space. a1 of the offset is used to decode the two selection (when a1 is 0, the index 70h and 71h is selected; when a1 is 1, the index 72h and 73h is selected). 0: ec access to the rt c registers is disabled. 1: ec access to the rt c registers is enabled. 0 r/w 0b pnpcfg register ec access enable (cfgae) 0: ec access to the pnpcfg registers is disabled. 1: ec access to the pnpcfg registers is enabled. 7.12.4.6 i-bus control register (ibctl) this register allows ec to the i-bus bridge operation. address offset: 05h bit r/w default description 7-4 - 0h reserved 3 - - reserved 2 r 0b ec write to ib (cwib) 0: no write operation is detected. 1: when write data to the ihd register. it is cleared when the write to the ib is completed. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 251 ec domain functions bit r/w default description 1 r/w 0b ec read from ib (crib) set 1 to begin a read from the ib; the read operation is based on the setting in ibmae register. a write of 0 to this bit is ignored. this bit is cleared when the read operation is completed and repr esents the data in ihd register is available. 0 r/w 0b ec to ib access enabled (csae) 0: ec access to the ib bus is disabled (default). 1: ec access to the ib bus is enabled. the module to be accessed is selected in the ibmae register. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 252 it8511 e /te/ g 7.12.5 ec2i programming guide the read/write cycles pnpcfg and swuc modules via ec2i are only valid when vcc is supplied. it means that such cycles may be executed after every vcc power-on. figure 7-31. program flow chart for ec2i read start write ihioa reg crib=0? cwib=0? write ibmae reg (only one bit can be set 1) crib =0? read completed write crib bit to 1 write csae bit to 1 read ihd reg program flow chart for ec2i read clear ibmae reg clear csae bit to 0 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 253 ec domain functions figure 7-32. program flow chart for ec2i write start write csae bit to 1 crib=0? cwib=0? write ibmae reg (only one bit set 1) cwib =0? write completed write ihioa reg write ihd reg program flow chart for ec2i write clear csae bit to 0 clear ibmae reg free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 254 it8511 e /te/ g 7.13 external timer and external watchdog (etwd) 7.13.1 overview besides the internal timer 0, 1, 2 and wdt inside t he 8032, there is external timer/wdt outside the 8032. external timer/wdt is based on 32.768 k clock and st ill works when ec is in idle/doze/sleep mode. the external timer is recommended to replace internal timer for periodical wakeup task. external timer/wdt have less power consumption t han internal timer/wdt due to the low frequency. etwd module cannot count external signal sources from pins. if the firmware wants to count external signal sources from pins, refer to tmri0, tmri1, tach0 and tach1. tmri0/tmri1 are used as timer1/2 sources of 8032 and tach0/1 are tachometer inputs of pwm. 7.13.2 features ? 32.768 khz, 1.024 khz and 32 hz prescaler for external timer ? 16-bit count-down external timer ? 16-bit count-down external wdt figure 7-33. simplified diagram 32.768 khz 1.024 khz 32 hz 16-bit counter {etcntlh, etcntll} ewdsrc@etwcfg 1 0 external watchdog external timer etps@etpsr 16-bit counter {ewdcntlh, ewdcntll} to int30 to reset circuit (ec domain) 7.13.3 functional description 7.13.3.1 external timer operation the external timer is a 16-bit counter down timer. its clock source is based on 32.768 k clock and can be selected by a prescaler defined at etps field in etpsr register. the count number is defined in etcntlh and etcntll registers. external timer is stopped after reset and started after writing data to etcntll register and never stops until reset. it asserts an interrupt to intc when it counts to zero every time. the external timer re-starts when x it counts to zero periodically. x data is written to etcntll register. x 1 is written to etrst bit in etwctrl register. external timer asserts periodical inte rrupt to ec 8032 via int30 of intc. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 255 ec domain functions 7.13.3.2 external wdt operation external wdt is a 16-bit counter down timer. its clock s ource is either external timer output or the same clock source of external timer, and it is cont rolled by ewdsrc bit in etwcfg register. the count number is defined in ewdcntl register. exte rnal wdt is stopped after reset and started after writing data to ewdcntl register a nd cannot be stopped until reset. it asserts an external watchdog reset to ec domain when it counts to zero. external wdt requires starting external timer regardless of ewdsrc field in etwcfg register. external wdt cannot be started until external timer is started. the external wdt re-starts when it is touched by the firmware. there are two following ways to touch (re-start) external wdt: ? writing data to ewdcntl register (if lewdcn tl bit in etwcfg register is not set) ? writing 5ch to ewdkeyr register, called key-match external wdt asserts an external watchdog reset to ec domain when ? it counts to zero. ? data except 5ch is written to ewdkeyr register. 7.13.4 ec interface registers the following set of the registers is accessible only by the ec. they are listed below and the base address is 1f00h. table 7-24. ec view register map, etwd 7 0 offset external timer/wdt configur ation register (etwcfg) 01h external timer prescaler register (etpsr) 02h external timer counter high byte (etcntlhr) 03h external timer counter low byte (etcntllr) 04h external timer/wdt control register (etwctrl) 05h external wdt counter high byte (ewdcntlhr) 09h external wdt counter low byte (ewdcntllr) 06h external wdt key register (ewdkeyr) 07h reset scratch register (rstscr) 08h for a summary of the abbreviations used for the register type, see ?register abbreviations and access rules? 7.13.4.1 external timer/wdt configuration register (etwcfg) address offset: 01h bit r/w default description 7 - 0h reserved 6 r/w 0b external wdt stop mode (ewdsm) 1: stop counting wdt when lpc memo ry/fwh cycles are processing. 0: otherwise 5 r/w 0b external wdt key enabled (ewdkeyen) 1: enable the key match function to touch the wdt 0: otherwise 4 r/w 0b external wdt clock source (ewdsrc) 1: select clock after presca ler of the external timer 0: select clock from the output of the external timer 3 r/w 0b lock ewdcntl register (lewdcntl) 1: writing to ewdcntl is ignored. 0: writing to ewdcntl is allowed. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 256 it8511 e /te/ g bit r/w default description 2 r/w 0b lock etcntlx registers (letcntl) 1: writing to etcntlh/etcntl is ignored. 0: writing to etcntlh/etcntl is allowed. 1 r/w 0b lock etps register (letps) 1: writing to etps is ignored. 0: writing to etps is allowed. 0 r/w 0b lock etwcfg register (letwcfg) 1: writing to etwcfg itself is ignored, and this bit can?t be cleared until reset. 0: writing to etwcfg itself is allowed. 7.13.4.2 external timer prescaler register (etpsr) address offset: 02h bit r/w default description 7-2 - 0h reserved 1-0 r/w 00b external timer prescaler select (etps) these bits control the clock input source to the external timer. 00b: 32.768 khz 01b: 1.024 khz 10b: 32 hz 11b: reserved note the prescaler will not output cloc k until data is written to etcntllr register. 7.13.4.3 external timer counter high byte (etcntlhr) address offset: 03h bit r/w default description 7-0 r/w ffh external timer counter high byte (etcntlh) define the count number of high byte of the 16-bit count-down timer. 7.13.4.4 external timer counter low byte (etcntllr) address offset: 04h bit r/w default description 7-0 r/w ffh external timer counter low byte (etcntll) define the count number of low byte of the 16-bit count-down timer. the external timer starts or re-s tarts after writing this register. 7.13.4.5 external timer/wdt control register (etwctrl) address offset: 05h bit r/w default description 7-2 - 00h reserved 1 r 0b external timer terminal count (ettc) 1: indicates the external timer has c ounted down to zero, and it is cleared after reading it. 0: otherwise writing to this bit is ignored. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 257 ec domain functions bit r/w default description 0 w - external timer reset (etrst) writing 1 forces the external timer to re-start. writing 0 is ignored. read always returns zero. 7.13.4.6 external wdt counter high byte (ewdcntlhr) address offset: 09h bit r/w default description 7-0 r/w 00h external wdt counter high byte (ewdcntl) define the count number of high byte of the 16-bit count-down wdt. 7.13.4.7 external wdt low counter (ewdcntllr) address offset: 06h bit r/w default description 7-0 r/w 0fh external wdt low counter (ewdcntl) define the count number of 16-bit count-down wdt. 7.13.4.8 external wdt ke y register (ewdkeyr) address offset: 07h bit r/w default description 7-0 w - external wdt key (ewdkey) external wdt is re-started (touched) if 5c h is written to this register. writing with other values causes an external watchdog reset. this function is enabled by edwkeyen bit. read returns unpredictable value. 7.13.4.9 reset scratch register (rstscr) this register is used to detect the latest reset source. this register is obsolete and only used to be compatible with old it8510 firmware and should not be used in new firmware. address offset: 08h bit r/w default description 7-3 r/w 0b reserved 2 r/w 0b external wdt reset scratch bit (ewrstsb) this bit is reset by external wa tchdog reset and vstby power-up reset only. reading this bit returns the last written value. this register bit is obsolete. 1 r/w 0b internal wdt reset scratch bit ( iwrstsb) this bit is reset by internal wa tchdog reset and vstby power-up reset only. read this bit returns the last written value. this register bit is obsolete. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 258 it8511 e /te/ g bit r/w default description 0 r/w 0b warm reset scratch bit (wrstsb) this bit is reset by warm rese t and vstby power-up reset only. read this bit returns the last written value. this register bit is obsolete. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 259 ec domain functions 7.14 general control (gctrl) 7.14.1 overview this module controls ec function that doesn?t belong to the specified module. 7.14.2 features ? by module reset 7.14.3 functional description wait next clock rising: when writing 0 wnckr register, the r8 032tt will be paused and wait for a low to high transition of the internal 65.536khz clock. this may be useful to get a delay. for a loop that writing 0 to wnckr register for n time s, the delay value will be ( (n-1) / 65.536khz) to ( n / 65.536khz) e.g. consecutively writing 0 to wnckr register for 33 ti mes get 0.5ms delay with ?2.3% ~ +0.7% tolerance. consecutively writing 0 to wnckr register for 66 times get 1ms delay with ?0.8% ~ +0.7% tolerance. consecutively writing 0 to wnckr register for 132 times get 2ms delay with ?0.05% ~ +0.7% tolerance. 7.14.4 ec interface registers the following set of the registers is accessible only by ec. they are listed below and the base address is 2000h. table 7-25. ec view register map, gctrl 7 0 offset chip id byte 1 (echipid1) 00h chip id byte 2 (echipid2) 01h chip version (echipver) 02h reserved 03h identify input register (idr) 04h reserved 05h reset status (rsts) 06h reset control 1 (rstc1) 07h reset control 2 (rstc2) 08h reset control 3 (rstc3) 09h reserved 0ah wait next clock rising (wnckr) 0bh oscillator control r egister (osctrl) 0ch special control 1 (spctrl1) 0dh reset control host side (rstch) 0eh for a summary of the abbreviations used for the register type, see ?register abbrev iations and access rules?. 7.14.4.1 chip id byte 1 (echipid1) the content of this ec side register is the same as that of the chipid1 register in the host side. address offset: 00h bit r/w default description 7-0 r 85h chip id byte 1 (echipid1) this register contains the chip id byte 1. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 260 it8511 e /te/ g 7.14.4.2 chip id byte 2 (echipid2) the content of this ec side register is the same as that of the chipid2 register in the host side. address offset: 01h bit r/w default description 7-0 r 11h chip id byte 2 (echipid2) this register contains the chip id byte 2. 7.14.4.3 chip version (echipver) this register contains re vision id of this chip. the content of this ec side register is the same as that of the chipver regi ster in the host side. address offset: 02h bit r/w default description 7-0 r 10h chip version (echipver) 7.14.4.4 identify input register (idr) address offset: 04h bit r/w default description 7 r - identify input 7 (id7) 6 r - identify input 6 (id6) 5 r - identify input 5 (id5) 4 r - identify input 4 (id4) 3 r - identify input 3 (id3) 2 r - identify input 2 (id2) 1 r - identify input 1 (id1) 0 r - identify input 0 (id0) 7.14.4.5 reset status (rsts) address offset: 06h bit r/w default description 7-6 r/w 10b vcc detector option (vccdo) 10b: the vcc power status is detected by internal circuit. 00b: the vcc power status is treated as power-off. 01b: the vcc power status is treated as power-on. otherwise: reserved no matter which option is selected, the vcc power status is always recognized as power-off if lp cpd# input is level low. the vcc power status is used as inte rnal ?power good? signal to prevent current leakage while vcc is off. the current vcc power status can be read from vccpo bit in swctl1 cregister in 6.4.5.1 on page 86. intentionally toggling this field when vcc is supplied can reset logic vcc domain in ec. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 261 ec domain functions bit r/w default description 5 - - reserved 4 - - reserved 3 r/w 1b host global reset (hgrst) 0: the reset source of pnpcfg is rstpnp bit in rstch register and wrst#. 1: the reset source of pnpcfg are rs tpnp bit in rstch register, internal vcc status controlled by vccdo bit in rsts regsiter, lpcpd#, lpcrst# and wrst#. 2 r/w 1b global reset (grst) this bit controls whether to reset ec domain globally during internal/external watchdog reset. 0: only reset 8032; each module can be reset by rstc register 1: reset all the ec domain 1-0 r - last reset source (lrs) 00b, 01b: vstby power-up reset or warm reset 10b: internal watchdog reset 11b: external watchdog reset 7.14.4.6 reset control 1 (rstc1) write 1 to the selected bit(s) to possibly reset corresponding module(s). refer to vccdo field in rsts register to reset logic in vcc domain in ec. address offset: 07h bit r/w default description 7 w - reset smfi (rsmfi) 6 w - reset intc (rintc) 5 w - reset ec2i (rec2i) 4 w - reset kbc (rkbc) 3 w - reset swuc (rswuc) 2 w - reset pmc (rpmc) 1 w - reset gpio (rgpio) 0 w - reset pwm (rpwm) 7.14.4.7 reset control 2 (rstc2) write 1 to the selected bit(s) to possibly reset corresponding module(s). address offset: 08h bit r/w default description 7 w - reset adc (radc) 6 w - reset dac (rdac) 5 w - reset wuc (rwuc) 4 w - reset kbs (rkbs) 3 - - reserved 2 w - reset egpc (rexgpio) 1 w - reset cir (rcir) 0 w - reset tmkbc (rtmkbc) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 262 it8511 e /te/ g 7.14.4.8 reset control 3 (rstc3) write 1 to the selected bit(s) to possibly reset corresponding module(s). address offset: 09h bit r/w default description 7 w - reset ps/2 channel 4 (rps24) 6 w - reset ps/2 channel 3 (rps23) 5 w - reset ps/2 channel 2 (rps22) 4 w - reset ps/2 channel 1 (rps21) to reset the logic of ps/2 shared with all channels, write 1111b to bits 7-4 at the same time. 3 - - reserved 2 w - reserved 1 w - reset smbus channel 2 (rsmb2) 0 w - reset smbus channel 1 (rsmb1) to reset the logic of smbus shared with all channels, write 1111b to bits 3-0 at the same time. writing 0011b is reserved. 7.14.4.9 wait next clock rising (wnckr) address offset: 0bh bit r/w default description 7-0 w - wait next 65k rising (wn65k) writing 00h to this register and the r8032tt program counter will be paused until the next low to high trans ition of 65.536khz clock. writing other values is reserved. 7.14.4.10 oscillator cont rol register (osctrl) address offset: 0ch bit r/w default description 7-1 - - reserved 0 r/w 1b oscillator enable (oscen) 1b: 32.768 khz oscillator will keep r unning if vbs/vstby power = on/off 0b: 32.768 khz oscillator in this case 7.14.4.11 special control 1 (spctrl1) address offset: 0dh bit r/w default description 7 r/w 0b p80l enable (p80len) this bit will be set if 1 is written and cl eared if 1 is written or there is a vcc on->off transition. this bit is suppli ed by the vbs power and only reset by vbs power-up reset. refer to section 6.8.3.4 p80l on page 119. 1b: enable p80l function. 0b: otherwise free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 263 ec domain functions bit r/w default description 6 r/w 0b accept port 80h cycle (acp80) this bit will be set if 1 is written and cl eared if 1 is written or there is a vcc on->off transition. this bit is suppli ed by the vbs power and only reset by vbs power-up reset. refer to section 6.8.3.4 p80l on page 119. 1b: the host lpc i/o cycle with address 80h will be accepted by ec. if p80len is set, enabling this bit to guarantee lpc i/o port 80h data can be latched even there is a transaction cycle to bram or ec2i->rtc in ec side. 0b: otherwise 5-2 - - reserved 1-0 r/w 00b i2ec control (i2ecctrl) 00b: i2ec is disabled 10b: i2ec is read-only. 11b: i2ec is read-write. 01b: reserved refer to section 7.17.3.2 ec memory snoop (ecms)on page 280. 7.14.4.12 reset control host side (rstch) address offset: 0eh bit r/w default description 7-3 - - reserved 2 w - reset pnpcfg (rstpnp) 1-0 - - reserved free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 264 it8511 e /te/ g free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 265 ec domain functions 7.15 battery-backed sram (bram) 7.15.1 overview this module provides 256 bytes of battery-b acked memory area and power-switching circuit. 7.15.2 features ? 256 bytes of battery-backed sram shared with rtc sram ? power-switching circuit 7.15.3 functional description this module provides 256 bytes of battery-backed sram for data-saving function shared with host module rtc figure 7-34. bram mapping diagram . rtc bank0/1 timer function sram bank 1 sram bank 0 i-bus ec-bus 22ffh 2200h 15ffh physical 256b srrm 15f0h bram pmc 00h 7fh 00h 7fh rtc bank 1 rtc bank 0 00h 7fh 00h 7fh ec2i for such timer relative registers (e.g. bank 0 offset 00h), ec2i can not access sram content in these registers. the firmware can not access timer relative registers in rtc via bram but sram only. pmc2ex/h p80l pmc2ex/ec mbx/ec read/write bram read/write mbx/h read/write rtc read/write(from host lpc/ec2i) p80l write 7.15.3.1 p80l if this function is enabled by p80len bit in spctrl1 regi ster, lpc i/o port 80h written data will be latched into sram of rtc bank 1. the data may fail to latch data if there is a transaction cy cle to bram or ec2i->rtc in the ec side at the same time unless acp80 bit in spctrl1 register is set, wh ich guarantees written data is latched into sram by issuing long wait sync on host lpc bus. the 7-bit destination address range in rtc bank 1 is determined by p80lb, p80le regi ster in the host side, which constructs a queue. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 266 it8511 e /te/ g p80lb: it indicates the start index of the queue. readable/writable. p80le: it indicates the end index of the queue. readable/writable. p80lc: it indicates the current index of the queue. read-only. these three registers are supplied by vbs power and not affected by vcc status. whenever written data is latched, p 80lc increases one. if it reaches p80le (queue end), it will wrap back to p80lb (queue begin). 7.15.4 ec interface registers the registers of the battery-backed sram ar e listed below. the base address is 2200h. table 7-25. ec view register map 7 0 offset sram byte n registers (sbt0) 00h ? ? sram byte n registers (sbt255) ffh 7.15.4.1 sram byte n registers (sbtn, n= 0-255). address offset: 00h ? ffh for byte 0 ? byte 255 bit r/w default description 7-0 r/w - sram data (sd) after data is written to this register , it will be saved in the corre sponding memory space. when this register is read, the data saved in corresponding memory space can be read. for example, when data is written to the sram byte 0 register, it will be saved in the memory space 2200h. when the sram byte 63 regist er is read, the data saved in memory space 223fh can be read. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 267 ec domain functions 7.16 consumer ir (cir) 7.16.1 overview the cir module is used in the consumer remote c ontrol equipment, and is a programmable amplitude shift keyed (ask) serial communication pr otocol. by adjusting frequencies, baud ra te divisor values and sensitivity ranges, cir registers are able to support the major pr otocols such as rc-5, nec, and recs-80. new protocols can be supported by programming the software driver. 7.16.2 features ? supports 1 cir channels ? supports 28 khz ~ 57 khz (low frequency) or 400 kh z ~ 500 khz (high frequency) carrier transmission ? the baud rate up to 115200 bps (high frequency) ? demodulation optional ? supports transmission run-length encoding and deferral functions ? supports one 32-byte fifo for dat a transmission or data reception figure 7-35. simplified diagram interrupt gen. demodulator deserialization receiver fifo modulator serialization transmitter fifo transmitter receiver 00000000 11110000 interface & registers baud rate gen. bus interface 7.16.3 functional description the cir channel consists of two main elements, tran smitter and receiver. the transmitter transmits data to the fifo, processes the fifo data by serialization, m odulation and sends out the data through the led device. the receiver is responsible for receiving the fifo data, processing data by demodul ation and deserialization, and storing data into the receiver fifo. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 268 it8511 e /te/ g 7.16.3.1 transmit operation the transmit data formats written to the transmitter fi fo differ from one another with respect to different communication protocols. only physical layer functions ar e provided in this module. the data written to the transmitter fifo will be exactly serialized from lsb to msb, modulated with the carri er frequency and sent to the pad output. the communication commands are decoded by software. before the data transmission can be started, code byte write operations must be performed to the transmitter fifo c0dr. the bit txrle in the c0tcr should be set to ?1? before the run-length decode data can be written into the transmitter fifo. the bit width of the serializ ed bit string is determined by programming the baud rate divisor registers, c0bdlr and c0bdhr. when bits hcf s and cfq[4:0] in the c0cfr are set, either the high-speed or low-speed carrier range is selected, and the corresponding carrier frequency will also be determined. bits txmpm[1:0] and txmpw[ 2:0] in the c0tcr specify the pul se numbers in a bit width and the required duty cycles of the carrier pulse according to t he communication protocol. only a logic 0 can activate the transmitter led in the format of a series of modulating pulses. 7.16.3.2 receive operation the receiver function is enabled if bit rxen in the c0r cr is set to ?1?. either demodulated or modulated rx# signal is loaded into the receiver fifo, and bit rxe nd in the c0rcr determines how the demodulation logic should be used. when bits hcfs and cfq[4:0] in the c0cfr are set, either t he high-speed or low-speed carrier range is selected, and the corresponding carrier fr equency will also be determined. bit rxact in the c0rcr is set to ?1? if the serial data or the selected carrier is incoming, and the sampled data will then be kept in the receiver fifo. write ?1? to clear bit rxact and then stop operation of receiver fifo; write ?0? to bit rxen to disable all the receiver functions. it is st rongly suggested that software clear rxact every time when you will change the expected carrier frequency. 7.16.3.3 wakeup(power on) controller programming sequence software power-off is performed by setting the resetting bits of rcrst and wcrst to ?1?, and the cirpois bit to ?0? at the initial state in the c0wps register. when the system is on, users can rese t the read/write counter to 0 at any time. however, if users need to save codes in to 20 bytes in the power-switch-code area, the best way is to reset the write counter first sinc e users may not know the value in the c ounter. therefore, it is possible that users will make a mistake when saving the codes. user s can also reset the read counter before reading the code in the power-switch-code area. be fore users perform the power-off functi on, it is necessary to save the correct length into the c0wcl register and the coded in to the power-switch-code area or the power-on function will not function normally. the cirpois bit is set to one w hen the data received by cir for first time matches the code data on the power-switch-code area. the cirp ois bit is toggled when the data received again by cir matches the code data on t he power-switch-code area. note: if the system designer needs to use the remote power-on function, the designer should program the relative receive registers to some proper values via software before shutdown. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 269 ec domain functions 7.16.4 ec interface registers the ec interface registers are listed bel ow. the base address for cir is 2300h. table 7-28. ec view register map, cir 7 0 offset cir data register (c0dr) 00h cir master control register (c0mstcr) 01h cir interrupt enable register (c0ier) 02h cir interrupt identificat ion register (c0iir) 03h cir carrier frequency register (c0cfr) 04h cir receiver control register (c0rcr) 05h cir transmitter contro l register (c0tcr) 06h cir slow clock control register (c0sck) 07h cir baud rate divisor low byte register (c0bdlr) 08h cir baud rate divisor high byte register (c0bdhr) 09h cir transmitter fifo status register (c0tfsr) 0ah cir receiver fifo status register (c0rfsr) 0bh cir wakeup code length register (c0wcl) 0dh cir wakeup code read/write register (c0wcr) 0eh cir wakeup power control/status register (c0wps) 0fh 7.16.4.1 cir data register (c0dr) the c0r, an 8-bit register, is the data port for cir. data is transmitted and received through this register. note: reading an empty fifo w ill return a default value, ff . address offset: 00h bit r/w default description 7-0 r/w - cir fifo data (cfd[7:0]) writing data to this register causes data to be written to the transmitter fifo. reading data from this register causes data to be received from the receiver fifo. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 270 it8511 e /te/ g 7.16.4.2 cir master control register (c0mstcr) the c0mtcr, an 8-bit register, is used to control cir functions. address offset: 01h bit r/w default description 7-6 - - reserved 5 r/w 0 internal loopback select (ilsel) this bit is used to determine the internal loopback source. when this bit is set to ?0?, the serial data is the internal loopback source. when this bit is set to ?1?, the mo dulated data is the internal loopback source. 4 r/w 0 internal loopback enable (ile) this bit is used to execute internal loopback for test and must be ?0? in normal operation. when this bit is set to ?0?, the internal loopback mode is disabled. when this bit is set to ?1?, the internal loopback mode is enabled. 3-2 r/w 0 fifo threshold level (fifotl) these two bits are used to set the fifo threshold level. the fifo length is 32 bytes for tx or rx function (i le = 0) in normal operation, and 16 bytes for both tx and rx in the in ternal loopback mode (ile = 1). 16-byte mode 32-byte mode 00 1 1 (default) 01 3 7 10 7 17 11 13 25 1 r/w 0 fifo clear (fifoclr) writing a ?1? to this bit clears fifo. this bit is then cleared to ?0? automatically. 0 r/w 0 reset (reset) the function of this bit is software reset. writing a ?1? to this bit resets the registers of c0r, c0stcr, c0ier, c0iir, c0cfr, c0tcr, c0tfsr and c0rfsr. this bit is then cleared to ?0? automatically. 7.16.4.3 cir interrupt enable register (c0ier) the c0ier, an 8-bit register, is used to enable the cir interrupt request. address offset: 02h bit r/w default description 7 r/w 0 interrupt enable function control (iec) this bit is used to control the interrupt enabled function. set this bit to ?1? to enable the interrupt request for cir. set this bit to ?0? to disable the interrupt request for cir. 6 - 3 - - reserved 2 r/w 0 receiver fifo overrun interrupt enable (rfoie) this bit is used to control receiv er fifo overrun interrupt request. set this bit to ?1? to enable receiv er fifo overrun interrupt request. set this bit to ?0? to disable rece iver fifo overrun interrupt request. 1 r/w 0 receiver data available interrupt enable (rdaie) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 271 ec domain functions bit r/w default description this bit is used to enable receiver data available interrupt request. the receiver will generate this interrupt when the data available in fifo exceeds fifo threshold level. set this bit to ?1? to enable receiv er data available interrupt request. set this bit to ?0? to disable receiv er data available interrupt request. 0 r/w 0 transmitter low data level interrupt enable (tldlie) this bit is used to enable transmitter low data level interrupt request. the transmitter will generate this in terrupt when the data available in fifo is less than the fifo threshold level. set this bit to ?1? to enable transmi tter low data level interrupt request. set this bit to ?0? to disable transm itter low data level interrupt request. 7.16.4.4 cir interrupt identi fication register (c0iir) the c0iir, an 8-bit register, is used to identify the pending interrupt. address offset: 03h bit r/w default description 7 ro 1 no interrupt pending (nip) this bit will be set to ?1? if no interrupt is pending. 6 - 3 - - reserved 2 ro 0 receiver fifo overrun interrupt (rfoi) this bit will be set to ?1? if receiver fi fo overruns. 1 ro 0 receiver data available interrupt (rdai) this bit will be set to ?1? when the data available in the receiver fifo exceeds the fifo threshold level. 0 ro 0 transmitter low data level interrupt (tldli) this bit will be set to ?1? when the data available in the transmitter fifo is less than the fifo threshold level. 7.16.4.5 cir carrier fre quency register (c0cfr) the cxcfr, an 8-bit register, is used to determine the carrier frequency. address offset: 04h bit r/w default description 7-6 - - reserved 5 r/w 0 high-speed carrier frequency select (hcfs) this bit is used to select whether the carrier frequency is at a high speed or low speed. 0: 30-58 khz (default) 1: 400-500 khz 4-0 r/w 01011 carrier frequency (cfq[4:0]) these five bits are used to determine the modulation carrier frequency. see table 7-26. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 272 it8511 e /te/ g table 7-26. modulation carrier frequency cfq low frequency (hcfs =0) high frequency (hcfs = 1) 00000 27 khz - 00001 28 khz - 00010 29 khz - 00011 30 khz 400 khz 00100 31 khz - 00101 32 khz - 00110 33 khz - 00111 34 khz - 01000 35 khz 450 khz 01001 36 khz - 01010 37 khz - 01011 38 khz (default) 480 khz (default) 01100 39 khz - 01101 40 khz 500 khz 01110 41 khz - 01111 42 khz - 10000 43 khz - 10001 44 khz - 10010 45 khz - 10011 46 khz - 10100 47 khz - 10101 48 khz - 10110 49 khz - 10111 50 khz - 11000 51 khz - 11001 52 khz - 11010 53 khz - 11011 54 khz - 11100 55 khz - 11101 56 khz - 11110 57 khz - 11111 58 khz - free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 273 ec domain functions 7.16.4.6 cir receiver cont rol register (c0rcr) the c0rcr, an 8-bit register, is used to control the cir receiver. address offset: 05h bit r/w default description 7 r/w 0 receiver enable (rxen) this bit is used to enable the receiver function. set this bit to ?1? to enable the receiver function. set this bit to ?0? to disable the receiver function. when the receiver function is ena bled, rxact will be active if the selected carrier frequency is received. 6 - - reserved 5 r/w 0 receiver data without sync. (rdwos) this bit is used to control the sync. logic for receiving data. set this bit to ?1? to obtain the receiving data without sync. logic. set this bit to ?0? to obtain the receiving data in sync. logic. 4 r/w 0 receiver demodulation enable (rxend) this bit is used to control the receiver demodulation logic. set this bit to ?1? to enable the receiver demodulation logic. set this bit to ?0? to disable the receiver demodulation logic. set this bit to ?1? to the receiver device to demodulate the correct carrier. 3 r/wc 0 receiver active (rxact) this bit is used to control the receiver operation. this bit is set to ?0? when the receiver is inactive. this bit is set to ?1? when the receiver detects a pulse (rxend=0) or pulse-train (rxend=1) with the correct carrier frequency. the receiver then starts to sample the input data when receiver active is set. writing a ?1? to this bit to clear the receiver active condition and make the receiver enter an inactive mode. 2-0 r/w 001 receiver demodulation carrier range (rxdcr[2:0]) these three bits are used to set the tolerance of the receiver demodulation carrier frequency. see table 7-27 and table 7-28. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 274 it8511 e /te/ g table 7-27. receiver demodulation low frequency (hcfs = 0) rxdcr 001 010 011 100 101 110 cfq min. max. min. max. min. max. min. max. min. max. min. max. (hz) 00001 26.25 29.75 24.5 31.5 22.75 33.25 21 35 19.25 36.75 17.5 38.5 28k 00010 27.19 30.81 25.38 32.63 23.56 34.44 21.75 36.25 19.94 38.06 18.13 39.88 29k 00011 28.13 31.88 26.25 33.75 24.38 35.63 22.5 37.5 20.63 39.38 18.75 41.25 30k 00100 29.06 32.94 27.13 34.88 25.19 36.81 23.25 38.75 21.31 40.69 19.38 42.63 31k 00101 30 34 28 36 26 38 24 40 22 42 20 44 32k 00110 30.94 35.06 28.88 37.13 26.81 39.19 24.75 41.25 22.69 43.31 20.63 45.38 33k 00111 31.88 36.13 29.75 38.25 27.63 40.38 25.5 42.5 23.38 44.63 21.25 46.75 34k 01000 32.81 37.19 30.63 39.38 28.44 41.56 26.25 43.75 24.06 45.94 21.88 48.13 35k 01001 33.75 38.25 31.5 40.5 29.25 42.75 27 45 24.75 47.25 22.5 49.5 36k 01010 34.69 39.31 32.38 41.63 30.06 43.94 27.75 46.25 25.44 48.56 23.13 50.88 37k 01011 35.63 40.38 33.25 42.75 30.88 45.13 28.5 47.5 26.13 49.88 23.75 52.25 38k 01100 36.56 41.44 34.13 43.88 31.69 46.31 29.25 48.75 26.81 51.19 24.38 53.63 39k 01101 37.5 42.5 35 45 32.5 47.5 30 50 27.5 52.5 25 55 40k 01110 38.44 43.56 35.88 46.13 33.31 48.69 30.75 51.25 28.19 53.81 25.63 56.38 41k 01111 39.38 44.63 36.75 47.25 34.13 49.88 31.5 52.5 28.88 55.13 26.25 57.75 42k 10000 40.31 45.69 37.63 48.38 34.94 51.06 32.25 53.75 29.56 56.44 26.88 59.13 43k 10001 41.25 46.75 38.5 49.5 35.75 52.25 33 55 30.25 57.75 27.5 60.5 44k 10010 42.19 47.81 39.38 50.63 36.56 53.44 33.75 56.25 30.94 59.06 28.13 61.88 45k 10011 43.13 48.88 40.25 51.75 37.38 54.63 34.5 57.5 31.63 60.38 28.75 63.25 46k 10100 44.06 49.94 41.13 52.88 38.19 55.81 35.25 58.75 32.31 61.69 29.38 64.63 47k 10101 45 51 42 54 39 57 36 60 33 63 30 66 48k 10110 45.94 52.06 42.88 55.13 39.81 58.19 36.75 61.25 33.69 64.31 30.63 67.38 49k 10111 46.88 53.13 43.75 56.25 40.63 59.38 37.5 62.5 34.38 65.63 31.25 68.75 50k 11000 47.81 54.19 44.63 57.38 41.44 60.56 38.25 63.75 35.06 66.94 31.88 70.13 51k 11001 49.18 54.55 46.88 57.69 44.78 61.22 42.86 65.22 41.1 69.77 39.47 75 52k 11010 49.69 56.31 46.38 59.63 43.06 62.94 39.75 66.25 36.44 69.56 33.13 72.88 53k 11011 50.63 57.38 47.25 60.75 43.88 64.13 40.5 67.5 37.13 70.88 33.75 74.25 54k 11100 51.56 58.44 48.13 61.88 44.69 65.31 41.25 68.75 37.81 72.19 34.38 75.63 55k 11101 52.5 59.5 49 63 45.5 66.5 42 70 38.5 73.5 35 77 56k 11110 53.44 60.56 49.88 64.13 46.31 67.69 42.75 71.25 39.19 74.81 35.63 78.38 57k free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 275 ec domain functions table 7-28. receiver demodulation high frequency (hcfs = 1) rxdcr 001 010 011 100 101 110 cfq min. max. min. max. min. max. min. max. min. max. min. max. (khz) 00011 375 425 350 450 325 475 300 500 275 525 250 550 400k 01000 421.9 478.1 393.8 506.3 365.6 534.4 337.5 562.5 309.4 590.6 281.3 618.8 450k 01011 450 510 420 540 390 570 360 600 330 630 300 660 480k 01011 468.8 531.3 437.5 562.5 406.3 593.8 375 625 343.8 656.3 312.5 687.5 500k 7.16.4.7 cir transmitter control register (c0tcr) the c0tcr, an 8-bit register, is used to control the transmitter. address offset: 06h bit r/w default description 7 - - reserved 6 r/w 0 transmitter run length enable (txrle) this bit controls the transmitter run length encoding/decoding mode, which condenses a series of ?1? or ?0? into one byte according to the value stored in bit 7 and the value stored in bits 6-0 minus 1. if this bit is set to ?1?, the transmitter run length mode is enabled. if this bit is set to ?0?, the transmitter run length mode is disabled. 5 r/w 0 transmitter deferral (txendf) this bit is used to avoid the transmitter underrun condition. when this bit is set to ?1?, the tran smitter fifo data will be kept until the transmitter time-out condition occurs or when fifo is full. 4 - 3 r/w 00 transmitter modulation pulse mode (txmpm[1:0]) these two bits are used to define the transmitter modulation pulse mode. txmpm[1:0] modulation pulse mode 00 c_pls mode (default) pulses are generated continuously for the entire logic 0 bit time. 01 8_pls mode 8 pulses are generated for each logic 0 bit. 10 6_pls mode 6 pulses are generated for each logic 0 bit. 11 reserved 2-0 r/w 100 transmitter modulation pu lse width (txmpw[2:0]) these three bits are used to set tran smitter modulation pulse width. the duty cycle of the carrier will be deter mined according to the settings of carrier frequency and the selection of transmitter modulation pulse width. txmpw[2:0] hcfs= 0 hcfs= 1 000 reserved reserved 001 reserved reserved 010 6 s 0.7 s 011 7 s 0.8 s free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 276 it8511 e /te/ g bit r/w default description 100 8.7 s 0.9 s (default) 101 10.6 s 1.0 s 110 13.3 s 1.16 s 111 reserved reserved 7.16.4.8 cir slow clock control register (c0sck) the c0sck, an 8-bit register, is used to select the sl ow clock source of 32.768k or 1.8432m hz for operating with low power and can wake up ec from the sleep mode. in the sleep mode, cir only can receive serial data up to 2k hz when 1. c0bdlr = 01h ( max baud rate = 32.768k/16) 2. c0bdhr = 00h 3. scks = 1b 4. demodulation must be disabled. note: prior to set up wakeup code and receive enable before enter sleep mode (set scks bit in c0sck register). if firmware needs to compare received data st ored in the c0dr register with wakeup code(written into c0wcr previously), scks has to be set to zero befor ehand after wakeup code has received completely. address offset: 07h bit r/w default description 7 r 1 dll lock (dllock) this bit is available when dll1p8e = 1. 1: 1.8432m hz dll in the locked state 0: 1.8432m hz dll in the unlocked state 6-4 r/w 0 baud rate count mode (brcm) these three bits are used to select the baud rate counter number. they only need to be set when demodulation is disabled and scks = 1, dll1p8e =0. bits 6-4 baud counter 000 16 (488us) 001 14 (427us) 010 15 (457us) 011 18 (549us) 3 r/w 0 dll test enable (dllte) 1: set dll to the test mode. 0: dll in the normal mode 2 r/w 0 dll 1.8432m enable (dll1p8e) 1: dll 1.8432m hz enabled 0: dll 1.8432m hz disabled the slow clock selects 32.768k hz when this bit is set 0 and scks =1. the slow clock selects 1.8432m hz when this bit is set 1 and scks =1. 1 r/wc 0 txd clock gating (txdckg) 1: cir transmitter clock source gating 0: cir transmitter clock source not gating 0 r/w 0 slow clock select (scks) 1: select the slow clock source (32.768k or dll 1.8432m hz) for cir receiver to receive serial data which is input to crx when rxend = 0, rdwos =1, and rxen = 1. 0: unselect slow clock as the receiver clock source. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 277 ec domain functions 7.16.4.9 cir baud rate divisor low byte register (c0bdlr) the c0bdlr, an 8-bit register, is used to program the cir baud rate clock. address offset: 08h bit r/w default description 7-0 rw 00000000 baud rate divisor low byte (brdl[7:0]) these bits are the low byte of the register and used to divide the baud rate clock. 7.16.4.10 cir baud rate divisor high byte register (c0bdhr) the c0bdhr, an 8-bit register, is used to program the cir baud rate clock. address offset: 09h bit r/w default description 7-0 rw 00000000 baud rate divisor high byte (brdh[7:0]) these bits are the high byte of the register and used to divide the baud rate clock. baud rate divisor = 115200/baud rate ex1: 2400bps ? 115200 /2400 = 48 ? 48(d) = 0030 (h) c0bdhr = 00(h), c0bdlr = 30(h) ex2: bit width = 0.565 ms ? 1770 bps ? 115200/1770 = 65 (d) = 0041 (h) c0bdhr = 00(h), b0bdlr = 0041(h) 7.16.4.11 cir transmitter fifo status register (c0tfsr) the c0tfsr, an 8-bit register, provides the status information of transmitter fifo. address offset: 0ah bit r/w default description 7 - 6 - - reserved 5 - 0 ro 000000 transmitter fifo byte count (txfbc[5:0]) return the number of bytes left in transmitter fifo. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 278 it8511 e /te/ g 7.16.4.12 cir receiver fifo status register (c0rfsr) the c0rfsr, an 8-bit register, provides t he status information of receiver fifo. address offset: 0bh bit r/w default description 7 ro 0 receiver fifo time-out (rxfto) this bit will be set to ?1? when the receiver fifo time-out condition occurs. the conditions required for the occurrence of receiver fifo time-out include the followings: a. at least one byte data queued in received fifo for more than 64 ms. b. the receiver has been inactive (rxact=0) for over 64ms. c. more than 64 ms have elapsed since the last byte is read from receiver fifo by cpu. 6 - - reserved 5-0 ro 000000 receiver fifo byte count (rxfbc[5:0]) return the number of bytes left in receiver fifo. 7.16.4.13 cir wakeup code length register (c0wcl) the c0wcl, an 8-bit register, keeps the value of the va lid code length minus 1 in the power-switch-code area. the wakeup controller in cir module compares the received code with the code saved in the power-switch-code area of wakeup controller c0wcl - 1 bytes. address offset : 0dh bit r/w default description 7-6 - 00 reserved 5-0 r/w 111111 cir wakeup code length (wcl[5:0]) the value in this register is the valid code length minus 1. for instance, when c0wcl is equal to 0, the valid code length is 1. 7.16.4.14 cir wakeup code re ad/write register (c0wcr) the c0wcr, an 8-bit register, is the read/write port for accessing 20 wakeup code bytes. these bytes are accessed sequentially according to t he read counter or write counter. address offset : 0eh bit r/w default description 7-0 r/w 0 cir wakeup code read/write register (wcr[7:0]) a port is for accessing 20 wakeup code bytes. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 279 ec domain functions 7.16.4.15 cir wakeup power control/status register (c0wps) the c0wps, an 8-bit register, is used to record the power-on source, and two control bits are used to reset the read or write counter for accessing 20 code bytes through c0wcr. address offset : 0fh bit r/w default description 7-6 - 00 reserved 5 r/w 0 cir wakeup code writing counter resetting bit (wcrst) this bit is used to reset the writing count er to 1, and it is where the first byte saved in the power-switch -code area. after the counter is reset, this bit will be reset to 0. 4 r/w 0 cir wakeup code reading counter resetting bit (rcrst) this bit is used to reset the reading counter to 1, and it is where the first byte is saved in the power-switch-code area. 3 - 00 reserved 2 r/w 0 cir power on/off interrupt identification (cirpoii) this bit is set to denote that the ci r power on/off interrupt(int15) event has occurred . writing 0 clears this identification bit, and writing 0 is ignored. 1 r 0 cir power on/off interrupt status (cirpois) this bit is set to denote that the cir power on request event has been generated by the cir remote-contro ller-pressed power on/off key. setting 0 denotes that the cir power off request event has been generated by the cir remote-controller-pressed power on/off key. 0 r/w 0 cir power on/off status inte rrupt enable (cirposie) this bit is set to enable the cir power on/off interrupt event(int15), which is generated by the cir remote-controller-pressed power on/off key. setting 0 to disable interr upt by the power on/off event. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 280 it8511 e /te/ g 7.17 debugger (dbgr) 7.17.1 overview this ec side module provides three 18-bit 8032 rom trigger addresses and issues an int0# and ec memory snoop (ecms). 7.17.2 features ? 3 trigger addresses ? ec memory snoop (ecms = i2ec + d2ec) 7.17.3 functional description 7.17.3.1 rom address match interrupt the trigger address, where an instruction is constructed by one, two or three bytes, must be the first byte of each instruction. int0rm is set when the trigger address matches the 8032 pr ogram counter except that the trigger address is equal to zero. if parallel port cable is detected by internal hardware strap, this function is disabled. note that dbgr module is clock-gated in default and cann ot work until 0 is written to dbgrcg bit in the cgctrl3r register. 7.17.3.2 ec memory snoop (ecms) ecms is available through one of the two ways 1. i2ec (i-bus to ec memory) local machine snoops ec memory through the lpc i/o cycle. 2. d2ec (dbgr to ec memory) remote machine snoops ec memory through epp cycle. i2ec/d2ec utility is provided by ite. i2ec is not enabled until its controlled regist er in the ec side register is written. i2ec can be configured as read-only for all targets. if d2ec is enabled by the utility, i2ec will be disabled until reset. i2ec/d2ec will not affect any register content of read-clear registers. the writing action of i2ec/d2ec to f/f based register is okay; however, the result of writing to non-f/f based register is not expected. such regist ers may be write-clear, or writing to start internal state-machine, etc. table 7-29. i2ec/d2ec accessable targets i2ec d2ec uc external memory (except bram) r/w controlled by i2ecctrl field in spctrl1 reg. r/w uc external memory - bram not accessable ro free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 281 ec domain functions 7.17.4 ec interface registers the following set of the registers is accessible only by the ec. they are listed below and the base address is 2500h. table 7-30. ec view register map, dbgr 7 0 offset trigger 1 address low byte register (bka1l) 10h trigger 1 address middle byte register (bka1m) 11h trigger 1 address high byte register (bka1h) 12h trigger 2 address low byte register (bka1l) 13h trigger 2 address middle byte register (bka1m) 14h trigger 2 address high byte register (bka1h) 15h trigger 3 address low byte register (bka1l) 16h trigger 3 address middle byte register (bka1m) 17h trigger 3 address high byte register (bka1h) 18h for a summary of the abbreviations us ed for the register type, see ?register abbreviations and access rules?. 7.17.4.1 trigger 1 address low byte register (bka1l) address offset: 10h bit r/w default description 7-0 w 00h trigger 1 address (bk1a7-0) 7.17.4.2 trigger 1 address middle byte register (bka1m) address offset: 11h bit r/w default description 7-0 w 00h trigger 1 address (bk1a15-8) 7.17.4.3 trigger 1 address hi gh byte register (bka1h) address offset: 12h bit r/w default description 7-2 - 00h reserved 1-0 w 00b trigger 1 address (bk1a17-16) 7.17.4.4 trigger 2 address low byte register (bka2l) address offset: 13h bit r/w default description 7-0 w 00h trigger 2 address (bk2a7-0) 7.17.4.5 trigger 2 address middle byte register (bka2m) address offset: 14h bit r/w default description 7-0 w 00h trigger 2 address (bk2a15-8) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 282 it8511 e /te/ g 7.17.4.6 trigger 2 address hi gh byte register (bka2h) address offset: 15h bit r/w default description 7-2 - 00h reserved 1-0 w 00b trigger 2 address (bk2a17-16) 7.17.4.7 trigger 3 address low byte register (bka3l) address offset: 16h bit r/w default description 7-0 w 00h trigger 3 address (bk3a7-0) 7.17.4.8 trigger 3 address middle byte register (bka3m) address offset: 17h bit r/w default description 7-0 w 00h trigger 3 address (bk3a15-8) 7.17.4.9 trigger 3 address hi gh byte register (bka3h) address offset: 18h bit r/w default description 7-2 - 00h reserved 1-0 w 00b trigger 3 address (bk3a17-16) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 283 ec domain functions 7.18 parallel port (pp) 7.18.1 overview it8511 supports ieee 1284 parallel port interface to a llow in-system programming regardless of running firmware code. 7.18.2 features ? isp via parallel port interf ace on existed kbs connector ? fast flash programming with software provided by ite ? programming software supports epp/spp mode 7.18.3 functional description 7.18.3.1 kbs connection with parallel port connector figure 7-36. parallel port female 25-pin connector ksi3/slin# ksi1/afd# ksi2/init# ksi0/stb# kso11/err# kso12/slct kso9/busy kso10/pe kso7/pd7 kso8/ack# kso6/pd6 kso5/pd5 kso4/pd4 kso3/pd3 kso0/pd0 kso1/pd1 kso2/pd2 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ground ground ground ground ground ground ground ground ksi4 ksi5 1k 1k 7.18.3.2 in-system programming operation in-system programming takes place when vstby is supp lied (other power is don?t-care) and both ec chip and the flash are soldered on pcb. parallel port interface oc cupies the same interface pins as kbs to use the existing kbs connector. it8511 enters in-system programming mode if it detects parallel port signals when vstby power on or hardware strap pin ppen is pulled high. it can be disabled by ovrppk/ovrppen bit in the ksictrlr register if parallel port cable is detected by internal hardware st rap, the following functions will be disabled. 1. rom address match interrupt 2. internal/external watchdog free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 284 it8511 e /te/ g this page is intentionally left blank. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 285 register list 8. register list section register name pge addr 6.2.2 super i/o configuration registers 43 6.2.2.1 logical device number (ldn) 43 07h 6.2.2.2 chip id byte 1 (chipid1) 43 20h 6.2.2.3 chip id byte 2 (chipid2) 43 21h 6.2.2.4 chip version (chipver) 43 22h 6.2.2.5 super i/o control register (sioctrl) 43 23h 6.2.2.6 super i/o irq configuration register (sioirq) 44 25h 6.2.2.7 super i/o general purpose register (siogp) 44 26h 6.2.2.8 super i/o power mode register (siopwr) 44 2dh 6.2.4 system wake-up control (swuc) configuration registers 47 6.2.4.1 logical device activate register (lda) 48 30h 6.2.4.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 48 60h 6.2.4.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 48 61h 6.2.4.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 48 62h 6.2.4.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 48 63h 6.2.4.6 interrupt request number and wake-up on irq enable (irqnumx) 48 70h 6.2.4.7 interrupt request type select (irqtp) 48 71h 6.2.5 kbc / mouse interface configuration registers 49 6.2.5.1 logical device activate register (lda) 49 30h 6.2.5.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 49 60h 6.2.5.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 49 61h 6.2.5.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 49 62h 6.2.5.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 50 63h 6.2.5.6 interrupt request number and wake-up on irq enable (irqnumx) 50 70h 6.2.5.7 interrupt request type select (irqtp) 50 71h 6.2.6 kbc / keyboard interface configuration registers 50 6.2.6.1 logical device activate register (lda) 50 30h 6.2.6.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 50 60h 6.2.6.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 51 61h 6.2.6.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 51 62h 6.2.6.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 51 63h 6.2.6.6 interrupt request number and wake-up on irq enable (irqnumx) 51 70h 6.2.6.7 interrupt request type select (irqtp) 51 71h 6.2.7 shared memory/flash interface (smfi) configuration registers 51 6.2.7.1 logical device activate register (lda) 52 30h 6.2.7.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 52 60h 6.2.7.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 52 61h 6.2.7.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 52 62h 6.2.7.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 52 63h 6.2.7.6 interrupt request number and wake-up on irq enable (irqnumx) 52 70h 6.2.7.7 interrupt request type select (irqtp) 52 71h 6.2.7.8 shared memory configuration register (shmc) 53 f4h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 286 it8511 e /te/ g 6.2.8 real time clock (rtc) configuration registers 53 6.2.8.1 logical device activate register (lda) 53 30h 6.2.8.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 53 60h 6.2.8.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 54 61h 6.2.8.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 54 62h 6.2.8.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 54 63h 6.2.8.6 interrupt request number and wake-up on irq enable (irqnumx) 54 70h 6.2.8.7 interrupt request type select (irqtp) 54 71h 6.2.8.8 ram lock register (rlr) 54 f0h 6.2.8.9 date of month alarm register offset (domao) 55 f1h 6.2.8.10 month alarm register offset (monao) 55 f2h 6.2.8.11 p80l begin index (p80lb) 55 f3h 6.2.8.12 p80l end index (p80le) 55 f4h 6.2.8.13 p80l current index (p80lc) 55 f5h 6.2.9 power management i/f channel 1 configuration registers 56 6.2.9.1 logical device activate register (lda) 56 30h 6.2.9.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 56 60h 6.2.9.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 56 61h 6.2.9.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 56 62h 6.2.9.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 57 63h 6.2.9.6 interrupt request number and wake-up on irq enable (irqnumx) 57 70h 6.2.9.7 interrupt request type select (irqtp) 57 71h 6.2.10 power management i/f channel 2 configuration registers 57 6.2.10.1 logical device activate register (lda) 57 30h 6.2.10.2 i/o port base address bits [15:8] for descriptor 0 (iobad0[15:8]) 58 60h 6.2.10.3 i/o port base address bits [7:0 ] for descriptor 0 (iobad0[7:0]) 58 61h 6.2.10.4 i/o port base address bits [15:8] for descriptor 1 (iobad1[15:8]) 58 62h 6.2.10.5 i/o port base address bits [7:0 ] for descriptor 1 (iobad1[7:0]) 58 63h 6.2.10.6 i/o port base address bits [15:8] for descriptor 2 (iobad2[15:8]) 58 64h 6.2.10.7 i/o port base address bits [7:0 ] for descriptor 2 (iobad2[7:0]) 58 65h 6.2.10.8 interrupt request number and wake-up on irq enable (irqnumx) 59 70h 6.2.10.9 interrupt request type select (irqtp) 59 71h 6.8 real-time clock (rtc) 118 6.8.4 host interface registers 119 6.8.4.1 rtc bank 0 register 121 00h 6.8.4.1.1 seconds register (secreg) 121 01h 6.8.4.1.2 seconds alarm 1 register (seca1reg) 121 02h 6.8.4.1.3 minutes register (minreg) 122 03h 6.8.4.1.4 minutes alarm 1 register (mina1reg) 122 04h 6.8.4.1.5 hours register (hrreg) 122 05h 6.8.4.1.6 hours alarm 1 register (hra1reg) 122 06h 6.8.4.1.7 day of week register (dowreg) 122 07h 6.8.4.1.8 date of month register (domreg) 123 08h 6.8.4.1.9 month register (monreg) 123 09h 6.8.4.1.10 year register (yrreg) 123 0ah 6.8.4.1.11 rtc control register a (ctlrega) 123 0bh 6.8.4.1.12 rtc control register b (ctlregb) 124 0ch 6.8.4.1.13 rtc control register c (ctlregc) 125 0dh 6.8.4.1.14 rtc control register d (ctlregd) 126 pnp 6.8.4.1.15 date of month alarm 1 register (doma1reg) 126 pnp free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 287 register list 6.8.4.1.16 month alarm 1 register (mona1reg) 126 00h 6.8.4.2 rtc bank 1 register 126 6.8.4.2.1 seconds alarm 2 register (seca2reg) 126 00h 6.8.4.2.2 minutes alarm 2 register (mina2reg) 126 01h 6.8.4.2.3 hours alarm 2 register (hra2reg) 127 02h 6.8.4.2.4 date of month alarm 2 register (doma2reg) 127 03h 6.8.4.2.5 month alarm 2 register (mona2reg) 127 04h 6.8.4.3 rtc i/o register 127 6.8.4.3.1 rtc index register of bank 0 (rirb0) 127 70h 6.8.4.3.2 rtc data register of bank 0 (rdrb0) 127 71h 6.8.4.3.3 rtc index register of bank 1 (rirb1) 128 72h 6.8.4.3.4 rtc data register of bank 1 (rdrb1) 128 73h 6.3 shared memory flash interface bridge (smfi) 62 6.3.4 ec interface registers 67 6.3.4.1 fbiu configuration register (fbcfg) 68 1000h 6.3.4.2 flash programming configuration register (fpcfg) 68 1001h 6.3.4.3 flash ec code banking select register (fecbsr) 69 1005h 6.3.4.4 flash memory size select register (fmssr) 70 1007h 6.3.4.5 shared memory ec control and status register (smeccs) 71 1020h 6.3.4.6 shared memory host semaphore register (smhsr) 71 1022h 6.3.4.7 shared memory ec override read pr otect registers 0-1 (smecorpr0-1) 72 1023h/1024h 6.3.4.8 shared memory ec override write pr otect registers 0-1 (smecowpr0-1) 72 1029h/102ah 6.3.4.9 host control 2 register (hctrl2r) 72 1036h 6.3.4.10 trusted rom register (tromr) 73 1037h 6.3.4.11 ec-indirect memory address register 0 (ecindar0) 73 103bh 6.3.4.12 ec-indirect memory address register 1 (ecindar1) 73 103ch 6.3.4.13 ec-indirect memory address register 2 (ecindar2) 73 103dh 6.3.4.14 ec-indirect memory address register 3 (ecindar3) 73 103eh 6.3.4.15 ec-indirect memory data register (ecinddr) 73 103fh 6.3.4.16 scratch sram 0 address low byte register (scar0l) 74 1040h 6.3.4.17 scratch sram 0 address middle byte register (scar0m) 74 1041h 6.3.4.18 scratch sram 0 address high byte register (scar0h) 74 1042h 6.3.4.19 scratch sram 1 address low byte register (scar1l) 74 1043h 6.3.4.20 scratch sram 1 address middle byte register (scar1m) 74 1044h 6.3.4.21 scratch sram 1 address high byte register (scar1h) 74 1045h 6.3.4.22 scratch sram 2 address low byte register (scar2l) 75 1046h 6.3.4.23 scratch sram 2 address middle byte register (scar2m) 75 1047h 6.3.4.24 scratch sram 2 address high byte register (scar2h) 75 1048h 6.3.4.25 scratch sram 3 address low byte register (scar3l) 75 1049h 6.3.4.26 scratch sram 3 address middle byte register (scar3m) 75 104ah 6.3.4.27 scratch sram 3 address high byte register (scar3h) 75 104bh 6.3.4.28 scratch sram 4 address low byte register (scar4l) 76 104ch 6.3.4.29 scratch sram 4 address middle byte register (scar4m) 76 104dh 6.3.4.30 scratch sram 4 address high byte register (scar4h) 76 104eh 6.3.5 host interface registers 76 6.3.5.1 shared memory indirect memory address register 0 (smimar0) 76 00h 6.3.5.2 shared memory indirect memory address register 1 (smimar1) 77 01h 6.3.5.3 shared memory indirect memory address register 2 (smimar2) 77 02h 6.3.5.4 shared memory indirect memory address register 3 (smimar3) 77 03h 6.3.5.5 shared memory indirect memo ry data register (smimdr) 77 04h 6.3.5.6 shared memory host semaphore register (smhsr) 77 0ch 6.3.5.7 m-bus control register (mbctrl) 78 0fh free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 288 it8511 e /te/ g 7.2 interrupt controller (intc) 157 7.2.4 ec interface registers 158 7.2.4.1 interrupt status register 0 (isr0) 159 1100h 7.2.4.2 interrupt status register 1 (isr1) 159 1101h 7.2.4.3 interrupt status register 2 (isr2) 160 1102h 7.2.4.4 interrupt status register 3 (isr3) 160 1103h 7.2.4.5 interrupt enable register 0 (ier0) 160 1104h 7.2.4.6 interrupt enable register 1 (ier1) 161 1105h 7.2.4.7 interrupt enable register 2 (ier2) 161 1106h 7.2.4.8 interrupt enable register 3 (ier3) 161 1107h 7.2.4.9 interrupt edge/level-triggered mode register 0 (ielmr0) 161 1108h 7.2.4.10 interrupt edge/level-triggered mode register 1 (ielmr1) 162 1109h 7.2.4.11 interrupt edge/level-triggered mode register 2 (ielmr2) 162 110ah 7.2.4.12 interrupt edge/level-triggered mode register 3 (ielmr3) 162 110bh 7.2.4.13 interrupt polarity register 0 (ipolr0) 162 110ch 7.2.4.14 interrupt polarity register 1 (ipolr1) 163 110dh 7.2.4.15 interrupt polarity register 2 (ipolr2) 163 110eh 7.2.4.16 interrupt polarity register 3 (ipolr3) 163 110fh 7.2.4.17 interrupt vector register (ivct) 163 1110h 7.2.4.18 8032 int0# status (int0st) 164 1111h 7.2.4.19 power fail register (pfailr) 164 1112h 7.12 ec access to host controlled modules (ec2i bridge) 248 7.12.4 ec interface registers 248 7.12.4.1 indirect host i/o addr ess register (ihioa) 249 1200h 7.12.4.2 indirect host data register (ihd) 249 1201h 7.12.4.3 lock super i/o host access register (lsioha) 249 1202h 7.12.4.4 super i/o access lock violation register (siolv) 250 1203h 7.12.4.5 ec to i-bus modules access enable register (ibmae) 250 1204h 7.12.4.6 i-bus control register (ibctl) 250 1205h 6.5 keyboard controller (kbc) 91 6.5.4 host interface registers 92 6.5.4.1 kbc data input r egister (kbdir) 93 pnp 6.5.4.2 kbc data output register (kbdor) 93 pnp 6.5.4.3 kbc command regi ster (kbcmdr) 93 pnp 6.5.4.4 kbc status register (kbstr) 93 pnp 6.5.5 ec interface registers 94 6.5.5.1 kbc host interface cont rol register (kbhicr) 94 1300h 6.5.5.2 kbc interrupt control register (kbirqr) 95 1302h 6.5.5.3 kbc host interface keyboard/mou se status register (kbhisr) 96 1304h 6.5.5.4 kbc host interface keyboard data output register (kbhikdor) 96 1306h 6.5.5.5 kbc host interface mouse data output register (kbhimdor) 96 1308h 6.5.5.6 kbc host interface keyboard/mouse data input register (kbhidir) 97 130ah 6.4 system wake-up control (swuc) 79 6.4.4 host interface registers 83 6.4.4.1 wake-up event status register (wkstr) 83 00h 6.4.4.2 wake-up event enable register (wker) 84 02h 6.4.4.3 wake-up signals monitor register (wksmr) 84 06h 6.4.4.4 wake-up acpi status register (wkacpir) 85 07h 6.4.4.5 wake-up smi enable register (wksmier) 85 13h 6.4.4.6 wake-up irq enable re gister (wkirqer) 86 15h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 289 register list 6.4.5 ec interface registers 86 6.4.5.1 swuc control status 1 register (swctl1) 86 1400h 6.4.5.2 swuc control status 2 register (swctl2) 87 1402h 6.4.5.3 swuc control status 3 register (swctl3) 88 1404h 6.4.5.4 swuc host configuration base addr ess low byte register (swcbalr) 88 1408h 6.4.5.5 swuc host configuration base addr ess high byte register (swcbahr) 88 140ah 6.4.5.6 swuc interrupt enable register (swcier) 88 140ch 6.4.5.7 swuc host event status register (swchstr) 89 140eh 6.4.5.8 swuc host event interrupt enable register (swchier) 90 1410h 6.6 power management channel (pmc) 98 6.6.4 host interface registers 102 6.6.4.1 pmc data input register (pmdir) 102 pnp 6.6.4.2 pmc data output register (pmdor) 103 pnp 6.6.4.3 pmc command register (pmcmdr) 103 pnp 6.6.4.4 status register (pmstr) 103 pnp 6.6.5 ec interface registers 104 6.6.5.1 pm status register (pmsts) 104 1500h/1510h 6.6.5.2 pm data out port (pmdo) 105 1501h/1511h 6.6.5.3 pm data out port with sci (pmdosci) 105 1502h/1512h 6.6.5.4 pm data out port with smi (pmdosmi) 105 1503h/1513h 6.6.5.5 pm data in port (pmdi) 106 1504h/1514h 6.6.5.6 pm data in port with sci (pmdisci) 106 1505h/1515h 6.6.5.7 pm control (pmctl) 106 1506h/1516h 6.6.5.8 pm interrupt control (pmic) 107 1507h/1517h 6.6.5.9 pm interrupt enable (pmie) 107 1508h/1518h 6.6.5.10 pm interrupt enable (pmie) 108 1519h 6.6.5.11 16-byte pmc2ex mailbox 0-15 (mbxec0-15) 108 15f0h-15ffh 7.5 general purpose i/o port (gpio) 176 7.5.3 ec interface registers 176 7.5.3.1 general control register (gcr) 176 1600h 7.5.3.2 port data registers a-m (gpdra-gpdrm) 177 1601h-160dh 7.5.3.3 port data mirror regist ers a-m (gpdmra-gpdmrm) 177 1661h-166dh 7.5.3.4 port control n registers (gpcrn, n = a0-i7) 178 1610h-16a5h 7.5.3.5 output type registers a-i (gpota-gpoti) 180 1671h-1679h 7.8 ps/2 interface 202 7.8.4 ec interface registers 203 7.8.4.1 ps/2 control register 1-4 (psctl1-4) 203 1700h-1703h 7.8.4.2 ps/2 interrupt control register 1-4 (psint1-4) 204 1704h-1707h 7.8.4.3 ps/2 status register 1-4 (pssts1-4) 204 1708h-170bh 7.8.4.4 ps/2 data register 1-4 (psdat1-4) 205 170ch-170fh 7.11 pwm and smartauto fan control (pwm) 222 7.11.4 ec interface registers 229 7.11.4.1 channel 0 clock prescaler register (c0cprs) 229 1800h 7.11.4.2 cycle time register (ctr) 230 1801h 7.11.4.3 pwm duty cycle register 0 to 7(dcri) 230 1802h-1809h 7.11.4.4 pwm polarity register (pwmpol) 230 180ah 7.11.4.5 prescaler clock frequency select register (pcfsr) 231 180bh 7.11.4.6 prescaler clock source select group low (pcssgl) 231 180ch free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 290 it8511 e /te/ g 7.11.4.7 prescaler clock source select group high (pcssgh) 232 180dh 7.11.4.8 cr256 prescaler clock source select group (cr256pcssg) 232 180eh 7.11.4.9 prescaler clock source gating register (pcsgr) 233 180fh 7.11.4.10 fan 1 configuration register (fan1cnf) 233 1810h 7.11.4.11 fan 2 configuration register (fan2cnf) 234 1811h 7.11.4.12 smartauto fan minimum-region sp eed range register (afmisrr) 235 1812h 7.11.4.13 smartauto fan maximum-region s peed range register (afmasrr) 236 1813h 7.11.4.14 min/off pwm limit register (mopl) 237 1814h 7.11.4.15 fan 1 minimum pwm duty cycle register (f1mpdcr) 237 1815h 7.11.4.16 fan 2 minimum pwm duty cycle register (f2mpdcr) 237 1816h 7.11.4.17 fan 1 temperature limit register (f1tlimitr) 238 1817h 7.11.4.18 fan 2 temperature limit register (f2tlimitr) 238 1818h 7.11.4.19 fan 1 absolute temperature limit register (f1atlimitr) 238 1819h 7.11.4.20 fan 2 absolute temperature limit register (f2atlimitr) 239 181ah 7.11.4.21 zone hysteresis register (zhysr) 239 181bh 7.11.4.22 fan 1 temperature record register (f1trr) 239 181ch 7.11.4.23 fan 2 temperature record register (f2trr) 240 181dh 7.11.4.24 fan 1 tachometer lsb reading register (f1tlrr) 240 181e h 7.11.4.25 fan 1 tachometer msb reading register (f1tmrr) 240 181fh 7.11.4.26 fan 2 tachometer lsb reading register (f2tlrr) 240 1820h 7.11.4.27 fan 2 tachometer msb reading register (f2tmrr) 240 1821h 7.11.4.28 zone interrupt status cont rol register (zintscr) 241 1822h 7.11.4.29 zone temperature interrupt enable register (ztier) 241 1823h 7.11.4.30 channel 4 clock prescaler register (c4cprs) 242 1827h 7.11.4.31 channel 4 clock prescaler msb register (c4mcprs) 242 1828h 7.11.4.32 channel 6 clock prescaler register (c6cprs) 242 182bh 7.11.4.33 channel 6 clock prescaler msb register (c6mcprs) 243 182ch 7.11.4.34 channel 7 clock prescaler register (c7cprs) 243 182dh 7.11.4.35 channel 7 clock prescaler msb register (c7mcprs) 243 182eh 7.11.4.36 fan 1 temperature criterion register 1-3 (f1tc1-3) 244 1830h-1832h 7.11.4.37 fan 2 temperature criterion register 1-3(f2tc1-3) 244 1834h-1836h 7.11.4.38 fan 1 pwm duty cycle criterion register 1-3(f1pdc1-3) 244 1838h-183ah 7.11.4.39 fan 2 pwm duty cycle criterion register 1-3(f2pdc1-3) 244 183ch-183eh 7.10 analog to digital converter (adc) 208 7.10.4 ec interface registers 211 7.10.4.1 adc status register (adcsts) 211 1900h 7.10.4.2 adc configuration register (adccfg) 212 1901h 7.10.4.3 adc clock control register (adcctl) 213 1902h 7.10.4.4 voltage channel 0 control register (vch0ctl) 213 1904h 7.10.4.5 calibration data control register (kdctl) 214 1905h 7.10.4.6 voltage channel 1 control register (vch1ctl) 215 1906h 7.10.4.7 volt channel 1 data buffer lsb (vch1datl) 215 1907h 7.10.4.8 volt channel 1 data buffer msb (vch1datm) 215 1908h 7.10.4.9 voltage channel 2 control register (vch2ctl) 216 1909h 7.10.4.10 volt channel 2 data buffer lsb (vch2datl) 216 190ah 7.10.4.11 volt channel 2 data buffer msb (vch2datm) 216 190bh 7.10.4.12 voltage channel 3 control register (vchn3ctl) 216 190ch 7.10.4.13 volt channel 3 data buffer lsb (vch3datl) 217 190dh 7.10.4.14 volt channel 3 data buffer msb (vch3datm) 217 190eh 7.10.4.15 volt high scale calibration data buffer lsb (vhscdbl) 217 1914h 7.10.4.16 volt high scale calibration data buffer msb (vhscdbm) 217 1915h 7.10.4.17 voltage channel 0 data buffer lsb (vch0datl) 218 1918h 7.10.4.18 voltage channel 0 data buffer msb (vch0datm) 218 1919h 7.10.4.19 volt high scale gain-error calibra tion data buffer lsb (vhsgcdbl) 218 191ch free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 291 register list 7.10.4.20 volt high scale gain-error calibra tion data buffer msb (vhsgcdbm) 218 191dh 7.9 digital to analog converter (dac) 206 7.9.4 ec interface registers 206 7.9.4.1 dac control register (dacctrl) 206 1a00h 7.9.4.2 dac data channel 0~3 register (dacdat0~3) 207 1a01h-1a04h 7.9.4.3 dac power down register (dacpdreg) 207 1a05h 7.3 wake-up control (wuc) 168 7.3.4 ec interface registers 168 7.3.4.1 wake-up edge mode register (wuemr1) 168 1b00h 7.3.4.2 wake-up edge mode register (wuemr2) 169 1b01h 7.3.4.3 wake-up edge mode register (wuemr3) 169 1b02h 7.3.4.4 wake-up edge mode register (wuemr4) 169 1b03h 7.3.4.5 wake-up edge sense register (wuesr1) 169 1b04h 7.3.4.6 wake-up edge sense register (wuesr2) 170 1b05h 7.3.4.7 wake-up edge sense register (wuesr3) 170 1b06h 7.3.4.8 wake-up edge sense register (wuesr4) 170 1b07h 7.3.4.9 wake-up enable regi ster (wuenr1) 171 1b08h 7.3.4.10 wake-up enable regi ster (wuenr2) 171 1b09h 7.3.4.11 wake-up enable regi ster (wuenr3) 171 1b0ah 7.3.4.12 wake-up enable regi ster (wuenr4) 171 1b0bh 7.7 sm bus interface (smb) 191 7.7.4 ec interface registers 196 7.7.4.1 host status register (hosta) 196 1c00h/1c11h 7.7.4.2 host control register (hoctl) 197 1c01h/1c12h 7.7.4.3 host command register (hocmd) 198 1c02h/1c13h 7.7.4.4 transmit slave address register (trasla) 198 1c03h/1c14h 7.7.4.5 data 0 register (d0reg) 198 1c04h/1c15h 7.7.4.6 data 1 register (d1reg) 198 1c05h/1c16h 7.7.4.7 host block data byte register (hobdb) 198 1c06h/1c17h 7.7.4.8 packet error check register (pecerc) 199 1c07h/1c18h 7.7.4.9 smbus pin control register (smbpctl) 199 1c0ah/1c1bh 7.7.4.10 host control register 2 (hoctl2) 199 1c10h/1c21h 7.7.4.11 4.7 s low register (4p7usl) 200 1c22h 7.7.4.12 4.0 s low register (4p0usl) 200 1c23h 7.7.4.13 300 ns register (300nsreg) 200 1c24h 7.7.4.14 250 ns register (250nsreg) 200 1c25h 7.7.4.15 25 ms register (25msreg) 200 1c26h 7.7.4.16 45.3 s low register (45p3uslreg) 201 1c27h 7.7.4.17 45.3 s high register (45p3ushreg) 201 1c28h 7.7.4.18 4.7 s and 4.0 s high register (4p7a4p0h) 201 1c33h 7.4 keyboard matrix scan controller 174 7.4.3 ec interface registers 174 7.4.3.1 keyboard scan out low byte data register (ksol) 174 1d00h 7.4.3.2 keyboard scan out high byte data 1 register (ksoh1) 174 1d01h 7.4.3.3 keyboard scan out control register (ksoctrl) 174 1d02h 7.4.3.4 keyboard scan out high byte data 2 register (ksoh2) 175 1d03h 7.4.3.5 keyboard scan in data register (ksir) 175 1d04h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 292 it8511 e /te/ g 7.4.3.6 keyboard scan in control register (ksictrlr) 175 1d05h 7.6 ec clock and power management controller (ecpm) 187 7.6.3 ec interface registers 187 7.6.3.1 clock frequency select register (cfselr) 187 1e00h 7.6.3.2 clock gating control 1 register (cgctrl1r) 187 1e01h 7.6.3.3 clock gating control 2 register (cgctrl2r) 188 1e02h 7.6.3.4 clock gating control 3 register (cgctrl3r) 189 1e05h 7.6.3.5 pll control (pllctrl) 189 1e03h 7.6.3.6 auto clock gating (autocg) 189 1e04h 7.13 external timer and external watchdog (etwd) 254 7.13.4 ec interface registers 255 7.13.4.1 external timer/wdt configur ation register (etwcfg) 255 1f01h 7.13.4.2 external timer prescaler register (etpsr) 256 1f02h 7.13.4.3 external timer counter high byte (etcntlhr) 256 1f03h 7.13.4.4 external timer counter low byte (etcntllr) 256 1f04h 7.13.4.5 external timer/wdt control register (etwctrl) 256 1f05h 7.13.4.6 external wdt counter high byte (ewdcntlhr) 257 1f09h 7.13.4.7 external wdt low counter (ewdcntllr) 257 1f06h 7.13.4.8 external wdt key register (ewdkeyr) 257 1f07h 7.13.4.9 reset scratch register (rstscr) 257 1f08h 7.14 general control (gctrl) 259 7.14.4 ec interface registers 259 7.14.4.1 chip id byte 1 (echipid1) 259 2000h 7.14.4.2 chip id byte 2 (echipid2) 260 2001h 7.14.4.3 chip version (echipver) 260 2002h 7.14.4.4 identify input register (idr) 260 2004h 7.14.4.5 reset status (rsts) 260 2006h 7.14.4.6 reset control 1 (rstc1) 261 2007h 7.14.4.7 reset control 2 (rstc2) 261 2008h 7.14.4.8 reset control 3 (rstc3) 262 2009h 7.14.4.9 wait next clock rising (wnckr) 262 200bh 7.14.4.10 oscillator control r egister (osctrl) 262 200ch 7.14.4.11 special control 1 (spctrl1) 262 200dh 7.14.4.12 reset control host side (rstch) 263 200eh 7.15 battery-backed sram (bram) 265 7.15.4 ec interface registers 266 7.15.4.1 sram byte n registers (sbtn, n= 0-255). 266 2200h-22ffh 7.16 consumer ir (cir) 267 7.16.4 ec interface registers 269 7.16.4.1 cir data register (c0dr) 269 2300h 7.16.4.2 cir master control register (c0mstcr) 270 2301h 7.16.4.3 cir interrupt enable register (c0ier) 270 2302h 7.16.4.4 cir interrupt identification register (c0iir) 271 2303h 7.16.4.5 cir carrier frequency register (c0cfr) 271 2304h 7.16.4.6 cir receiver control register (c0rcr) 273 2305h 7.16.4.7 cir transmitter control register (c0tcr) 275 2306h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 293 register list 7.16.4.8 cir slow clock control register (c0sck) 276 2307h 7.16.4.9 cir baud rate divisor low byte register (c0bdlr) 277 2308h 7.16.4.10 cir baud rate divisor high byte register (c0bdhr) 277 2309h 7.16.4.11 cir transmitter fifo stat us register (c0tfsr) 277 230ah 7.16.4.12 cir receiver fifo stat us register (c0rfsr) 278 230bh 7.16.4.13 cir wakeup code length register (c0wcl) 278 230dh 7.16.4.14 cir wakeup code read/write register (c0wcr) 278 230eh 7.16.4.15 cir wakeup power control/status register (c0wps) 279 230fh 6.7 trusted mobile kbc (tmkbc) 109 6.7.4 host interface registers 109 6.7.4.1 tmkbc vendor id register (tvendid) 109 01h-00h 6.7.4.2 tmkbc device id r egister (tdevid) 110 03h-02h 6.7.4.3 tmkbc version register (tver) 110 05h-04h 6.7.4.4 generic capabilities re porting register (cap) 110 06h 6.7.4.5 tmkbc revision id register (trevid) 110 07h 6.7.4.6 configuration register (cnf) 111 09h-08h 6.7.4.7 control register (cnt) 111 0bh-0ah 6.7.4.8 irq capabilities reportin g register (irqcap) 112 0dh-0ch 6.7.4.9 status register (sts) 112 11h-10h 6.7.4.10 extended status register (extsts) 112 13h 6.7.4.11 interrupt trigger enable register (inttrig) 113 17h 6.7.4.12 tmkbc data input register (tdatin) 113 1bh-18h 6.7.4.13 tmkbc data output register (tdatout) 113 23h-20h 6.7.5 ec interface registers 114 6.7.5.1 ec side configuration register (eccon) 114 2400h 6.7.5.2 status control register (stscon) 114 2401h 6.7.5.3 ec data input register (edatin) 115 2402h 6.7.5.4 ec data output register (edatout) 115 2403h 6.7.5.5 ec buffer status register (ebufsts) 115 2404h 6.7.5.6 ec status register (ests) 115 2405h 6.7.5.7 ec vendor id low register (evenl) 116 2406h 6.7.5.8 ec vendor id high register (evenh) 116 2407h 6.7.5.9 ec device id low register (edevl) 116 2408h 6.7.5.10 ec device id high register (edevh) 116 2409h 6.7.5.11 ec version low register (everl) 116 240ah 6.7.5.12 ec version high register (everh) 117 240bh 6.7.5.13 ec revision id register (erevid) 117 240ch 7.17 debugger (dbgr) 280 7.17.4 ec interface registers 281 7.17.4.1 trigger 1 address low byte register (bka1l) 281 2510h 7.17.4.2 trigger 1 address middle byte register (bka1m) 281 2511h 7.17.4.3 trigger 1 address high byte register (bka1h) 281 2512h 7.17.4.4 trigger 2 address low byte register (bka2l) 281 2513h 7.17.4.5 trigger 2 address middle byte register (bka2m) 281 2514h 7.17.4.6 trigger 2 address high byte register (bka2h) 282 2515h 7.17.4.7 trigger 3 address low byte register (bka3l) 282 2516h 7.17.4.8 trigger 3 address middle byte register (bka3m) 282 2517h 7.17.4.9 trigger 3 address high byte register (bka3h) 282 2518h 7.1 8032 embedded controller (ec) 131 7.1.9 ec internal register description 144 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 294 it8511 e /te/ g 7.1.9.1 port 0 register (p0r) 145 80h 7.1.9.2 stack pointer register (spr) 145 81h 7.1.9.3 data pointer low register (dplr) 145 82h 7.1.9.4 data pointer high register (dphr) 145 83h 7.1.9.5 data pointer 1 low register (dp1lr) 145 84h 7.1.9.6 data pointer 1 high register (dp1hr) 145 85h 7.1.9.7 data pointer select register (dpsr) 145 86h 7.1.9.8 power control register (pcon) 146 87h 7.1.9.9 timer control register (tcon) 146 88h 7.1.9.10 timer mode register (tmod) 147 89h 7.1.9.11 timer 0 low byte register (tl0r) 147 8ah 7.1.9.12 timer 1 low byte register (tl1r) 147 8bh 7.1.9.13 timer 0 high byte register (th0r) 147 8ch 7.1.9.14 timer 1 low byte register (th1r) 148 8dh 7.1.9.15 clock control register (ckcon) 148 8eh 7.1.9.16 port 1 register (p1r) 148 90h 7.1.9.17 serial port control register (scon) 149 98h 7.1.9.18 serial port buffer register (sbufr) 149 99h 7.1.9.19 port 2 register (p2r) 149 a0h 7.1.9.20 interrupt enable register (ie) 150 a8h 7.1.9.21 port 3 register (p3r) 150 b0h 7.1.9.22 interrupt priority register (ip) 151 b8h 7.1.9.23 status register (status) 151 c5h 7.1.9.24 timer 2 control register (t2con) 151 c8h 7.1.9.25 timer mode register (t2mod) 152 c9h 7.1.9.26 timer 2 capture low byte register (rcap2lr) 152 cah 7.1.9.27 timer 2 capture high byte register (rcap2hr) 152 cbh 7.1.9.28 timer 2 low byte register (tl2r) 152 cch 7.1.9.29 timer 2 high byte register (th2r) 153 cdh 7.1.9.30 program status word register (psw) 153 d0h 7.1.9.31 watch dog timer control register (wdtcon) 153 d8h 7.1.9.32 accumulator register (acc) 154 e0h 7.1.9.33 b register (br) 154 f0h free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 295 dc characteristics 9. dc characteristics (vstby, vcc =3.3v 0.3v, avcc =3.3v 0.15v, vbat = 2.3~3.3v, ta=0 c to 70 c) absolute maximum ratings* applied voltage of vstby, vcc, avcc, vbat ????????????.?? 0.3v to +3.6v input voltage of 3.3v inte rface? -0.3v to vcc +0.3v tcase???????????.. 0 c to +70 c storage temperature????? -40 c to +125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (ta=0 c to 70 c) symbol parameter min. typ. max. conditions 3.3v cmos interface v il input low voltage -0.3v vcc x 0.3 vcc=3.0 - 3.6v v ih input high voltage vcc x 0.7 vcc+ 0.3v vcc=3.0 - 3.6v v ih input high voltage (5v tolerant pad) vcc x 0.7 6.3v vcc=3.0 - 3.6v v ol output low voltage 0.4 i ol = -2, -4, -6, -8ma v oh output high voltage 2.4 i oh = 2, 4, 6, 8ma v t- schmitt trigger negative going threshold voltage 0.9 1.2 v t+ schmitt trigger positive going threshold voltage 2.1 2.5 i il input leakage current -10 a 1 a 10 a no pull-up or pull-down i oz tri-state leakage current -10 a 1 a 10 a no pull-up or pull-down r pu input pull-up resistance 40k ? 75k ? 190k ? v i = 0v r pd input pull-down resistance 40k ? 75k ? 190k ? v i = vcc cin input capacitance 2.8pf cout output capacitance 2.7pf 4.9pf cbld bi-directional buffer 2.7pf 4.9pf free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 296 it8511 e /te/ g table 9-1. power consumption symbol parameter min. typ. max. conditions 3.3v cmos interface i sleep vstby supply current 100 a internal pull are disabled vil = gnd vih = vstby no load i bat vbat supply current 1.7 a 2.4 a vstby and vcc are not supplied free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 297 ac characteristics 10. ac characteristics figure 10-1. vstby power-on reset timing vstby internal vstby por# 0v 3.3v 0v 3.3v vt+ vt- t lh vt- t lh t hd t hd table 10-1. vstby power-on reset ac table symbol parameter min. typ. max. unit vt+ level detection positive going threshold voltage 2.89 v vt- level detection negative going threshold voltage 2.65 v t hd internal vstby por going high delay 500 s t lh minimum hold time after vstby < vt- and before internal vstby por going low 10 s figure 10-2. reset timing internal vstby por# or wrst# hardware strap signal stabilized pll clock sleep mode wakeup from sleep mode t plls1 t plls2 t per t strap internal ec logic reset# t rstpw table 10-2. reset ac table symbol parameter min. typ. max. unit t rstpw internal ec logic reset after vstby por or wrst# 1650 tick (by 32.768 khz) t strap strap sampling time 0 ns t plls1 pll stabilization time hardware 5 ms t plls2 pll stabilization time after waking up from sleep mode 5 ms t per pll clock period 1/ freqpll ns freqpll pll clock frequency if pllfreq = 0011b 10 mhz freqec ec clock frequency if pllfreq = 0111b 10 mhz free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 298 it8511 e /te/ g figure 10-3. warm reset timing wrst# t wrstw table 10-3. warm reset ac table symbol parameter min. typ. max. unit t wrstw warm reset width 10 s figure 10-4. wakeup from doze mode timing int0#, int1# wakeup event: fallin g edge of int0#/int1# of 8032 8032 clock t wdoze table 10-4. wakeup from doze mode ac table symbol parameter min. typ. max. unit t wdoze doze wakeup time from falling edge of int0#/int1# to rising edge of first 8032 clock. 2 / (ec clock freq) figure 10-5. wake up from sleep mode timing int0#, int1# wakeup event: falling edge of int0#/int1# of 8032 8032 clock t wsleep table 10-5. wake up from sleep mode ac table symbol parameter min. typ. max. unit t wsleep sleep wakeup time from falling edge of int0#/int1# to rising edge of first 8032 clock. 4.2 ms figure 10-6. asynchronous external wakeup/interrupt source edge detected timing wux/int28 (rising edge mode) wux/int28 (falling edge mode) t wuw free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 299 ac characteristics table 10-6. asynchronous external wakeup/interrupt source edge detected ac table symbol parameter min. typ. max. unit t wuw wakeup source pulse width 1 ns figure 10-7. lpc and serirq timing t val t on t off lpc signals/ serirq (output) lclk lpc signals/ serirq (input) input valid t h t su table 10-7. lpc and serirq ac table symbol parameter min. typ. max. unit t on float to active delay 3 ns t val output valid delay 12 ns t off active to float delay 20 ns t su input setup time 7 ns t h input hold time 0 ns figure 10-8. swuc wake up timing t ril t rih ring#/ri1#/ri2 pwureq#/smi# t wupd table 10-8. swuc wake up ac table symbol parameter min. typ. max. unit t ril ring#, ri1# , ri2# low time 10 ns t rih ring#, ri1# , ri2# high time 10 ns t wupd wake up propagation delay time 20 ns free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 300 it8511 e /te/ g figure 10-9. flash read cycle timing t rad 1 t r ad2 fa[21:0] fwr# t rd w frd# t csw fcs# t frdd t frdh fd[7:0] table 10-9. flash read cycle ac table symbol parameter min. typ. max. unit t rad1 read address delay time1 0 ns t rad2 read address delay time2 0 ns t csw read chip select width time 1/ frequc ns t rdw read data output enable signal width 1/ frequc ns t frdd read data output delay 80 note1 ns t frdh frd data hold time 0 ns note 1: ?read cycle time? and ?write cycle time? of t he flash/eprom have to be faster than or equal to t frdd . 2: frequc = freqec if cfsel bit in cfselr register is set. frequc = freqec / [( cdnum + 1) * 2 ] if cfsel bit in cfselr register is cleared. figure 10-10. flash write cycle timing internal flash clock t wad1 t wad2 fa[21:0] frd# t fwp fwr# t cwd fcs# t wdd1 t wdd2 table 10-10. flash write cycle ac table symbol parameter min. typ. max. unit t wad1 write address delay time1 1/ freqec ns free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 301 ac characteristics t wad2 write address delay time2 1/ freqec ns t fwp write width pulse time 1/ freqec ns t cwd chip select to write delay time 1/ freqec ns t wdd1 write data delay time1 1/ freqec ns t wdd2 write data delay time2 1/ freqec ns figure 10-11. pwm output timing internal 1 pwm clock pwm0-7 data out t ovd t odh table 10-11. pwm output ac table symbol parameter min. typ. max. unit t ovd pwm output valid delay time 0.5 t note1 t odh pwm output hold time 0 ns note 1: t is one time unit and its length is equal to the ec clock period x c0cprs +1 (ns) for ch0~3, or x c4cprs +1 (ns) for ch4~7. figure 10-12. pmc smi#/sci# timing obf (internal) smi# t smie t smid sci# t scie t scid table 10-12. pmc smi#/sci# ac table symbol parameter min. typ. max. unit t smie obf asserted to smi# asserted time 10 ns t smid obf de-asserted to smi# de-asserted time 5 ns t scie obf asserted to sci# asserted time 10 ns t scid obf de-asserted to sci# de-asserted time 5 ns free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 302 it8511 e /te/ g figure 10-13. pmc ibf/sci# timing internal 1 ibf_clr_sci sci# t scice t scicd table 10-13. pmc ibf/sci# ac table symbol parameter min. typ. max. unit t scice ibf_clr_sci asserted to sci# asserted time 70 ns t scicd ibf_clr_sci de-asserted to sci# de-asserted time 40 ns note 1: ibf_clr_sci means the invert signal of ibf, ibf_ clr_sci set to one when ec read pmdi or pmdisci. figure 10-14. ps/2 receive/transmit timing receive: clk data t psdset t clklow transmit: clk data t psdo table 10-14. ps/2 receive/transmit ac table symbol parameter min. typ. max. unit t psdset data line input set up time 1 ns t clklow clk line low time 1 s t psdo data line output data time 1 s free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 303 ac characteristics figure 10-15. smbus timing t low t high smbclk t hd;sta smbdat t buf t su;dat t hd;dat stop start smbclk t su;sta t su;sto smbdat start stop table 10-15. smbus ac table symbol parameter min. typ. max. unit t buf bus free time between stop and start condition 4.7 s t hd;sta hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 s t low clock low period 4.7 s t high clock high period 4.0 50 s t su;dat data setup time 250 ns t hd;dat data hold time 300 ns t su;sta repeated start condition setup time 4.7 s t su;sto stop condition setup time 4.0 s free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 304 it8511 e /te/ g figure 10-16. consumer ir (cir) timing p2s serial port ctx/crx t 1 t 2 table 10-16. consumer ir (cir) ac table symbol parameter conditions min. max. unit transmitter t btn ? tclk note1 t btn + tclk note1 ns t 1 single bit time in p2s of cir receiver t btn ? 2% t btn + 2% ns transmitter tpwd ? tclk note2 tpwd +tclk note2 ns t 2 modulation signal pulse width in ctx/crx receiver tpwd ?2% tpwd +2% ns note 1: t btn is the nominal bit time in serial port of p2s bloc k of cir. it is determin ed by the setting on the baud rate divisor registers (c0bdhr/c0bd lr). tclk equals to 1/ freqec. note 2: t pwd is normal modulated pulse width on ctx/crx pi n. it is determined by c0tcr registers. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 305 package information 11. analog device characteristics table 11-1. adc characteristics parameter condition min. typ. max. unit resolution 10 bit integral non-linearity error (inl) adc0-9 4 lsb differential non-linearity error (dnl) adc0-9 4 lsb offset error adc0-9 4 lsb gain error adc0-9 4 lsb external input accuracy adc0-9 4 lsb adc input voltage range 0 3 v adc input leakage current adc0-9: 0 Q vin Q avcc 1 a adc input resistance 4 m adc input capacitance 8 pf adc clock frequency 0.5 mhz voltage conversion delay 16 512 1000 s voltage conversion time 3.6 ms table 11-2. dac characteristics parameter condition min. typ. max. unit resolution 8 bit integral non-linearity error (inl) avcc = 3.3v 1 lsb differential non-linearity error (dnl) avcc = 3.3v 0.5 lsb offset error avcc = 3.3v 1 lsb gain error avcc = 3.3v 1 lsb dac output voltage range 0 avcc v dac settling time c load = 50pf 1 s dac output resistance 0 Q vout Q avcc 3 800 dac output capacitance 6.5 pf note: c load = (dac output capacitance) + (external load capacitance) free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 306 it8511 e /te/ g this page is intentionally left blank. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 307 package information 12. package information lqfp 176l outline dimensions unit: inches/mm detail "a" base metal with plating b c detail "b" l 1 l gage plane o c aa 2 a 1 seating plane detail "b" d detail "a" y y e b 1 176 133 88 45 132 89 44 d 1 d e 1 e pin 1 identifier dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a 0.063 1.60 a 1 0.002 0.05 a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.005 0.008 0.12 0.20 d 1.018 1.024 1.030 25.85 26.00 26.15 d 1 0.941 0.945 0.949 23.90 24.00 24.10 e 1.018 1.024 1.030 25.85 26.00 26.15 e 1 0.941 0.945 0.949 23.90 24.00 24.10 e 0.020 bsc 0.50 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref y 0.004 0.10 0 3.5 7 0 3.5 7 note: 1. dimensions d 1 and e 1 do not include mold protrusion. but mold mismatch is included. 2. dimensions b does not include dambar protrusion. 3. controlling dimension: millimeter di-lqfp176(24*24)v1 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 308 it8511 e /te/ g tqfp 176l outline dimensions unit: inches/mm detail "a" base metal with plating b c d 1 d e 1 e b e 44 1 45 88 89 132 133 176 a 2 a 1 a see detail "b" y seating plane see detail "a" y d detail "b" l 1 l gage plane o c dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a 0.039 0.043 0.047 1.00 1.10 1.20 a 1 0.002 0.004 0.006 0.05 0.1 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.006 0.16 c 0.004 0.008 0.09 0.20 d 0.866 bsc 22.00 bsc d 1 0.787 bsc 20.00 bsc e 0.866 bsc 22.00 bsc e 1 0.787 bsc 20.00 bsc e 0.016 bsc 0.40 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref y 0.004 0.10 0 3.5 7 0 3.5 7 note: 1. dimensions d 1 and e 1 do not include mold protrusion. but mold mismatch is included. 2. dimensions b does not include dambar protrusion. 3. controlling dimension: millimeter di-tqfp176(20*20)v1 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 309 package information tfbga 180 outline dimensions unit: inches/mm a pin #1 -a- d -b- e ccc detail : a cavity a2 a1 a solder ball seating plane 2 b a ddd eee 1 2 detail : b 3 b a d1 e e1 b free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 310 it8511 e /te/ g dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a -- -- 0.055 -- -- 1.40 a 1 0.012 0.014 0.016 0.30 0.35 0.40 a 2 0.033 0.035 0.037 0.84 0.89 0.94 d 0.469 0.472 0.476 11.90 12.00 12.10 e 0.469 0.472 0.476 11.90 12.00 12.10 d1 -- 0.409 -- -- 10.40 -- e1 -- 0.409 -- -- 10.40 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 ccc 0.005 0.12 ddd 0.006 0.15 eee 0.003 0.08 note : 1. controlling dimension : millimeter. 2. primary datum c and seating plane are defined the spherical crowns of the solder balls. 3. dimension b is measured at the maximum solde r ball diameter, parallel to primary datum c. 4. there shall be a minimum clearance of 0.25mm between the edge of the solder ball and the b edge. 5. referance document : jedec mo-205. di-tfbga180(12*12)v0 free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 311 ordering information 13. ordering information part no. package it8511e lqfp 176l it8511te tqfp 176l IT8511G tfbga 180 ite provides lead-free component for the package of lqfp 176l . please mark " -l " at the end of the part no. when the parts ordered are lead-free. for the other two packages, please contact with ite sales personnel if there is any lead-free component requirement. free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 312 it8511 e /te/ g free datasheet http:/// www.ite.com.tw it8511e/te/g v0.4.1 313 top marking information it8511e 0607-xxx xxxxxx l date code (the seventh week of the year 2006) lotid it8511te 0607-xxx xxxxxx l date code (the seventh week of the year 2006) lotid IT8511G 0607-xxx xxxxxx l date code (the seventh week of the year 2006) lotid 14. top marking information part no. for lead free package (optional) tracking code part no. for lead free package (optional) tracking code part no. for lead free package (optional) tracking code free datasheet http:/// |
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