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| this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. january 2014 docid025743 rev 1 1/99 stm32f031xx arm-based 32-bit mcu with up to 32 kbytes flash, timers, adc and communication interfaces, 2.0-3.6 v datasheet ?? target specification features ? core: arm ? 32-bit cortex?-m0 cpu, frequency up to 48 mhz ? memories ? 16 to 32 kbytes of flash memory ? 4 kbytes of sram with hw parity checking ? crc calculation unit ? reset and supply management ? voltage range: 2.0 to 3.6 v ? power-on/power-down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? up to 39 fast i/os ? all mappable on external interrupt vectors ? up to 25 i/os with 5 v tolerant capability ? 5-channel dma controller ? 1 12-bit, 1.0 s adc (up to 10 channels) ? conversion range: 0 to 3.6v ? separate analog supply from 2.4 up to 3.6 v ? up to 9 timers ? 1 x 16-bit 7-channel advanced-control timer for 6 channels pwm output, with deadtime generation and emergency stop ? 1 x 32-bit and 1 x 16-bit timer, with up to 4 ic/oc, usable for ir control decoding ? 1 x 16-bit timer, with 2 ic/oc, 1 ocn, deadtime generation and emergency stop ? 1 x 16-bit timer, with ic/oc and ocn, deadtime generation, emergency stop and modulator gate for ir control ? 1 x 16-bit timer with 1 ic/oc ? independent and system watchdog timers ? systick timer: 24-bit downcounter ? calendar rtc with alarm and periodic wakeup from stop/standby ? communication interfaces ? 1 x i 2 c interface; supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, and wakeup from stop ? 1 x usart supporting master synchronous spi and modem control; one with iso7816 interface, lin, irda capability auto baud rate detection and wakeup feature ? 1 x spi (18 mbit/s) with 4 to 16 programmable bit frames, with i 2 s interface multiplexed ? serial wire debug (swd) ? 96-bit unique id ? extended temperature range: -40 to +105c ? all packages ecopack ? 2 table 1. device summary reference part number stm32f031xx stm32f031c4, stm32f031f4, stm32f031g4, stm32f031k4 stm32f031c6, STM32F031F6, stm32f031g6, stm32f031k6 lqfp48 7x7 ufqfpn32 5x5 tssop20 ufqfpn28 4x4 www.st.com
contents stm32f031xx 2/99 docid025743 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm? cortextm-m0 core with embedded flash and sram . . . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 16 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.2 general-purpose timers (tim2..3, tim14..17) . . . . . . . . . . . . . . . . . . . . 19 3.11.3 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.4 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20 3.13 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 universal synchronous/asynchronous receiver transmitters (usart) . . 22 docid025743 rev 1 3/99 stm32f031xx contents 4 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 23 3.16 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 42 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 42 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.18 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.19 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 contents stm32f031xx 4/99 docid025743 rev 1 6.3.20 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 95 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 docid025743 rev 1 5/99 stm32f031xx list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f031xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. stm32f031xx i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. stm32f031xx usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. stm32f031xx spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. alternate functions selected through gpioa_afr registers for port a . . . . . . . . . . . . . . . 32 table 13. alternate functions selected through gpiob_afr registers for port b . . . . . . . . . . . . . . . 33 table 14. stm32f031xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. typical and maximum current consumption from the v dd supply at v dd = 3.6 . . . . . . . . . 45 table 24. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 46 table 25. typical and maximum current consumption in stop and standby modes . . . . . . . . . . . . . 47 table 26. typical and maximum current consumption from the v bat supply. . . . . . . . . . . . . . . . . . . 48 table 27. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 28. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 50 table 29. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 31. low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 34. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 35. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 36. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 37. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 38. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 39. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 40. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 41. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 42. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 43. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 44. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 45. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 46. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 47. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 list of tables stm32f031xx 6/99 docid025743 rev 1 table 48. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 49. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 50. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 51. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 52. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 53. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 54. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 55. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 56. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 57. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 58. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 59. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 60. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 61. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 62. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 63. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 87 table 64. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 65. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 66. tssop20 ? 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 93 table 67. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 68. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 69. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 docid025743 rev 1 7/99 stm32f031xx list of figures 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. lqfp48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. ufqfpn32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. ufqfpn28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. tssop20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 13. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 14. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 figure 15. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 16. hsi oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 17. hsi14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 18. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 19. five volt tolerant (ft and ftf) i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 20. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 21. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 22. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 23. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 24. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 25. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 26. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 27. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 28. i2s slave timing diagram (philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 figure 29. i2s master timing diagram (philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 30. lqfp48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 87 figure 31. lqfp48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 32. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . . 89 figure 33. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 34. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . . 91 figure 35. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 36. tssop20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 37. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 introduction stm32f031xx 8/99 docid025743 rev 1 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f031xx microcontrollers. this document should be read in conjunction with the stm32f0xxxx reference manual (rm0091). the reference manual is available from the stmicroelectronics website www.st.com. for information on the arm cortex?-m0 core, please refer to the cortex?-m0 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html. docid025743 rev 1 9/99 stm32f031xx description 23 2 description the stm32f031xx microcontrollers incorporate the high-performance arm cortex?-m0 32-bit risc core operating at a 48 mhz maximum frequency, high-speed embedded memories (up to 32 kbytes of flash memory and up to 4 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (one i 2 c, one spi, one i2s, and one usart), one 12-bit adc, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control pwm timer. the stm32f031xx microcontrollers operate in the -40 to +85 c and -40 to +105 c temperature ranges, from a 2.0 to 3.6 v power supply. a comprehensive set of power- saving modes allows the design of low-power applications. the stm32f031xx microcontrollers include devices in four different packages ranging from 20 pins to 48 pins. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of stm32f031xx peripherals proposed. these features make the stm32f031xx microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs. description stm32f031xx 10/99 docid025743 rev 1 table 2. stm32f031xx family device features and peripheral counts peripheral stm32f031fx stm32f031gx stm32f031kx stm32f031cx flash (kbytes) 16 32 16 32 16 32 16 32 sram (kbytes) 4 4 4 4 timers advanced control 1 (16-bit) general purpose 4 (16-bit) 1 (32-bit) comm. interfaces spi (i2s) (1) 1 i 2 c1 usart 1 12-bit adc (number of channels) 1 (9 ext. + 3 int.) 1 (10 ext. + 3 int.) gpios 15 23 27 39 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: -40c to 105c / -40 c to 125 c packages tssop20 ufqfpn28 ufqfpn32 lqfp48 1. the spi interface can be used either in spi mode or in i2s audio mode. docid025743 rev 1 11/99 stm32f031xx description 23 figure 1. block diagram 0 ! ; = % 8 4 ) 4 . 6 ) # 3 7 # , + 3 7 $ ! 4 . 2 3 4 6 $ $ t o 6 ! & ! ( " 3 2 ! - 7 + 5 0 6 3 3 ' 0 $ - ! c h a n n e l s 8 4 ! , / 3 # - ( z 8 4 ! , k ( z / 3 # ) . 0 & / 3 # / 5 4 0 & / 3 # ? / 5 4 / 3 # ? ) . ! ( " 0 # , + ( # , + ! 0 " 0 # , + & , ! 3 ( 6 / , 4 2 % ' 6 4 / 6 6 $ $ 0 / 7 % 2 2 4 # i n t e r f a c e a s ! & " u s - a t r i x b i t s ) n t e r f a c e + " 2 4 # # / 2 4 % 8 - # 0 5 f ( # , + - ( z o b l f l a s h " a c k u p r e g 3 # , 3 $ ! 3 - " a l ) # a s ! & c h a n n e l s c o m p l c h a n n e l s " 2 + % 4 2 i n p u t a s ! & c h % 4 2 a s ! & & # , + 0 o w e r ) 7 $ ' 6 $ $ 6 3 7 0 / 2 0 $ 2 3 5 0 0 , 9 6 $ $ ! 6 $ $ ! 6 " ! 4 6 t o 6 2 8 4 8 # 4 3 2 4 3 # + a s ! & . 6 ) # 3 0 ) ) 3 # o n t r o l l e r 6 $ $ ! 3 5 0 % 2 6 ) 3 ) / . 0 6 $ 2 e s e t ) n t 6 $ $ ! 0 " 0 / 2 4 ! - 0 % 2 2 4 # 2 % 3 % 4 # , / # + # / . 4 2 / , ! $ # # , + 0 , , ! , ! 2 - / 5 4 3 e r i a l 7 i r e $ e b u g # % # # , + - ) 3 / - # + 0 " ; = 0 # ; = 0 & ; = c h % 4 2 a s ! & c h a n n e l a s ! & 6 $ $ + " 2 # ( 3 - ( z 5 3 ! 2 4 # , + c h a n n e l c o m p l " 2 + a s ! & c h a n n e l c o m p l " 2 + a s ! & c o n t r o l l e r 3 2 ! - 3 9 3 # & ' ) & m ! f o r & - ) 2 ? / 5 4 a s ! & $ " ' - # 5 ! ( " d e c o d e r - 3 6 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 5 3 ! 2 4 ' 0 ) / p o r t ! ' 0 ) / p o r t " ' 0 ) / p o r t # ' 0 ) / p o r t & b i t ! $ # ! $ # ? ) . 6 $ $ ! 4 e m p s e n s o r 6 3 3 ! 6 $ $ ! ) & 2 # ( 3 - ( z 2 # , 3 3 # + # + - / 3 ) 3 $ . 3 3 7 3 a s ! & 7 7 $ ' # 2 # functional overview stm32f031xx 12/99 docid025743 rev 1 3 functional overview 3.1 arm ? cortex tm -m0 core with embedded flash and sram the arm cortex?-m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? 4 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. ? the non-volatile memory is divided into two arrays: ? 16 to 32 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10. docid025743 rev 1 13/99 stm32f031xx functional overview 23 3.4 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a crc-32 (ethernet) polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v dda = 2.0 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 10: power supply scheme . 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. functional overview stm32f031xx 14/99 docid025743 rev 1 in standby mode, it is put in power down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). 3.5.4 low-power modes the stm32f031xx microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled.the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc alarm, i2c1, or usart1. the i2c1 and usart1 can be configured to enable the hsi rc oscillator for processing incoming data. if this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. docid025743 rev 1 15/99 stm32f031xx functional overview 23 3.6 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillator. a software interrupt is generated if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). several prescalers allow the application to configure the frequency of the ahb and the apb domains. the maximum frequency of the ahb and the apb domains is 48 mhz. figure 2. clock tree - ( z ( 3 % / 3 # / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 - ( z ( 3 ) 2 # t o ) 7 $ ' 0 , , x x x 0 , , - 5 , - # / ! ( " ! 0 " p r e s c a l e r ( # , + 0 , , # , + t o ! ( " b u s c o r e m e m o r y a n d $ - ! , 3 % , 3 ) ( 3 ) ( 3 ) ( 3 % t o 2 4 # 0 , , 3 2 # 3 7 3 9 3 # , + 2 4 # # , + 2 4 # 3 % , ; = t o 4 ) - ) f ! 0 " p r e s c a l e r x e l s e x & , ) 4 & # , + t o & l a s h p r o g r a m m i n g i n t e r f a c e t o ) # t o 5 3 ! 2 4 , 3 % ( 3 ) 3 9 3 # , + 0 # , + 3 9 3 # , + ( 3 ) 0 # , + - 3 6 t o ) 3 t o c o r t e x 3 y s t e m t i m e r & # , + # o r t e x f r e e r u n n i n g c l o c k t o ! 0 " ! ( " p r e s c a l e r # 3 3 , 3 % / 3 # k ( z , 3 ) 2 # k ( z 0 2 % $ ) 6 - a i n c l o c k o u t p u t 0 , , # , + ( 3 ) ( 3 % - # / 3 9 3 # , + ( 3 ) , 3 ) , 3 % 0 , , . / $ ) 6 t o 4 ) - - # / 0 2 % - ( z ( 3 ) 2 # ( 3 ) t o ! $ # c l o c k i n p u t p e r i p h e r a l s a s y n c h r o n o u s functional overview stm32f031xx 16/99 docid025743 rev 1 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.8 direct memory access controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2s, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m0) and 4 priority levels. ? closely coupled nvic gives low latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 39 gpios can be connected to the 16 external interrupt lines. docid025743 rev 1 17/99 stm32f031xx functional overview 23 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7c2 - 0x1fff f7c3 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7ba - 0x1fff f7bb functional overview stm32f031xx 18/99 docid025743 rev 1 3.10.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.11 timers and watchdogs the stm32f031xx devices include up to five general-purpose timers and an advanced control timer. table 5 compares the features of the advanced-control general-purpose timers. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim14 16-bit up any integer between 1 and 65536 no 1 no tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 yes docid025743 rev 1 19/99 stm32f031xx functional overview 23 3.11.1 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pwm generator, it has full modulation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can therefore work together with the other timers via the timer link feature for synchronization or event chaining. 3.11.2 general-purpose timers (tim2..3, tim14..17) there are six synchronizable general-purpose timers embedded in the stm32f031xx devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim2, tim3 stm32f031xx devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers can work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim16 and tim17 both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. functional overview stm32f031xx 20/99 docid025743 rev 1 they each have a single channel for input capture/output compare, pwm or one-pulse mode output. tim16 and tim17 have a complementary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.11.3 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.4 system window watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.11.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. docid025743 rev 1 21/99 stm32f031xx functional overview 23 the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm with wake up from stop and standby mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. ? 2 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? reference clock detection: a more precise second source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32 3.13 inter-integrated circuit interfaces (i 2 c) the i 2 c interface (i2c1) can operate in multimaster or slave modes. it can support standard mode (up to 100 kbit/s) fast mode (up to 400 kbit/s) and fast mode plus (up to 1 mbit/s) with 20 ma output drive. it supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). it also includes programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. functional overview stm32f031xx 22/99 docid025743 rev 1 from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interface can be served by the dma controller. 3.14 universal synchronous/asynchronous receiver transmitters (usart) the device embeds an universal synchronous/asynchronous receiver transmitter (usart1), which communicate at speeds of up to 6 mbit/s. it provides hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. usart1 supports also smartcard communication (iso 7816), irda sir endec, lin master/slave capability and auto baud rate feature, and has a clock domain independent from the cpu clock, allowing usart1 to wake up the mcu from stop mode. the usart interface can be served by the dma controller. table 7. stm32f031xx i 2 c implementation i2c features (1) 1. x = supported. i2c1 7-bit addressing mode x 10-bit addressing mode x standard mode (up to 100 kbit/s) x fast mode (up to 400 kbit/s) x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x independent clock x smbus x wakeup from stop x table 8. stm32f031xx usart implementation usart modes/features (1) usart1 hardware flow control for modem x continuous communication using dma x multiprocessor communication x synchronous mode x smartcard mode x single-wire half-duplex communication x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x docid025743 rev 1 23/99 stm32f031xx functional overview 23 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) the spi is able to communicate up to 18 mbits/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. one standard i 2 s interface (multiplexed with spi1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. it can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by an 8-bit programmable linear prescaler. when operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. 3.16 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x 1. x = supported. table 8. stm32f031xx usart implementation (continued) usart modes/features (1) usart1 table 9. stm32f031xx spi/i2s implementation spi features (1) 1. x = supported. spi hardware crc calculation x rx/tx fifo x nss pulse mode x i2s mode x ti mode x pinouts and pin description stm32f031xx 24/99 docid025743 rev 1 4 pinouts and pin description figure 3. lqfp48 48-pin package pinout figure 4. ufqfpn32 32-pin package pinout , 1 & 0 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 0 " 6 3 3 6 $ $ 0 & 0 & 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 6 " ! 4 . 2 3 4 6 3 3 ! 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ 6 3 3 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ! 0 ! - 3 6 0 # 0 # / 3 # ? ) . 0 & / 3 # ? ) . 0 & / 3 # ? / 5 4 0 # / 3 # ? / 5 4 0 ! 6 $ $ . 2 3 4 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 ! 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 " " / / 4 0 " 0 " 0 " - 3 6 6 $ $ ! 0 " 0 " 0 ! 0 " 0 " 0 ! 0 & / 3 # ? ) . 0 & / 3 # ? / 5 4 0 ! 6 3 3 6 3 3 ! docid025743 rev 1 25/99 stm32f031xx pinouts and pin description 33 figure 5. ufqfpn28 28-pin package pinout figure 6. tssop20 20-pin package pinout 3 $ 3 $ 3 $ 3 % 3 $ 3 $ 3 $ % 2 2 7 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 $ 3 % 3 % 3 $ 3 $ 3 % 3 % 0 6 9 3 $ 3 $ 3 $ 1 5 6 7 3 % 9 ' ' $ 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 - 3 6 0 & / 3 # ? ) . " / / 4 0 & / 3 # ? / 5 4 . 2 3 4 6 $ $ ! 0 ! 0 ! 6 $ $ 0 ! 0 ! 0 ! 0 " 6 3 3 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! pinouts and pin description stm32f031xx 26/99 docid025743 rev 1 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers docid025743 rev 1 27/99 stm32f031xx pinouts and pin description 33 table 11. pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions 1 - - - vbat s backup power supply 2 - - - pc13 i/o tc (1)(2) rtc_tamp1, rtc_ts, rtc_out, wkup2 3- - - pc14/osc32_in (pc14) i/o tc (1)(2) osc32_in 4- - - pc15/osc32_out (pc15) i/o tc (1)(2) osc32_out 52 2 2 pf0/osc_in (pf0) i/o ft osc_in 63 3 3 pf1/osc_out (pf1) i/o ft osc_out 7 4 4 4 nrst i/o rst device reset input / internal reset output (active low) 8 0 - - vssa s analog ground 9 5 5 5 vdda s analog power supply 10 6 6 6 pa0 i/o tta tim2_ch1_etr, usart1_cts adc_in0, rtc_tamp2, wkup1 11 7 7 7 pa1 i/o tta tim2_ch2, eventout, usart1_rts adc_in1 12 8 8 8 pa2 i/o tta tim2_ch3, usart1_tx adc_in2 13 9 9 9 pa3 i/o tta tim2_ch4, usart1_rx adc_in3 14 10 10 10 pa4 i/o tta spi1_nss, i2s1_ws, tim14_ch1, usart1_ck adc_in4 pinouts and pin description stm32f031xx 28/99 docid025743 rev 1 15 11 11 11 pa5 i/o tta spi1_sck, i2s1_ck, tim2_ch1_etr adc_in5 16 12 12 12 pa6 i/o tta spi1_miso, i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, eventout adc_in6 17 13 13 13 pa7 i/o tta spi1_mosi, i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 18 14 14 - pb0 i/o tta tim3_ch3, tim1_ch2n, eventout adc_in8 19 15 15 14 pb1 i/o tta tim3_ch4, tim14_ch1, tim1_ch3n adc_in9 20 16 - - pb2 i/o ft 21 - - - pb10 i/o ftf tim2_ch3, i2c1_scl 22 - - - pb11 i/o ftf tim2_ch4, eventout, i2c1_sda 23 0 16 15 vss s ground 24 17 17 16 vdd s digital power supply 25 - - - pb12 i/o ft tim1_bkin, eventout, spi1_nss table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions docid025743 rev 1 29/99 stm32f031xx pinouts and pin description 33 26 - - - pb13 i/o ft tim1_ch1n, spi1_sck 27 - - - pb14 i/o ft tim1_ch2n, spi1_miso 28 - - - pb15 i/o ft tim1_ch3n, spi1_mosi rtc_refin 29 18 18 - pa8 i/o ft usart1_ck, tim1_ch1, eventout, mco 30 19 19 17 pa9 i/o ftf usart1_tx, tim1_ch2, i2c1_scl 31 20 20 18 pa10 i/o ftf usart1_rx, tim1_ch3, tim17_bkin, i2c1_sda 32 21 - - pa11 i/o ft usart1_cts, tim1_ch4, eventout 33 22 - - pa12 i/o ft usart1_rts, tim1_etr, eventout 34 23 21 19 pa13 (swdio) i/o ft (3) ir_out, swdio 35 - - - pf6 i/o ftf i2c1_scl 36 - - - pf7 i/o ftf i2c1_sda 37 24 22 20 pa14 (swclk) i/o ft (3) usart1_tx, swclk table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions pinouts and pin description stm32f031xx 30/99 docid025743 rev 1 38 25 23 - pa15 i/o ft spi1_nss, i2s1_ws, tim2_ch_etr, eventout, usart1_rx 39 26 24 - pb3 i/o ft spi1_sck, i2s1_ck, tim2_ch2, eventout 40 27 25 - pb4 i/o ft spi1_miso, i2s1_mck, tim3_ch1, eventout 41 28 26 - pb5 i/o ft spi1_mosi, i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 42 29 27 - pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n 43 30 28 - pb7 i/o ftf i2c1_sda, usart1_rx, tim17_ch1n 44 31 1 1 boot0 i b boot memory selection 45 32 - - pb8 i/o ftf i2c1_scl, tim16_ch1 46 - - - pb9 i/o ftf i2c1_sda, ir_out, tim17_ch1, eventout 47 0 - - vss s ground 48 1 - - vdd s digital power supply table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions docid025743 rev 1 31/99 stm32f031xx pinouts and pin description 33 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led). 2. after the first rtc domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the rtc registers which are not reset by the system reset. for details on how to manage these gpios, refer to the rtc domain and rtc register descriptions in the reference manual. 3. after reset, these pins are configured as swdio and swclk alternate functions, and the internal pull-up on the swdio pin and the internal pull-down on the swclk pin are activated. pinouts and pin description stm32f031xx 32/99 docid025743 rev 1 table 12. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 usart1_cks tim2_ch1_ etr pa1 eventout usart1_tx tim2_ch2 pa2 usart1_rx tim2_ch3 pa3 usart1_cts tim2_ch4 pa4 spi1_nss, i2s1_ws usart1_rts tim14_ch1 pa5 spi1_sck, i2s1_ck tim2_ch1_ etr pa6 spi1_miso, i2s1_mck tim3_ch1 tim1_bkin tim16_ch1 eventout pa7 spi1_mosi, i2s1_sd tim3_ch2 tim1_ch1n tim14_ch1 tim17_ch1 eventout pa8 mco usart1_ck tim1_ch1 eventout pa9 usart1_tx tim1_ch2 i2c1_scl pa10 tim17_bkin usart1_rx tim1_ch3 i2c1_sda pa11 eventout usart1_cts tim1_ch4 pa12 eventout usart1_rts tim1_etr pa13 swdio ir_out pa14 swclk usart1_tx pa15 spi1_nss, i2s1_ws usart1_rx tim2_ch1_ etr eventout stm32f031xx pinouts and pin description docid025743 rev 1 33/99 table 13. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 pb0 eventout tim3_ch3 tim1_ch2n pb1 tim14_ch1 tim3_ch4 tim1_ch3n pb2 pb3 spi1_sck, i2s1_ck eventout tim2_ch2 pb4 spi1_miso, i2s1_mck tim3_ch1 eventout pb5 spi1_mosi, i2s1_sd tim3_ch2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n pb7 usart1_rx i2c1_sda tim17_ch1n pb8 i2c1_scl tim16_ch1 pb9 ir_out i2c1_sda tim17_ch1 eventout pb10 i2c1_scl tim2_ch3 pb11 eventout i2c1_sda tim2_ch4 pb12 spi1_nss eventout tim1_bkin pb13 spi1_sck tim1_ch1n pb14 spi1_miso tim1_ch2n pb15 spi1_mosi tim1_ch3n memory mapping stm32f031xx 34/99 docid025743 rev 1 5 memory mapping figure 7. memory map 2 e s e r v e d ! ( " x & & & & & & & & 0 e r i p h e r a l s 3 2 ! - & l a s h m e m o r y r e s e r v e d r e s e r v e d 3 y s t e m m e m o r y / p t i o n b y t e s x % - 3 6 & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n " / / 4 c o n f i g u r a t i o n x x % x # x ! x x x x x x x x & & & % # x & & & & x & & & & # x & & & & & & & x r e s e r v e d # / $ % ! 0 " ! 0 " r e s e r v e d x x x x r e s e r v e d x ! ( " x r e s e r v e d x & & x & & x x # o r t e x - i n t e r n a l p e r i p h e r a l s docid025743 rev 1 35/99 stm32f031xx memory mapping 36 table 14. stm32f031xx peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1kb gpiof 0x4800 0c00 - 0x4800 13ff 2kb reserved 0x4800 0800 - 0x4800 0bff 1kb gpioc 0x4800 0400 - 0x4800 07ff 1kb gpiob 0x4800 0000 - 0x4800 03ff 1kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 3400 - 0x4002 43ff 4kb reserved 0x4002 3000 - 0x4002 33ff 1kb crc 0x4002 2400 - 0x4002 2fff 3kb reserved 0x4002 2000 - 0x4002 23ff 1kb flash interface 0x4002 1400 - 0x4002 1fff 3kb reserved 0x4002 1000 - 0x4002 13ff 1kb rcc 0x4002 0400 - 0x4002 0fff 3kb reserved 0x4002 0000 - 0x4002 03ff 1kb dma 0x4001 8000 - 0x4001 ffff 32kb reserved apb 0x4001 5c00 - 0x4001 7fff 9kb reserved 0x4001 5800 - 0x4001 5bff 1kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3kb reserved 0x4001 4800 - 0x4001 4bff 1kb tim17 0x4001 4400 - 0x4001 47ff 1kb tim16 0x4001 3c00 - 0x4001 43ff 2kb reserved 0x4001 3800 - 0x4001 3bff 1kb usart1 0x4001 3400 - 0x4001 37ff 1kb reserved 0x4001 3000 - 0x4001 33ff 1kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1kb tim1 0x4001 2800 - 0x4001 2bff 1kb reserved 0x4001 2400 - 0x4001 27ff 1kb adc 0x4001 0800 - 0x4001 23ff 7kb reserved 0x4001 0400 - 0x4001 07ff 1kb exti 0x4001 0000 - 0x4001 03ff 1kb syscfg 0x4000 8000 - 0x4000 ffff 32kb reserved memory mapping stm32f031xx 36/99 docid025743 rev 1 apb 0x4000 7400 - 0x4000 7fff 3kb reserved 0x4000 7000 - 0x4000 73ff 1kb pwr 0x4000 5800 - 0x4000 6fff 6kb reserved 0x4000 5400 - 0x4000 57ff 1kb i2c1 0x4000 3400 - 0x4000 53ff 8kb reserved 0x4000 3000 - 0x4000 33ff 1kb iwdg 0x4000 2c00 - 0x4000 2fff 1kb wwdg 0x4000 2800 - 0x4000 2bff 1kb rtc 0x4000 2400 - 0x4000 27ff 1kb reserved 0x4000 2000 - 0x4000 23ff 1kb tim14 0x4000 0800 - 0x4000 1fff 6kb reserved 0x4000 0400 - 0x4000 07ff 1kb tim3 0x4000 0000 - 0x4000 03ff 1kb tim2 table 14. stm32f031xx peripheral register boundary addresses (continued) bus boundary address size peripheral docid025743 rev 1 37/99 stm32f031xx electrical characteristics 85 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading conditions figure 9. pin input voltage - 3 6 & s ) - # 5 p i n - 3 6 - # 5 p i n 6 ) . electrical characteristics stm32f031xx 38/99 docid025743 rev 1 6.1.6 power supply scheme figure 10. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 9 ' ' / h y h o v k l i w h u , 2 o r j l f . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v , 1 2 8 7 5 h j x o d w r u * 3 , 2 v 9 [ q ) [ ? ) [ 9 6 6 [ 9 ' ' 9 % $ 7 9 & 2 5 ( 3 r z h u v z l w f k $ ' & ' $ & $ q d o r j 5 & v 3 / / ? 9 5 ( ) 9 5 ( ) 9 ' ' $ q ) ? ) 9 ' ' $ 9 6 6 $ 9 ' ' , 2 0 6 y 9 docid025743 rev 1 39/99 stm32f031xx electrical characteristics 85 6.1.7 current consumption measurement figure 11. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 15: voltage characteristics , table 16: current characteristics , and table 17: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. - 3 6 6 " ! 4 6 $ $ 6 $ $ ! ) $ $ ) $ $ ! * % % @ 7 # " 5 table 15. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v ddx ?v ss external main supply voltage (including v dda, v dd and v bat ) ?0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda - 0.4 v v in (2) 2. v in maximum must always be respected. refer to table 16: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 v input voltage on any other pin v ss ?? 0.3 4.0 v | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ?? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics electrical characteristics stm32f031xx 40/99 docid025743 rev 1 table 16. current characteristics symbol ratings max. unit ? i vdd total current into sum of all vdd power lines (source) (1) 120 ma ? i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 ? i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) (3) injected current on ft, ftf and b pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count qfp packages. 3. a positive injection is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 15: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 53: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 17. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025743 rev 1 41/99 stm32f031xx electrical characteristics 85 6.3 operating conditions 6.3.1 general operating conditions table 18. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 48 mhz f pclk internal apb clock frequency 0 48 v dd standard operating voltage 2 3.6 v v dda analog operating voltage (adc not used) must have a potential equal to or higher than v dd 2 3.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.65 3.6 v v in i/o input voltage tc and rst i/o ?0.3 v ddiox +0.3 v tta i/o ?0.3 v dda +0.3 ft and ftf i/o ?0.3 5.5 (1) boot0 0 9.0 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) lqfp48 - 364 mw ufqfpn32 - 526 ufqfpn28 - 169 tssop20 - 182 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low power dissipation (3) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 1. to sustain a voltage higher than v ddiox +0.3 v, the internal pull-up/pull-down resistors must be disabled. 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). electrical characteristics stm32f031xx 42/99 docid025743 rev 1 6.3.2 operating conditions at power-up / power-down the parameters given in table 19 are derived from tests performed under the ambient temperature condition summarized in table 18 . 6.3.3 embedded reset and power control block characteristics the parameter given in table 20 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 19. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate 0 ? v dda fall time rate 20 ? table 20. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.80 1.88 1.96 (3) 3. data based on characterization results, not tested in production. v rising edge 1.84 (3) 1.92 2.00 v v pdrhyst (1) pdr hysteresis - 40 - mv t rsttempo (4) 4. guaranteed by design, not tested in production. reset temporization 1.50 2.50 4.50 ms table 21. programmable voltage detector characteristics symbol parameter conditions min typ max unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v docid025743 rev 1 43/99 stm32f031xx electrical characteristics 85 6.3.4 embedded reference voltage the parameters given in table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (1) pvd hysteresis - 100 - mv i dd(pvd) pvd current consumption - 0.15 0.26 (1) a 1. guaranteed by design, not tested in production. table 21. programmable voltage detector characteristics (continued) symbol parameter conditions min typ max unit table 22. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint (2) 2. the shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 17.1 (3) 3. guaranteed by design, not tested in production. -- s ? v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (3) mv t coeff temperature coefficient - - 100 (3) ppm/c electrical characteristics stm32f031xx 44/99 docid025743 rev 1 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled except when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 23 to table 26 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . docid025743 rev 1 45/99 stm32f031xx electrical characteristics 85 table 23. typical and maximum current consumption from the v dd supply at v dd = 3.6 symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, code executing from flash hse bypass, pll on 48 mhz 18.4 20.0 20.1 20.4 11.4 12.5 12.5 12.6 ma 32 mhz 12.4 13.2 13.2 13.8 7.9 8.3 8.5 8.6 24 mhz 9.9 10.7 10.7 11.0 6.2 6.8 7.0 7.0 hse bypass, pll off 8 mhz 3.3 3.6 3.8 3.9 2.2 2.6 2.6 2.6 1 mhz 0.8 1.1 1.1 1.1 0.7 0.9 0.9 0.9 hsi clock, pll on 48 mhz 18.9 20.9 21.1 21.5 11.7 12.3 12.9 13.1 32 mhz 12.8 13.7 14.2 14.8 8.0 8.7 9.1 9.1 24 mhz 9.7 10.4 11.2 11.3 6.1 6.5 6.7 6.9 hsi clock, pll off 8 mhz 3.5 4.0 4.0 4.1 2.4 2.6 2.7 2.7 supply current in run mode, code executing from ram hse bypass, pll on 48 mhz 17.3 19.7 (2) 19.8 20.0 (2) 10.3 11.2 (2) 11.3 11.7 (2) 32 mhz 11.2 12.5 12.7 12.7 6.7 7.3 7.6 7.6 24 mhz 8.9 10.0 10.1 10.2 5.1 5.5 5.8 5.9 hse bypass, pll off 8 mhz 2.8 3.1 3.3 3.4 1.7 2.0 2.1 2.1 1 mhz 0.3 0.6 0.6 1.3 0.2 0.5 0.8 0.9 hsi clock, pll on 48 mhz 17.4 19.7 20.0 20.2 10.4 11.2 11.3 11.8 32 mhz 11.8 12.8 13.1 13.3 6.8 7.4 7.7 7.9 24 mhz 9.0 10.0 10.1 10.2 5.2 5.7 6.0 6.0 hsi clock, pll off 8 mhz 3.0 3.2 3.5 3.6 1.8 2.0 2.2 2.2 supply current in sleep mode, code executing from flash or ram hse bypass, pll on 48 mhz 10.7 11.7 (2) 11.9 12.5 (2) 2.4 2.6 (2) 2.7 2.9 (2) 32 mhz 7.1 7.8 8.1 8.2 1.6 1.7 1.9 1.9 24 mhz 5.5 6.3 6.4 6.4 1.3 1.4 1.5 1.5 hse bypass, pll off 8 mhz 1.8 2.0 2.0 2.1 0.4 0.4 0.5 0.5 1 mhz 0.2 0.5 0.5 0.5 0.1 0.1 0.1 0.1 hsi clock, pll on 48 mhz 10.8 11.9 12.1 12.6 2.4 2.7 2.7 2.9 32 mhz 7.3 8.0 8.4 8.5 1.7 1.9 1.9 2.0 24 mhz 5.5 6.2 6.5 6.5 1.3 1.5 1.5 1.6 hsi clock, pll off 8 mhz 1.9 2.2 2.3 2.4 0.5 0.5 0.5 0.6 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). electrical characteristics stm32f031xx 46/99 docid025743 rev 1 table 24. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run or sleep mode, code executing from flash or ram hse bypass, pll on 48 mhz 150 170 (3) 178 182 (3) 164 183 (3) 195 198 (3) a 32 mhz 104 121 126 128 113 129 135 138 24 mhz 82 96 100 103 88 102 106 108 hse bypass, pll off 8 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 1 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 hsi clock, pll on 48 mhz 220 240 248 252 244 263 275 278 32 mhz 174 191 196 198 193 209 215 218 24 mhz 152 167 173 174 168 183 190 192 hsi clock, pll off 8 mhz 72 79 82 83 83.5 91 94 95 1. current consumption from the v dda supply is independent of whether the digital peripherals are enabled or disabled, being in run or sleep mode or executing from flash or ram. furthermore, when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production unless otherwise specified. 3. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). docid025743 rev 1 47/99 stm32f031xx electrical characteristics 85 table 25. typical and maximum current consumption in stop and standby modes sym- bol para- meter conditions typ @v dd (v dd = v dda ) max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 15 15.1 15.25 15.45 15.7 16 18 (2) 38 55 (2) a regulator in low- power mode, all oscillators off 3.15 3.25 3.35 3.45 3.7 4 5.5 (2) 22 41 (2) supply current in standby mode lsi on and iwdg on 0.8 0.95 1.05 1.2 1.35 1.5 - - - lsi off and iwdg off 0.65 0.75 0.85 0.95 1.1 1.3 2 (2) 2.5 3 (2) i dda supply current in stop mode v dda monitoring on regulator in run mode, all oscillators off 1.85 2 2.15 2.3 2.45 2.6 3.5 (2) 3.5 4.5 (2) regulator in low- power mode, all oscillators off 1.85 2 2.15 2.3 2.45 2.6 3.5 (2) 3.5 4.5 (2) supply current in standby mode lsi on and iwdg on 2.25 2.5 2.65 2.85 3.05 3.3 - - - lsi off and iwdg off 1.75 1.9 2 2.15 2.3 2.5 3.5 (2) 3.5 4.5 (2) supply current in stop mode v dda monitoring off regulator in run mode, all oscillators off 1.11 1.15 1.18 1.22 1.27 1.35 - - - regulator in low- power mode, all oscillators off 1.11 1.15 1.18 1.22 1.27 1.35 - - - supply current in standby mode lsi on and iwdg on 1.5 1.58 1.65 1.78 1.91 2.04 - - - lsi off and iwdg off 1 1.02 1.05 1.05 1.15 1.22 - - - 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ) . electrical characteristics stm32f031xx 48/99 docid025743 rev 1 typical current consumption the mcu is placed under the following conditions: ? v dd =v dda =3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively table 26. typical and maximum current consumption from the v bat supply symbol parameter conditions typ @ v bat max (1) unit = 1.65 v = 1.8 v = 2.4 v = 2.7 v = 3.3 v = 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd _ vbat rtc domain supply current lse & rtc on; ?xtal mode?: lower driving capability; lsedrv[1:0] = '00' 0.41 0.43 0.53 0.58 0.71 0.80 0.85 1.1 1.5 a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1:0] = '11' 0.71 0.75 0.85 0.91 1.06 1.16 1.25 1.55 2 1. data based on characterization results, not tested in production. docid025743 rev 1 49/99 stm32f031xx electrical characteristics 85 table 27. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 18.4 11.4 ma 36 mhz 13.9 8.9 32 mhz 12.4 7.9 24 mhz 9.9 6.2 16 mhz 6.6 4.3 8 mhz 3.3 2.2 4 mhz 1.7 1.6 2 mhz 1.3 1.2 1 mhz 0.8 0.7 500 khz 0.6 0.6 i dda supply current in run mode from v dda supply 48 mhz 140 140 a 36 mhz 109 109 32 mhz 96 96 24 mhz 76 76 16 mhz 51 51 8 mhz 1.7 1.7 4 mhz 1.6 1.6 2 mhz 1.5 1.5 1 mhz 1.1 1.1 500 khz 1.1 1.1 electrical characteristics stm32f031xx 50/99 docid025743 rev 1 table 28. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 48 mhz 10.7 2.4 ma 36 mhz 8.1 1.8 32 mhz 7.1 1.6 24 mhz 5.5 1.3 16 mhz 3.7 0.9 8 mhz 1.9 0.5 4 mhz 1.5 0.4 2 mhz 1.1 0.3 1 mhz 0.8 0.3 500 khz 0.6 0.3 125 khz 0.5 0.3 i dda supply current in sleep mode from v dda supply 48 mhz 140 140 a 36 mhz 109 109 32 mhz 96 96 24 mhz 76 76 16 mhz 51 51 8 mhz 1.7 1.7 4 mhz 1.6 1.6 2 mhz 1.5 1.5 1 mhz 1.1 1.1 500 khz 1.1 1.1 125 khz 1.1 1.1 docid025743 rev 1 51/99 stm32f031xx electrical characteristics 85 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low . the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 47: i/o static characteristics. for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently , as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 30: peripheral current consumption), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: i sw v ddiox f sw c u u = where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. electrical characteristics stm32f031xx 52/99 docid025743 rev 1 table 29. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c =c int 4 mhz 0.07 ma 8 mhz 0.15 16 mhz 0.31 24 mhz 0.53 48 mhz 0.92 v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 10 pf c = c int + c ext + c s 4 mhz 0.32 8 mhz 0.64 16 mhz 1.25 24 mhz 2.23 48 mhz 4.442 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 33 pf c = c int + c ext + c s 4 mhz 0.64 8 mhz 1.25 16 mhz 3.24 24 mhz 5.02 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 v ddiox = 2.4 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.66 8 mhz 1.43 16 mhz 2.45 24 mhz 4.97 docid025743 rev 1 53/99 stm32f031xx electrical characteristics 85 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in table 30 . the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and supply voltage conditions summarized in table 15: voltage characteristics ? the peripheral clock used is 48 mhz. table 30. peripheral current consumption peripheral typical consumption at 25 c unit i dd i dda adc (1) 1. adc is in ready state after setting the aden bit in the adc_cr register (adrdy bit in adc_isr is high). 0.53 0.964 ma crc 0.10 - dbgmcu 0.18 - dma 0.35 - gpioa 0.48 - gpiob 0.58 - gpioc 0.12 - gpiof 0.06 - i2c1 0.43 - pwr 0.22 - spi1/i2s1 0.63 - syscfg 0.28 tim1 1.01 - tim2 1.00 - tim3 0.78 - tim6 0.32 - tim14 0.45 - tim16 0.57 - tim17 0.59 - usart1 1.07 - wwdg 0.22 - electrical characteristics stm32f031xx 54/99 docid025743 rev 1 6.3.6 wakeup time from low-power mode the wakeup times given in table 31 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wait for interruption) instruction, 16 cpu cycles must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setting is kept unchanged after wakeup from sleep mode. after wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions except when explicitly mentioned. table 31. low-power mode wakeup timings symbol parameter conditions typ @v dd max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 4.20 4.20 4.20 4.20 4.20 5 s regulator in low power mode 8.05 7.05 6.60 6.27 6.05 9 t wustandby wakeup from standby mode 60.35 55.60 53.50 52.02 50.96 - t wusleep wakeup from sleep mode 4 sysclk cycles - docid025743 rev 1 55/99 stm32f031xx electrical characteristics 85 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 12: high-speed external clock source ac timing diagram . figure 12. high-speed external clock source ac timing diagram table 32. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f hse_ext user external clock source frequency 1 8 32 mhz v hseh osc_in input pin high level voltage 0.7 v dd -v dd v v hsel osc_in input pin low level voltage v ss - 0.3 v dd t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 - 3 6 6 ( 3 % ( t f ( 3 % 4 ( 3 % t t r ( 3 % 6 ( 3 % , t 7 ( 3 % ( t 7 ( 3 % , electrical characteristics stm32f031xx 56/99 docid025743 rev 1 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 13 . figure 13. low-speed external clock source ac timing diagram table 33. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v dd -v dd v v lsel osc32_in input pin low level voltage v ss - 0.3 v dd t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 - 3 6 6 , 3 % ( t f , 3 % 4 , 3 % t t r , 3 % 6 , 3 % , t 7 , 3 % ( t 7 , 3 % , docid025743 rev 1 57/99 stm32f031xx electrical characteristics 85 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 34 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 14 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 34. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 - k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time - 8.5 ma v dd = 3.3 v, rm = 30 ? , cl = 10 pf@8 mhz - 0.4 - v dd = 3.3 v, rm = 45 ? , cl = 10 pf@8 mhz - 0.5 - v dd = 3.3 v, rm = 30 ? , cl = 5 pf@32 mhz - 0.8 - v dd = 3.3 v, rm = 30 ? , cl = 10 pf@32 mhz -1- v dd = 3.3 v, rm = 30 ? , cl = 20 pf@32 mhz - 1.5 - g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms electrical characteristics stm32f031xx 58/99 docid025743 rev 1 figure 14. typical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % # , 2 & - ( z r e s o n a t o r 2 % 8 4 # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n docid025743 rev 1 59/99 stm32f031xx electrical characteristics 85 low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 35 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 35. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability - 0.5 0.9 a lsedrv[1:0]= 01 medium low driving capability --1 lsedrv[1:0] = 10 medium high driving capability - - 1.3 lsedrv[1:0]=11 higher driving capability - - 1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer electrical characteristics stm32f031xx 60/99 docid025743 rev 1 figure 15. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f , 3 % # , k ( z r e s o n a t o r # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s $ r i v e p r o g r a m m a b l e a m p l i f i e r docid025743 rev 1 61/99 stm32f031xx electrical characteristics 85 6.3.8 internal clock source characteristics the parameters given in table 36 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator figure 16. hsi oscillator accuracy characterization results table 36. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 - mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. - 4.6 (3) % t a = ?10 to 85 c ?2.9 (3) - 2.9 (3) % t a = 0 to 70 c ?2.3 (3) - 2.2 (3) % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - 80 100 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! electrical characteristics stm32f031xx 62/99 docid025743 rev 1 high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) figure 17. hsi14 oscillator accuracy characterization results table 37. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - 14 - mhz trim hsi14 user-trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 105 c ?4.2 (3) 3. data based on characterization results, not tested in production. - 5.1 (3) % t a = ?10 to 85 c ?3.2 (3) - 3.1 (3) % t a = 0 to 70 c ?2.5 (3) - 2.3 (3) % t a = 25 c ?1 - 1 % t su(hsi14) hsi14 oscillator startup time 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption - 100 150 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! docid025743 rev 1 63/99 stm32f031xx electrical characteristics 85 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 38. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 39. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) - 48 mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps electrical characteristics stm32f031xx 64/99 docid025743 rev 1 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 6.3.11 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 42 . they are based on the ems levels and classes defined in application note an1709. table 40. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 40 53.5 60 s t erase page (1 kb) erase time t a ?? ?40 to +105 c 20 - 40 ms t me mass erase time t a ?? ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 41. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 docid025743 rev 1 65/99 stm32f031xx electrical characteristics 85 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 42. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp64, t a ?? +25 c, f hclk ?? 48 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp64, t a ?? +25 c, f hclk ?? 48 mhz, conforming to iec 61000-4-4 3b table 43. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd ?? 3.6 v, t a ?? 25 c, lqfp64 package compliant with iec 61967-2 0.1 to 30 mhz -3 db v 30 to 130 mhz 28 130 mhz to 1ghz 23 sae emi level 4 - electrical characteristics stm32f031xx 66/99 docid025743 rev 1 6.3.12 electrical sensitivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. table 44. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 45. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a docid025743 rev 1 67/99 stm32f031xx electrical characteristics 85 functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator frequency deviation). the characterization results are given in table 46 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 47 are derived from tests performed under the conditions summarized in table 18: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 46. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ?0 na ma injected current on all ft and ftf pins ?5 na injected current on all tta, tc and reset pins ?5 +5 table 47. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) boot0 - - 0.3 v ddiox ?0.3 (1) all i/os except boot0 pin - - 0.3 v ddiox v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- boot0 0.2 v ddiox +0.95 (1) -- all i/os except boot0 pin 0.7 v ddiox -- electrical characteristics stm32f031xx 68/99 docid025743 rev 1 v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss ? ? v in ? ?? v ddiox -- ? ? 0.1 a tta in digital mode v ddiox ? ? v in ? ?? v dda --1 tta in analog mode v ss ? ? v in ? ?? v dda -- ? ? 0.2 ft and ftf i/o (3) v ddiox ? ?? v in ? ?? 5 v --10 r pu weak pull-up equivalent resistor (4) v in ?? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (4) v in ?? v ddiox 25 40 55 k ? c io i/o pin capacitance - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 46: i/o current injection susceptibility . 3. to sustain a voltage higher than v ddiox +0.3 v, the internal pull-up/pull-down resistors must be disabled. 4. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 47. i/o static characteristics (continued) symbol parameter conditions min typ max unit docid025743 rev 1 69/99 stm32f031xx electrical characteristics 85 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 18 for standard i/os, and in figure 19 for 5 v tolerant i/os. figure 18. tc and tta i/o input characteristics figure 19. five volt tolerant (ft and ftf) i/o input characteristics & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' , 2 [ 9 , + p l q 9 ' ' , 2 [ 7 h v w h g u d q j h 8 q g h i l q h g l q s x w u d q j h 9 , / p d [ 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w v 7 h v w h g u d q j h 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w 0 6 9 9 9 , 1 9 9 ' ' , 2 [ 0 6 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w & 0 2 6 v w d q g d u g u h t x l u h p h q w v 7 h v w h g u d q j h 9 , + p l q 9 ' ' , 2 [ 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 8 q g h i l q h g l q s x w u d q j h & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' , 2 [ 7 h v w h g u d q j h 9 9 , 1 9 9 ' ' , 2 [ electrical characteristics stm32f031xx 70/99 docid025743 rev 1 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 16: current characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximum consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating ? i vss (see table 16: current characteristics ). output voltage levels unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). table 48. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox ? 2.7 v - 1.3 v v oh (3) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 6 ma - 0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v olfm+ (4) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox ? 2.7 v - 0.4 v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must always respect the absolute maximum rating specified in table 16: current characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings ? i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. data based on characterization results. not tested in production. 4. data based on design simulation only. not tested in production. docid025743 rev 1 71/99 stm32f031xx electrical characteristics 85 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 20 and table 49 , respectively. unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 49. i/o ac characteristics (1)(2) 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32f0xxxx rm0091 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) 3. the maximum frequency is defined in figure 20 . c l = 50 pf - 2 mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf - 10 mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox ? 2.7 v - 50 mhz c l = 50 pf, v ddiox ? 2.7 v - 30 c l = 50 pf, v ddiox ? 2.7 v- 20 t f(io)out output fall time c l = 30 pf, v ddiox ? 2.7 v - 5 ns c l = 50 pf, v ddiox ? 2.7 v- 8 c l = 50 pf, v ddiox ? 2.7 v- 12 t r(io)out output rise time c l = 30 pf, v ddiox ? 2.7 v- 5 c l = 50 pf, v ddiox ? 2.7 v- 8 c l = 50 pf, v ddiox ? 2.7 v- 12 fm+ configuration (4) 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f0xxxx reference manual rm0091 for a detailed description of fm+ i/o configuration. f max(io)out maximum frequency (3) c l = 50 pf - 2 mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 t extipw pulse width of external signals detected by the exti controller 10 - ns electrical characteristics stm32f031xx 72/99 docid025743 rev 1 figure 20. i/o ac characteristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ w k h v s h f l i l h g f d s d f l w d q f h u i u , 2 r x w w i , 2 r x w w table 50. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage 0.445 v dd +0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) v in ?? v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (1) -- ns 2.0 < v dd < 3.6 500 (1) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order) . docid025743 rev 1 73/99 stm32f031xx electrical characteristics 85 figure 21. recommended nrst pin protection 1. the external capacitor protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 50: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 51 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions summarized in table 18: general operating conditions . note: it is recommended to perform a calibration after each power-up. 5 3 8 9 ' ' 0 6 9 , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 51. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dd = v dda = 3.3 v - 0.9 - ma f adc adc clock frequency 0.6 - 14 mhz f s (2) sampling rate 0.05 - 1 mhz f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz - - 17 1/f adc v ain conversion voltage range 0 - v dda v r ain (2) external input impedance see equation 1 and table 52 for details - - 50 k ? r adc (2) sampling switch resistance --1k ? c adc (2) internal sample and hold capacitor --8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc r ain t s f adc c adc 2 n2 + ln u u ------------------------------------------------------------- - r adc ? electrical characteristics stm32f031xx 74/99 docid025743 rev 1 equation 1: r ain max formula the formula above (equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). w latency (2) adc_dr register write latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 ?s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 ?s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 ?s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 ?s 1.5 - 239.5 1/f adc t stab (2) power-up time 0 0 1 ?s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 - 18 ?s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x adc clock period), an additional consumption of 100 ?a on i dda and 60 ?a on i dd should be taken into account. 2. guaranteed by design, not tested in production. table 51. adc characteristics (continued) symbol parameter conditions min typ max unit table 52. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k :) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 docid025743 rev 1 75/99 stm32f031xx electrical characteristics 85 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 53. adc accuracy (1)(2)(3) 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. symbol parameter test conditions typ max (4) 4. data based on characterization results, not tested in production. unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 3 v to 3.6 v t a = 25 c 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.7 v to 3.6 v t a = ? 40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 table 52. r ain max for f adc = 14 mhz (continued) t s (cycles) t s ( ? s) r ain max (k ? ) (1) electrical characteristics stm32f031xx 76/99 docid025743 rev 1 figure 22. adc accuracy characteristics figure 23. typical connection diagram using the adc 1. refer to table 51: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 10: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. % / % ' , 3 " ) $ % ! , % x a m p l e o f a n a c t u a l t r a n s f e r c u r v e 4 h e i d e a l t r a n s f e r c u r v e % n d p o i n t c o r r e l a t i o n l i n e % 4 4 o t a l 5 n a d j u s t e d % r r o r m a x i m u m d e v i a t i o n b e t w e e n t h e a c t u a l a n d t h e i d e a l t r a n s f e r c u r v e s % / / f f s e t % r r o r d e v i a t i o n b e t w e e n t h e f i r s t a c t u a l t r a n s i t i o n a n d t h e f i r s t i d e a l o n e % ' ' a i n % r r o r d e v i a t i o n b e t w e e n t h e l a s t i d e a l t r a n s i t i o n a n d t h e l a s t a c t u a l o n e % $ $ i f f e r e n t i a l , i n e a r i t y % r r o r m a x i m u m d e v i a t i o n b e t w e e n a c t u a l s t e p s a n d t h e i d e a l o n e % , ) n t e g r a l , i n e a r i t y % r r o r m a x i m u m d e v i a t i o n b e t w e e n a n y a c t u a l t r a n s i t i o n a n d t h e e n d p o i n t c o r r e l a t i o n l i n e % 4 % $ % , 6 $ $ ! 6 3 3 ! - 3 6 0 6 9 9 ' ' $ $ , 1 [ , / ? ? $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid025743 rev 1 77/99 stm32f031xx electrical characteristics 85 6.3.17 temperature sensor characteristics 6.3.18 v bat monitoring characteristics 6.3.19 timer characteristics the parameters given in the following tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 54. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - ? ? 1 ? ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( ?? 5 c) (2) 2. measured at v dda = 3.3 v ?? 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte ?? refer to table 3: temperature sensor calibration values . 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(3) 3. the shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 - - s table 55. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k ? q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q ?1 - +1 % t s_vbat (1)(2) 2. the shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat (for 1 mv accuracy) 5- - s table 56. timx (1) characteristics symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 48 mhz 20.8 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz electrical characteristics stm32f031xx 78/99 docid025743 rev 1 6.3.20 communication interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. res tim timer resolution timx (except tim2) -16 bit tim2 - 32 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 48 mhz - 89.48 s 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim6, tim14, tim15, tim16 and tim17 timers. table 57. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller?s internal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 58. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 table 56. timx (1) characteristics (continued) symbol parameter conditions min max unit docid025743 rev 1 79/99 stm32f031xx electrical characteristics 85 the i 2 c characteristics are described in table 59 . refer also to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 59. i2c characteristics (1) symbol parameter standard fast mode fast mode + unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t low low period of the scl clock 4.7 - 1.3 - 0.5 - s t high high period of the scl clock 4 0.6 - 0.26 - s tr rise time of both sda and scl signals - 1000 - 300 - 120 ns tf fall time of both sda and scl signals - 300 - 300 - 120 ns t hd;dat data hold time 0 - 0 - 0 - s t vd;dat data valid time - 3.45 (2) - 0.9 (2) - 0.45 (2) s t vd;ack data valid acknowledge time - 3.45 (2) - 0.9 (2) - 0.45 (2) s t su;dat data setup time 250 - 100 - 50 - ns t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - s t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - s c b capacitive load for each bus line - 400 - 400 - 550 pf t sp pulse width of spikes that are suppressed by the analog filter 050 (3) 050 (3) 050 (3) ns 1. the i2c characteristics are the requirements from the i2c bus specification rev03. they are guaranteed by design when the i2cx_timing register is correctly programmed (refer to reference manual). these characteristics are not tested in production. 2. the maximum t hd;dat could be 3.45 s, 0.9 s and 0.45 s for standard mode, fast mode and fast mode plus, but must be less than the maximum of t vd;dat or t vd;ack by a transition time. 3. the minimum width of the spikes filtered by the analog filter is above t sp(max) . electrical characteristics stm32f031xx 80/99 docid025743 rev 1 figure 24. i 2 c bus ac waveforms and measurement circuit legend: rs: series protection resistors. rp: pull-up resistors. v dd_i2c : i 2 c bus supply. spi/i 2 s characteristics unless otherwise specified, the parameters given in table 61 for spi or in table 62 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 18: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 60. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns 0 6 9 5 v , & e x v 5 s 5 v 9 ' ' b , & 0 & 8 6 ' $ 6 & / 5 s 9 ' ' b , & d p o u j o v f e d p o u j o v f e 4 % " 4 $ - 4 % " 4 $ - u g u g u s u s u 4 6 % " 5 u ) % % " 5 u ) * ( ) u 7 % % " 5 u g 4 $ - u - 0 8 u i d m p d l t u d m p d l d z d m f u 4 6 4 5 " u ) % 4 5 " u 4 1 u 7 % " $ , u 4 6 4 5 0 u # 6 ' u i d m p d l 4 s 4 1 4 ) % 4 5 " docid025743 rev 1 81/99 stm32f031xx electrical characteristics 85 table 61. spi characteristics (1) symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z electrical characteristics stm32f031xx 82/99 docid025743 rev 1 figure 25. spi timing diagram - slave mode and cpha = 0 figure 26. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . a i c 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . . 3 3 i n p u t t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # + ( t w 3 # + , t v 3 / t h 3 / t r 3 # + t f 3 # + t d i s 3 / t s u 3 ) t h 3 ) a i 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # , ( t w 3 # , , t v 3 / t h 3 / t r 3 # , t f 3 # , t d i s 3 / t s u 3 ) t h 3 ) . 3 3 i n p u t docid025743 rev 1 83/99 stm32f031xx electrical characteristics 85 figure 27. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / table 62. i 2 s characteristics (1) symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.597 1.601 mhz slave mode 0 6.5 t r(ck) i 2 s clock rise time capacitive load c l = 15 pf - 10 ns t f(ck) i 2 s clock fall time - 12 t w(ckh) i2s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 - t w(ckl) i2s clock low time 312 - t v(ws) ws valid time master mode 2 - t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 7 - t h(ws) ws hold time slave mode 0 - ducy(sck) i2s slave input clock duty cycle slave mode 25 75 % electrical characteristics stm32f031xx 84/99 docid025743 rev 1 figure 28. i2s slave timing diagram (philips protocol) 1. measurement points are done at cmos levels: 0.3 v ddiox and 0.7 v ddiox . 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. t su(sd_mr) data input setup time master receiver 6 - ns t su(sd_sr) data input setup time slave receiver 2 - t h(sd_mr) (2) data input hold time master receiver 4 - t h(sd_sr) (2) slave receiver 0.5 - t v(sd_st) (2) data output valid time slave transmitter (after enable edge) slave transmitter (after enable edge) master transmitter (after enable edge) master transmitter (after enable edge) -20 t h(sd_st) data output hold time 13 - t v(sd_mt) (2) data output valid time - 4 t h(sd_mt) data output hold time 0 - 1. data based on design simulation and/or characterization results, not tested in production. 2. depends on f pclk . for example, if f pclk = 8 mhz, then t pclk = 1/f plclk = 125 ns. table 62. i 2 s characteristics (1) (continued) symbol parameter conditions min max unit # + ) n p u t # 0 / , # 0 / , t c # + 7 3 i n p u t 3 $ t r a n s m i t 3 $ r e c e i v e t w # + ( t w # + , t s u 7 3 t v 3 $ ? 3 4 t h 3 $ ? 3 4 t h 7 3 t s u 3 $ ? 3 2 t h 3 $ ? 3 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b , 3 " r e c e i v e , 3 " t r a n s m i t docid025743 rev 1 85/99 stm32f031xx electrical characteristics 85 figure 29. i2s master timing diagram (philips protocol) 1. data based on characterization results, not tested in production. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t package characteristics stm32f031xx 86/99 docid025743 rev 1 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. docid025743 rev 1 87/99 stm32f031xx package characteristics 97 figure 30. lqfp48 - 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. d d1 d3 a1 l1 l k c b ccc c a1 a2 a c seating plane 0.25 mm age plane e3 e1 e 12 13 24 25 48 1 36 37 pin 1 identification 5me table 63. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0 3.5 7 0 3.5 7 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f031xx 88/99 docid025743 rev 1 figure 31. lqfp48 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 docid025743 rev 1 89/99 stm32f031xx package characteristics 97 figure 32. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table 11: pin definitions . seating plane ddd c c a3 a1 a d e 9 16 17 24 32 pin # 1 id r = 0.30 8 e l l d2 1 b e2 a0b8_me bottom view table 64. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data dim. millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 0.00 0.02 0.05 0 0.0008 0.0020 a3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 d 4.90 5.00 5.10 0.1929 0.1969 0.2008 d2 3.50 0.1378 e 4.90 5.00 5.10 0.1929 0.1969 0.2008 e2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e 0.500 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f031xx 90/99 docid025743 rev 1 figure 33. ufqfpn32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. docid025743 rev 1 91/99 stm32f031xx package characteristics 97 figure 34. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. dimensions are in millimeters. 3. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. x 4 e b 3 e a t i n g 0 l a n e ! ! # o x ? 0 i n c o r n e r , , 2 o 4 y p $ e t a i l : $ $ % % 0 i n ) $ 3 e a t i n g 0 l a n e " ! $ e t a i l : ! " ? - % ? 6 table 65. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 -0.05 0 0.05 -0.002 0 0.002 d 3.9 4 4.1 0.1535 0.1575 0.1614 d1 2.9 3 3.1 0.1142 0.1181 0.122 e 3.9 4 4.1 0.1535 0.1575 0.1614 e1 2.9 3 3.1 0.1142 0.1181 0.122 l 0.3 0.4 0.5 0.0118 0.0157 0.0197 l1 0.25 0.35 0.45 0.0098 0.0138 0.0177 t 0.152 0.006 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 e 0.5 0.0197 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f031xx 92/99 docid025743 rev 1 figure 35. ufqfpn28 recommended footprint 1. dimensions are in millimeters 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. ! " ? - % ? & 0 docid025743 rev 1 93/99 stm32f031xx package characteristics 97 figure 36. tssop20 - 20-pin thin shrink small outline 1. drawing is not to scale. 9 ! ? - % # 0 c , % % $ ! ! k e b ! , a a a table 66. tssop20 ? 20-pin thin shrink small outline package mechanical data symbol millimeters inches (1) min typ max min typ a 1.2 0.0472 a1 0.05 0.15 0.002 0.0059 a2 0.8 1 1.05 0.0315 0.0394 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 d (2) 6.4 6.5 6.6 0.252 0.2559 0.2598 e 6.2 6.4 6.6 0.2441 0.252 0.2598 e1 (3) 4.3 4.4 4.5 0.1693 0.1732 0.1772 e 0.65 0.0256 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 8.0 0.0 8.0 aaa 0.1 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. dimension ?e1? does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25mm per side. package characteristics stm32f031xx 94/99 docid025743 rev 1 figure 37. tssop20 recommended footprint 1. dimensions are in millimeters. docid025743 rev 1 95/99 stm32f031xx package characteristics 97 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 18: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum ambient temperature in c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the microcontroller at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. table 67. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lqfp48 - 7 7 mm 55 c/w thermal resistance junction-ambient ufqfpn32 - 5 5 mm 38 thermal resistance junction-ambient ufqfpn28 - 4 4 mm 118 thermal resistance junction-ambient tssop20 110 package characteristics stm32f031xx 96/99 docid025743 rev 1 example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 80 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 67 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 80 c + (55c/w 447 mw) = 80 c + 24.585 c = 104.585 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see table 18: general operating conditions on page 41 . in this case, parts must be ordered at least with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the tamax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (55c/w 447 mw) = 105-24.585 = 80.415 c suffix 7: t amax = t jmax - (55c/w 447 mw) = 125-24.585 = 100.415 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 67 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 100 c + (55 c/w 134 mw) = 100 c + 7.37 c = 107.37 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. docid025743 rev 1 97/99 stm32f031xx part numbering 97 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. table 68. ordering information scheme example : stm32 f 031 g 6 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 031 = stm32f031xx pin count f = 20 pins g = 28 pins k = 32 pins c = 48 pins code size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory package p = tssop u = ufqfpn t = lqfp temperature range 6 = ?40 c to +85 c 7 = ?40 c to +105 c options xxx = programmed parts tr = tape and reel revision history stm32f031xx 98/99 docid025743 rev 1 9 revision history table 69. document revision history date revision changes 13-jan-2014 1 initial release. docid025743 rev 1 99/99 stm32f031xx 99 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? 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