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? 2 0 0 3 s ilico n sto r a g e t e ch n o lo g y , in c. s 712 50-0 0 -00 0 10/03 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. ad van ce in f o rmat io n features: ? s in g l e v o l t ag e rea d an d w r it e o p er at io n s ? 2 .7 - 3 .6v f o r ss t 25v f 080 s er ial i n t e rf ace ar c h it ect u r e ? s p i co mpa t ib le : mo de 0 an d mo de 3 3 3 m h z m a x cloc k fr e q ue n c y s uperi o r rel i abilit y ? e n dur an ce : 10 0,00 0 cy c l es ( t y p i c a l ) ? g r e ater th an 100 y ear s data rete nti o n l o w p o we r c o ns ump t ion: ? a c t i v e read cur r ent : 7 m a ( t y p i c a l ) ? s ta ndb y cur r ent : 8 a ( t y p i c a l ) f le x i b l e er ase cap ab i l i t y ? u ni f o r m 4 k b y te s e ct or s ? u ni f o r m 32 kb y t e o v er l a y b l o c ks f ast e r as e an d b y t e - p r o g r am: ? c hi p- er a s e t i me : 70 ms ( t y p ic al ) ? s e c to r - o r bl oc k - e r as e t i me: 18 m s ( t y pi c a l ) ? b yt e - pr og r a m t i me : 14 s ( t yp ic al ) a uto ad dr e s s inc r e m e n t (aai ) pr ogr a mmi n g ? d ec r eas e to tal c hip pr ogr amm i ng ti me o v er by te- p r o g r am op er ati ons e nd- of-w r i te de t e c t ion ? s o ftw ar e s t at us h ol d p i n (hold# ) ? s u s p end s a se r i a l s equ enc e t o th e me mor y wit hout des el ec tin g th e de v i c e w r i t e p r ote c t ion (w p# ) ? e n a b l es /di s a b l e s the lo c k - d o w n func ti on of th e st atus r egi s t er s o f t w ar e w r it e pr o t ect io n ? w r i te p r otec ti on t h r oug h b l oc k - pr ote c t i on bi ts in st atus r egi s t er t e m pe r a t u r e ra ng e ? c om mer c ial : 0 c to +7 0c ? i nd ust r ial : - 4 0 c to +8 5c p ac ka g e s a v a i l a b l e ? 8 - l e ad s o ic 20 0 m i l bod y widt h pr o d uct descr i ption s s t ? s s e r i a l fl as h f a mi l y f e at ur e s a f o u r - w i r e, s p i - c om - p a ti b l e in te r f ace t h a t al lo w s f o r a lo w pi n- cou n t pac kag e o ccup y ing less bo ar d sp ace a nd u l ti mat e ly lo w e r i ng t o t a l syst em co st s . sst25 vf080 spi se r i al f l ash memo r i es ar e m anu f a c t u r ed wi t h s s t ? s pr o p r i e t a r y , h i gh pe r f o r - m ance cm o s supe r f lash tech nol og y . t he sp lit - gat e ce ll d e sign a nd t h ic k- o x ide t unn elin g inje cto r at ta in be tt er r e li- a b ilit y a nd man u f a ct ur ab ilit y com pare d w i t h a l te r n at e ap p r oa c h es. t h e sst 25 vf 080 de vice s sign ifi c ant ly im pr o v e p e r f or - m ance , w h il e lo w e r i n g p o w er con s ump t io n. t h e t o t a l en e r g y c o ns u m ed i s a fu nc t i on o f th e ap p l i e d v o l t ag e , cu r r e n t , an d t i me o f ap pli c ati on. since f o r an y giv e n v o l t - a ge r a nge , th e su per f l a s h t e chn o lo g y use s less cur r e n t t o p r og r a m an d h a s a sh or ter er ase ti me , t h e to ta l e ner g y co nsum ed du r i n g an y er ase o r pr o g r a m ope r a ti on is l e ss t han a l t e r nat iv e f l ash m e mo r y te chno log i es . t h e s s t 2 5 v f 0 8 0 de vices ope r a te w i th a sing le 2 . 7- 3. 6v p o w er su ppl y . t h e sst 2 5 vf 080 d e v i ces ar e off e r ed in an 8- l ead so i c p a c k age wit h 2 00 mi l bod y wid t h . se e f i gur e 1 f o r p i n a ssign men t s . 8 mbit spi serial flash ss t25vf080 s s t 25 v f 0808 mb s e r i a l p e ri pher al inte rface (s p i ) fl ash memo ry http://
2 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 1250 b1.0 i/o buffers and data latches superflash memor y x - decoder control logic address buff ers and latches ce# y - decoder sck si so wp# hold# serial interface f unctional b lock d iagram
advance information 8 mbit spi serial flash SST25VF080 3 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 pin descript i o n f i gure 1 : p in a ssig n me n t s fo r 8- lea d s o ic t able 1 : p in d e s cri p t io n sym bol pin nam e func tion s sc k s er ia l c l o c k t o pro v id e the t i mi ng of the ser i al int e rf a c e . c o m m a nds , a ddre s s e s , or i npu t dat a are lat c he d on the r i si ng e d g e of th e c l oc k in put , w h il e ou tpu t da ta i s s h i fted ou t on the f a lli ng edg e o f th e c l oc k in pu t. si ser i a l dat a inpu t t o tr ans f e r comm an ds , addre s s e s , or dat a s e r i a lly in to the de vic e . inp u ts are la tch ed on t he r i si ng edg e o f th e s e r i a l c l oc k. so ser i a l dat a ou t p u t t o tr ans f e r da ta s e r i a l l y o u t o f th e de v i c e . d ata is sh ift ed o ut o n t he f al lin g e dge of the se r i al cl oc k . c e # c h i p enab l e the de vi ce is en ab le d b y a h i gh to lo w tr ans iti on on c e #. c e # m u s t re ma in lo w f o r the dur a t ion of an y c o m m a n d se que nc e . wp# wr i te prote c t t he wr i t e pro t ec t (wp # ) pi n i s u s e d to en ab le /di s ab l e bpl bi t in the st atu s re gis t er . h o ld # h o l d t o tem por a r ily s t op se r i al co mm uni ca tion wi t h spi f l as h m em or y wi th out res ett ing the de vi ce . v dd p o w e r sup p l y t o pro v id e p o w er s u p p ly v o lta ge: 2 . 7-3. 6v f o r sst 25vf 080 v ss gro und t1. 0 125 0 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd hold# sck si t op vie w 1250 08-soic p1.0
4 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 pr o d uct i d ent i fica ti on memory organization t h e sst 25 vf 080 s u p e r f l a s h m e m o r y a r r a y i s o r g a n i z e d i n 4 k b yt e sec t o r s w i t h 32 kby t e o v er l a y b l oc ks . device o peration t h e s s t 2 5 v f 0 8 0 i s a c c e ss ed t h r o ug h t h e spi ( s e r ia l p e r i ph e r al in t e r f ac e) b u s co mp at i b le p r ot o c o l . t h e s p i b u s co ns i s t of f o ur c o n t r o l l i n e s ; ch ip e nab l e ( c e # ) is u s e d t o se le c t the de v i c e , a nd d a ta is ac c e s s ed t h r o u gh t he s e r i al dat a in pu t ( s i ) , se r i a l da ta o u tp ut ( s o ) , an d s e r i al cl oc k (s ck). t h e s s t 2 5 v f 0 8 0 su pp or ts b o th m ode 0 ( 0 ,0 ) an d mod e 3 ( 1 ,1 ) of sp i b u s op er a t io ns. t h e d i f f e r enc e be tw e e n th e tw o m ode s , as sh o w n in f i gu r e 2 , i s th e s t a t e of th e s c k si gn al whe n th e b u s ma s t er i s i n s t an d- b y m o d e an d n o da ta is bei ng t r ans f e r r e d . t h e sc k s i g nal i s l o w f o r m o d e 0 an d s c k s i gn al i s hi gh f o r mod e 3. f o r bo th mo de s , th e se r i a l dat a i n ( s i) i s s a m p le d at the r i s i ng e dge of th e s c k cl ock s i g nal and the s e r i al data o u tpu t ( s o ) is dr i v e n aft e r the f a l l i n g ed ge of the s c k cl oc k s i gna l. f i gure 2 : s p i p ro t o c o l t able 2 : p r o duct i de nt if ica t i o n ad dre s s da ta m a n u f a c t ure r ? s id 0 000 0h bfh de vi ce id sst2 5 vf0 8 0 0 000 1h 80 h t2 .0 125 0 1250 f02.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high imped ance msb msb
advance information 8 mbit spi serial flash SST25VF080 5 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 hold o p era t ion ho ld# p i n i s us ed to pa us e a se r i a l se qu enc e un de r w a y wi th t he s p i fl as h m e m o r y wi th out r e s e tt in g th e c l o c k i n g se qu enc e . t o ac ti v a te th e ho ld# m o d e , c e # mus t be i n ac ti v e lo w s t a t e . t h e ho ld# m o d e be gi ns w hen the s c k ac ti v e l o w st ate c o i n c i d e s w i th th e f a ll i ng ed ge of th e ho ld# s i gn al . t h e ho ld m o d e en ds whe n th e ho ld # si gn al ? s r i si ng ed ge co in ci de s wit h th e s c k ac ti v e low s t ate. i f th e f a l lin g e d g e of th e h o l d # si gn al do es no t c o i n ci de wi th the s c k ac ti v e lo w s t at e , t hen t he de v i c e en ter s h o l d mo de wh en t h e s c k ne x t r eac h e s t h e a c t i v e l o w s t at e . si mi l a r l y , i f th e r i si ng ed ge o f th e ho ld # s i g nal do es no t co in c i d e wi th th e s c k a c t i v e lo w s t ate, th en the d e vi c e e x i t s in hol d m o d e wh en t he s c k ne x t r e a c h e s th e ac ti v e lo w s t at e . s e e f i g u r e 3 f o r h o l d co nd iti o n w a v e f o r m . o n ce th e de v i ce en t e r s ho l d m o d e , s o wi ll be in hi gh - im pe dan ce s t at e w h i l e si an d s c k c a n be v il or v ih . if ce # is dr i v en a c t i v e h i g h d u r i ng a hol d c o ndi ti on , it r e s e ts the i n t e r n a l lo gi c of t he de v i ce . a s l o n g as ho l d # s i g nal is lo w , th e me mo r y r e ma in s i n t he h o l d c o n d i t io n. t o r e s u m e c o m m u ni ca ti on w i th th e d e vic e , h o ld # m u s t be dr iv en ac ti v e hi gh , a nd ce # m u st be dr i v en ac ti v e l o w . se e f i gu r e 17 f o r ho ld ti mi ng. f i gure 3 : h ol d c ondi t ion w av e f o r m w r it e prot ec tion s s t 2 5 v f 0 8 0 pr o v i des s oftw a r e w r ite pr ote c tio n. t h e w r i t e pr o t ect pi n ( w p# ) en ab le s o r di sab l e s t h e lo c k - d o w n functio n o f t he st atu s r egi s t er . t he bl oc k - p r o t ec ti on bi ts ( b p 1 , b p 0 , an d bp l) in the s t a t us r egi s t er pr o v id e w r it e pr ot ec ti on to the m e m o r y a r r a y and th e st atu s r egi s t er . se e t a b l e 5 f o r bl oc k - pr o t ec ti on de sc r i p t i o n . w r i t e pr ote c t pi n (w p# ) t h e wr i t e pr ot ec t ( w p# ) p i n en ab le s the lo c k - d o w n f unc - ti on o f th e b p l bi t ( b i t 7) i n th e s t a t us r egi s t er . w h e n w p # i s dr i v e n lo w , t h e e x ec ut io n o f t h e wr i t e - s t a t us - r eg is te r ( w r s r) i n s t r u ct io n i s det er mi ne d b y the v a l ue o f th e b p l bi t ( s e e t a b l e 3) . w h e n w p # is hi gh , the lo c k - d o w n f unc - ti on of t h e bp l bi t i s di sa b l ed . activ e hold activ e hold activ e 1250 f03.0 sck hold# table 3 : c ond i t i o n s to exe c u t e w ri te -s ta t u s - r eg ist e r (w rs r) i ns truct io n wp# b pl ex ecu te wrsr i n struc t ion l1 n o t a l l o w e d l0 a l l o w e d hx a l l o w e d t 3 .0 1 250
6 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 s t at us register t h e sof t w a r e s t a t us r e gi st er p r o v i d e s s t a t us on w h e t he r t h e fl as h m e m o r y ar r a y is a v ai la b l e f o r an y rea d o r w r ite o per - ati o n , w het her the de v i ce i s wr ite e nab l ed, an d the s t at e o f t h e m e m o r y wr it e pr o t ec ti on . d u r i ng an i n t e r n a l e r as e o r pr o g r a m ope r ati on , the s t a t us r egi s t er ma y b e r ea d onl y t o de ter m in e t he c o mp le ti on of an op er a t io n in p r o g r e s s . t a b l e 4 de sc r i be s t h e f u nc ti on o f e a c h b i t i n t h e s o f t w ar e st atu s r egi s t er . busy t h e bu sy b i t de ter m in es whe t he r th er e i s an in ter n al er a s e or p r ogr am op er a t io n in pr o g r e s s . a ? 1 ? f o r th e bu sy bi t i n d i - ca te s the d e vi c e is b u sy wi th an op er a t io n in p r og r e ss. a ? 0 ? in di ca tes t he de v i c e is r e a d y f o r t he ne x t v a l i d op er a t io n. wr it e e n able la t c h ( w e l ) t h e wr i t e - e n ab le - l atc h bi t i ndi c a te s the s t atu s of the in ter - na l m e m o r y w r i t e e n a b l e l a tc h . if th e w r it e- en ab l e - l a t c h bi t is s e t to ? 1 ? , i t i ndi c a te s th e de v i c e is wr i t e e n a b l e d . if th e bi t is s e t t o ? 0 ? ( r e s et) , i t i ndi c a te s th e d e v i c e is no t w r it e en ab le d an d do es not a c ce pt a n y m e m o r y w r ite ( p r ogr am / er a s e) c o m m an ds. t h e w r it e- en ab l e - l a t c h b i t is au tom a t i - ca ll y r e s e t un der t he f o ll o w i n g c ond it io ns : po w e r - u p wr i t e- d i sa b l e ( w r d i ) in st r u ct ion c o mp let i on by te- p ro g r am in st r u c t ion c o mp let i on a u to ad dr es s i n c r e m en t ( a a i ) pr ogr amm i ng r eac hed it s h i gh es t me mor y a ddres s s e c t or -er a se in st r u ct i o n co m p l e t i o n bl oc k - e r as e i n s t r u c t i on c o m p le tio n c h i p - e ra se ins t r u ct i on co mpl e t i on t able 4 : s oft w are s tat u s r eg ist e r bit n ame f uncti on defau lt at po w e r - u p r e a d / w r i t e 0 b u s y 1 = int e r nal wr ite operation is in pr og ress 0 = n o inter nal wr ite operation is in prog r e ss 0r 1 w e l 1 = d e vice is memor y w r ite enab led 0 = d e vice is not m e m or y wr it e enab led 0r 2 b p 0 indicate curr ent le v e l of b l oc k w r ite protection ( s ee t a b l e 5) 1 r / w 3 b p 1 indicate curr ent le v e l of b l oc k w r ite protection ( s ee t a b l e 5) 1 r / w 4 : 5 r e s res e r v ed f o r fut u re us e 0 n / a 6 a a i a u to ad dress increment p r og ramm ing s t atus 1 = aa i pr og r a mming mode 0 = byt e -pr o g r am mode 0r 7 b p l 1 = bp 1, b p 0 are read-only bit s 0 = bp 1, b p 0 are read/w r itab le 0r / w t4 .0 125 0
advance information 8 mbit spi serial flash SST25VF080 7 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 bloc k p r ot e c tion ( b p 1 , bp 0 ) t h e b l ock - pr o t e c ti on ( b p 1 , b p 0 ) bi ts de fi ne t h e s i z e o f t h e m e mo r y ar e a , a s d e f i n ed in t a b l e 5, t o be so ft w a r e p r o- t e ct ed a gai nst a n y mem o r y wr it e ( p r o g r a m o r er as e) op er at io ns. t h e wr it e- s t at us - r e g i s t er ( w r s r) i n s t r u c t i o n is use d to pr o g r am t h e bp1 a nd bp0 bi ts as lon g a s wp # i s hi g h o r t h e b l o c k - p r ot ec t - lo c k ( b p l ) bi t is 0. ch ip - e r a s e ca n on ly be e x ecu t e d if bl oc k- pr o t e c ti on bi ts ar e bot h 0. af t e r po w e r-up , bp1 a nd bp0 a r e set to 1 . bloc k p r ot e c tion loc k - down ( b p l ) wp # p i n d r iv en lo w ( v il ) , en ab le s t h e blo c k - pr ot ect i o n - l o c k - d o w n ( bpl) bit . whe n bpl is se t to 1, i t p r e v en ts an y f u r t her alt e r a tio n o f th e bp l, bp1 , a n d bp0 bit s . wh en th e w p # p i n is dr i v en h i gh ( v ih ) , t h e bp l bit ha s n o ef f e ct an d i t s v a lu e i s ?do n ?t c a re ?. a f t e r p o we r-u p , t h e bp l b i t is r e s e t to 0 . au t o ad d r es s in cr emen t ( aai) t h e a u to a ddr e s s inc r em en t p r ogr am mi ng - s ta tus bi t pr o- vi de s s t at us o n whe t he r th e de v i c e is in a a i pr o g r a mm in g mo de or by te - p r ogr am m o d e . t h e de f a ul t a t po wer u p is by te - p r ogr am m ode . t able 5 : s oft w are s tat u s r eg ist e r b lo c k p ro t e c t i o n 1 1. def ault at po wer-up f o r b p 1 and b p 0 is ?11?. pr o t ecti on le ve l status r e gi ster bit pr ote c ted m e mory area bp1 b p0 8 mbit 00 0 n o n e 1 (1/4 me mo r y arr a y) 0 1 0 c 000 0h-0fffff h 2 (1/2 me mo r y arr a y) 1 0 0 800 00h-0 ffff fh 3 (fu ll me mo r y arr a y) 1 1 0 000 00h-0 ffff fh t 5 .0 12 50
8 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 ins t ructions ins t r u c t io ns ar e u s ed t o re ad, wr i t e ( e r a s e a n d pr ogr am ) , an d c onf ig ur e th e s s t 2 5 v f 0 8 0 . t he i n s t r u c t io n b u s cy c l es ar e 8 bi ts ea c h f o r c o m m a nds ( o p c ode ) , da ta, an d ad dr es s e s . pr i o r to e x ec uti n g a n y by te - p r ogr am , a u t o a d d r e ss i n cr em en t (a ai ) pro g r a m m i n g , s e ct o r-e r a se , bl oc k - e r as e , or c h i p - e r a s e i n s t r u c t io ns, t he w r it e- en ab l e ( w r e n) in str u c t io n m u st be e x e c u t ed fi r s t . t h e c o m p l e t e li s t of th e in st r u c t i ons is pr o v id ed i n t a b l e 6. a l l i n s t r u c t io ns a r e syn ch r o ni z e d of f a hi gh t o lo w t r an si ti on o f c e #. i n pu t s wi ll be ac c ept ed on the r i si ng ed ge of s c k s t ar tin g w i th th e mo st si gn ifi c an t bi t. ce # mus t b e dr i v en l o w be f o r e a n in st r u c t i on i s ent er ed a n d m u st b e d r iv en h i g h a fter th e l a s t b i t of t h e in st r u ct io n ha s be e n sh if t e d i n ( e xc ep t f o r re a d , rea d - i d an d r ead - s ta tu s- re gi st er i n s t r u ct io ns ) . a n y l o w to hi gh tr an si ti on on ce #, bef o r e r e c e i v in g t he la st bi t o f a n i n s t r u ct io n b u s cyc le , w i ll te r m in at e th e in st r u c t i o n in pr ogr es s and r e tu r n th e d e v i ce to the st and b y m o d e . ins t r u c t io n c o mm an ds ( o p c ode ) , add r e s s e s , a nd d a ta a r e al l in put fr om th e m os t s i gni fi c a nt bi t ( m s b ) fi r s t. t able 6 : d ev i c e o p e rat io n i ns t ruct io ns 1 1. a ms = mo st signif i c ant addre ss a ms = a 19 f o r s s t 25vf 080 addres s bi t s abo v e t he m o st signif i c ant bit of each densit y c an be v il or v ih cy c l e t y pe / o p er ati o n 2, 3 2. o pe r at i on : s in = se r i a l in , s out = se r i a l ou t 3. x = dum m y i nput cycles (v il or v ih ); - = non-a ppl ic ab le cycles (cy cles are not necess a r y) bu s cy c l e 4 4. o n e b u s cyc l e is ei gh t cloc k per iods . 12 3 4 5 6 s in s out s in s out s in s out s in s out s in s out s in s out r e ad 03 h h i- z a 23 -a 16 hi -z a 15 -a 8 hi -z a 7 -a 0 hi -z x d out sec t or-e ra s e 5, 6 5. sect or address e s: use a ms -a 12 , remaining address e s can be v il or v ih 6. pr ior t o an y byt e -pr o g r am, a a i - p r og ram, sect or-e r a s e , bloc k - erase , or ch i p - e rase oper at ion, t he w r i t e-e nab le (w re n) inst r u ct i on m u s t be e x ecut ed. 20 h h i- z a 23 -a 16 hi -z a 15 -a 8 hi -z a 7 -a 0 hi -z - - blo c k - er a s e 5, 7 7. bloc k address e s f o r : us e a ms -a 15 , rem a ini n g addres ses can be v il or v ih 52 h h i- z a 23 -a 16 hi -z a 15 -a 8 hi -z a 7 -a 0 hi -z - - ch i p -er a se 6 60 h h i- z - - - - - - - - b y te - p r ogr am 6 02 h h i- z a 23 -a 16 hi -z a 15 -a 8 hi -z a 7 -a 0 hi -z d in hi -z a u to ad dres s inc r em en t (aai) si ng le-by t e prog r a m 6, 8 8. t o cont in ue prog ramm ing t o t he n e xt sequen t i al addr ess locat i on, ent er t he 8-bit com m an d, af h, f o llo w ed b y t he dat a t o be pr og ramm ed. afh h i - z a 23 -a 16 hi -z a 15 -a 8 hi -z a 7 -a 0 hi -z d in hi -z rea d -sta tus - regi ste r (rdsr) 05 h h i- z x d out -n o t e 9 9. t he read-s t at us-r egi s t er is cont i nuous wit h ongoing c l o c k c ycles unt i l t e r m i n a t ed b y a lo w t o high t r ansit i on on ce#. -n o t e 9 -n o t e 9 ena b le-w r i te-s tatu s-regi s t er (ewsr) 10 10. t he enab le-w r i t e - s t a t u s- regist e r (e w s r) ins t r u c t ion and t he w r it e-s t at us-re g i s t e r (w rsr) inst r u ct i o n must w o r k in conjunc t i o n of each ot her . t he w r s r in s t r u c t ion must be e x ecut ed i m mediat ely ( v er y ne x t b u s c ycle) af t e r t he ew s r ins t r u c t ion t o mak e bot h i n s t r u c t ions ef f e c t iv e. 50 h h i- z - - - - - - - - wr i t e-sta t us -r egi st er (wrsr) 10 01 h h i- z d a t a h i- z - - - . - - - wr i t e -en a b l e (wren) 0 6 h h i -z - - - - - - - - wr i t e - di sa b l e (wrdi) 0 4 h hi -z - - - - - - - - r e a d -id 9 0h or abh hi -z 0 0 h h i - z 0 0 h hi -z id addr 11 11. manuf act u rer? s i d is read w i t h a 0 =0, and de v i ce i d i s rea d wit h a 0 =1. a l l ot h e r addr ess bit s are 00h. t he m a n u f a ct urer and d e vice i d out put s t r eam i s c ont in uou s unt il t er m inat ed b y a lo w t o high t r ans i t ion on ce # hi -z x d out 12 12. de vice i d = 80h f o r s s t 25vf 080 t6.0 1250
advance information 8 mbit spi serial flash SST25VF080 9 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 rea d t h e re ad in s t r u c t i o n s upp or t s up to 2 0 m h z , i t out pu ts th e da ta st ar ti ng fr o m t he s pec i f i ed ad dr es s l oc ati on . t h e dat a ou tpu t s t r eam is c o n t inuo us th r o ug h al l add r e s s e s unt il ter - mi na ted b y a low to hi gh tr an si ti on on ce# . t h e i nte r nal ad dr es s po in ter wi ll a u to mat i c a l l y i n c r em en t un ti l th e h i g h - es t m e m o r y ad dr es s i s r e ac he d. o n ce the hi gh es t m e m o r y ad dr es s i s r e a c h e d , t he ad dr es s poi nt er w i l l au tom a ti c a l l y in cr e m e n t to th e be gi nn in g ( w r a p - ar ou nd) o f th e ad dr es s sp ac e , i . e . f o r 8 m bi t de ns it y , on ce the d a ta f r o m ad dr es s l o c a tio n 0 fffffh h a d b e e n re a d , t h e n e xt o u tp u t wil l b e fr om ad dr es s l o c a ti on 00 00 00h . t h e rea d in str u c t i on is i n i t i a te d b y e x e c u t i ng an 8- bi t co m- ma nd, 03 h, f o l l o w e d b y ad dr es s bi ts [a 23 -a 0 ]. c e # mus t re m a i n a c t i v e l o w f o r t h e du r a t i o n o f t h e r e a d cycl e . s e e f i gu r e 4 f o r th e r e ad se qu en ce . f i gure 4: r ead s equence 1250 f04.0 ce# so si sck add . 01 2 3 4 5 6 7 8 add . add . 03 high imped ance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out
10 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 by te -pr ogr a m t h e by te - p r ogr am in st r u c t i on p r og r a ms th e bi ts i n th e se le c t ed b y te t o the des i r ed d a ta . t h e s e l e c t e d b y t e mus t be i n the e r as ed s t at e ( f f h ) wh en in it ia tin g a pr o g r a m op er at io n. a b y te- p r o g r am instr u ction applied to a pr o- tected m e mor y area will be ignored. pr i or to an y w r i t e op er at io n, the w r i t e- e nab l e ( w re n) in st r u c t i o n mus t b e e x ec ute d . ce # m u st r e m a i n ac ti v e l o w f o r the dur a t i on o f the by te - p r ogr am in st r u c t i on. t h e b y t e - pr o g r a m i n s t r u ct io n i s in it iat e d b y e x ec uti n g an 8- bi t co m- ma nd, 0 2 h, f o ll o w e d b y ad dr es s bi ts [a 23 -a 0 ]. f o l l owin g th e a d d r e s s , t h e d a t a is i n p u t in or de r f r om ms b ( b it 7) to ls b ( b i t 0) . ce # mus t b e dr i v en h i g h be f o r e th e i n s t r u c t i o n is e x ec ut ed. t h e u s er m a y po ll t he b u s y bi t in th e so ftw a r e st atu s r e gi s t er o r w a i t t bp f o r th e c o m p l e t i on of th e i n te r nal se lf - t im ed b y te- p r o g r a m op er a t io n. s ee f i gur e 5 f o r th e by te - p r ogr am s e q uen c e . fi gure 5 : b yt e -p r ogra m s e q ue nce 1250 f05.0 ce# so si sck add . 01 2 3 4 5 6 7 8 add . add . d in 02 high imped ance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb
advance information 8 mbit spi serial flash SST25VF080 11 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 au t o ad d r es s in cr emen t ( aai) p r o g r a m t h e aa i pr og r a m i n st r u ct io n al lo w s m u lt ip le b y t e s o f da t a to be pr o g r a m me d wit hou t r e - i s s u i n g t h e ne x t s e que nti a l ad dr es s l o c a t i o n . t h i s f e atu r e de cr ea s e s t o ta l p r o g r a m- mi ng ti me whe n th e e n ti r e m e m o r y a r r a y i s to be pr o- g r a m m ed. a n aa i pr ogr am i n s t r u ct io n poi nt ing t o a pr ot ec ted mem or y ar e a wi ll be i gn or ed . t he s el ec t e d ad dr es s r a n g e mus t b e in th e e r as ed s t a t e ( f f h ) whe n in i- ti ati n g an aa i pr ogr am in s t r u c t i o n . pr i o r t o any w r ite op er a t io n, t he wr i t e - e n a b l e ( w re n) in st r u c t i o n m u s t be e x e c u t ed . t h e a a i pr o g r a m i n s t r u ct io n is i n i t ia ted b y e x e c uti n g an 8 - bi t c o mm an d, a f h, f o l l o w e d b y ad dr es s bi ts [ a 23 -a 0 ] . f o l l o wi ng th e ad dr es s e s, the dat a i s in pu t s e q u e n t ia lly f r o m m s b (b it 7) t o l s b (bit 0 ) . c e # m u s t be d r iv e n hi gh bef or e the aa i pr o g r a m i n s t r u c t i o n is e x ec ut ed. t h e us er m u st po ll th e bus y bi t i n t h e so ftw a r e st atu s r e gi st er or w a i t t bp f o r the c o mp le ti on o f ea c h in ter - n a l s e l f - t i m e d by t e -p rog r a m cycl e . on ce t h e de v i ce c o m - pl ete s p r og r a mm in g b y t e , th e ne x t s equ en tia l a ddr e s s ma y be pr o g r a m, en ter the 8 - b i t c o m ma nd, a f h, f o ll o w ed b y th e da ta t o be pr o g r a m m e d . wh en the la st de si r ed b y te ha d be en p r ogr amm e d , e x ec u t e t he w r i t e- di s a b l e ( w r d i) in st r u c t i on, 0 4 h, t o ter m in ate a a i. af ter e x ec ut io n of th e wr di co mm and , t he us er mu st po ll th e sta t us r e gi st er t o en su r e th e de v i ce c o mp le tes p r o g r a mm in g. s e e f i g u r e 6 f o r a a i pr ogr am mi ng s equ enc e . t h e r e is no wr ap mo de d u r i ng a a i pr o g r a mmi ng ; on c e th e hi gh es t u npr o t ec te d mem o r y add r e s s i s r eac he d, th e de v i c e wi ll e x i t a a i o per a t i on an d r e s e t the w r i t e- e nab l e - la tc h b i t ( w e l = 0 ) . f i gure 6 : a uto a ddress i ncrement (aai) p rogram s equence ce# si sck a[23:16] a[15:8] a[7:0] af data byte 1 af data byte 2 ce# si so sck wr ite disab le (wrdi) instr uction to ter minate aai oper ation read status register (rdsr) instr uction to v er ify end of aai oper ation 04 last data byte af 05 d out mode 3 mode 0 t bp t bp t bp 1250 f06.0 0 1 2 3 4 5 6 7 8 3 23 33 43 53 63 73 83 9 15 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 01234567 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 0123456789 1 0 1 1 1 2 1 3 1415
12 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 se ct o r - e r ase t h e se c t or - e r a s e in s t r u ct io n c l e a r s all bits in th e s e le ct ed 4 kb y t e s e c t o r t o f f h . a se ct or - e r a se in st r u c t i on a p p l i ed t o a pr ot ec ted m e m o r y ar ea wi ll be ig no r e d. p r io r to a n y w r it e op er at io n, t he w r i t e- e n a b l e ( w re n) i n s t r u ct ion mus t b e e x ec ut ed. ce # mus t r e ma in ac ti v e lo w f or t he du r ati on o f the any c o mm and s equ en ce . t h e se c t or - e r a s e i n s t r u ct io n i s i n i t i a t e d b y e x e c u t in g an 8 - bi t co mm an d , 20 h , f o llo w e d b y a ddr e s s bi ts [a 23 -a 0 ]. a d d r e s s b i ts [a ms -a 12 ] (a ms = m os t si gn ifi c ant add r e s s ) a r e us e d to de ter m ine th e se c t or add r e s s ( s a x ) , r e m a i n i n g ad dr es s b i t s can b e v il or v ih . c e # m u s t be dr i v en hi gh bef o r e th e i n s t r u ct io n i s e x e- c u te d. th e us e r ma y po ll the b u s y b i t in the s o ft w a r e s t a t us r egi s t er o r w ai t t se f o r th e c o mp le tio n of the i n te r n al s e l f - t i m e d se ct or- e r a se cyc le . s e e fi gu re 7 f o r t h e se ct o r - er a s e s e q uen c e . f i gure 7 : s ec t o r -e ras e s e q ue nce b l o c k- er as e t h e b l o c k- e r as e in st r u c t i on c l e a r s al l bi ts i n t h e s e l e c t ed 3 2 kb y t e b l oc k to f f h . a b l o c k - e r as e in st r u c t i on app li ed to a pr ot ec ted m e mo r y a r ea wi ll be i g n o r e d . p r ior t o an y wr ite oper ation, the wr ite- enab le ( w ren) instr u c t ion m u s t be e x ecuted. c e # m u st r e ma in ac ti v e lo w f o r the dur a t i on o f a n y co mm a n d se qu e n ce . th e b l o c k-er ase in st r u ct io n i s in it ia ted b y e x ec u t in g an 8- bi t c o mm an d, 52 h, f o ll o w e d b y ad dr es s bi ts [a 23 -a 0 ] . ad dr ess bi ts [a ms -a 15 ] ( a ms = mo st si gn if ic an t a ddr e s s ) a r e us ed to de ter m in e b l oc k ad dr es s (b a x ) , r e ma in in g a ddr e s s b i t s ca n be v il or v ih . c e # m u s t be dr iv en high bef or e t he instr u ction is e x ecuted. t he us er ma y poll the busy bit in the s o ft w a r e s t atu s r e g i s t e r or w a i t t be f or the c om pl eti on o f t he i nte r n al s el f - t i m e d bl oc k - er a s e c y c l e . se e f i gu r e 8 f o r the b l o c k- e r as e se qu enc e . f i gure 8 : b lo c k -e rase s eque nce ce# so si sck add. 0123 4 5 6 7 8 add . add . 20 high imped ance 15 16 23 24 31 mode 0 mode 3 1250 f07.0 msb msb ce# so si sck add . 01 2 3 4 5 6 7 8 add . add . 52 high imped ance 15 16 23 24 31 mode 0 mode 3 1250 f08.0 msb msb
advance information 8 mbit spi serial flash SST25VF080 13 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 ch ip - e r ase th e c h i p - e r a se i n st r u ct io n cl ea rs all bi t s in t h e de vice t o f f h . a chi p - e r a s e i n s t r u ct io n wi ll be ig no r e d i f any o f th e me mor y ar ea is p r o t ec te d. pr i o r t o an y wr ite oper ation, the wr ite- enab le ( w r e n ) ins t r u ction m u st be e x ecuted. ce # m u s t r e m a i n ac tiv e low f o r t h e du r a ti on of th e c h i p - e r a s e i n s t r u ct io n s e q u e n c e . th e c h ip -er a se i n s t r u ct io n i s in it ia t e d b y e x ec u t in g an 8 - b i t c o m m a nd, 6 0 h. ce# must be dr iv en high bef or e the ins t r u ction is e x ecuted. t he us er ma y poll the busy bit in the so ftw a r e s t a t us r e gi s t er or w a it t ce fo r the c o m p l e ti on of th e i n t e r n a l se lf - t im ed chi p - e r a s e c y c l e . se e f i gu r e 9 f o r th e c h ip - e r a se s e q uen c e . f i gure 9 : c hi p -e ras e s e q ue nce rea d -s t a t u s - r e gister (rds r ) the re ad - s ta tus - reg i s t e r (rds r) i n s t r u c t i on al l o ws rea d - in g of t he s t a t us r e gi s t er . t h e s t a t us r e g i s t er m a y be r e ad a t an y ti me e v e n du r i n g a w r i t e ( p r ogr am/ e r a se ) ope r a ti on . w h e n a wr i t e op er a t io n is i n pr og r e s s , t h e bu sy b i t m a y be ch ec k e d b e f o r e s e ndi ng an y ne w c o mm and s t o a s s u r e tha t the n e w c o m m a nds ar e pr op er l y r e c e i v e d b y the d e vi c e . ce # mus t be dr i v en lo w be f o r e t h e rds r in str u c t io n is en ter e d a nd r e ma in l o w u n t i l th e s t a t us dat a i s r e a d . rea d - st atu s - r e g i s ter i s c o n t i n u ous wit h ong oi ng c l o c k c y c l e s un til i t is t e r m i n a t ed b y a low t o h i g h tr an si ti on of th e c e # . se e f i gu r e 1 0 f o r t he rds r i n s t r u ct io n s e q u e n c e . f igure 10: r ead -s tatus -r egister (rdsr) s equence ce# so si sck 01 2 3 4 5 6 7 60 high imped ance mode 0 mode 3 1250 f09.0 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1250 f10.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high imped ance status register out msb msb
14 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 wr it e- en ab l e ( w re n) t h e w r it e- en ab l e ( w r e n ) in st r u ct io n se t s t h e wr i t e - en ab le - l a t ch b i t to 1 al lo wi ng w r i t e ope r a ti on s to oc c u r . t h e wr en in st r u ct io n m u s t be e x e c ut e d pr i o r to a n y wr i t e ( p r ogr am /e r as e) op er at io n. ce # m u s t be dr i v en h i g h be f o r e th e w r e n i n s t r u c t io n i s e x ec u t ed . f i gure 11 : w rit e e nab l e ( w re n) s e q ue nce wr it e- disa b l e ( w rdi) t h e w r it e- d i sa b l e ( w r d i ) ins t r u c t io n r e s e ts the w r it e- en able-latch bit and aai bit to 0 disabling any new write operations from occurring. ce# must be driven high before the wrdi instruction is executed. f i gure 12 : w rit e d is ab le ( w rdi) s e q ue nce e n a b l e -w ri te -s ta tus - re gi s t e r (ew s r) the e n ab le - w r i te- s ta tus - reg i s t e r ( e w s r) i n s t r u c t io n ar m s t he w r i t e- s t at us - r eg is te r ( w rs r) i n s t r u c t i o n an d op ens t he sta t u s r e gi st er f o r a l te r a ti on . t h e e n a b l e - w r i t e - st atu s - r e g i s ter in str u c t io n do es n o t ha v e an y e f f e c t an d w i l l be w a st ed , if i t is no t f o ll o w e d im me di at e l y b y th e wr i t e - s t a t us - r eg ist e r ( w r s r) in st r u ct i o n . ce # m u s t b e dr iv en lo w before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. ce# so si sck 01 2 3 4 5 6 7 06 high imped ance mode 0 mode 3 1250 f11.0 msb ce# so si sck 01 2 3 4 5 6 7 04 high imped ance mode 0 mode 3 1250 f12.0 msb
advance information 8 mbit spi serial flash SST25VF080 15 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 wr it e- st at u s - r eg is t e r ( w rsr ) t h e w r i t e- s t at us - r eg is te r i n s t r u ct io n w o r k s i n co nj un ct io n wi th th e en ab l e - w r i te - s ta tus - re gi s t er ( e w s r ) i n s t r u c t io n to w r ite ne w v a l ues to t he b p 1 , b p 0 , an d b p l bi ts o f th e st atu s r e g i s t e r . t h e w r i t e- s t at us - r egi s t er in st r u c t i on mus t be e x e c u t ed i m m edi at el y aft e r t he e x ec ut io n o f the e nab l e - w r i t e-s t at u s -r eg is t e r i n st r u ct i o n (v er y n e xt i n s t r u ct io n b u s cy c l e) . t h is tw o - s t e p in st r u c t i on s equ en ce o f th e ew s r in st r u c t i o n f o ll o w e d b y t h e wr s r i n s t r u ct io n w o r k s l i ke sd p ( s of tw ar e d a ta pr ot ec ti on) c o m m a n d st r u c t ur e whi c h pr e v ent s a n y ac ci de nta l a l t e r a t i on of t he s t a t us r e g i s t e r v a l- u e s . t h e w r i t e- s t at u s - r eg is te r in st r u ct io n w ill be i g n o r ed whe n w p # i s l o w an d b p l b i t i s s e t t o ? 1 ? . w hen t he w p # i s lo w , t h e bpl bi t ca n o n l y be s e t f r om ? 0 ? t o ? 1 ? to lo c k - do w n th e s t a t us r e gi st er , b u t ca nn ot b e r e se t f r o m ? 1 ? to ? 0 ? . wh en w p # is hi gh , the l o ck- down fu nc ti on of t he b p l bi t is d i s a b l ed an d t h e b p l , bp 0, an d bp 1 b i t s in t h e st at u s r e g - is te r c a n a l l b e ch an ged . as lo ng as bp l bi t is se t to 0 or w p # pi n i s d r iv e n hi gh ( v ih ) p r io r t o th e low - to- h igh tran s i - t i o n of th e c e # pi n at t h e e n d of t h e w r s r in st r u c t i o n , t h e bp 0, b p 1, an d bp l b i t i n the s t a t us r egi s t er ca n al l b e al ter e d b y th e w r s r in str u c t i on. i n thi s ca se, a s i n g l e wr sr i n s t r u ct io n ca n s e t th e bp l bi t to ? 1 ? to l o c k do w n the st atu s r e gi ste r as w e l l as al ter i ng the b p 0 an d b p 1 bi t at t he s a m e ti me . se e t a b l e 3 f o r a s u m m a r y des c r ip ti on o f wp # a nd b p l f unc ti on s . ce # mus t be dr iv en l o w be f o r e the c o m m an d s e que nc e of t he wr sr in st r u c t i on is e n t e r e d an d dr i v e n hi gh b e f o r e th e wr s r in st r u c t i o n i s e x ec ut ed. s e e f i gur e 13 f o r ew s r a n d w r s r i n s t r u ct io n se qu enc e s . figure 13: e nable -w rite -s tatus -r egister (ewsr) and w rite -s tatus -r egister (wrsr) s equence 1250 f13.0 mode 3 high imped ance mode 0 st a tus register in 7 65 4321 0 msb msb msb 01 mode 3 sck si so ce# mode 0 50 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 rea d -id th e r e a d -i d i n st r u ct io n id en t i f i e s t h e d e vi ce s a s s s t 25 v f 0 8 0 an d m a n u f a ct u r er a s ss t . t h e de vic e in f o r - ma tio n c an be r e ad fr om e x ec uti n g a n 8- bi t c o mm an d, 90 h or a b h , f o ll o w ed b y ad dr es s bi ts [a 23 -a 0 ]. f o l l o w in g th e rea d - i d i n s t r u ct io n, th e m anuf ac tur e r ? s i d is l o c a te d i n ad dr es s 0 0 0 00h a n d t h e d e vi c e id i s l o c a t ed i n ad dr es s 00 001 h. o n ce th e de v i ce i s i n rea d- i d m od e , th e m anu- f a c t ur er ? s and d e v i ce id ou tpu t d ata to ggl es b etwee n ad dr es s 0 000 0h an d 000 01 h u n ti l te r m i nat ed b y a low t o hi gh tr an si ti on on ce #. f i gure 14 : r ead -id s equence 1250 f14.0 ce# so si sck 00 01 2 3 4 5 6 7 8 00 add 1 90 or ab high imped ance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf de vice id bf de vice id note: the man uf acturer's and de vice id output stream is contin uous until ter minated b y a lo w to high tr ansition on ce#. de vice id = 80h f or SST25VF080 1. 00h will output the manf acturer's id first and 01h will output de vice id first bef ore toggling betw een the tw o . high imped ance mode 3 mode 0 msb msb msb
advance information 8 mbit spi serial flash SST25VF080 17 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 el ec t r ic a l sp e c if ic a t i o n s ab so lu t e m aximu m st re ss ra t i n g s ( a ppl ie d c onditi ons g r ea ter tha n tho s e li ste d un der ? a b s o l ut e ma xi m u m str e ss rati ng s? ma y ca us e pe r m an ent d a ma ge to the de vi ce. t h is i s a str e s s r a ti ng o n ly an d fun c t i on al oper a t io n of th e de vi c e at the s e co ndi tio n s o r c o n d it ion s gr e a ter tha n tho s e d e fi ned i n th e ope r a ti onal se ct ion s of t h is dat a sh eet is no t im pl ied . e x po su r e to abs ol ute max i mum st r e ss r a ti ng co ndi tio n s ma y aff e c t d e v i c e r e li abi li ty .) t e mp er atu r e und e r bi as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 5 5 c to + 125 c sto r age t e mp er atu r e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 6 5 c to + 150 c d . c . v o ltag e o n a n y p i n to g r ou nd p o te nti a l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0. 5v to v dd +0 . 5 v t r ans ie nt v o l t ag e ( < 20 n s ) on a n y p i n to g r ou nd p o te nti a l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 2. 0v to v dd +2 . 0 v p a c k ag e p o wer di ss ip ati on c apab il ity ( t a = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w su r f ac e m oun t le ad s o l der i n g t e mp er atu r e ( 3 s e c o nds ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c o u tpu t s hor t cir c uit cur r ent 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 ma 1. o u t put sh or t ed f o r no m o re t han one second. n o m o re t han one out put sho r t ed at a t i me . o p e rati n g r ang e range ambie n t t e m p v dd com m e r ci al 0 c to + 70c 2 .7 -3.6v ind u s tr i a l -40c t o +8 5c 2 .7 -3.6v ac c ondi ti ons of t es t inp u t r i se /f al l ti me . . . . . . . . . . . . . . . 5 n s o u tp ut l oad . . . . . . . . . . . . . . . . . . . . . c l = 30 pf s e e figures 19 and 20 t able 7 : dc o p e rat ing c haracte r i s ti cs sym bol p a rameter limits t e st con d ition s mi n ma x uni t s i dd r r ead cu rre nt 10 m a c e # = 0. 1 v dd /0 .9 v dd @2 0 mhz , so=o p e n i dd w prog r a m an d er a s e c u rren t 30 m a c e # =v dd i sb stan db y c u rren t 15 a c e # = v dd , v in =v dd or v ss i li inp u t l eak ag e c u rre nt 1 a v in = g nd to v dd , v dd =v dd ma x i lo ou tpu t le ak age cu rre nt 1 a v out =gnd to v dd , v dd =v dd ma x v il inp u t l o w v o ltag e 0 .8 v v dd =v dd mi n v ih inp u t hi gh v o lta g e 0 .7 v dd vv dd =v dd ma x v ol o u tpu t lo w v o l t ag e 0 .2 v i ol = 1 00 a , v dd =v dd mi n v oh o ut p ut hi gh v ol t a ge v dd -0.2 v i oh = - 100 a, v dd =v dd mi n t7 .0 125 0 t able 8 : r eco mme nded s ys te m p ow e r - up t im i n gs sym bol p a r a me ter m i n im um units t pu - r e ad 1 1. t h is paramet er is m easured only f o r init ial qualif ic at ion and af t er a design o r pro ces s chan ge t hat could af f e ct t h i s paramet er . v dd mi n to re ad op era t i o n 1 0 s t pu - w ri te 1 v dd m i n t o wr i t e o p er ati o n 1 0 s t8 .0 125 0
18 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 t able 9 : c ap aci tance ( t a = 2 5 c , f = 1 m h z, o t he r p i ns ope n ) p a r a me ter d es criptio n t est condit i on m axi m u m c out 1 o u tpu t pi n cap a c i ta nc e v out = 0v 12 pf c in 1 inp u t c a pac it anc e v in = 0v 6 pf t9 .0 125 0 1. t h is paramet er is m easured only f o r init ial qualif ic at ion and af t er a design o r pro ces s chan ge t hat could af f e ct t h i s paramet er . t able 1 0 : r e l i abi li ty c haract e r is ti cs sym bol p a r a me ter m inim u m spe c ifi cati o n u nits t e st m e th od n en d 1 1. t h is paramet er is m easured only f o r init ial qualif ic at ion and af t er a design o r pro ces s chan ge t hat could af f e ct t h i s paramet er . end u r a n c e 10, 000 c y cl es jed e c st and ard a117 t dr 1 d a ta re te nti o n 100 y e ars j ed ec st and ard a103 i lt h 1 la tch up 1 00 + i dd m a jed e c st and ard 78 t10 . 0 125 0 t able 1 1 : a c o p e rat i ng c haract e r i s ti cs sym bol p a rame ter m in m a x u nits f cl k ser i al c l oc k f r equ enc y 2 0 m h z t sc kh ser i al c l oc k hi g h ti me 20 ns t sc kl ser i al c l oc k lo w tim e 20 ns t ce s 1 1. relat iv e to s ck . c e # ac ti v e s e tup ti me 20 ns t ce h 1 c e # ac ti v e ho ld tim e 20 ns t ch s 1 c e # n o t ac tiv e se tup tim e 10 ns t ch h 1 ce# no t acti v e ho l d t i me 1 0 n s t cp h c e # h i gh tim e 100 ns t ch z c e # h i gh to h i gh-z ou tpu t 20 ns t cl z sc k lo w to lo w - z o u tp ut 0 n s t ds data in setu p ti me 5 n s t dh data in h o ld tim e 5 n s t hl s h o ld # l o w se tup tim e 10 ns t hh s h o ld # h i gh setup ti me 10 ns t hl h h o ld # l o w ho ld t i m e 15 ns t hh h h o ld # h i gh h o ld tim e 10 ns t hz h o ld # l o w to hi g h -z o u tput 20 ns t lz h o ld # h i gh to l o w -z o u tput 20 ns t oh o u tpu t hol d f r om sck cha nge 0 n s t v o u tpu t v a li d fro m sc k 2 0 n s t se sec t or-e ra s e 25 m s t be blo c k - er a s e 25 m s t sc e ch i p -er a se 100 m s t bp b y te - p r ogr am 2 0 s t11 . 0 125 0
advance information 8 mbit spi serial flash SST25VF080 19 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 f i gure 15 : s er i a l i np ut t im i n g d ia gr am figure 16: s erial o utput t iming d iagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1250 f15.0 1250 f16.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb
20 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 f i gure 17 : h ol d t im i n g d ia gr am figure 18: p ower - up t iming d iagram t hz t lz t hhh t hls t hlh t hhs 1250 f17.0 hold# ce# sck so si time v dd min v dd max v dd de vice fully accessib le t pu-read t pu-write chip selection is not allo w ed. all commands are rejected b y the de vice . 1250 f18.0
advance information 8 mbit spi serial flash SST25VF080 21 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 f i gure 19 : a c i np u t /o ut p ut r efer e n c e w av e f o r m s f i gure 20 : a t est l oad e xa m p le 1250 f19.0 reference points output input v ht v lt v ht v lt v iht v il t a c te st in put s a r e dr i v en a t v ih t (0 . 9 v dd ) f o r a l o g i c ?1 ? a n d v il t (0 . 1 v dd ) f o r a l o g i c ? 0 ? . m eas ur e m e n t r e f e r e nc e p o i n ts f o r i npu ts an d o u tp uts a r e v ht ( 0 .7 v dd ) a nd v lt (0 . 3 v dd ) . inp u t r i s e and f a l l tim e s ( 1 0 % ? 90% ) ar e < 5 ns. note: v ht - v high te s t v lt - v lo w te s t v iht - v input high test v ilt - v input low test 1250 f20.0 t o tester t o dut c l
22 ad va nc e inf o r m at ion 8 m b it spi s e rial fla s h s s t25vf0 80 ?2003 silicon storage technology, inc. s71250-00-000 10/03 pr o d uct o r der i n g informat i o n va lid co mb in at io n s f o r ss t 25v f 080 ss t 25v f 080 - 2 0- 4c- s 2a ss t 25v f 080 - 2 0- 4c- s 2ae ss t 25v f 080 - 2 0- 4i- s 2a ss t 25v f 080 - 2 0- 4i- s 2ae note : v a li d c o m b in ati ons ar e th ose pro d u c ts in ma ss pr odu cti on or w i l l b e i n m a s s p r od uct i on . c o n s u l t y o ur sst sa le s re pres en tati v e to c o n f ir m a v a i l abi lit y o f v a li d c o m b in ati ons an d to de ter m in e a v ail abi li ty o f n e w c o m b i nat ion s . s s t 25 l f 080 - 33 - 4c - s a e xx x xxxxx x - xxx -xx -xxx x e n v i r onme n ta l at tr ib ute e = no n- pb p a c kag e mo d i f i er a = 8 lea d s or c onta c t s p ac kag e t yp e s2 = soic 2 00 m i l bod y wid t h t e mp er at u r e r a n g e c = com m er c i al = 0c to + 7 0 c i = ind u s t r i al = - 40 c to + 8 5 c m i nim u m e ndur a n c e 4 = 10 ,000 cy c l es ope r a t ing fr e que nc y 20 = 2 0 mhz ve r s i o n de vic e de nsity 080 = 8 mb it vo l t a g e v = 2. 7- 3.6v p r oduc t se r i e s 25 = s p i ser i al f l a s h
advance information 8 mbit spi serial flash SST25VF080 23 ? 2 0 0 3 silico n sto r a g e t e ch n o l o g y , in c. s 7125 0-00 -000 10 /03 pa ckaging d i agra ms 8- lea d s mal l o ut li ne i nte g rat e d c ir cui t ( s o ic) 200 mi l bod y wi d t h ( 5 .2 mm x 8 mm ) ss t p a cka g e c ode : s 2 a t able 1 2 : r ev i s i o n h ist o r y nu m b e r de s c r ip tion da te 00 ini t ia l r e l eas e of da ta s h e e t o c t 20 03 08-soic-eiaj-s2a-2 note: 1. all linear dimensions are in millimeters (max/min). 2. coplanar ity: 0.1 mm 3. maxim um allo w ab le mold flash is 0.15 mm at the pac kage ends and 0.25 mm betw een leads . t op view side view end view 5.40 5.15 8.10 7.70 5.40 5.15 pin #1 identifier 0.50 0.35 1.27 bsc 0.25 0.05 2.20 1.75 0.25 0.19 0.80 0.50 0? 8? 1mm sil icon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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