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cop y ri gh t ? rd a mi croelec t ro n i cs inc. 20 06. a l l righ t s are rese r v e d . the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n p a rt w i thout prior written per mission of rda. rda5802n/ns/nm s ingle -c hip b roadcast fm r adio t uner rev . 2.0?m ar .201 1 1 general description the rda58 02n series is the newe s t genera t io n single-chip br oadcast fm stereo radio tuner with fu lly integra t ed s y nthesizer , if selectivity , r d s/rbds an d mpx decode r . the tuner uses the c m os process, support multi-interface an d require the least e x terna l component. the rda580 2n series have three typ e p a ckage size s , respective are rda580 2n (qfn 4x4 mm, 24pins), rda5802ns (qfn 3x3 mm, 20pins) an d RDA5802NM (qfn 2x2 mm, 12pins). all these make it very suit ab le for port able de vices. the rda580 2n series ha s a power ful low-if d i git a l audio processor , th is ma ke it ha ve o ptimum soun d quality with va rying receptio n conditions. the rda580 2n series sup port frequenc y range is fro m 50mhz to 1 1 5 m hz . 1.1 features ? cmos single-chi p full y-in tegra t ed fm tuner ? low power con s umption ? total current con s ump t ion lower than 20ma at 3 . 0 v power supply wh en under normal situa t ion ? support wo rldwid e frequency ban d ? 50 -115 mh z ? support flexible channel spa c ing mode ? 100khz, 200 kh z, 50kh z and 25 khz ? support rd s/rbds ? digital low- if tun e r ? image -reje ct dow n-conve r te r ? high performance a/d conve r te r ? if selectivi t y performed inte rnally ? fully in tegra t ed d i gi tal frequency synthesi z er ? fully in tegra t ed o n -chip rf and if vco ? fully in tegra t ed o n -chip loop fil t er ? autono mous sea r ch tuning ? support 32 .768khz crystal o scilla tor ? digital auto gain control (agc) ? digital adapti v e n o ise can c ella tion ? mono/ste r eo swi t ch ? s o ft m u t e ? high cu t ? progra mmable d e -emphasi s (50 / 75 ? s) ? receive signal strength indica tor (rssi) and snr ? bass boost ? v o l u m e c o nt r o l an d m u t e ? i 2 s digi tal ou tpu t i n terface ? line-level analog outpu t vol t age ? 32.768 khz 12m,24m,13m,26 m ,1 9.2m,38 . 4mh z referen c e clock ? only suppo r t 2-w i re bu s in terface 2 3 4 5 6 1 7 17 16 15 14 13 18 8 9 10 11 12 24 23 22 21 20 19 gn d pad gnd gnd lna p gn d rd a 58 02 n vd d gnd lo u t gn d l nan rout gn d vd d gn d gn d scl k sd i o rcl k vio gnd nc nc gpio1 gp io2 gp io3 figure1 -1. rd a 580 2n t op v i ew http://
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 2 of 29 ? directly suppo rt 3 2 ? re sistance loa d ing ? integ r ated ldo regulator ? 1.8 to 5.5 v operation voltage ? support qfn 4 x 4mm 24pins, qf n 3 x 3mm 20pin s and qfn 2x2mm 12 pins three packa ge types. 1. 2 app l i cat ion s ? cellular hand sets ? m p 3, m p 4 p l a y er s ? portable radios ? pdas, noteboo k
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 3 of 29 t a ble of content s 1 ? general desc ription ............................................................................................................ ........................ 1 ? 1.1 ? features ......................................................................................................................................... 1 ? 1.2 ? a pplica tio ns ............................................................................................................................... ..... 2 ? t a ble of cont ents .............................................................................................................. ................................... 3 ? 2 ? functional d e scription......................................................................................................... ....................... 4 ? 2. 1 ? fm rec e iver .................................................................................................................... .............. 4 ? 2. 2 ? synthesizer .................................................................................................................... ................ 4 ? 2. 3 ? power supply ................................................................................................................... ............. 5 ? 2. 4 ? reset a nd c ontr o l interfac e select ............................................................................................. 5 ? 2. 5 ? control interf ace .............................................................................................................. ............. 5 ? 2. 6 ? i 2 s audio data interface ......................................................................................................... ...... 5 ? 2. 7 ? gpio outputs ................................................................................................................... ............. 5 ? 3 ? electr i c a l ch ar acteristics ..................................................................................................... ...................... 6 ? 4 ? receiver characte ristics ....................................................................................................... ...................... 7 ? 5 ? serial in terface ............................................................................................................... ............................. 8 ? 5. 1 ? i 2 c interface t i m i ng ............................................................................................................. ......... 8 ? 6 ? register definition ............................................................................................................ .......................... 9 ? 9 ? application diagr am ............................................................................................................ ..................... 19 ? 9.1 ? rda5802n c o m m on application : ............................................................................................ 19 ? 9.1 . 1 ? bill of materials: ............................................................................................................. ............ 19 ? 9.2 ? rda5802ns com m on applica t ion: ........................................................................................... 20 ? 9.2 . 1 ? bill of materials: ............................................................................................................. ............ 20 ? 9.3 ? RDA5802NM com m on application: ......................................................................................... 21 ? 9.3 . 1 ? bill of materials: ............................................................................................................. ............ 21 ? 10 ? physical dim e nsion ............................................................................................................. ...................... 22 ? 11 ? pcb land p a ttern ............................................................................................................... ...................... 25 ? 12 ? change list .................................................................................................................... ............................ 28 ? 13 ? no tes ............................................................................................................................... ........................ 28 ? 14 ? contact info rmation ............................................................................................................ ..................... 29 ?
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 4 of 29 2 functional description i ad c l dac r dac q adc + - a udi o dsp co r e digital filter mpx decoder stereo/mono audio vco synthesizer gpio interface bus rssi vio sd io sc lk mcu gp i o lo ut rout l nan ln ap rc lk 2.7-5.5 v 32 .7 68 kh z vd d ldo limiter lna i pga q pga rds /rbds figure 2-1. rda580 2n fm t une r block diag ram 2 . 1 fm receiv er the receiver use s a di git a l low-if archite c ture th at avoids the dif f iculties a s soci ated wi th direct conve r si on while delive r i ng lowe r sol u tion co st and redu ce s compl e xity , and integ r a t es a lo w noise ampli f ier (l na) supp orting the fm broa dcast b a nd (5 0 to 1 1 5mhz), a m u lti-pha se image -rej e ct mixer array , a pro g ra mm able gai n control (pga ), a high re solution anal o g -to-digit a l conve r ters (adcs), an a udio dsp a n d a high - fidelity digit a l-to-anal og con v erters (dacs). the lna has dif f e r enti al input po rt s (l nap an d lnan) a n d sup port s a n y input po rt by set according reg i sters bit s (lna_por t _ sel[1:0]). it default input comm on mod e volt age is g nd. the limiter p r event s ove r loadin g and l i mit s the amount of intermod ulation produ ct s created by stron g adja c e n t chan nel s. the multi-p h a se mixe r array down co nvert s the lna o u tput d i f f erential rf sign al to low-if , it also has im age -reject fun c tio n and harm onic to ne s rejection. the pga a m plifies the mix e r outp u t if signal an d then digitized with adcs. the dsp co re finish es the cha nnel sele ction, fm demod ulation , stereo mp x deco der a nd output audio sign al. the mpx de cod e r can au tonomou s swit ch from stere o to mo no to limit the output noise. the da cs convert digit a l audio sign al to analog and ch ang e the volume at same time. the dacs has lo w-p a ss feature and -3db freque ncy is about 30 khz. 2 . 2 sy nthesizer the frequ en cy synthesi z er gene rate s the local oscillator signal whi c h divi de to multi-phase, then be used to downconve r t the rf input to a con s t a nt low intermedi ate freque ncy (if). the synthe sizer referen c e clo c k is 32.7 68 khz. the synthe si zer freq uen cy is define d by bit s cha n[9:0] with the ra nge fro m 5 0 mhz to 1 15m hz.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 5 of 29 2 . 3 po w e r suppl y the rda58 02n integ r at ed one l d o which sup p lie s po wer to the chi p . the external su pply volt age ra nge is 1.8-5.5 v . 2 . 4 reset and con t rol inter f ace select the rda580 2n is rese t it self whe n vio is powe r up. a nd al so supp ort so f t re set by trigge r 02h bit1 fro m 0 to 1. t he rda5 8 02n only sup port i 2 c control inte rface bus mo de. 2 . 5 con t rol inter f ace the rda58 02n o n ly sup port s i 2 c co ntro l interface. the i 2 c int e rface is compliant to i 2 c bus s pecification 2.1. it include s two pins: sclk and sdio. a i 2 c interface tran sfer be gin s with st ar t con d ition, a comman d byte and dat a bytes, each byte has a fol l owe d ack (or na ck) bit, and end s with st op co ndition. the comman d byte include s a 7-bit chi p address (00 1 0000 b) and a r/ w bit. the ack (o r nack) is always sent o u t by re ceive r . whe n in write tran sfer , d a t a bytes i s written o u t from mcu, a nd when in read tran sfer , dat a bytes is rea d out from rda 580 2n. the r e is no visible regi ster a ddress in i 2 c interface tran sfe r s. th e i 2 c interface ha s a fixed st a r t registe r ad dre ss (0x02 h for write tran sfer and 0x0a h for read tra n sfer), and an internal in cre m ent al ad dre ss counte r . if register address mee t s the end of r egister file , 0x3ah, regi ster ad dress will wra p back to 0x00h. for write transfe r , mcu pro g ra ms regi sters fro m regi ster 0x02h high byte, then register 0x02 h low byte, then re giste r 0x03h hi gh b y te, till the last re giste r . rda5 802 n al ways gives o u t ack af ter every byte, and m c u giv e s o u t st op con d ition whe n re giste r prog ram m ing is finished. for rea d tran sfer , af ter comm and byt e from mcu, rda58 02 n sen d s out regi ster 0x0a h high byte, then regi ste r 0x0ah low byte, then register 0x0bh high byte, till receive s nack from mcu. m cu giv e s out ac k for dat a bytes besi d e s last dat a byte. mcu gives out nack fo r la st dat a byte, an d then rda5 802 n will return the bu s to mcu, a nd mcu will give out st op condition. 2.6 i 2 s audio da t a interface the rda580 2n su ppo rt s i 2 s (inter_ic sound bus) audio interfa c e. the interface is fully compli ant with i 2 s bus specifi c ation. whe n setting i2sen bit high, rda5802n will output sck, ws, sd signal s from gpio3, gpio1, gpio2 as i 2 s m a ster and transmitter , the sampl e rate is 48kbp s 44.1kbp s,32 kbp s ?.. rda5802 n al so suppo rt as i 2 s slaver mode and tran smitter , the sample rate is less than 1 00kbp s. 2 . 7 gpio outpu t s the rda580 2n ha s three gpios. the functio n of gpios coul d pro g ra mme d with bit s g p io1[1:0], gpio2[1:0], gpio3[1:0] and i2sen. if i2sen is s e t to low , gpio pins c ould be prog ram m ed to output low or hig h or hig h -z, or be prog ram m ed to output interru pt a nd ste r eo indicator with bit s gpio1[1:0], gpio2[1:0], gpio3[1:0]. gpio2 coul d be progra mmed to output a low interrupt (inte rru pt will be gene rated only with inte rrupt en able bi t stcien is set to high) whe n see k /tu ne pro c e s s complete s. gpio3 could be pro g ramm ed to output stereo indi cato r bit st . con s t a nt low , high o r high-z functi onality is available reg a rdle ss of the st ate of vdd su pplie s or the enable bit. sc k ms b sd ws 1 sck left channel ls b msb 1 sck r i ght c hanne l lsb figure 3-2 i 2 s d i gi tal a u di o form at
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n p a rt w i thout prior written per mission of rda. page 6 of 29 3 electrical characteristics table 3-1 dc electrical specificati on (recommended operation conditions): symbol description min typ max unit vdd supp l y v o lta g e 1.8 3.3 5.5 v vio interface sup p l y volt age 1.0 - 3.6 v t amb ambie n t t e mp erature -20 27 + 75 v il cmos lo w le vel input volt a ge 0 0.3*vio v v ih cmos high l e v el input volt a ge 0.7*vio vio v v th cmos t h reshold vo ltag e 0.5*vio v table 3-2 dc electric a l specificat ion (absolute maximum ratings): symbol description min typ max unit vio interface sup p l y volt age -0.5 + 3 .6 v t amb ambie n t t e mp erature -40 + 90 c i in input current (1) -10 +10 ma v in input volta g e (1 ) -0.3 vio+0.3 v v lna lna f m input leve l + 10 dbm notes: 1. for pin: sclk, sdio table 3-3 power consumption specification (vdd = 3 v, vio=3 v, t a = 25 , unless otherwise specified) symbol description condition typ unit i vdd supp l y curre nt (1 ) enable=1 20 ma i vdd supp l y curre nt (2 ) enable=1 21 ma i vio interface sup p l y curr ent sclk an d rc lk active 60 ? a i pd po w e r d o w n current enable=0 5 ? a i vio interface po w e rdo w n curre nt enable= 0 10 ? a no tes: 1 . for s t rong in p u t s i gna l c ond ition 2. for weak input signal condition
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 7 of 29 4 receiver characteristics table 4-1 receiv e r ch aracteristic s (vdd = 3 v,vio=3 v, t a = 25 c, unless oth e r w ise s pecifi e d) symbol parameter conditions min typ max unit general specifications f in f m input f r equenc y r a n g e adjust band regist er 50 115 mhz 50mhz - 1.4 1.8 65mhz - 1.2 1.5 88mhz - 1.2 1.5 98mhz - 1.3 1.5 108mhz - 1.3 1.5 v rf sensitiv it y 1, 2 , 3 s/n= 26db 115m hz - 1.3 1.8 ? v emf ip3 in input ip3 4 agcd= 1 80 - - db ? v am am suppression 1,2 m=0.3 60 - - db s 200 adjacent channel selectivity 200khz 50 70 - db s 400 400khz selectivity 400khz 60 85 - db v afl ; v afr audio l/r output voltage 1,2 (pins lout and rout) volum e [3:0] =111 1 - 360 - mv mono 2 55 57 - s/n maximum signal to nois e ratio 1 ,2,3,5 stereo 6 53 55 - db scs stereo ch an ne l separ atio n 35 - - db r l audi o output loading resistance sing le-e nd ed 32 - - r lo a d =1 k - 0.15 0.2 thd audi o t o tal harmonic distortio n 1,3,6 volum e [3:0] = 1111 r lo a d =32 - 0.2 - % aoi audi o output l / r imbala n ce 1,6 - - 0.05 db r mute mute attenuation ratio 1 volume[3:0]=0000 60 - - db lo w freq 9 - 100 - bw audio audi o resp ons e 1 1khz= 0db 3 db poi nt high f r e q - 14 - hz pins ln a n , ln a p , lout, rout a nd nc(2 2 , 2 3 ) v com_rfi n pins lna n /lnap input common mode voltage 0 v v com audi o output common m o d e voltage 8 1.0 1.05 1.1 v v com_nc pins nc ( 22,2 3 ) common mode vo ltag e floa t i ng v notes: 1. f in = 65 to 1 1 5 m hz; f mo d =1khz; de-emp hasis =75 ? s; mono= 1 ; l=r unle s s noted other wise; 2. ? f = 2 2 . 5 k h z ; 3 . b af = 300 hz to 15khz, rb w <=10hz; 4. |f 2 -f 1 |> 1mhz, f 0 =2 x f 1 -f 2 , ag c disabl e, f in =7 6 to 108 m h z; 5. p rf =60 db u v; 6 . ? f= 75kh z ,f p ilot =10% 7. meas ured at v em f = 1 m v , f rf = 65 t o 108 mhz 8. at lo ut and ro u t pins 9. adjus t able
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 8 of 29 5 serial interface 5.1 i 2 c interfa ce t i ming table 5-1 i 2 c interface timing cha r acteris tics (vdd = 3 v, vio=3 v, t a = 25 c, unless oth e r w ise s pecifi e d) parameter symbol test condition min typ max unit sclk f r equ en c y f scl 0 - 400 khz sclk hi gh t i me t high 0.6 - - ? s sclk lo w t i me t lo w 1.3 - - ? s setup t i me for st ar t condit i on t su:sta 0.6 - - ? s hold t i me for st ar t conditi on t hd:sta 0.6 - - ? s setup t i me for st op conditi on t su:sto 0.6 - - ? s sdio input to sclk setup t su:dat 100 - - ns sdio input to sclk hold t hd:dat 0 - 900 ns stop to s t ar t t i me t buf 1.3 - - ? s sdio output f a ll t i me t f:out 20+ 0.1c b - 250 ns sdio input, s c lk rise/fall t i me t r:in / t f: i n 20+ 0.1c b - 300 ns input spike s u ppress i on t sp - - 50 ns sclk, sdio capac itive l oad i ng c b - - 50 pf digita l input pi n cap a cita nce 5 pf figure 5-1. i 2 c interfa c e w r ite t i ming di agra m figure 5-2. i 2 c interfa c e read t i min g di agra m
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 9 of 29 6 register definition reg bits name function default 00h 15:8 chipid[7:0] chip id. 0x58 02h 15 dhiz a u d i o o u t p u t hi gh- z disa ble. 0 = high i m p e d a nce; 1 = nor m al opera tio n 0 14 dmute mute di sable. 0 = mute ; 1 = no rmal o p erati o n 0 13 mon o mono s e lect. 0 = s t ereo; 1 = force mo no 0 12 b a ss bass b oost . 0 = disable d; 1 = bass b oos t e n able d 0 11 rclk non-calibrate mode 0=rclk clock is always supply 1=rclk clock is not always supply when fm w ork ( when 1, rda5802n can?t directly support -20 ~70 temperature. only suppory 20 temperature swing from tune point) 0 10 rclk di rect input mode 1=rclk clock u se the directl y i npu t m ode 0 9 seekup seek up. 0 = seek do wn; 1 = seek up 0 8 seek seek. 0 = disable sto p seek; 1 = e n abl e seek b e gin s i n the direc t io n s p ecified by see kup an d e n d s whe n a chan n e l is foun d, o r the entire b a nd has b een searche d . the seek b i t is s e t l o w an d th e stc bit is set h i gh w h en th e seek o p erati on com p letes . 0 7 skmode seek mod e 0 = w r ap at the upper or lo w e r band limi t an d c onti nue seekin g 1 = sto p seeki n g at t h e upp er o r lo w e r band lim it 0 6:4 clk_m o de [2:0 ] 000=32.768k hz 001=12mhz 101=24mhz 010=13mhz 1 10=26mhz 01 1=19.2mhz 1 1 1 =38.4mhz 000 3 rds_en rds/rbds ena b le if 1, rds/r bds enable 0 2 new_meth od ne w demodulate method enable, can improve the receive sensitivity about 1db. 0 1 soft_reset sof t reset. if 0, n o t rese t; if 1, reset . 0 0 en a b le po w e r up enabl e . 0 = disable d; 1 = enable d 0
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 10 of 29 reg bits name function default 03h 15:6 ch a n [ 9 :0 ] chan nel selec t . ba n d = 0 frequ ency = chan nel sp acin g (khz) x ch a n + 87.0 m h z ba n d = 1 o r 2 frequ ency = chan nel sp acin g (khz) x ch a n + 76.0 m h z ba n d = 3 frequ ency = chan nel sp acin g (khz) x ch a n + 65.0 m h z ch a n is up date d aft e r a seek o p erati on. 0x00 5 direct mode directly control mode, only used when test. 0 4 tune t u n e 0 = disable 1 = enable the tu ne o p era t ion begi ns w h e n t h e t une bit i s set hig h . th e stc bi t is se t hi gh w h en the t u n e opera tio n co mple tes. the tu ne bi t i s reset to l o w aut o ma ticall y w h en the tun e operat i on co mp letes.. 0 3:2 b a n d [ 1:0 ] band sel ect. 00 = 87?108 m h z (us/euro pe) 01 = 76?91 mhz (jap an) 10 = 76?108 m h z ( w orld w ide) 11 1 = 65 ?76 mh z east europ e or 50-65m h z 00 1:0 sp a c e [ 1:0 ] chan nel s p acin g . 00 = 100 khz 01 = 200 khz 10 = 50khz 1 1 = 25khz 00 04h 15 rdsien rds read y i n ter r upt e n able. 0 = disable i n te rrupt 1 = enable i n ter r upt settin g stcie n = 1 w ill generate a lo w pulse on gpio2 w h en the i n terrupt oc curs. 0 14 stcien seek/t u ne c o m p lete i n terru pt e n able. 0 = disable i n te rrupt 1 = enable i n ter r upt settin g stcie n = 1 w ill generate a lo w pulse on gpio2 w h en the i n terrupt oc curs. 0 13 rbds 1 = rbds m o d e enable 0 = rds m ode o n l y 0 12 rds_fi f o_e n 1 = rds fif o mo de ena b le. 0 11 de de-e mph asis. 0 = 75 s; 1 = 50 s 0 10 rsvd reser v e d 1 if 0x07h_bit[9]( band )=1, 65-7 6 mhz; =0, 50-7 6 mhz
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 11 of 29 reg bits name function default 9 sof t mute_e n if 1, so f t mu te e n able 1 8 a f c d a f c d i sable . if 0, afc w o rk; if 1, afc disa ble d . 0 7 rsvd reser v ed 6 i2s_en a b le d i2s bus e n abl e if 0, dis a ble d ; if 1, ena b le d. 0 5:4 gpio3[1: 0] general purp os e i/o 3. 00 = high im pe dance 01 = mon o /s tere o indi cat or (st ) 10 = lo w 11 = h i g h 00 3:2 gpio2[1: 0] genera l purp os e i/o 2. 00 = high im pe dance 01 = interru pt (i nt) 10 = lo w 11 = h i g h 00 1:0 gpio1[1: 0] genera l purp os e i/o 1. 00 = high im pe dance 01 = reserve d 10 = lo w 11 = h i g h 00 05h 15 int _m ode if 0, ge nerate 5 m s in terrup t; if 1, in terrup t la st un til rea d reg 0 ch action occ u rs. 1 14:13 seek_mo d e [ 1:0] rd a5802n seek mode select 00 12 rsvd reser ved 0 11:8 seekth[3 :0] 2 seek snr t hreshold value: noise_ th(db) = 79 ? seek_th 1000 7:6 ln a _ p o r t _se l [1: 0 ] ln a i npu t p o rt selecti on bi t: 00: n o in put 01: ln a n 10: ln a p 1 1 : dual por t in put 10 5:4 rsvd res v ered 00 3:0 volume [3:0 ] d a c gain con t r o l bits (vol ume ) . 0000=min ; 1111 = m a x v o lu me scale i s logarit h mi c w hen 0000, output mute and output impedance is very large 1111 06h 15 rsvd reser ved 0 14:13 open_m ode[ 1: 0] ope n reserved register mode. 11=ope n behind registers writing function others: only open behind registers reading function 00 12 i2s_mode 3 if 0, ma ster mod e ; if 1, sla v e mo de . 0 2 the d e fau lt no ise threshold is 7 1db 3 this fun c tion is open when i2s_enabled=1.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 12 of 29 reg bits name function default 11 s w _ l r 3 ws relatio n to l/ r chan nel. if 0, w s =0 ->r , w s=1 ->l; if 1, w s =0 ->l, w s =1 ->r . 10 10 sclk_i_ed g e 3 when i2s e n abl e if 0, use nor mal sclk int e rnall y ; if 1, in v er t e sclk intern all y . 0 9 d a t a _ s igned 3 if 0, i2s o u t put unsi gne d 16- bit audi o da t a . if 1, i2s o u t put signe d 16- bit a u dio d a t a . 0 8 ws_i_edge 3 if 0, use nor mal w s internall y ; if 1, in v e r t e w s i n terna l l y . 0 7:4 i2s_sw_cnt [4: 0] 3 o n ly v a l i d in mas t er m ode 4'b1000: ws_s tep_48; 4'b0111: ws_s tep=44.1kb ps; 4'b0110: ws_s tep=32kbp s; 4'b0101: ws_s tep=24kbp s; 4'b0100: ws_s tep=22.05kb ps ; 4'b0011: ws_s tep=16kbp s; 4'b0010: ws_s tep=12kbp s; 4'b0001: ws_s tep=11.025k bp s; 4'b0000: ws_s tep=8kb p s; 0000 3 sw_o_ed g e 3 if 1, inve r t w s o u tp ut w h en as master . 0 2 sclk_ o _ed g e 3 if 1, in v e r t sclk out pu t when as master. 0 1 l_del y 3 if 1, l ch ann e l d a t a d e la y 1 t . 0 0 r_del y 3 if 1, r c h an nel d a t a d e lay 1t. 0 07h 15 rsvd reserved 0 14:10 th_s ofr blend[5:0] thres hold for n o ise so f t ble nd setti ng, unit 2d b 10000 9 65m_50m mode v a lid w h en ban d [1: 0 ] = 2? b1 1 (0 x03h_bi t <3:2> ) 1 = 65~76 mhz; 0 = 50~76 mhz. 1 8 rsvd reser v ed 0 7:2 seek_th_ o l d 4 seek thres hol d for ol d seek mo de, v a lid w h en seek_mod e=01 000000 1 softblend_en if 1, so f t blen d e n able 1 0 freq_mode if 1, t h en freq se ttin g ch ang e d. freq = 7600 0(or 87000) k h z + fr eq_direc t (0 8h) khz. 0 0ah 15 rdsr rds ready 0 = no rds/rbd s group read y( default) 1 = ne w rds/ rbds group ready 0 14 stc seek/tune comp lete. 0 = not c o m p let e 1 = com p let e the seek/ tun e com p lete fla g i s set w h en the seek or tu n e operat i on co mp letes. 0 13 sf seek fail. 0 = seek successful; 1 = seek fa ilure the seek fail fla g is set when th e seek opera tio n fails t o fin d a chan nel with an rssi level grea ter tha n seekth[5:0 ] . 0 12 rdss rds synchroniza tion 0 4 0x05h_bit[14: 13] , seek_mode register . default value is 0 0 ; when = 01, w ill add the 5802 e seek m ode.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 13 of 29 reg bits name function default 0 = rds decoder not synchronized(default) 1 = rds decoder synchronized available only in rds verbose mode 11 blk_e when rds ena b le: 1 = block e has been fo und 0 = no bl ock e has be en f o u n d 0 10 st stereo in dica tor . 0 = mono ; 1 = s t ereo s t ereo ind i cati o n is availabl e o n gp i o3 by se tt ing g p io 3[ 1 : 0] =01. 1 9:0 re a d ch a n [9 :0 ] read c h an nel. ba n d = 0 frequ e nc y = c h ann e l s p acin g (khz) x re a d ch a n [ 9 :0 ]+ 87.0 mhz ba n d = 1 o r 2 frequ e nc y = c h ann e l s p acin g (khz) x re a d ch a n [ 9 :0 ]+ 76.0 mhz ba n d = 3 frequ e nc y = c h ann e l s p acin g (khz) x re a d ch a n [ 9 :0 ]+ 65.0 mhz re a d ch a n [9 :0 ] is u p da ted af te r a tun e or see k operat i on. 8?h 00 0bh 15:9 rssi[6:0 ] rssi. 000000 = mi n 111111 = m a x rssi scale is l o garith mic. 0 8 fm tr ue 1 = the c u rrent chan nel is a s t a t ion 0 = the c u rrent chan nel is not a st ati on 0 7 fm_re a d y 1=read y 0=not re ad y 0 6:5 rsvd reserved 00 4 a b c d _e 1= the block i d of regi ster 0c h, 0dh,0e h,0fh i s e 0= the block i d of regi ster 0c h, 0dh, 0e h,0fh is a , b, c, d 0 3:2 bler a [ 1:0 ] block errors l e v e l of rds_d a t a _ 0 , and is al w a y s read a s errors le v e l of rds bl oc k a ( i n rds mo de) o r bl ock e (in rbds m ode w h en a b c d _e fl ag is 1) 00= 0 errors requiring c o rrecti o n 01= 1~2 errors r e quirin g c o rrect ion 10= 3~5 errors r e quirin g c o rrect ion 1 1 = 6+ errors or error in ch eck w o rd, corre ctio n not pos sible. a v a i labl e onl y i n rds v e rb ose mod e 00 1:0 blerb [ 1:0 ] block errors l e v el o f rds_d a t a _ 1 , a n d is al w a y s read as errors le v e l o f rds bl ock b (in rds mo de ) or e (in rb ds mod e w h en a b cd_e fla g is 1 ) . 00= 0 errors requiring c o rrecti o n 01= 1~2 errors r equirin g c o rrect ion 00
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 14 of 29 reg bits name function default 10= 3~5 errors r equirin g c o rrect ion 1 1= 6+ errors or error in ch eck w o rd, corre ctio n not pos sible. a v a i labl e onl y i n rds v e rb ose mod e 0ch 15:0 rds a [ 15 :0] block a ( in r ds m ode ) or b l oc k e (in rb ds m ode w h en a b c d_e flag i s 1) 16? h58 03 0dh 15:0 rdsb[15 :0] block b ( in rds mo de) or block e (i n r bds mo de w h e n a b c d_e flag i s 1) 16? h58 04 0eh 15:0 rdsc[15 :0] block c ( in rds mo de) or block e (i n r bds mo de w h e n a b c d_e flag i s 1) 16? h58 08 0fh 15:0 rdsd[15 :0] block d ( in rds mo de) or block e (i n r bds mo de w h e n a b c d_e flag i s 1) 16? h58 04
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 15 of 29 8 pins description 8.1 rda58 02n pins description figure 8-1. rda580 2n t o p v i ew table 8-1 rda5 802 n pins description symbol pin description gnd 1,3,5,6,7,8,14,17,24,25 ground. connect to ground plane on pcb lnan,lnap 2,4 lna dual input port. sclk 9 clock input for serial control bus sdio 10 data input/output for serial control bus rclk 11 32.768khz c r y s t a l o s c i l l a t o r a n d r e f e r e n c e c l o c k inp ut vio 12 power supply for i/o vdd 13,18 power supply rout ,l out 15,16 right/lef t audio output gpio1,gpio2,gpio3 21,20,19 general purpose input/output nc 22,23 no connect 2 3 4 5 6 1 7 17 16 15 14 13 18 8 9 10 11 12 24 23 22 21 20 19 gnd pad gn d gn d l nap gnd rda 5802 n vdd gn d lo u t gn d l nan rout gn d vd d gn d sc l k sd i o rc lk vio gnd nc nc gp io 1 gp io 2 gp io 3 gnd
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 16 of 29 8. 2 rda58 02ns pi ns descri p tion figure 8-2. rda580 2ns t op v i ew table 8-2 rda5 802 ns pins description symbol pin description gnd 2,4,5,11,14,20,21 ground. connect to ground plane on pcb lnan,lnap 1,3 lna dual input port. sclk 6 clock input for serial control bus sdio 7 data input/output for serial control bus rclk 8 32.768khz crystal oscillator and reference clock input vio 9 power supply for i/o vdd 10 power supply rout,lout 12,13 right/left audio output gpio1,gpio2,gpio3 15,16,17 general purpose input/output nc 18,19 no connect 2 3 4 5 1 6 15 14 13 12 11 7 8 9 10 20 19 18 17 16 gnd pad gn d gn d lna p gn d rda 5802 ns vdd gn d lo ut lna n rout gn d scl k sd i o rc lk vi o gn d nc nc gp io1 gp i o2 gp io3
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 17 of 29 8. 3 rda58 02nm pi ns descri p tion figure 8-3. rda580 2nm t op v i ew table 8-3 rda5 802 n m pins description symbol pin description gnd 10,12,13 ground. connect to ground plane on pcb lnan,lnap 1,2 lna dual input port. sclk 3 clock input for serial control bus sdio 4 data input/output for serial control bus rclk 5 32.768khz crystal oscillator and reference clock input vio 6 power supply for i/o vdd 7 power supply rout ,l out 8,9 right/left audio output gpio2 1 1 general purpose input/output 2 3 2 3 1 4 15 14 9 8 7 5 8 9 6 12 11 18 17 10 gnd pad ln a n lna p 5802 nm ro ut lout vdd sd i o rc l k gn d gnd gp i o 2 scl k
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 18 of 29 table 8-4 internal pin configuration symbol pin description lnan/lnap 2/4(rda5802n) 1/3 (rda5802ns) 1/2 (RDA5802NM) rload rclk 11 (rda5802n) 8 (rda5802ns) 5 (RDA5802NM) rclk 5m 20pf 6pf inv 5m 0x02h_bit < vi o =1 =0 sclk/s dio 9/10 (rda5802n) 6/7 (rda5802ns) 3/4 (RDA5802NM) 47k s in s out mn1 sdio\sclk gpio1/ gpi o 2/gpi o 3 21/20/19(rda5802n) 17/16/15(rda5802ns) 11(RDA5802NM) 5 gpio 1 \2 \3 in out 5 only include gpio2
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 19 of 29 9 application diagram 9.1 rda5 802 n common appl ication : 7 19 figure 9-1. rda580 2n fm t une r app lication dia g ra m (tcxo ap plicatio n) 9.1.1 bill of materi als: component value description supplier u1 rda5 802 n broad ca st f m radio t u n e r rda j1 comm on 32 ? re sist an ce hea d ph one l3/c3 100n h/24 pf lc cho ck for lna input murata c4,c5 125f audio ac co uple cap a cito rs murata c6 22nf powe r suppl y byp ass ca p acitor murata f1/f2 1.5k@1 00m hz fm band fe rrite murat a notes: 1. j1: common 32 ? resist ance hea dph on e; 2. u1: rda58 0 2 n chi p ; 3. v1: pow e r supply (1.8~5.5v); 4. f m choke (l3 an d c3) for audio common and lna input co mmon; 5. pins nc(2 2 ,23) can b e le a ved floatin g ; 6. place c6 c l o se to 58 02n p i n1 3. 7.ferrite f1/f 2 sh ou ld cl ose to j 1 .
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 20 of 29 9.2 rda5 802 ns common ap plication 6 : j1 c4 12 5uf c5 125uf f1 1.5k@100mhz f2 1.5k@100mhz u1 gn d gn d ln ap gnd r da580 2ns gn d lo ut lnan rou t gnd gp io 3 1 11 scl k rclk sdio vi o gpi o 1 gpio 2 v1 c6 24nf gpio3 c1 1nf c7 c8 fm _l in fm_rin figure 9-2. rda580 2ns f m t une r appl i c ation diag ra m (tcxo ap plicatio n) 9.2.1 bill of materi als: component value description supplier u1 rda5 802 ns broad ca st f m radio t u n e r rda j1 comm on 32 ? re sist an ce hea d ph one l3/c3 100n h/24 pf lc cho ck for lna input murata c4,c5 125f audio ac co uple cap a cito rs murata c6 22nf powe r suppl y byp ass ca p acitor murata f1/f2 1.5k@1 00m hz fm band fe rrite murat a c1 7 1nf ac couple cap a c i tor murat a c7/c 8 8 0.22uf audio co uple cap a cito rs murat a 6 pin-to-pin compatible with rd a5820ns. rda5820ns is the n e west gen e ration fm receive/tran smit tuner . 7 c1 can be instead by 0ohm resister if not need compatible with rda5802ns 8 c7/c8 can be floating if not need compatible with rda5820ns notes: 1. j1: common 32 ? resist ance hea dph on e; 2. u1: rda58 0 2 ns ch ip; 3. v1: pow e r supply (1.8~5.5v); 4. f m choke (l3 an d c3) for audio common and lna input co mmon; 5. pins nc(1 8 ,19), can be le a ved floatin g or pl ac e capac itor c7/ c 8 ; 6. place c6 c l o se to 58 02ns pin1 0. 7.ferrite f1/f 2 sh ou ld cl ose to j 1 . c1: ac couple cap for compatible rd a 582 0n s c7 & c8 : a udio input couple cap for fm transmit ? pin1 (lnan) is receive/transmit dual port for rda5820ns
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 21 of 29 9.3 rda5 802 nm common application : j1 c4 125 uf c5 125uf f1 1.5k@100mhz f2 1.5k@100mhz 1 7 scl k rclk sdio vi o v1 c6 24nf 5802nm gn d pa d ln an lna p sc lk vdd ro ut lout figure 9-3. rda580 2nm fm t une r appl i c ation diag ra m (tcxo ap plicatio n) 9.3.1 bill of materi als: component value description supplier u1 RDA5802NM broadcast fm radio tuner rda j1 comm on 32 ? re sist an ce hea d ph one l3/c3 100nh/24pf lc chock for lna input murata c4,c5 125f audio ac couple capacitors murata c6 22nf power supply bypass capacitor murata f1/f2 1.5k@100mhz fm band ferrite murata notes: 1. j1: common 32 ? resist ance hea dph on e; 2. u1: rda58 0 2 nm chi p ; 3. v1: pow e r supply (1.8~5.5v); 4. f m choke (l3 an d c3) for audio common and lna input co mmon; 5. place c6 c l o se to 58 02nm pin7. 6.ferrite f1/f 2 sh ou ld cl ose to j 1 .
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 22 of 29 10 ph ysical dimension 10.1 rda5 802n physical dimension figure 10-1 illustrate s the p a ckage det ails for the rda58 02n. the p a ckag e is lead-f r ee an d ro hs-compli ant. mi n n o m max d 4.00 bsc e 4.00 bsc d2 2.60 2.70 2.80 e2 2.60 2.70 2.80 e 0.50 bsc l 0.30 0.40 0.50 b 0.18 0.25 0.30 a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 ref figure 10-1. 24-pin 4x4 q uad flat no -l ead (q fn)
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 23 of 29 10.2 rda5 802ns phys ical dimension figure 10-2 illustrate s the p a ckag e det ails for the rda580 2ns. the p a ckag e is lead-free and ro hs-compli ant. figure 10-2. 20-pin 3x3 q uad flat no -l ead (q fn)
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 24 of 29 10.3 rda5 802nm phy s ical dimen s ion figure 10 -3 illustrate s the p a ckage det ail s for the rda58 02 nm. the p a ckage is lead -free and ro hs-compli ant. figure 10-3. 12-pin 2x2 q uad flat no -l ead (q fn)
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n p a rt w i thout prior written per mission of rda. page 25 of 29 11 pcb lan d pattern figure 18.classificati on reflo w profile profile feature sn-pb eute ctic assembl y pb-free as sembl y average ra mp-up rate (t smax to t p ) 3 o c/second max. 3 o c/second max. preheat -temperature min (t sm in ) -temperature max (t sm ax ) -time (t sm in to t sm ax ) 100 o c 100 o c 60-120 seco nds 150 o c 200 o c 60-180 seco nds time mainta ined above: -temperature (t l ) -time (t l ) 183 o c 60-150seco nds 217 o c 60-150 seco nds peak /classification temperature(t p ) see table-ii see table-iii time within 5 o c of actu al peak temperature (t p ) 10-30 seconds 20-40 seconds ramp-down rate 6 o c/second max. 6 o c/seconds max. time 25 o c to peak temperature 6 minutes max. 8 minutes max.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 26 of 29 table-i classification reflow prof iles package thickness volume mm 3 <350 volume mm 3 350 2.5mm 240 + 0/-5 o c 225 + 0/-5 o c 2.5mm 225 + 0/-5 o c 225 + 0/-5 o c table ? ii snpb eutectic process ? package peak reflow temperatures package thickness volume mm 3 350 volume mm 3 350-2000 volume mm 3 2000 1.6mm 260 + 0 o c * 260 + 0 o c * 260 + 0 o c * 1.6mm ? 2.5mm 260 + 0 o c * 250 + 0 o c * 245 + 0 o c * 2.5mm 250 + 0 o c * 245 + 0 o c * 245 + 0 o c * * tolerance : the device manufacturer/supplier sh all assure pr ocess compatibility up to and including the stated classification temperatur e(this mean peak reflow temperature + 0 o c. for example 260+ 0 o c ) at the rated msl level. table ? iii pb-free proces s ? package classification reflow temperatures note 1: all temperature refer topside of the package. measured on the pa ckage body surface. note 2: the profiling tolerance is + 0 o c, - x o c (based on machine variation capability)whatever is r equired to control the p r ofile proce ss but at n o time will i t exceed - 5 o c. the producer assures proce ss compatibility at the pe ak reflow pr ofile temperatures defin ed in table ?iii. note 3: pa ckage volu me excludes external term inals(balls, bumps, lands, leads) and/or non integral heat sinks. note 4: the maximu m component temperature reached during reflow de pends on pa ckage the thickness a nd volume. the use of convection reflow processes reduce s the thermal gradients b e tween packages. ho wever, thermal gradients due to difference s in thermal mas s of smd pa ckage may sill exist. note 5: components intended for use in a ?lead-free? assembly proces s shall be evaluated using the ?lead free? classification temperat ures and profiles defined in table-i ii ii i whether or not lead free.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n p a rt w i thout prior written per mission of rda. page 27 of 29 rohs compliant the pro duc t d o es no t c o n t ai n l ead , m ercury , cadm i u m , hexa valen t c h r o m i u m , poly b r o m inate d b i p h eny l s (pbb) or po ly brom inate d d i p h e n y l eth e rs (pbd e), an d are therefore c onsi d er ed r o hs com p li ant . esd sensitivity in t e g r at ed cir c uits are e s d sensitiv e and can be dam a ged by static e l ectric ity . p r oper esd techniques should be used when handling these devices.
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 28 of 29 12 change li st rev date auther change description v1.0 201 1-0 2 -09 chu n zhao, y anan li u original draft. v1.1 201 1-0 3 -1 1 chu n zhao, y anan li u correct some errors v2.0 201 1-0 3 -24 chu n zhao, kai w a n g add qfn4x4mm and qfn2x2mm packages 13 notes
rda mic r oelec tronics , inc . rda58 02n/ns/nm f m t uner v2.0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be dist ributed, rep r od uced, or disclose d in w h o le or i n p a rt w i thout prior written per mission of rda. page 29 of 29 14 cont act information rda mi croele c troni cs (sha nghai ), inc. suite 1 108 bl ock a, e-wi n g cente r , 1 1 3 zhichu n ro a d haidi an di strict, beijing t e l: 86-1 0 -6263 5 360 fax: 86-1 0 -8261 2 663 post al code: 1000 86 suite 302 bui l ding 2, 690 b i bo ro ad pud ong di stri ct, shangh ai t e l: 86-2 1 -5027 1 108 fax: 86-2 1 -5027 1 099 post al code: 2012 03 cop y ri gh t ? rd a mi croelec t ro n i cs inc. 20 06. a l l righ t s are rese r v e d . reproduction in w h ole or in p a rt is prohibited w i thout the prior w r itt en consent of the cop y right o w ner .

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