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eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 256mb (4m 4bank 16) synchronous dram features ? fully synchronou s to posi tive clock edge ? single 2.7v ~ 3.6v powe r supply ? l v ttl com p atible with multiplexed address ? programm a ble burst len gth (b/l) - 1, 2, 4, 8 or full page ? programm a ble cas late n cy (c/ l ) - 2 or 3 ? dat a ma sk (dqm ) for re ad / w r ite ma ski ng ? programm a ble w r ap seq uen ce ? sequential (b/l = 1/2/4/8 /full page) ? interleave (b/l = 1/2/4/8) ? burst rea d with single - bi t w r ite ope r a t ion ? all input s are sampled at the risin g edge of the system clock ? auto refre s h and self re fresh ? 8,192 refre s h cy cle s / 64ms (7.8u s ) description the em48a m1684vb d i s synch r o n o u s dynami c ran dom access memo ry (sdram) o r gani zed a s 4meg wo rd s x 4 ban ks by 16 bit s . all input s an d output s are synchroni zed with the posit ive edge of t he clo ck. the 256 mb sdram u s e s syn c hroni zed pipelin ed architectu re t o achi eve hi gh sp eed d a t a tran sfer rates and i s d e sig ned to op erate at 3.3v low po we r memory syst em. it also provides a u to refresh with power saving / down mod e . all input s and outp u t s volt age level s are co mp atib le with l v tt l . a v ailable p a ckag es:tfb g a 54b 12mm x 8mm. ordering information part no organiz ation max. fr eq package grade pb em48am16 8 4 vbd-7 5f 16m x 16 133m hz @cl3 tfbga -54b comm ercial free em48am16 8 4 vbd-7 5fe 16m x 16 133m hz @cl3 tfbga -54b extend temp. f ree * eorex re serves the righ t to change p r odu ct s o r spe c ificatio n with out notice. 1/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m pin assignment: tfbga 54b 1 2 3 7 8 9 v s s d q 1 5 v s s q a v d d q d q 0 v d d d q 1 4 d q 1 3 v d d q b v s s q d q 2 d q 1 d q 1 2 d q 1 1 v s s q c v d d q d q 4 d q 3 d q 1 0 d q 9 v d d q d v s s q d q 6 d q 5 d q 8 n c v s s e v d d l d q m d q 7 ud q m c l k c k e f / c a s / r a s / w e a 1 2 a 1 1 a 9 g ba 0 ba 1 / c s a 8 a 7 a 6 h a 0 a 1 a 1 0 v s s a 5 a 4 j a 3 a 2 v d d 54ball tfbga / (12mm 8mm) 2/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m pin desc ription (simplified) pin name functio n f 2 c l k (sy s tem clock) maste r clo c k input (active o n the positive rising e dge ) g 9 / c s (chip selec t ) s e lect s c h ip whe n act i v e f 3 c k e (cloc k enabl e ) activates the clk wh en ?h? and de activ a tes when ?l?. cke sho u ld be enabl ed at least on e cycle p r io r to new comm and. di sabl e input b u f f ers for p o wer do wn in st andby . h7,h8,j8, j 7, j3, j2,h3,h2, h 1, g3, h9,g2,g 1 a0~a12 (ad d res s ) ro w add ress (a0 to a12) is determi ned by a0 to a1 2 level at the ban k acti ve comma nd cycle clk ri si ng edg e. ca (ca 0 to ca8) is dete r m i ned by a0 to a8 level at th e read o r write comma nd cycl e clk rising e dge. and this colu mn address become s burst access st a r t addre s s. a10 define s the pre - cha r ge mod e . when a10 = hi gh at the pre - charge comman d cycl e, all banks a r e pre-cha r g e d . but whe n a1 0= l o w at the pre - cha r ge comman d cy cl e, only the ban k that is selecte d by ba0/ba1 is pre - ch arged. g 7 , g 8 b a 0 , b a 1 (ba n k addre ss) select s whi c h bank i s to be active. f 8 / r a s (ro w ad dres s s t robe ) latch es ro w addre s se s on the positive rising e dge of the clk with /ras ?l?. enables ro w access & pre - ch arge. f 7 / c a s (column ad dress s t ro be ) latch es col u mn add r e s se s on t he p o si tive rising ed ge of the clk with /ca s low . enable s col u mn a c cess. f 9 / w e (w ri te enabl e ) latch es col u mn add r e s se s on t he p o si tive rising ed ge of the clk with /ca s low . enable s col u mn a c cess. f 1 / e 8 u d q m / l d q m (da t a input/ o utpu t mas k ) dqm c ontrols i/o buf fers . a8,b9,b8,c9,c8, d9,d8,e9,e1,d2, d1,c2,c1,b2,b1, a2 d q 0~d q 15 (da t a input/ o utpu t) dq pin s h a ve the sam e function a s i/o pins o n a con v entional dram. a9,e7,j 9 / a1,e3,j 1 v dd /v ss (po w e r supp ly /ground) v dd and v ss are po we r su pply pins for i n ternal circuit s . a7,b3,c7,d3/ a3,b7,c3,d7 v ddq /v ssq (po w e r supp ly /ground) v ddq and v ss q are po wer supply pin s for the output bu f f ers. e 2 n c (no conn ection) this pi n is recom m en ded to be lef t no conn ecti on on the device. 3/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m absolute m aximum rating symbol item rating unit s v in , v out input, output v o lt age -0.3 ~ +4.6 v v dd , v ddq powe r suppl y v o lt age -0.3 ~ +4.6 v comm ercial 0 ~ +7 0 t op operating t e mperature ra nge e x t e n d e d - 2 5 ~ + 8 5 c t st g s t orage t e m peratu r e ran ge -55 ~ +15 0 c p d powe r di ssi p a tion 1 w i os short circuit curre n t 50 ma not e : cautio n exposi ng t he devi c e to stre ss ab ove thos e li sted i n absolute m a ximum ratings co uld cau s e pe rma nent dama ge. the device is not m eant to be operate d unde r con d i t ions out side the limit s de scrib ed in the ope rational se ction of this sp e c ificatio n. exposure to ab solute maxim u m rating con d itions for extended pe riod s may af fect de vice relia bility . capacitance (v cc =3.3v , f= 1m hz, t a =25c) symbol paramete r min. ty p . max. unit s c clk clo ck ca p a cit ance - 4.0 pf c i input cap a cit ance for clk, cke, address, /cs, /ras, /c as, /we, dqml, dqmu - 5 . 0 pf c o input/output ca p a cit a n c e - 6.5 pf recommended dc operating conditions (t a =0c ~+7 0c) symbol paramete r min. ty p . max. unit s v dd powe r suppl y v o lt age 2.7 3.3 3.6 v v ddq powe r suppl y v o lt age (for i/o buf f er) 2.7 3.3 3.6 v v ih input logi c hi gh v o lt ag e 2.0 v dd +0. 3 v v il input logi c l o w v o lt a ge -0.3 0.8 v not e : * all volt ages referred to v ss . * v ih (max.) = 5.6v for pulse wid t h 3n s * v il (min.) = -2.0v for pulse wid t h 3ns 4/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m recommended dc operating conditions (v dd =3. 3 v 0.3v , t a =0 c ~ 70 c) symbol paramete r t e st conditions max. unit s i cc1 operating cu rre nt (no t e 1 ) burs t length=1, t rc t rc (min.), i ol =0ma , one ba nk a c t i ve 7 0 m a i cc2p cke v il (max.), t ck =15ns 1 m a i cc2p s precharge s t andby curren t in powe r do wn mode cke v il (max.), t ck = 1 m a i cc2n cke v il (min.), t ck =15ns, /cs v ih (min.) input sign als are chan ged one time du ri ng 30n s 2 0 m a i cc2n s precharge s t andby curren t in non - po we r d o wn mo de cke v il (min.), t ck = , input sign als are st able 1 0 m a i cc3p cke v il (max.), t ck =15ns 3 m a i cc3p s active s t andb y current in powe r do wn mode cke v il (max.), t ck = 3 m a i cc3n cke v il (min.), t ck =15ns, /cs v ih (min.) input sign als are chan ged one time du ri ng 30n s 3 0 m a i cc3n s active s t andb y current in non - po we r d o wn mo de cke v il (min.), t ck = , input sign als are st able 2 0 m a i cc4 operating cu rre nt (burst mode ) (n ote 2 ) t ccd 2clks, i ol =0ma 9 0 m a i cc5 refre s h cu rrent (no t e 3 ) t rc t rc (min.) 1 2 5 m a i cc6 self refres h current cke 0.2v 0.8 (no t e 4) ma *all volt ages referen c e d to v ss . not e 1: i cc1 d epen ds o n ou tput loading a nd cycl e rate s. s pecified val ues a r e obt ai ned with the output ope n. input sign als are chan ged only one time during t ck (min.) not e 2: i cc4 d epen ds o n ou tput loading a nd cycl e rate s. s pecified val ues a r e obt ai ned with the output ope n. input sign als are chan ged only one time during t ck (min.) not e 3: input signal s are chang ed only one time du ri ng t ck (min.) not e 4: s t an dard p o wer v e rsi on. recommended dc operating conditions (continued) symbol paramete r t e st conditions min. ty p . max. unit s i il input lea kag e curre n t 0 v i v ddq , v ddq =v dd all other pin s not unde r test =0v - 0 . 5 + 0 .5 u a i ol output lea ka ge cu rrent 0 v o v ddq , d out is disa bl ed - 0 . 5 + 0 .5 u a v oh high l e vel o u tput v o lt age i o = - 0 . 1 m a 2 . 4 v v ol low l e vel ou tput v o lt age i o = + 0 . 1 m a 0 . 2 v 5/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m block diagram 6/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m ac operating t e s t conditions (v dd =3. 3 v 0.3v , t a =0 c ~70 c) item conditions output refe rence level 1.4v/1.4v output loa d see diag ram as bel ow input signal l e vel 2.4v/0.4v t r a n sition t i me of input signal s 1ns input referen c e level 1.4v ac operating t e st characteristics (v dd =3. 3 v 0.3v , t a =0 c ~70 c) -7.5 symbol paramete r min. max. unit s cl =3 7 . 5 t ck clo ck cy cle t i me cl =2 1 0 ns cl =3 5 . 4 t ac a cce s s t i me f o rm clk cl =2 6 ns t ch clk hig h le vel wid t h 2.5 ns t cl clk lo w lev el wid t h 2.5 ns cl =3 3 t oh dat a -out hol d t i me cl =2 3 ns cl =3 3 7 t hz dat a -out hi g h impedan ce ti m e (n ote 5 ) cl =2 ns t lz dat a -out lo w impedan ce t i me 1 ns t ih input hold t i me 1 ns t is input setup t i me 1.5 ns * all volt ages referen c ed to v ss . not e 5: t hz defines the tim e at whi c h th e output a c hi eve the ope n circuit conditi on and i s not referen c ed to output volt ag e levels. 7/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m ac operating t e st characteristics (continued) (v dd =3. 3 v 0.3v , t a =0 c ~70 c) -7.5 symbol paramete r min. max. unit s t rc active to active com m and period (no t e 6 ) 6 7 n s t ras active to p r echarge comm and pe riod (no t e 6) 4 2 1 0 0 k n s t rp precharge to active comm and pe riod (no t e 6) 1 5 n s t rcd active to read/write delay ti m e (n ote 6 ) 1 5 n s t rrd active(one ) to active(another) comm and (n ote 6 ) 1 5 n s t ccd read/write command to read/w rit e comman d 1 clk t dpl date-i n to pr echa rge comm and 2 clk t bdl date-i n to burst s t op co mmand 1 clk cl =3 3 t roh dat a -out to high impedan ce from precharge command cl =2 clk t ref refre s h t i me (8,192 cycle ) 64 ms * all volt ages referen c ed to v ss . not e 6: th ese p a ramete rs account for t he numb e r of cl ock cy cle s and de pen d o n the operatin g freque ncy of the clock, as follo ws: the numb e r of clock cycle s = s pec ified value of timin g /clo ck pe rio d (cou nt fra c tion s as a whole numbe r) recommended power on and initialization the followin g power on an d initialization seque nce gu ar ante e s the device is pre c on ditioned t o each u s er ? s spe c ific need s. (li k e a co nventional dram) du ring powe r o n , all v dd and v ddq pins mu st be built up simult a neo usl y to the speci f ied volt age whe n the inp u t signal s are held in the ?nop? st ate. the po we r o n volt age mu st not exce ed v dd +0.3v on a n y of the inp u t pins or v dd suppli e s. (clk si gnal st arted at sam e time) af ter powe r on, an initial p ause of 20 0 s is requi red followed by a precha rge of all banks u s ing the pre c ha rg e co mmand. t o preve n t d a t a contentio n on th e dq bus du ring p o we r o n , it is req u ire d that the dqm a n d cke pi ns b e held high during the initial p ause pe rio d . once a ll banks have been pre c h a rg ed, the mode registe r set comm and m u st be issue d to initialize the mode reg i ster . a minim u m of eight auto refre s h cycles (cbr) are al so requi red, and the s e may be don e before o r af ter pro g ra mm ing the mode regi ste r . 8/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m simplified s tate diagram c k e c k e s e l f s e l f e x i t act rea d r e a d w i t h w r i t e w i t h bst p r e p r e 9/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m address input for mode re gister set ba1 ba0 a12/a1 1 a10 a9 a8 a7 a6 a5 a4 a 3 a 2 a1 a0 operation mo de cas laten cy b t b u r s t le ngth burst le ngth sequential i nterleave a 2 a1 a0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 re serv e d re serv e d 1 0 0 re serv e d re serv e d 1 0 1 re serv e d re serv e d 1 1 0 full page re serve d 1 1 1 burst t y pe a3 i n t e r l e a v e 1 s e q u e n t i a l 0 cas laten cy a6 a5 a4 re serve d 0 0 0 re serve d 0 0 1 2 0 1 0 3 0 1 1 re serve d 1 0 0 re serve d 1 0 1 re serve d 1 1 0 re serve d 1 1 1 ba1 ba0 a12/a1 1 a10 a9 a8 a7 operation mo de 0 0 0 0 0 0 0 n o r m a l 0 0 0 0 1 0 0 burst read with single-bit w r i t e 10/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m burst t y pe (a3) burst le ngth a2 a1 a0 sequential a ddre s sing interleave ad dre ssi ng x x 0 0 1 0 1 2 x x 0 1 0 1 0 x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 full page* n n n cn cn+1 cn +2?? - * page length is a function of i/o organi zation and col u mn add re ssi ng 16 (ca0 ~ ca8 ) : full p a g e = 5 12bit s 1. command t r ut h t a ble cke comm and symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a1 1, a9~ a 10 ignore comm a n d d e s l h x h x x x x x x no op eratio n nop h x l h h h x x x burs t s t op bsth h x l h h l x x x rea d read h x l h l h v l v rea d with au to pre- cha r ge reada h x l h l h v h v w r i t e w r i t h x l h l l v l v w r ite with auto pre- cha r g e wri t a h x l l h h v h v bank a c tivate act h x l l h h v v v pre-c h arge selec t bank pre h x l l h l v l x pre-cha r g e all banks p a ll h x l l h l x h x mode regi ster set mrs h x l l l l l l v h = hi gh leve l, l = low lev e l, x = high o r low level (don't ca re), v = v a lid da t a i nput 1 1 /17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 2. dqm t r uth t a ble cke comm and symbol n-1 n /cs dat a w r ite/o u tput enable enb h x h dat a mask /output disable mask h x l upp e r byte w r ite ena b le/ o utput enabl e bsth h x l rea d r e a d h x l read with auto pre-c h arge reada h x l w r i t e w r i t h x l w r ite with auto pre-c h arge wri t a h x l bank a c tivate act h x l pre-c h arge selec t bank pre h x l pre-cha r g e all banks p a ll h x l mode regi ster set mrs h x l h = hi gh leve l, l = low lev e l, x = high o r low level (don't ca re), v = v a lid da t a i nput 3. cke t r uth t a ble cke item comm and symbol n-1 n /cs /ras /cas /we addr . activating clo ck su spe nd mode entry h l x x x x x any clo ck su spe nd mode l l x x x x x clo ck suspe nd clo ck su spe nd mode exit l h x x x x x idle cbr r e fre s h comma nd ref h h l l l h x i d l e s e l f refres h e n t r y s e l f h l l l l h x l h l h h h x self refres h self refres h exit l h h x x x x i d l e p o w e r d o w n e n t r y h l x x x x x powe r do wn powe r do wn e x i t l h x x x x x rem a r k h = high level, l = low level, x = high o r l o w level (don 't care ) 12/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 4. operative command t a ble (note 7) cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop o r po we r down (no t e 8) l h h x x nop or bst nop o r po we r down (no t e 8) l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a a c t ro w activ a tin g l l h l ba, a 1 0 pre/p a l l nop l l l h x r e f / s e l f refres h or self refresh (no t e 10) idle l l l l o p - c o d e m r s mode regi ster accessin g h x x x x de s l nop l h h x x nop or bst nop l h l h ba/ ca/ a 10 re ad/r ea d a begin re ad: determin e ap (n o t e 1 1 ) l h l l ba/ ca/ a 10 writ/writ a begin write: determine a p (n ote 1 1 ) l l h h ba/ r a a c t illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l pr e - c h ar ge (note 12 ) l l l h x r e f / s e l f illegal (n ot e 10) ro w active l l l l o p - c o d e m r s illegal h x x x x de s l contin ue bu rst to end row ac tive l h h h x n o p contin ue bu rst to end row ac tive l h h l x bst burs t s t op ro w activ e l h l h ba/ ca/ a 10 re ad/r ea d a t e rminate b u rst, new read: determine a p (n ote 13 ) l l l l ba/ ca/ a 10 writ/writ a t e rminate b u rst, st art write: determine a p (n ote 13 , 14) l l h h ba/ r a a c t illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l t e rminate b u rst, pre-ch argi ng (no t e 10) l l l h x r e f / s e l f illegal read l l l l o p - c o d e m r s illegal h x x x x de s l contin ue bu rst to end wr i t e r e cover i ng l h h h x n o p contin ue bu rst to end wr i t e r e cover i ng l h h l x bst burs t s t op ro w activ e l h l h ba/ ca/ a 10 re ad/r ea d a t e rminate b u rst, st art read: determine a p 7, 8 (n ote 13 , 14) l l l l ba/ ca/ a 10 writ/writ a t e rminate b u rst, new write: determine a p 7 (n ote 13 ) l l h h ba/ r a a c t illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l t e rminate b u rst, pre-ch argi ng (no t e 15) l l l h x r e f / s e l f illegal wr i t e l l l l o p - c o d e m r s illegal rem a r k h = high level, l = low level, x = high o r l o w level (don 't care ) 13/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 4. operative command t a ble (continued) (n ot e 7) cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l contin ue bu rst to end pre-cha r gi ng l h h h x n o p contin ue bu rst to end pre-cha r gi ng l h h l x b s t illegal l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a act illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l illegal (n ot e 9) l l l h x r e f / s e l f illegal read w i th ap l l l l o p - c o d e m r s illegal h x x x x de s l burst to end w r ite re co vering with auto pre-cha r ge l h h h x n o p contin ue bu rst to end wr i t e recoveri ng wi th auto pre - charg e l h h l x b s t illegal l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a act illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l illegal (n ot e 9) l l l h x r e f / s e l f illegal wr i t e w i t h ap l l l l o p - c o d e m r s illegal h x x x x de s l nop enter idle af ter t rp l h h h x n o p nop enter idle af ter t rp l h h l x b s t illegal l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a act illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l nop enter idle af ter t rp l l l h x r e f / s e l f illegal pre-charging l l l l o p - c o d e m r s illegal h x x x x de s l nop enter idle af ter t rcd l h h h x n o p nop enter idle af ter t rcd l h h l x b s t illegal l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a act illegal (n ot e 9, 16) l l h l ba, a 1 0 pre/p a l l illegal (n ot e 9) l l l h x r e f / s e l f illegal ro w activating l l l l o p - c o d e m r s illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge 14/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 4. operative command t a ble (continued) (n ot e 7) cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop enter row ac tive af t e r t dpl l h h h x n o p nop enter row ac tive af t e r t dpl l h h l x bst nop enter row ac tive af t e r t dpl l h l h ba/ ca/ a 10 re ad/r ea d a s t art read, determine ap l h l l ba/ ca/ a 10 writ/writ a ne w write, d e termin e ap (n o t e 14 ) l l h h ba/ r a act illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l illegal (n ot e 9) l l l h x r e f / s e l f illegal wr i t e recovering l l l l o p - c o d e m r s illegal h x x x x de s l nop enter pre - charge af ter t dpl l h h h x n o p nop enter pre - charge af ter t dpl l h h l x bst nop enter pre - charge af ter t dpl l h l h ba/ ca/ a 10 re ad/r ea d a illegal (n ot e 9, 14) l h l l ba/ ca/ a 10 writ/writ a illegal (n ot e 9) l l h h ba/ r a act illegal (n ot e 9) l l h l ba, a 1 0 pre/p a l l illegal l l l h x r e f / s e l f illegal wr i t e recovering with ap l l l l o p - c o d e m r s illegal h x x x x de s l nop enter idle af ter t rc l h h x x nop/ bst nop enter idle af ter t rc l h l x x re ad/w rit illegal l l h x x act / p r e/ p a l l illegal refreshing l l l x x ref/self/mrs illegal h x x x x de s l nop l h h h x n o p nop l h h l x bst illegal l h l x x re ad/w rit illegal mode register accessi ng l l x x x act / p r e/ p a l l / ref/self/mrs illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge not e 7: all entrie s assu me that cke wa s active (h igh level) du ri ng the pre c e d i ng clo c k cycl e. not e 8: if all banks are id le, and cke is ina c tive (lo w level), sdram will enter powe r do wn mode. all input buf fers ex cept ck e will be disa bled. not e 9: illega l to bank in specifie d st ate s ; functio n may be legal in the ban k indicated by bank a ddre s s (ba), depe nding o n the st ate of that bank. note 10: if all banks are idl e , and cke is inactive (lo w level), sdra m will enter s e lf refre s h mo de. all input buf fers ex cept ck e will be disa bled. not e 1 1 : illegal if t rc d is not satisfied. note 12: illegal if t ra s is not satisfied. note 13: must s a tis f y burs t interrupt c o ndition. note 14: m u st satisfy bus contention, bu s turn a r ou nd , and/or write recovery re qu ireme n t s . note 15: m u st mask p r e c e d ing dat a whi c h do n't sati sfy t dp l . note 16: illegal if t rr d is not satisfied. 15/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m 5. command t r ut h t a ble for cke cke curre n t s t ate n-1 n /cs /r /c /w addr . action h x x x x x x inv a lid, cl k(n-1 ) woul d exit self refre s h l h h x x x x self refre s h r e cov e ry l h l h h x x self refre s h r e cov e ry l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maint a in self refresh h h h x x x x idle af ter t rc h h l h h x x idle af ter t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x illegal h l l h h x x illegal h l l h l x x illegal self refresh recovery h l l l x x x illegal h x x x x x x inv a lid, cl k(n-1 ) would exit power do wn l h x x x x x exit power do wn idle po w e r do wn l l x x x x x ma in t a in po we r d o w n mode h h h x x x h h l h x x h h l l h x refer to op erations in o p e r ative comm and t a ble h h l l l h x refre s h h h l l l l o p-code h l h x x x h l l h x x h l l l h x refer to op erations in o p e r ative comm and t a ble h l l l l h x self refres h (n o t e 17 ) h l l l l l o p-code refer to op erations in o p e r ative comm and t a ble both ban ks idle l x x x x x x powe r do wn (n o t e 17 ) h x x x x x x refer to op erations in o p e r ative comm and t a ble ro w active l x x x x x x powe r do wn (n o t e 17 ) h h x x x x refer to op erations in o p e r ative comm and t a ble h l x x x x x begin clo c k susp end n e xt cycle (no t e 18) l h x x x x x exit clock su spend n e xt cycle any s t ate oth er than listed ab ove l l x x x x x maint a in clo c k su sp end rem a r k : h = high level, l = low level, x = high o r l o w level (don 't care ) notes 17 : se lf refresh ca n be entered o n ly from the both ban ks idl e st ate. powe r do wn can b e entere d only from b o th ban ks idl e or ro w a c tive st ate. notes 18 : m u st be leg a l comman d as d e fined in op e r ative comm and t able 16/17
eor e x pr eliminary EM48AM1684VBD m a r . 2008 www .eor ex.c o m package description 17/17

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