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irf.com ? 2009 international rectifier october 11, 2010 automotive grade auirs2336s 3-phase bridge driver ic features ? drives up to six igbt/mosfet power devices ? gate drive supplies up to 20 v per channel ? over-current protection ? over-temperature shutdown input ? advanced input filter ? integrated deadtime protection ? shoot-through (cross-conduction) protection ? undervoltage lockout for v cc & v bs ? enable/disable input and fault reporting ? adjustable fault clear timing ? separate logic and power grounds ? 3.3 v input logic compatible * qualification standards c an be found on ir?s web site www. ? tolerant to negative transient voltage ? designed for use with bootstrap power supplies ? matched propagation delays for all channels ? -40c to 125c operating range ? rohs compliant ? lead-free ? automotive qualified* typical applications ? hvac compressor ? brushless automotive applications product summary topology 3 phase v offset 600 v v out 10 v ? 20 v i o+ & i o- (typical) 200 ma & 350 ma t on & t off (typical) 530 ns & 530 ns deadtime (typical) 275 ns package options 28-lead soic wide body typical connection diagram
auirs2336s www.irf.com ? 2009 international rectifier 2 table of contents page description 3 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 static electrical characteristics 7-8 dynamic electrical characteristics 9 functional block diagram 10 input/output pin equivalent circuit diagram 11 lead definitions 12 lead assignments 13 application information and additional details 14-29 parameter temperature trends 30-33 package details 34 tape and reel details 35 part marking information 36 ordering information 36
auirs2336s www.irf.com ? 2009 international rectifier 3 description the auirs2336s are high voltage, high speed, power mosfet and igbt gate drivers with three high-side and three low-side referenced output channels for 3-phase applicati ons. this ic is designed to be used with low-cost bootstrap power supplies. proprietary hvic and latch immune cmos technologies have been implemented in a rugged monolithic structure. the float ing logic input is compatible with standard cmos or lsttl outputs (down to 3.3 v logic). a current trip function which terminat es all six outputs can be derived from an external current sense resistor. enable functionality is available to terminate all six outputs simultaneously. an open-drain fault signal is provided to indicate that a fault (e.g ., over-current, over-temperat ure, or undervoltage shutdown event) has occurred. fault conditions are cleared automat ically after a delay programmed externally via an rc network connected to the rcin input. the output driv ers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. shoot-through prot ection circuitry and a minimum deadtime circuitry have been integrated into this ic. propagation delays are matched to simplify the hvic?s use in high frequency applications. the floating channels can be used to drive n-channel power mosfets or igbts in the high-side configuration, which operate up to 600 v.
auirs2336s www.irf.com ? 2009 international rectifier 4 qualification information ? automotive (per aec-q100 ?? ) qualification level comments: this family of ics has passed an automotive qualification. ir?s industr ial and consumer qualification level is granted by extension of the higher automotive level. moisture sensitivity level msl3 ??? 260c (per ipc/jedec j-std-020) machine model class m2 (200v) (per aec-q100-003) human body model class h1c (1500v) ( per aec-q100-002 ) esd charged device model class c4 (1000v) (per aec-q100-011) ic latch-up test class ii level a (per aec-q100-004) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? exceptions to aec-q100 requirements are noted in the qualification report. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information.
auirs2336s www.irf.com ? 2009 international rectifier 5 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. these are stress ratings only, functional operation of the device at these or any other condition beyond those indicated in the ?recommended operating condition? is not implied. expos ure to absolute maximum-rated conditions for extended periods may affect device reliability. all voltage parameters are absolute voltages referenced to v ss unless otherwise stated in the table. the therma l resistance and power dissipation ratings are measured under board mounted and still air conditions. voltage clamps are included between v cc & com (25 v), v cc & v ss (20 v), and v b & v s (20 v). symbol definition min max units v cc low side supply voltage -0.3 20 ? v in logic input voltage (hin, lin, itrip, en) v ss -0.3 v ss +5.2 v rcin rcin input voltage v ss -0.3 v cc +0.3 v b high-side floating well supply voltage -0.3 620 ? v s high-side floating well supply return voltage v b -20 ? v b +0.3 v ho floating gate drive output voltage v s -0.3 v b +0.3 v lo low-side output voltage com-0.3 v cc +0.3 v flt fault output voltage v ss -0.3 v cc +0.3 com power ground v cc -25 v cc +0.3 v dv s /dt allowable v s offset supply transient relative to v ss ? 50 v/ns pw hin high-side input pulse width 500 ? ns p d package power dissipation @ t a +25oc ? 1.6 w rth ja thermal resistance, junction to ambient ? 78 oc/w t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 oc ? all supplies are tested at 25 v. an in ternal 20 v clamp exists for each supply.
auirs2336s www.irf.com ? 2009 international rectifier 6 recommended operating conditions for proper operation, the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to v ss unless otherwise stated in the table. t he offset rating is tested with supplies of (v cc -com) = (v b -v s ) = 15 v. symbol definition min max units v cc low-side supply voltage 10 20 v in hin, lin, & en input voltage v ss v ss +5 v b high-side floating well supply voltage v s +10 v s +20 v s high-side floating well supply offset voltage ? com-8 600 v s (t) transient high-side floating supply voltage ?? -50 600 v ho floating gate drive output voltage v s v b v lo low-side output voltage com v cc com power ground -5 5 v flt fault output voltage v ss v cc v rcin rcin input voltage v ss v cc v itrip itrip input voltage v ss v ss +5 v t a ambient temperature -40 125 oc ? logic operation for v s of ?8 v to 600 v. logic state held for v s of ?8 v to ?v bs . ?? operational for transient negative v s of v ss - 50 v with a 50 ns pulse width. guaranteed by design. refer to the application information section of this datasheet for more details.
auirs2336s www.irf.com ? 2009 international rectifier 7 static electrical characteristics unless otherwise noted, these specifications apply for an operating junction temperature range of -40c tj 125c with bias conditions of (v cc -com) = (v b -v s ) = 15 v. the v in and i in parameters are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to respective v s and com and are applicable to the respective output leads ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . symbol definition min typ max units test conditions v ccuv + v cc supply undervoltage positive going threshold 8 8.9 9.8 v ccuv - v cc supply undervoltage negative going threshold 7.4 8.2 9 v ccuvhy v cc supply undervoltage hysteresis 0.3 0.7 ? v bsuv+ v bs supply undervoltage positive going threshold 8 8.9 9.8 v bsuv- v bs supply undervoltage negative going threshold 7.4 8.2 9 v bsuvhy v bs supply undervoltage hysteresis 0.3 0.7 ? v na i lk high-side floating well offset supply leakage ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 70 120 a i qcc quiescent v cc supply current ? 2 3 ma all inputs are in the off state v oh high level output voltage drop, v bias -v o ? 0.90 1.5 v v ol low level output voltage drop, v o ? 0.40 0.6 v i o = 20 ma i o+ output high short circuit pulsed current 75 200 ? v o =0 v,v in =0 v, pw 10 s i o- output low short circuit pulsed current 150 350 ? ma v o =15 v,v in =5 v, pw 10 s logic ?0? input voltage v ih logic ?1? input voltage 2.5 ? ? logic ?1? input voltage v il logic ?0? input voltage ? ? 0.8 na v in,clamp input voltage clamp (hin, lin, itrip and en) 4.8 5.2 5.65 v i in = 100 a i hin+ input bias current (ho = high) ? 150 200 v in = 0 v i hin- input bias current (ho = low) ? 110 150 v in = 4 v i lin+ input bias current (lo = high) ? 150 200 v in = 0 v i lin- input bias current (lo = low) ? 110 150 a v in = 4 v v rcin,th rcin positive going threshold ? 8 ? v rcin,hy rcin hysteresis ? 3 ? v na i rcin rcin input bias current ? ? 1 a v rcin = 0 v or 15 v r on,rcin rcin low on resistance ? 50 100 ? i = 1.5 ma
auirs2336s www.irf.com ? 2009 international rectifier 8 static electrical char acteristics (continued) symbol definition min typ max units test conditions v it,th+ itrip positive going threshold 0.37 0.46 0.55 v it,th- itrip negative going threshold ? 0.4 ? v it,hys itrip hysteresis ? 0.07 ? v na i itrip+ ?high? itrip input bias current ? 5 20 v in = 4 v i itrip- ?low? itrip input bias current ? ? 1 a v in = 0 v v en,th+ enable positive going threshold ? ? 2.5 v en,th- enable negative going threshold 0.8 ? ? v na i en+ ?high? enable input bias current ? 5 20 v in = 4 v i en- ?low? enable input bias current ? ? 1 a v in = 0 v r on,flt fault low on resistance ? 50 100 ? i = 1.5 ma
auirs2336s www.irf.com ? 2009 international rectifier 9 dynamic electrical characteristics unless otherwise noted, these specifications apply for an operating junction temperature range of -40c tj 125c with bias conditions of v cc = v b = 15 v, v s = v ss = com, t a = 25 o c, and c l = 1000 pf. the dynamic electrical characteristics are measured using the te st definitions shown in figure . symbol definition min typ max units test conditions t on turn-on propagation delay 400 530 750 t off turn-off propagation delay 400 530 750 t r turn-on rise time ? 125 320 t f turn-off fall time ? 50 120 t fil,in input filter time ? (hin, lin, itrip) 200 350 510 v in = 0 v & 5 v t en enable low to output shutdown propagation delay 350 460 650 v in, v en = 0 v or 5 v t filter,en enable input filter time 100 200 ? ns na t fltclr fault clear time rcin: r = 2 m ?, c = 1 nf 1 1.65 2.5 ms v in = 0 v or 5 v v itrip = 0 v t itrip itrip to output shutdown propagation delay 500 750 1200 v itrip = 5 v t bl itrip blanking time ? 400 ? t flt itrip to fault propagation delay 400 600 950 v in = 0 v or 5 v v itrip = 5 v dt deadtime 190 275 420 mdt dt matching ?? ? ? 100 v in = 0 v & 5 v without external deadtime mt delay matching time (t on , t off ) ?? ? ? 50 v in = 0 v & 5 v with external deadtime larger than dt pm pulse width distortion ??? ? ? 100 ns pw input=10 s ? the minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the input filter is exceeded. ?? this parameter applies to all of the channels. pl ease see the application section for more details. ??? pm is defined as pw in - pw out .
auirs2336s www.irf.com ? 2009 international rectifier 10 functional block diagram: auirs2336
auirs2336s www.irf.com ? 2009 international rectifier 11 input/output pin equivalent circuit diagrams: esd diode esd diode v cc itrip or en v ss r pd
auirs2336s www.irf.com ? 2009 international rectifier 12 lead definitions: symbol description vcc low-side supply voltage vss logic ground vb1 high-side gate drive floating supply (phase 1) vb2 high-side gate drive floating supply (phase 2) vb3 high-side gate drive floating supply (phase 3) vs1 high voltage floating supply return (phase 1) vs2 high voltage floating supply return (phase 2) vs3 high voltage floating supply return (phase 3) hin1/n logic inputs for high-side gate driver out puts (phase 1); input is out-of-phase with output hin2/n logic inputs for high-side gate driver out puts (phase 2); input is out-of-phase with output hin3/n logic inputs for high-side gate driver out puts (phase 3); input is out-of-phase with output lin1/n logic inputs for low-side gate driver out puts (phase 1); input is out-of-phase with output lin2/n logic inputs for low-side gate driver out puts (phase 2); input is out-of-phase with output lin3/n logic inputs for low-side gate driver out puts (phase 3); input is out-of-phase with output ho1 high-side driver outputs (phase 1) ho2 high-side driver outputs (phase 2) ho3 high-side driver outputs (phase 3) lo1 low-side driver outputs (phase 1) lo2 low-side driver outputs (phase 2) lo3 low-side driver outputs (phase 3) com low-side gate drive return fault/n indicates over-current, over-temperature (itrip ), or low-side undervoltage lockout has occurred. this pin has negative logic and an open-drain out put. the use of over-current and over- temperature protection requires the use of external components. en logic input to shutdown functionality. logic functi ons when en is high (i.e., positive logic). no effect on fault and not latched. itrip analog input for over-current shutdown. when active, itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive , fault stays active low for an externally set time t fltclr , then automatically becomes i nactive (open-drain high impedance). rcin an external rc network input used to define the fault clear delay (t fltclr ) approximately equal to r*c. when rcin > 8 v, the fault pin goes back into an open-drain high-impedance state.
auirs2336s www.irf.com ? 2009 international rectifier 13 lead assignments soic-28l wide body
auirs2336s www.irf.com ? 2009 international rectifier 14 application information and additional details information regarding the following topics are included as subsections within this section of the datasheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shoot-through protection ? enable input ? fault reporting and programmable fault clear timer ? over-current protection ? over-temperature shutdown protection ? truth table: undervoltage lockout, itrip, and enable ? advanced input filter ? short-pulse / noise rejection ? bootstrap power supply design ? separate logic and power grounds ? tolerant to negative v s transients ? pcb layout tips ? additional documentation igbt/mosfet gate drive the auirs2336s hvics are designed to drive up to six mosf et or igbt power devices. figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the hvic. t he output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the high-side power switch and v lo for the low-side power switch; this parameter is sometimes generically called v out and in this case does not differentiate betw een the high-side or low-side output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + - v s (or com) ho (or lo) v b (or v cc ) i o- figure 1: hvic sourcing current figure 2: hvic sinking current
auirs2336s www.irf.com ? 2009 international rectifier 15 switching and timing relationships the relationship between the input and output signals of the auirs2336s is illust rated below in figures 3. from these figures, we can see the definitions of several timing parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. figure 3: switching time waveforms the following two figures illustrate the timing relationships of some of the functionality of the auirs2336s; this functionality is described in further detail later in this document. during interval a of figure 5, the hv ic has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the hvic has prevented this condition and both the high- and low-side output are held in the off state. interval b of figures 5 and 6 shows that the signal on the itrip input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that hox has returned to the low state; lox is also held low), the voltage on the rcin pin has been pulled to 0 v, and a fault is repor ted by the fault output transitioning to the low state. once the itrip input has returned to the low state, the output will remain disabled and the fault condition reported until the vo ltage on the rcin pin charges up to v rcin,th (see interval c in figure 6); the charging characteristics are dictated by the rc network attached to the rcin pin. during intervals d and e of figure 5, we can see that t he enable (en) pin has been pulled low (as is the case when the driver ic has received a command from the control ic to shutdown); this results in the outputs (hox and lox) being held in the low state until the enable pin is pulled high.
auirs2336s www.irf.com ? 2009 international rectifier 16 fault rcin hox lox en itrip hinx linx a bc d e figure 5: input/output timing diagram for auirs2336s figure 6: detailed view of b & c intervals deadtime this hvic features integrated deadtime protection circuitry. the deadtime for this ics is fixed; other ics within ir?s hvic portfolio feature programmable deadtime for greater des ign flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low- side power switches are held off; this is done to ensure that the power switch being turned off has fully turned o ff before the second power switch is turned on. this minimum deadtime is automatically inserted whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 7 illustrates the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the auirs2336s is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. figure 7 defines the two deadtime parameters (i.e., dt 1 and dt 2 ) of a specific channel; the deadtime matchi ng parameter (mdt) associated with the auirs2336s specifies the maximum difference between dt 1 and dt 2 . the mdt parameter also applies when comparing the dt of one channel of the auirs2336s to that of another.
auirs2336s www.irf.com ? 2009 international rectifier 17 hinx linx 50% 50% 50% 50% dt dt hox lox figure 7: illustration of deadtime matched propagation delays the auirs2336s is designed with propagation delay matching circui try. with this feature, the ic?s response at the output to a signal at the input requires appr oximately the same time duration (i.e., t on , t off ) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (mt). additionally, the propagation delay for each low-side c hannel is matched when compared to the other low-side channels and the propagation delays of t he high-side channels are matched with each other; the mt specification applies as well. the propagation turn-on delay (t on ) of the auirs2336s is matched to the propagation turn-on delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the auirs2336s has been designed to be compatible with 3.3 v and 5 v logic-level signals. it f eatures an integrated 5.2 v z ener clamp on the hin, lin, itrip, and en pins; figure 8 illustrates an input signal, its i nput threshold values, and the logic state of the ic as a result of the input signal. input signal v ih v il input logic level high low low figure 8: hin & lin input thresholds
auirs2336s www.irf.com ? 2009 international rectifier 18 undervoltage lockout protection this ic provides undervoltage lockout protection on both the v cc (logic and low-side circuitry) power supply and the v bs (high-side circuitry) power supply. figur e 9 is used to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/- or v bsuv+/- ) the undervoltage protection is enabled or disabled. upon power-up, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turn-on. additionally, if the v cc voltage decreases below the v ccuv- threshold during operation, the undervo ltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate driv e outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon power-up, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turn-on the high-side gate drive output. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the ic. the uvlo protection ensures that the ic drives the external power devic es only when the gate supply voltage is sufficient to fully enhance the power devices. without this f eature, the gates of the exte rnal power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. figure 9: uvlo protection shoot-through protection the auirs2336s is equipped with shoot-through protection ci rcuitry (also known as cross-conduction prevention circuitry). figure 10 shows how this protection circuitry prevents both t he high- and low-side switches from conducting at the same time. table 1 illustrates the input/output relationship of the devices in the form of a truth table.
auirs2336s www.irf.com ? 2009 international rectifier 19 hin lin ho lo shoot - through protection enabled figure 10: illustration of shoot-through protection circuitry hin lin ho lo 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 table 1: input/output truth table enable input the auirs2336s is equipped with an enable input pin that is used to shutdown or enable the hvic. when the en pin is in the high state the hvic is able to operate nor mally (assuming no other fault conditions). when a condition occurs that should shutdown the hvic, the en pin shoul d see a low logic state. the enable circuitry of the auirs2336s features an input filter; the mi nimum input duration is specified by t filter,en . please refer to the en pin parameters v en,th+ , v en,th- , and i en for the details of its use. table 2 gi ves a summary of this pin?s functionality and figure 11 illustrates the outputs? response to a shutdown command. enable input enable input high outputs enabled * enable input low outputs disabled table 2: enable functionality truth table (*assumes no other fault condition) figure 11: output enable timing waveform
auirs2336s www.irf.com ? 2009 international rectifier 20 fault reporting and programmable fault clear timer the auirs2336s provides an integrated fault reporting output and an adjustable f ault clear timer. there are two situations that would cause the hvic to report a fault via the fault pin. the first is an undervoltage condition of v cc and the second is if the itrip pin recognizes a fault. once the fault condition occurs, the fault pin is internally pulled to v ss . the fault clear timer is activated only if itrip pin re cognizes a fault: in this case the fault output stays in the low state until the fault conditi on has been removed and the fault clear time r expires; once the fault clear timer expires, the voltage on the fault pin will return to v cc . the length of the fault clear time period (t fltclr ) is determined by exponential char ging characteristics of the capacitor where the time constant is set by r rcin and c rcin . in figure 12 where we see that a fault condition has occurred (uvlo or itrip), rcin and fault are pulled to v ss , and once the fault has been removed, the fault clear timer begins. figure 13 shows that r rcin is connected between the v cc and the rcin pin, while c rcin is placed between the rcin and v ss pins. figure 12: rcin and fault pin waveforms figure 13: programming the fault clear timer the design guidelines for this network are shown in table 3. 1 nf c rcin ceramic 0.5 m ? to 2 m ? r rcin >> r on,rcin table 3: design guidelines the length of the fault clear time period can be determined by using the formula below. v c (t) = v f (1-e -t/rc ) t fltclr = -(r rcin c rcin )ln(1-v rcin,th /v cc )
auirs2336s www.irf.com ? 2009 international rectifier 21 over-current protection the auirs2336s is equipped with an itrip input pin. this functionality can be used to detect over-current events in the dc- bus. once the hvic detects an over-current event through the itrip pin, the outputs are shutdown, a fault is reported through the fault pin, and rcin is pulled to v ss . the level of current at which the ove r-current protection is initiated is det ermined by the resistor network (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 14, and the itrip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc- bus and select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the over-current threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc- (r 1 /(r 1 +r 2 )) v cc hin (x3) rcin en itrip v ss fault com lin (x3) lo (x3) ho (x3) v b (x3) v s (x3) r 1 r 2 r 0 i dc- v x figure 14: programming the over-current protection for example, a typical value for resistor r 0 could be 50 m?. the voltage of the itrip pin should not be allowed to exceed 5 v; if necessary, an exte rnal voltage clamp may be used. over-temperature shutdown protection the itrip input of the auirs2336s can also be used to det ect over-temperature events in the system and initiate a shutdown of the hvic (and power switches) at that time. in order to use this functionality, the circuit designer will need to design the resistor network as shown in figure 15 and select the maximum allowable temperature. this network consists of a ther mistor and two standard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node v x . the resistor values should be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the maximum allowable temperature is reached. the volt age of the itrip pin should not be allowed to exceed 5 v. when using both the over-current pr otection and over-temperature protection with the itrip input, or-ing diodes (e.g., dl4148) can be used. this network is shown in figure 16; the or-ing diodes have been labeled d 1 and d 2 .
auirs2336s www.irf.com ? 2009 international rectifier 22 figure 15: programming over-temperature protection figure 16: using over-current protection and over- temperature protection truth table: undervoltage lockout, itrip, and enable table 4 provides the truth table for the auirs 2336s. the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gat e drive outputs have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance state. the second case shows that the uvlo for v bs has been tripped and that the hi gh-side gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new falling transition of hin. the third case show s the normal operation of the hvic. the fourth case illustrates that the itrip trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. in the last case, the hvic has received a command through the en input to shutdown; as a result, the gate drive outputs have been disabled. vcc vbs itrip en rcin fault lo ho uvlo v cc < v ccuv ? ? ? high 0 0 0 uvlo v bs 15 v < v bsuv 0 v 5 v high high impedance lin 0 normal operation 15 v 15 v 0 v 5 v high high impedance lin hin itrip fault 15 v 15 v >v itrip 5 v low 0 0 0 en command 15 v 15 v 0 v 0 v high high impedance 0 0 table 4: uvlo, itrip, en, rcin, & fault truth table advanced input filter the advanced input filter allows an impr ovement in the input/output pulse symme try of the hvic and helps to reject noise spikes and short pulses. this input filter has been applied to the hin, lin, and en inputs. the working principle of the new filter is shown in figures 17 and 18. figure 17 shows a typical input filter and the asymmetr y of the input and output. the upper pair of waveforms (example 1) show an input signal with a duration much longer then t fil,in ; the resulting output is approximately the difference between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the difference between the input signal and t fil,in . figure 18 shows the advanced input f ilter and the symmetry between the i nput and output. the upper pair of waveforms (example 1) show an input signal with a duration much longer then t fil,in ; the resulting output is
auirs2336s www.irf.com ? 2009 international rectifier 23 approximately the same duration as the i nput signal. the lower pair of wavefo rms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately t he same duration as the input signal. figure 17: typical input filter fi gure 18: advanced input filter short-pulse / noise rejection this device?s input filter pr ovides protection against short-pulses (e.g., noise ) on the input lines. if the duration of the input signal is less than t fil,in , the output will not change states. example 1 of figure 19 shows the output in the high state with input positive noise spikes of durations less than t fil,in ; the output does not change states. example 2 of figure 19 shows the output in the low state with input negative noise spikes of durations less than t fil,in ; the output does not change states. exampl e 1 exampl e 2 figure 19: noise rejecting input filters figures 20 and 21 present lab data that illustrates the characte ristics of the input filter s while receiving on and off pulses. the input filter characteristic is shown in figure 20; the left side illustrates the narrow pulse on (short negative pulse) characteristic while the left shows the narrow pulse off (short positive pulse) charac teristic. the x-axis of figure 20 shows the duration of pw in , while the y-axis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the input signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the symmetry improving as the dur ation increases. to ensure pr oper operation of the hvic, it is suggested that the input pulse width for the high-side inputs be 500 ns.
auirs2336s www.irf.com ? 2009 international rectifier 24 the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 21; the careful reader will note the scale of the y-axis. the x-axis of figure 21 shows the duration of pw in , while the y-axis shows the resulting pw out ?pw in duration. this data illustrates the performance and near symmetry of this input filter. narrow pulse off 0 200 400 600 800 1000 0 200 400 600 800 1000 time (ns) time (ns) pw out pw in figure 20: input filter characteristic figure 21: difference between the input pulse and the output pulse
auirs2336s www.irf.com ? 2009 international rectifier 25 bootstrap power supply design for information related to the design of a standard bootst rap power supply (i.e., using an external discrete diode) please refer to design tip 04-4 (dt04-4) entitled ?using m onolithic high voltage gate drivers.? this design tip is available at www.irf.com . separate logic and power grounds the auirs2336s has separate logic and power ground pin (v ss and com respectively) to eliminate some of the noise problems that can occur in power conversion applic ations. current sensing shunts are commonly used in many applications for power inverter protection (i.e., ov er-current protection), and in the case of motor drive applications, for motor current measurements. in these si tuations, it is often benefic ial to separate the logic and power grounds. figure 24 shows a hvic with separate v ss and com pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and over-current circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the com pin is the referenc e point for the low-side gate drive circuitry. the output voltage used to drive the low-side gate is v lo -com; the gate-emitter voltage (v ge ) of the low-side switch is the output voltage of the driver minus the drop across r g,lo . v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc- bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + - v ge2 + - v ge3 + - itrip v x + - figure 24: separate v ss and com pins tolerant to negative v s transients a common problem in today?s high-power switching converte rs is the transient respons e of the switch node?s voltage as the power switches transition on and off quickly while carryi ng a large current. a typical 3-phase inverter circuit is shown in figure 25; here we define the power switches and diodes of the inverter. if the high-side switch (e.g., the igbt q1 in figures 26 and 27) switches off, while the u phase current is flowing to an inductive load, a current commutation occurs from high-side switch (q1) to the diode (d2) in parallel with the low- side switch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage.
auirs2336s www.irf.com ? 2009 international rectifier 26 figure 25: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc- bus figure 26: q1 conducting figure 27: d2 conducting also when the v phase current flows from the inductive load back to the inverter (see figures 28 and 29), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus vo ltage to the negative dc bus voltage. dc+ bus q3 off d3 d4 dc- bus v s2 q4 off i v figure 28: d3 conducting figure 29: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the le vel of the negative dc bus, rather it swings below the level of the negative dc bus . this undershoot voltage is called ?negative v s transient?. the circuit shown in figure 30 depicts one leg of the th ree phase inverter; figures 31 and 32 show a simplified illustration of the commutation of the cu rrent between q1 and d2. the parasitic i nductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e for each igbt. when the high-side switch is on,
auirs2336s www.irf.com ? 2009 international rectifier 27 v s1 is below the dc+ voltage by the voltage drops associat ed with the power switch and the parasitic elements of the circuit. when the high-side power switch turns o ff, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this current flows from the dc- bus (which is connected to the co m pin of the hvic) to the load and a negative voltage between v s1 and the dc- bus is induced (i.e., the com pin of the hvic is at a higher potential than the v s pin). figure 30: parasitic elements figure 31: v s positive figure 32: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3-5 v/ns. the negative v s transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. international rectifier?s hvics have been designed for t he robustness required in many of today?s demanding applications. the auirs2336s has been seen to withstand large negative v s transient conditions on the order of - 50 v for a period of 50 ns. an illustration of the au irs2336s performance can be seen in figure 33. this experiment was conducted using various loads to create this condition; the curve shown in this figure illustrates the successful operation of the auirs2336s under t hese stressful conditions. in case of -v s transients greater then -20 v for a period of time greater than 100 ns, the hvic is des igned to hold the high-side output s in the off state for 4.5 s in order to ensure that the high- and low-side power switches are not on at the same time. figure 33: negative v s transient results for an international rectifier hvic even though the auirs2336s has been shown able to handle these large negative v s transient conditions, it is highly recommended that the circuit des igner always limit the negative v s transients as much as possible by careful pcb layout and component use.
auirs2336s www.irf.com ? 2009 international rectifier 28 pcb layout tips distance between high and low voltage components: it?s strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. ground plane: in order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 34). in order to reduce the em coupling and improve the pow er switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. figure 34: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 f ceramic capacitor is suitable for most applications. this component should be placed as close as possible to t he pins in order to reduce parasitic elements. v cc hin (x3) rcin en itrip v ss fault com lin (x3) lo (x3) ho (x3) v b (x3) v s (x3) c in figure 35: supply capacitor
auirs2336s www.irf.com ? 2009 international rectifier 29 routing and placement : power stage pcb parasitic elements can cont ribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray induc tance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes placing a resistor (5 ? or less) between the v s pin and the switch node (see figure 36), and in some cases using a clamping diode between v ss and v s (see figure 37). see dt04-4 at www.irf.com for more detailed information. figure 36: v s resistor figure 37: v s clamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97-3: managing transients in control ic driven power stages an-1123: bootstrap network analysis: focusing on the integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics
auirs2336s www.irf.com ? 2009 international rectifier 30 parameter temperature trends figures illustrated in this chapter provide information on the experimental performanc e of the auirs2336s hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate the experimental cu rve. the line consists of three data points (one data point at each of the tested temperatures ) that have been connected together to illustrate the understood trend. the individual data points on the typ. curve were det ermined by calculating the averaged experimental value of the param eter (for a given temperature). 500 550 600 650 700 -50 -25 0 25 50 75 100 125 turn-on propagation delay (ns) typ. 500 550 600 650 700 -50 -25 0 25 50 75 100 125 turn-off propagation delay (ns temperature ( o c) max. min. temperature ( o c) ) typ. max. min. figure 38: t on vs. temperature figure 39: t off vs. temperature 200 250 300 350 400 -50 -25 0 25 50 75 100 125 temperature ( o c) dh turn-on propagation delay (ns) typ. max. min. 600 700 800 900 1000 -50-25 0 255075100125 temperature ( o c) itrip to output sd propagation delay (ns) typ. max. min. figure 40: dt vs. temperature figure 41: t itrip vs. temperature
auirs2336s www.irf.com ? 2009 international rectifier 31 400 500 600 700 800 -50 -25 0 25 50 75 100 125 trip to fault propagation delay (ns) typ. temperature ( o c) i max. min. 400 450 500 550 600 -50 -25 0 25 50 75 100 125 temperature ( o c) en low to output sd propagation delay (ns) typ. max. min. figure 42: t flt vs. temperature figure 43: t en vs. temperature 50 100 150 200 250 -50 -25 0 25 50 75 100 125 o turn-on rise time (ns) typ. temperature ( c) max. min. 0 25 50 75 100 -50 -25 0 25 50 75 100 125 o turn-off fall time (ns) temperature ( c) - typ. max. min. figure 44: tr vs. temperature figure 45: tf vs. temperature 0 20 40 60 80 -50 -25 0 25 50 75 100 125 temperature ( o c) pm (ns). typ. max. min. 0 4 8 12 16 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip input bias current (ua) . typ. max. min. figure 46: pm vs. temperature figure 47: i itrip+ vs. temperature
auirs2336s www.irf.com ? 2009 international rectifier 32 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) quiescent v cc supply current (ma) typ. max. min. 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) quiescent v bs supply current (ua) typ. max. min. figure 48: i qcc vs. temperature figure 49: i qbs vs. temperature -0.25 -0.20 -0.15 -0.10 -0.05 -50 -25 0 25 50 75 100 125 o output high short circuit pulsed current (a) temperature ( c) . typ. max min. 0.10 0.20 0.30 0.40 0.50 -50 -25 0 25 50 75 100 125 o output low short circuit current (a) typ. temperature ( c) max min. figure 50: i o+ vs. temperature figure 51: i o- vs. temperature 8.0 8.5 9.0 9.5 10.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply uv+ going threshold (v) typ. max. min. 7.0 7.5 8.0 8.5 9.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply uv- going threshold (v) typ. max min. figure 52: v ccuv+ vs. temperature figure 53: v ccuv- vs. temperature
auirs2336s www.irf.com ? 2009 international rectifier 33 8.0 8.5 9.0 9.5 10.0 -50 -25 0 25 50 75 100 125 v bs supply uv+ going threshold (v) typ. temperature ( o c) max. min. 7.0 7.5 8.0 8.5 9.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply uv- going threshold (v) typ. max. min. figure 54: v bsuv+ vs. temperature figure 55: v bsuv- vs. temperature 400 450 500 550 600 -50 -25 0 25 50 75 100 125 o itrip positive going threshold (mv typ. temperature ( c) max. min. 300 350 400 450 500 -50 -25 0 25 50 75 100 125 o itrip negative going threshold (mv) typ. temperature ( c) max min. figure 56: v it,th+ vs. temperature figure 57: v it,th- vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) rcin low on resistance ( ohm) typ. max. min. 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) fault low on resistance ( ohm) typ. max. min. figure 58: r on,rcin vs. temperature figure 59: r on,flt vs. temperature
auirs2336s www.irf.com ? 2009 international rectifier 34 package details: soic28w
auirs2336s www.irf.com ? 2009 international rectifier 35 package details: tape and reel sow28 carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
auirs2336s www.irf.com ? 2009 international rectifier 36 part marking information auirs2336s ir logo ayww ? part number date code pin 1 identifier lot code (prod mode ? 4 digit spn code) assembly site code per scop 200-002 ? xxxx marking code lead free released non-lead free released ? p ordering information standard pack package type form quantity complete part number tube/bulk 25 auirs2336s base part number soic28w tape and reel 1000 AUIRS2336STR
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