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low power, 8 - /16 - ch annel , 31.25 ksps , 24 - bit, highly integrated sigma - delta adc data sheet ad7173 - 8 features low p ower , 8 - /16 - c h annel, highly i ntegrated multiplexed analog - to - digital converter ( adc ) integration precision analog i nput buffers and reference input buffers 2.5 v precision r eference ( 3.5 ppm/c ) cross p oint m ultiplexer (enable system d iagnostic) 8 full differential or 16 single - ended c hannels clock o scillator gpio and gpo pins with automatic external mux control fast and flexible output rate : 1.25 sp s to 31.25 ksp s channel scan data rate : 6. 21 ksps/channel ( 161 s settling) performance specifications 17.5 noise free bits at 31. 25 k sp s 24 noise free bits at 1.2 5 sp s inl : 3 ppm / fsr 8 5 db r ejection of 50 hz and 60 hz with 50 ms settling operates with either 3.3 v or5 v supply single supply 3.3 v or 5 v avdd 1 , 2 v to 5 v avdd2 , and 2 v to 5 v iovdd optional s plit supply avdd1 and avss 2.5 v or avdd1 and avss 1.65 v current: 1 .4 ma 3 - / 4 - wire serial digital interface (schmitt trigger on sclk) crc error checking spi, qspi, microwire , and dsp compatible package: 40 - lead 6 mm 6 mm lfcsp temperature range: ?40c to +105c applications process control : plc/dcs modules voltage, c urrent, temperature, and p ressure measurement flow meters medical and scientific multichannel instrumentation seismic i nstrumentation chemical a nalysis instrumentation: c hromatography general description f ast settling, highly accurate, low power, 8 - / 16- channel, multiplexed adc for low bandwidth input signals with integrated input buff ers. integrated precision, 2.5 v, low drift (3.5 ppm/c), band gap reference and integrated oscillator. eight flexible setups with configurability for output data rate, digital filter mode, offset/gain error correction, reference selection, buffer enables and more. si nc5 + s inc1 filter maximizes channel scan rate, and s inc3 filter maximizes resolution and enhanced 50 hz/60 hz rejection, with four selectable options to maximize rejection. integrated diagnostic features, including crc, register checksum, temp erature sensor, crosspoint multiplexer, burnout currents, and gpios/gpos. functional block dia gram figure 1. avdd1 avdd analog input buffers reference input buffers avss avss pdsw gpio0 gpio1 gpio2 gpio3 xtal1 xtal2/clkio dgnd ref? ref+ refout avdd2 regcapa ain0/ref2? ain1/ref2+ ain15 ain16 - adc 1.8v ldo crosspoint multiplexer 1.8v ldo int ref temperature sensor iovdd regcapd i/o control serial interface and control digital filter ad7173-8 buffered precision reference xtal and internal clock oscillator circuitry cs sclk din dout/rdy sync error 1 1773-001 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
ad7173-8 data sheet table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptio ns ............................. 9 typical performance characteristics ........................................... 11 noise performance and resolution .............................................. 17 getting started ................................................................................ 18 power supplies ............................................................................ 19 digital communication ............................................................. 19 configuration overview ........................................................... 21 circuit description ......................................................................... 26 analog input ............................................................................... 26 reference options ...................................................................... 28 clock source ............................................................................... 28 digital filters ................................................................................... 30 sinc5 + sinc1 filter ..................................................................... 30 sinc3 filter ................................................................................... 31 single cycle settling ................................................................... 32 enhanced 50 hz and 60 hz rejection filters ......................... 32 operating modes ............................................................................ 35 continuous conversion mode ................................................. 35 continuous read mode ............................................................. 36 single conversion mode ........................................................... 37 standby and power - down modes ............................................ 38 calibration modes ...................................................................... 38 digital interface .............................................................................. 39 checksum protection ................................................................. 39 crc calculation ......................................................................... 40 diagnostics ...................................................................................... 42 general - purpose i/o ................................................................. 42 16- bit/24 - bit conversions ......................................................... 42 serial interface reset (dout_reset) .................................. 42 synchronization .......................................................................... 42 error flags ................................................................................... 43 data_stat ............................................................................... 43 iostrength bit ..................................................................... 43 grounding and layout .................................................................. 44 register summary .......................................................................... 45 register details ............................................................................... 47 communications register ......................................................... 47 status register ............................................................................. 49 adc mode register ................................................................... 50 interface mode register ............................................................ 51 register check ............................................................................ 52 data register ............................................................................... 52 gpio configuration register ................................................... 53 id register ................................................................................... 54 channel register 0 ..................................................................... 54 channel register 1 to channel register 15 ............................ 56 setup configuration register 0 ................................................ 57 setup configuration reg ister 1 to setup configuration register 7 ..................................................................................... 58 filter configuration register 0 ................................................. 59 filter configuration register 1 to filter configuration register 7 ..................................................................................... 60 offset register 0 ......................................................................... 61 offset register 1 to offset register 7 ....................................... 61 gain register 0 ............................................................................ 61 gain register 1 to gain register 7 ........................................... 61 outline dimensions ....................................................................... 62 ordering guide .......................................................................... 62 revision history 10 /13 revision 0: initial ve rs i on rev. 0 | page 2 of 64
data sheet ad7173- 8 specifications a vdd1 = 3 .0 v to 5 .5 v, a vdd2 = 2 v to 5.5 v , iovdd = 2 v t o 5.5 v , a vss = d gnd = 0 v , ref + = 2. 5 v , ref ? = a vss , internal master clock = 2 mhz , t a = t min to t max , unless otherwise noted. table 1 . parameter test conditions/comment s min typ max unit adc speed and performance output data rate (odr) 1.2 5 31 250 sps no missing codes 1 excluding s inc3 filter at 3 1 . 25 ksps 24 bits resolution see table 6 noise see table 6 noise free resolution sinc5 + s inc1 f ilter ( d efault) 31. 25 ksps, ref+ = 5 v 17. 5 bits 2.6 ksps, ref+ = 5 v 18.4 bits 1.2 5 sps, ref+ = 5 v 24 bits accuracy integral nonlinearity (inl) 2.5 v reference 3 7 .5 p pm/ fsr 5 v reference 5 p pm/ fsr offset error 2 internal s hort 40 v offset drift internal s hort 350 nv/c offset drift vs . time 3 4 5 0 nv/ 10 00 h rs gain error 2 25c, avdd1 = 5 v 10 50 ppm/ fsr gain drift vs. temperature 1 0.5 1 ppm/ fsr/ c gain drift vs . time 3 3 ppm/ fsr/ 1000 h r s rejection power supply rejection avdd1 and avdd2 , v in = 1 v 9 0 db common - mode rejection v in = 0.1 v at dc 95 db at 50 hz and 60 hz 1 20 sps odr (post filter) ; 50 hz 1 hz and 60 hz 1 hz 120 db normal mode rejection 1 50 hz 1 hz and 60 hz 1 hz internal clock , 20 sps odr (post filter) 71 90 db external clock , 20 sps odr (post filter) 85 90 db analog inputs differential input voltage range v ref v absolute ain voltage limits 1 buffers disabled avss ? 0.05 avdd1 + 0.05 v buffers enabled avss avdd1 ? 1.1 v analog input current buffers enabled single cycle settling e nabled ( d efault) input current 2 na input current drift 25 pa/c buffers disabled input current 6 a/v input current drift external clock 0. 1 na/v/c internal clock (2.5 % clock) 0.5 na/v/c crosstalk 1 khz input ? 120 db internal reference 100 nf external capacitor on refout to avss output voltage refout with respect to avss 2.5 v initial accuracy 1 t a = 25c 4 ? 0.1 + 0.1 % of v temperature coefficient 0c to +105c 3.5 8 ppm/c ?40c to +105c 3.5 10 ppm/c reference load current, i load i l ? 10 +10 ma rev. 0 | page 3 of 64
ad7173- 8 data sheet parameter test conditions/comment s min typ max unit power supply rejection (line regulation) avdd1 and avdd2 9 0 db load regulation ?v out /?i l 140 ppm/ma voltage noise e n , 0.1 hz to 10 hz 6 .5 v rms voltage noise density e n , 1 khz 215 nv/hz turn - on settling time 100 nf capacitor 60 s long - term stability 3 1000 hours 460 ppm short circuit i sc 25 ma external reference reference input voltage reference input = (ref+) ? (ref?) 1 2.5 avdd1 v absolute reference input voltage limits 1 buffers disabled avss ? 0.05 avdd1 + 0.05 v buffers enabled avss avdd1 v average reference input current buffers disabled 9 a/v buffers enabled 50 na average reference input current drift buffers d isabled external clock 5 na/v/c internal clock 6 na/v/c normal mode rejection 1 see the rejection parameter common - mode rejection 83 db temp erature sensor accuracy after user calibration at 25c 2 c sensitivity 477 v/c burnout currents source/sink current analog input buffers must be enabled 10 a bridge power - down switch r on 24 allowable currents 16 ma general - purpose i/o (gpio 0, g pio 1, gpo 2, gpo 3) with respect to avss input mode leakage current 1 ?10 +10 a floating state output capacitance 5 pf avdd1 ? avss = 5 v output high voltage, v oh 1 i source = 200 a avss + 4 v output low voltage, v ol 1 i sink = 800 a avss + 0.4 v input high voltage, v ih 1 avss + 3 v input low voltage, v il 1 avss + 0.7 v avdd1 ? avss = 3.3 v output high voltage, v oh 1 i source = 200 a avss + 2.7 v output low voltage, v ol 1 i sink = 800 a avss + 0.27 v input high voltage, v ih 1 avss + 2 v input low voltage, v il 1 avss + 0.45 v clock internal clock frequency 2 mhz accuracy ? 2.5 +2.5 % duty cycle 50:50 output low voltage, v ol 0.4 v output high voltage, v oh 0.8 iovdd v crystal frequency 14 16 16.384 mhz start - up time 10 s external clock (clkio) 2 2.048 mhz duty cycle 1 typical duty cycle 50:50 (max imum :min imum ) 30 :70 50:50 70 :30 rev. 0 | page 4 of 64
data sheet ad7173- 8 parameter test conditions/comment s min typ max unit logic inputs input high voltage, v inh 1 2 v iovdd 2.3 v 0.65 iovdd v 2.3 v iovdd 5.5 v 0.7 iovdd v input low voltage, v inl 1 2 v iovdd 2.3 v 0.35 iovdd v 2.3 v iovdd 5.5 v 0.7 v hysteresis 1 iovdd > 2.7 v 0.08 0.25 v iovdd < 2.7 v 0.04 0.2 v leakage currents ? 10 +10 a logic output (dout/ rdy ) output high voltage, v oh 1 iovdd 4.5 v, i source = 1 ma 0.8 iovdd v 2.7 v iovdd < 4.5 v, i source = 500 a 0.8 iovdd v iovdd < 2.7 v, i source = 200 a 0.8 iovdd v output low voltage, v ol 1 iovdd 4.5 v, i sink = 2 ma 0.4 v 2.7 v iovdd < 4.5 v, i sink = 1 ma 0.4 v iovdd < 2.7 v, i sink = 400 a 0.4 v leakage current floating state ? 10 +10 a output capacitance floating state 10 pf system calibration 1 full - scale calibration limit 1.05 fs v zero - scale calibration limit ? 1.05 fs v input span 0.8 fs 2.1 fs v power requirements power supply voltage avdd1 ? avss 3.0 5.5 v avdd2 ? avss 2 5.5 v avss ? dgnd ? 2.75 0 v iovdd ? dgnd 2 5.5 v iovdd ? avss for avss < dgnd 6.35 v power supply currents all outputs unloaded full operating mode avdd1 current avdd1 = 5 v typ ical , 5.5 v m ax imum ain and ref buffers disabled ; external r ef erence 0.23 0.27 ma ain and ref buffers disabled; internal r ef erence 0.42 0.49 ma ain and ref buffers enabled ; external ref erence 2.12 2.71 ma each enabled buffer ed pair: ain+, ain ? and ref+, ref ? 0.945 1.22 ma avdd1 = 3.3 v typ ical , 3.6 v m ax imum 1 ain and ref buffers disabled ; external ref erence 0.16 0.19 ma ain and ref buffers disabled; internal reference 0.34 0.4 ma ain and ref buffers enabled ; external reference 1.9 2.45 ma each enabled buffered pair: ain+, ain? and ref+, ref? 0.87 1.13 ma avdd2 current external r eference 1 1.15 ma internal r eference 1.25 1.4 ma iovdd current external c lock 0.24 0.39 ma internal c lock 0.52 0.7 6 ma external c rystal 0.9 ma standby mode standby (ldo on) reference o ff, total current consumption 25 a reference o n, total current consumption 4 00 a power - down mode full power - down, ldo, ref 2 10 a rev. 0 | page 5 of 64
ad7173- 8 data sheet parameter test conditions/comment s min typ max unit power diss i pation full o perating mode unbuffered, external clock and r eference ; avdd1 = 3 .3 v , avdd2 = 2 v, iovdd = 2 v 3 mw unbuffered, external clock and reference; a ll supplies = 5 v 7.35 mw unbuffered, external clock and reference ; all supplies = 5 .5 v 9.96 mw fully buffered, internal clock and reference (note that refout has no load ) ; avdd1 = 3 .3 v , avdd2 = 2 v, iovdd = 2 v 10.4 mw fully buffered, internal clock and r eference (note that refout has no load); a ll sup pl ies = 5 v 20.4 mw fully buffered, i nter nal clock and r eference (note that refout has no load); a ll supplies = 5 .5 v 28 mw standby mode ref erence o ff, all supplies = 5 v 125 w ref erence o n, all supplies = 5 v 2 mw power - down mode full power - down, all supplies = 5 v 10 w full power - down , all s upplies = 5 .5 v 55 w 1 specification is not production tested but is supported by characterization data at the in itial product release . 2 following a system or internal zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 this specification is noncumulative and includes msl preconditioning effects . 4 this specification includes msl preconditioning effects. rev. 0 | page 6 of 64
data sheet ad7173- 8 timing characteristi cs iovdd = 2 v to 5.5 v, dgnd = 0 v, input logic 0 = 0 v, input logic 1 = iovdd , c load = 2 0 pf , unless otherwise noted . table 2 . parameter limit at t min , t max unit test conditions/comments 1 , 2 sclk pulse width t 3 2 5 ns min sclk high pulse width t 4 2 5 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 15 ns max iovdd = 4.5 v to 5.5 v 4 0 ns max iovdd = 2 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 12 ns max iovdd = 4.5 v to 5.5 v 2 5 ns max iovdd = 2 v to 3.6 v t 5 5 2.5 ns min bus relinquish time after cs inactive edge 20 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high/low write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 8 ns min data valid to sclk edge setup time t 10 8 ns min data valid to sclk edge hold time t 11 5 ns min cs rising edge to sclk edge hold time 1 sample tested during initia l release to ensure compliance. 2 see figure 2 and figure 3 . 3 the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 rdy returns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can b e read again, if required, while rdy is high. it is important to e nsure that subsequent reads do not occur close to the next output update. if the continuous read feature is enabled, the digital word can be read only once. timing diagrams figure read cycle timing diagram figure 3 . write cycle timing diagram t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 1 1773-002 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 1 1773-003 rev. 0 | page 7 of 64
ad7173- 8 data sheet absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating avdd1, avdd2 to avss ? 0.3 v to +6.5 v avdd1 to dgnd ? 0.3 v to +6.5 v iovdd to dgnd ? 0.3 v to +6.5 v iovdd to avss ? 0.3 v to +7.5 v avss to dgnd ? 3.25 v to +0.3 v analog input voltage to avss ? 0.3 v to avdd1 + 0.3 v reference input voltage to avss ? 0.3 v to avdd1 + 0.3 v digital input voltage to dgnd ? 0.3 v to iovdd + 0.3 v digital output voltage to dgnd ? 0.3 v to iovdd + 0.3 v ain [16 :0] or digital input current 10 ma operating temperature range ? 40c to +105c storage temperature range ? 65c to +150c maximum junction temperature 150c lead soldering, reflow temperature 260c esd rating (hbm) 4 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device soldered on a jedec test board for surface - mount packages . the values listed in table 4 are based on simulated data. table 4 . thermal resistance package type ja unit 40 - lead , 6 mm 6 mm lfcsp 1 - l ayer jedec board 114 c/w 4 - l ayer jedec board 54 c/w 4 - l ayer jedec board with 16 thermal v ias 34 c/w esd caution rev. 0 | page 8 of 64
data sheet ad7173- 8 pin configuration an d function descripti ons figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description 1 ain16 ai analog i nput 16. selectable through cross point mux. 2 ain0/ ref 2 ? ai analog i nput 0 (ain0)/ r eference 2 , negative input (ref2 ? ) . an external reference can be applied between ref 2 + and ref 2 ? . ref 2 ? can span from avss to avdd1 ? 1 v. analog i nput 0 is selectable through cross point mux. reference 2 can be selected through the refsel bits in the setup configuration register. 3 ain1/ ref 2 + ai analog i nput 1 (ain0)/ r eference 2 , positive input (ref2+). an external reference can be applied between ref 2 + and ref 2 ? . ref 2 + can span from avdd1 to avss + 1 v . analog i nput 1 is selectable through cross point mux. reference 2 can be selected through the refsel bits in the setup configuration register. 4 ain2 ai analog i nput 2. selectable through cross point mux. 5 ain3 ai analog i nput 3. selectable through cross point mux. 6 refout ao buffered output of internal reference. the output is 2.5 v with respect to avss. 7 regcap a ao analog ldo regulator output. decouple this pin to avss using a 1 f capacitor. 8 av ss p negative analog supply. this supply ranges from 0 v to ?2.75 v and is nominally set to 0 v. 9 av dd1 p analog s upply voltage 1. this voltage ranges from 3.0 v minimum to 5 .5 v max imum with respect to avss. 10 av dd2 p analog supply voltage 2. this voltage ranges from 2 v to avdd1 with respect to avss. 11 pdsw ao power - down switch c onnected to avss. this pin is controlled by the pdsw bit in the gpiocon register. 12 xtal1 a i input 1 for c rystal. 13 xtal2 / clkio ai/ di input 2 for crystal (xtal2)/ clock input or output (clkio). see the clocksel bit settings in the adcmode r egist er ( table 25 ) for more information. 14 dout/ rdy do serial data output (dout) /data ready output ( rdy ) . this pin serves a dual purpose. it functions as a serial data out put pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control registers. the data - word/control word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. when cs is high, the dout/ rdy output is tristated. when cs is low , and a register is not being read, dout/ rdy operate s as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge c an be used as an interrupt to a processor, indicating that val id data is available. 1 ain16 2 ain0/ref2? 3 ain1/ref2+ 4 ain2 5 ain3 6 refout 7 regca p a notes 1. the exposed p ad should be soldered t o a similar p ad on the pcb under the exposed p ad t o confer mechanica l strength and for he a t dissi pa tion. the exposed p ad must be connected t o a vss through this p ad on the pcb. 8 a vss 9 a vdd1 10 a vdd2 23 gpio0 24 gpio1 25 gpo2 26 ain4 27 ain5 28 ain6 29 ain7 30 ain8 22 regcapd 21 dgnd 1 1 pdsw 12 x t al1 13 x t al2/clkio 15 din 17 cs 16 sclk 18 error 19 sync 20 iovdd 14 dout/rd y 33 ain 1 1 34 ain12 35 ain13 36 ain14 37 ain15 38 gpo3 39 ref? 40 ref+ 32 ain10 31 ain9 t o p view (not to scale) ad7173-8 1 1773-004 rev. 0 | page 9 of 64
ad7173- 8 data sheet pin no. mnemonic type 1 description 15 din di serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the register address (ra) bits of the communications register identifying the appropriate register. data is clocked in on the rising edge of sclk. 1 6 sclk di serial clock input. this serial clock input is for data transfers to and from the adc. sclk has a schmitt trigger input, making the interface suitable for opto - isolated applic ations. 17 cs di chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with sclk, din, and dout used to interface with the device. when cs is high, the dout/ rdy output is tristated. 18 error di/o this pin can be used in one of the following three modes: active low error input mode. t his mode sets the adc_error bit in the status register. active low, open - drain error output mode. t he status register error bits are mapped to the error pin. the error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. general - purpose output mode. t he status of the pin is controlled by the err_dat bit in the gpiocon register. the pin is referenced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the gpio 1 and gpio2 pins. the error pin has an active pull - up in this case. 19 sync di s ynchronization i nput . a llows synchronization of the digital filters and analog modulators when using multiple ad7173 - 8 devices. 20 iovdd p digital i/o supply voltage. iovdd voltage ranges from 2 v to 5 v. iovdd is independent of avdd1 and avdd2. for example, iovdd can be operated at 3.3 v when avdd1 or avdd2 equals 5 v, or vice versa. if avss is set to ?2.5 v, the voltage on iovdd must not exceed 3.6 v. 21 dgnd p digital ground. 22 regcap d ao digital ldo regulator output. this pin is for decoupling purposes only. de couple this pin to dgnd using a 1 f capacitor. 23 gpio 0 d i/o general - p urpos e input/o utput. logic input/output on this this pin is referred to the avdd1 and avss supplies. 24 gpio 1 d i/o general - purpose input/output. logic input/output on this this pin is referred to the avdd1 and avss supplies. 25 gp o 2 d o general - purpose o utput. logic output on this this pin is referred to the avdd1 and avss supplies. 2 6 ain 4 ai analog input 4. selectable through cross point mux. 2 7 ain 5 ai analog input 5. selectable through cross point mux. 2 8 ain 6 ai analog input 6. selectable through cross point mux. 2 9 ain 7 ai analog input 7. selectable through cross point mux. 30 ain 8 ai analog input 8 . selectable through cross point mux. 31 ain 9 ai analog input 9 . selectable through cross point mux. 32 ain 10 ai analog input 10 . selectable through cross point mux. 33 ain 11 ai analog input 11 . selectable through cross point mux. 34 ain 12 ai analog input 12 . selectable through cross point mux. 35 ain 13 ai analog input 13 . selectable through cross point mux. 36 ain 14 ai analog input 14 . selectable through cross point mux. 37 ain 15 ai analog input 15 . selectable through cross point mux. 38 gp o 3 do general - purpose output. logic output on this this pin is referred to the avdd1 and avss supplies. 39 ref ? ai reference 1 input negative terminal. ref? can span from avss to avdd1 ? 1 v. reference 1 can be selected through the refsel bits in the setup configuration register. 40 ref+ ai reference 1 input positive terminal. an external reference can be applied betw een ref+ and ref?. ref+ can span from avdd1 to avss + 1 v. reference 1 can be selected through the refsel bits in the setup configuration register. ep p exposed pad. the exposed pad should be soldered to a similar pad on the pcb under the exposed paddle to confer mechanical strength to the package and for heat dissipation. the exposed pad must be connected to avss through this pad on the pcb. 1 ai = analog input, ao = analog o utput , di/o = bidirectional digital input/output, do = digital output, di = digital input, p = power s uppl y . rev. 0 | page 10 of 64
data sheet ad7173- 8 typical performance characteristics a v d d1 = 5 v , a v d d2 = 5 v , i o v d d = 3.3 v , u n le ss o th e r wi s e n o t ed . figure 5. noise ( output data rate = 1.25 sps, analog input buffers disabled) figure 6. noise ( output data rate = 1.25 sps, analog input buffers enabled) figure 7. noise (output data rate = 10 ksps, analog input buffers disabled) figure 8. noise distribution histogram (output data rate = 1.25 sps , analog input buffers disabled)) figure 9. noise distribution histogram (output data rate = 1.25 sps , analog input buffers enabled) figure 10 . noise distribution histogram (output data rate = 10 ksps, analog input buffers disabled)) 8388536 8388537 8388538 8388539 0 100 200 300 400 500 600 700 800 900 1000 adc code sample 1 1773-005 8388548 8388549 8388550 8388551 0 100 200 300 400 500 600 700 800 900 1000 adc code sample 1 1773-006 8388490 8388500 8388510 8388520 8388530 8388540 8388550 8388560 8388570 8388580 0 100 200 300 400 500 600 700 800 900 1000 adc code sample 1 1773-007 0 100 200 300 400 500 600 700 8388536 8388537 8388538 8388539 occurrence adc code 1 1773-008 0 100 200 300 400 500 600 8388548 8388549 8388550 8388551 occurrence adc code 1 1773-009 0 10 20 30 40 50 60 8388499 8388502 8388505 8388508 83885 1 1 8388514 8388517 8388520 8388523 8388526 8388529 8388532 8388535 8388538 8388541 8388544 8388547 8388550 8388553 8388556 8388559 8388562 8388565 8388568 8388571 8388574 occurrence adc code 1 1773-010 rev. 0 | page 11 of 64
ad7173- 8 data sheet figure 11 . noise (output data rate = 10 ksps, analog input buffers enabled) figure 12 . noise (output data rate = 31.25 ksps, analog input buffers disabled) figure 13 . noise (output data rate = 31.25 ksps, analog input buffers enabled) figure 14 . noise distribution histogram (output data rate = 10 ksps, analog input buffers enabled)) figure 15 . noise distribution histogram (output data rate = 31.25 ksps, analog input buffers disabled) figure 16 . noise distribution histogram (output data rate = 31.25 ksps, analog input buffers enabled) 8388500 8388510 8388520 8388530 8388540 8388550 8388560 8388570 8388580 8388590 8388600 8388610 0 100 200 300 400 500 600 700 800 900 1000 adc code sample number 1 1773-0 1 1 8388490 8388500 8388510 8388520 8388530 8388540 8388550 8388560 8388570 8388580 0 100 200 300 400 500 600 700 800 900 1000 adc code sample number 1 1773-012 0 100 200 300 400 500 600 700 800 900 1000 adc code sample number 1 1773-013 8388480 8388500 8388520 8388540 8388560 8388580 8388600 8388620 0 5 10 15 20 25 30 35 40 45 50 8388506 8388510 8388514 8388518 8388522 8388526 8388530 8388534 8388538 8388542 8388546 8388550 8388554 8388558 8388562 8388566 8388570 8388574 8388578 8388582 8388586 8388590 8388594 8388598 occurrence adc code 1 1773-014 0 5 10 15 20 25 30 35 40 45 8388497 8388500 8388503 8388506 8388509 8388512 8388515 8388518 8388521 8388524 8388527 8388530 8388533 8388536 8388539 8388542 8388545 8388548 8388551 8388554 8388557 8388560 8388563 8388566 8388569 8388572 8388575 occurrence adc code 1 1773-015 0 5 10 15 20 25 30 35 40 8388494 8388499 8388504 8388509 8388514 8388519 8388524 8388529 8388534 8388539 8388544 8388549 8388554 8388559 8388564 8388569 8388574 8388579 8388584 8388589 8388594 8388599 8388604 8388609 occurrence adc code 1 1773-016 rev. 0 | page 12 of 64
data sheet ad7173- 8 figure 17 . rms noise vs. common - mode input voltage figure 18 . rms noise vs. master clock frequency ( output data rate = 31.25 ksps, analog input buffers enabled ) figure 19 . adc output fft; 1 khz input tone, ?0.5 dbfs input fft (output data rate = 10 ksps, external reference, external clock, buffers enabled) figure 20 . adc output fft; 1 khz input tone, ?6 dbfs i nput fft (output data rate = 10 ksps, external reference, external clock, buffers enabled) figure 21 . adc output fft; 1 khz input tone, ?0.5 dbfs input fft (output data rate = 31.25 ksps, external reference, external clock, buffers enabled) figure 22 . adc output fft; 1 khz input tone, ?6 dbfs input fft (output data rate = 31.25 ksps, external reference, external clock, buffers enabled) 0 2 4 6 8 10 12 14 0 1 2 3 4 5 rms noise (v) v cm (v) b u f fe r o n , d e v ice 1 b u f fe r o f f , d e v ice 1 b u f fe r o n , d e v ice 2 b u f fe r o f f , d e v ice 2 b u f fe r o n , d e v ice 3 b u f fe r o f f , d e v ice 3 1 1773-017 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 rms noise (v) frequenc y (mhz) 1 1773-018 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 amplitude (db) frequenc y (khz) 1 1773-019 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 amplitude (db) frequenc y (khz) 1 1773-020 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 amplitude (db) frequenc y (khz) 1 1773-021 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 amplitude (db) frequenc y (khz) 1 1773-022 rev. 0 | page 13 of 64
ad7173- 8 data sheet figure 23 . internal reference settling time figure 24 . internal reference settling time (extended) figure 25 . common - mode rejection ratio (10 hz to 70 hz) vs. frequency (20 sps enhanced filter) figure 26 . common - mode rejection ratio vs. frequency (output data rate = 31.25 ksps) figure 27 . power supply rejection ratio vs. frequency 1.0 0.5 0 ?0.5 ?1.0 0.00001 0.1 0.01 0.001 0.0001 error (%) time (seconds) from standby ? reference off from power-down 1 1773-023 0.10 0.05 0 ?0.05 ?0.10 0 10 20 30 40 50 error (%) time (seconds) 1 1773-024 ?140 ?135 ?130 ?125 ?120 ? 1 15 ? 1 10 ?105 ?100 10 20 30 40 50 60 70 rejection (db) frequenc y (hz) u n i t 1 b u ff e r s o f f u n i t 1 b u ff e r s on u n i t 2 b u ff e r s on u n i t 3 b u ff e r s on 1 1773-025 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50k 100k 150k 200k rejection (db) frequenc y (hz) u n i t 1 b u ff e rs of f u n it 1 b u ff e rs on u n it 2 b u ff e rs of f u n it 2 b u ff e rs on u n it 3 b u ff e rs of f u n it 3 b u ff e rs on 1 1773-026 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 1k 10k 100k 1m 10m rejection (db) frequenc y (hz) unit 1 buffers off unit 1 buffers on unit 2 buffers off unit 2 buffers on 1 1773-027 rev. 0 | page 14 of 64
data sheet ad7173- 8 figure 28 . integral nonlinearity (inl) error vs . reference voltage (differential input, external reference) figure 29 . integral nonlinearity (inl) distribution histogram (differential input, v ref = 2.5 v external) figure 30 . integral nonlinearity (inl) distribution histogram (differential input, v ref = 5 v external) figure 31 . integral nonlinearity (inl) error vs . temperature (differential input, v ref = 2.5 v) figure 32 . internal oscillator frequency vs. temperature figure 33 . internal reference voltage vs . temperature 0 1 2 3 4 5 6 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 in l error (ppm) reference vo lt age (v) 1 1773-028 b u f fe r o n , d e v ice 1 b u f fe r o f f , d e v ice 1 b u f fe r o n , d e v ice 2 b u f fe r o f f , d e v ice 2 b u f fe r o n , d e v ice 3 b u f fe r o f f , d e v ice 3 0 5 10 15 20 25 30 1.0 4.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 occurrence in l error (ppm) 1 1773-029 0 5 10 15 20 25 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 occurrence in l error (ppm) 1 1773-030 0 1 2 3 4 5 6 7 8 9 10 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 in l error (ppm) temper a ture (c) 1 1773-031 15.82 15.84 15.86 15.88 15.90 15.92 15.94 15.96 15.98 16.00 16.02 ?40 ?20 0 20 40 60 80 100 frequenc y (hz) temper a ture (c) d e v i c e 1 d e v i c e 2 d e v i c e 3 1 1773-032 2.4990 2.4992 2.4994 2.4996 2.4998 2.5000 2.5002 2.5004 2.5006 2.5008 2.5010 reference vo lt age (v) ?40 ?20 0 20 40 60 80 100 temper a ture (c) d e v i c e 1 d e v i c e 2 d e v i c e 3 1 1773-033 rev. 0 | page 15 of 64
ad7173- 8 data sheet figure 34 . offset error distribution histogram (internal short) figure 35 . offset error drift distribution histogram (internal short) figure 36 . gain error distribution histogram figure 37 . gain error drift distribution histogram figure 38 . current consumption vs . temperature (contin u ous conversion mode, buffers enabled, internal reference, internal clock) figure 39 . current consumption vs . temperature (power - down mode) 0 2 4 6 8 10 12 14 16 occurrence vo lt age (v) ?48 ?46 ?44 ?42 ?40 ?38 ?36 ?34 ?32 ?30 ?28 ?26 ?24 ?22 ?20 ?18 1 1773-034 0 1 2 3 4 5 6 7 250 300 350 400 450 occurrence offset drift (nv/c) 1 1773-035 0 5 10 15 20 25 30 35 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 occurrence gain error (ppm) 1 1773-036 0 1 2 3 4 5 6 7 8 9 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.40 0.38 occurrence gain error drift (ppm/c) 1 1773-037 0 1 2 3 4 5 6 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 current (ma) temper a ture (c) d e v i c e 1 d e v i c e 2 d e v i c e 3 1 1773-038 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 current (a) temper a ture (c) 1 1773-039 d e v i c e 1 d e v i c e 2 d e v i c e 3 rev. 0 | page 16 of 64
data sheet ad7173- 8 noise performance an d resolution table 6 show s the rms noise, peak - to - peak noise, effective resolution , and the noise free (peak - to - peak) resolution of the ad7173 - 8 for various output data rates and filters. the values listed are for the bipolar input range with an external 5 v ref erence. these values are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a s ingle channel. it is important to note that the peak - to - peak resolution is calculated based on the peak - to - peak noise. the peak - to - peak resolution represents the resolution for which there is no code flicker. using the s inc 3 filter at the fastest rate resu lts in the noise being quantization lim ited. this limitation degrades the noise specification at this rate and does not give a result of 24 bits , no missing codes. table 6 . rms noise and peak -to - peak resolution vs . output data rate using sinc5 + sinc1 filter (default) 1 output data rate (sps) sinc5 + sinc1 filter (default) rms noise (v rms) effective resolution (bits) peak - to - peak noise (v rms) peak - to - peak resolution (bits) 31,250 8.0 20.2 67 17.5 5208 4.5 21.1 30 18.3 1007 2.2 22.2 15 19.3 381 1.3 22.9 8.9 20.1 100.5 0.71 23.8 5.1 21 20.01 0.32 24 1.7 22.2 5 0. 15 24 0.75 23.4 1.25 0.07 24 0.32 24 1 selected rates only; 1000 samples. table 7 . rms noise and peak -to - peak resolution vs. output data rate using sinc3 filter 1 output data rate (sps) sinc3 filter rms noise (v rms) effective resolution (bits) peak - to - peak noise (v rms) peak - to - peak resolution (bits) 31,250 210 15.5 1665 12.8 5208 3.6 21.4 28 18.7 1008 1.5 22.7 12 19.9 400.6 1 23.3 6.6 20.5 100.5 0.55 24 3.5 21.4 20.01 0.25 24 1.2 22.4 5 0.11 24 0.56 23.4 1.25 0.07 24 0.27 24 1 selected rates only; 1000 samples. rev. 0 | page 17 of 64
ad7173- 8 getting started the ad7173 - 8 offers the user a fast settling, high resolution, multiplexed adc with high levels of configurability. ? eight fully differential or 16 single - ended analog inputs. ? cross point mux . s elects any analog input combination as a pairing to be converted. the sign als are routed to the input buffers and onto the modulator positive or negative input. ? adc input. selectable as a f ully differential input or as a single - ended i nput . ? per setup configurability . u p to eight different setups can be defined. a separate setup can be mapped to each of the channels. each set up allows the user to configure the following: ? output data rate ? digital filter m ode ? offset /gain e rror correction ? reference source selection (internal/external ) ? analog and reference input buffer e nables ? digital output c oding the ad7173 - 8 includes a precision 2.5 v low drift ( 3.5 ppm/c ) band gap internal reference. this reference can be selected to be used for the adc conversions, reducing the external com - ponent count. when enabled , the internal reference is output to the refout pin and can be used as a low noise biasing voltage for the external circuitry. an example of this is using the refout signal to set the input common mode for an external single - ended to differential amplifier . the ad7173 - 8 includes two separate linear regulator blocks for both the analog and digital circuitry . the analog ldo regulates the avdd2 supply to 1.8 v , supplying the adc core. the user can tie the avdd1 and avdd2 supplies together for easiest connection. if a clean analog supply rail is in the system in the range of 2 v to 5 .5 v (min imum to max imum ) , t he user can also choose to connect this supply rail to the avdd2 input, allowing for lower power dissipation. figure 40 . typical connection diagram dgnd ad7173-8 iovdd cs regcapd avss regcapa avdd2 avdd1 xtal1 39 40 1 37 36 3 2 12 13 14 15 16 17 20 21 22 9 10 7 8 6 8 5 3 1 4 7 2 ref? ref+ 4.7f 0.1f 0.1f vout gnd nc v in 0.1f 4.7f vin 0.1f adr44xbrz iovdd avdd2 0.1f avdd1 0.1f cx1 16mhz cx2 0.1f 1f 0.1f 1f optional external crystal circuitry capacitors clkin optional external clock input ain0/ref2? ain1/ref2+ ain14 ain15 ain16 see analog input section for further details xtal2/clkio dout/rdy din sclk cs dout/rdy din sclk 1 1773-040 rev. 0 | page 18 of 64
data sheet ad7173- 8 the linear regulator for the digital iovdd supply performs a similar function, regulating the input voltage applied at the iovdd pin to 1.8 v for the internal digital filtering. the serial interface signals always operate from the iovdd supply seen at the pin. this means that if 3.3 v is applied to the iovdd pin, the interface logic inputs and outputs operate at this level. the ad7173 - 8 can be used across a wide variety of applications, providi ng high resolution and accuracy. a sample of these scenarios follows: ? fast scanning of analog input channels using the internal mux ? fast scanning of analog input chann els using an external mux ? h igh resolution at lower speeds in either multi channel or adc per channel applications ? single adc per channel; the fast low latency output allows further application specific filtering in an external micro - controller, dsp, or fpga power supplies the ad7173 - 8 can run from either a 3.3 v or 5 v supply voltage. the device has three independent power supply pins: avdd1, avdd2, and iovdd. ? av dd1 and avdd2 are referred to avss . ? av dd2 p owe rs the inter nal regulator supplying the adc . ? av dd1 and av dd2 can be ti ed together for convenience. ? iovdd is refe rred to dgnd. the supply sets the interface logic levels on the spi interface and powers an internal regulator for oper ation of the digital processing . single supply operation ( avss = dgnd ) when the ad7173 - 8 is powered from a single supply that is connected to avdd1 , t he supply can be either 3.3 v or 5 v. in this configuration, avss and dgnd can be shorted together on one single ground plan e. with this setup , an external level shifting circuit is required to use fully differential inputs to shift the common - mode voltage. avdd2 is the input to the internal volt age regulator. c onnect av dd2 to av dd1 for convenience. o therwise , if a separate supply is available in the system , a voltage from 2 v to 5.5 v can be applied . iovdd can range from 2 v to 5.5 v in this uni polar input configuration. split supply operation (avss dgnd ) the ad7173 - 8 device has the ability to operate with avss set to a negative voltage , allowing true bipolar inputs to be applied. this allows for a fully differential input signal centered around 0 v and eliminates the need for an external level shifting circuit. for example, with a 5 v split supp ly , avdd1 = 2.5 v and avss = ? 2.5 v. in this use case , the ad7173 - 8 internally level shift s the signals , allowing the digital output to function between dgnd (nominally 0 v) and iovdd. when using a split supply for avdd1 and avss, the absolute maximum ratings must be considered ( refer to the absolute maximum ratings section). ensure that iovdd is set below 3.6 v to stay with in the absolute maximum rating for the device. digital communicati on the ad7173 - 8 has a 3 - wire or 4 - wire spi interface that is compatible with qspi?, microwire ? , and dsps. the interface operates in spi mode 3 and can be operated with cs tied low. in spi mode 3, sclk idles high, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. figure 41 . spi mode 3 sclk edges drive edge sample edge 1 1773-041 rev. 0 | page 19 of 64
ad7173- 8 data sheet accessing the adc register map the communications register controls access to the full register map of the adc. this register is an 8 - bit write only register. on power - up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the com - munications register. the data written to the communications register determ ines which register is being accessed and if the next operation is a read or write. the register address bits (r a [5:0]) determine the specific register to which the read or write operation applies. when the read or write operation to the selected register is complete, the i nterface returns to its default state, where it expects a write operation to the communications register. in situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with din high returns the adc to its default state by resetting the entire part, including the register contents. alternatively, if cs is being used with the digital interface, returning cs high re sets the digital interface to its default sta te and aborts any current operation. figure 42 and figure 43 illustrate writing to and reading from a register by first writing the 8 - bit command to the communications regist er followed by the data for the addressed register. reading the id register is the recommended method for verifying correct communication with the part. the id register is a read only register and contains the value 0x30dx for the ad7173 - 8 . the communication register and id register details are described i n table 8 and table 9 . figure 42 . writing to a register (8- bit command with register address followed by data of 8, 16, or 24 bits; data length is dependent on the register selected) figure 43 . reading from a register (8- bit comman d with register address followed by data of 8, 16, or 24 bits; data length on dout is dependent on the register selected) table 8 . communications register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w table 9 . id register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x07 id [15:8] id[15:8] 0x30dx 1 r [7:0] id[7:0] 1 x = dont care. din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits of data cmd d at a 1 1773-042 din sclk cs 8-bit command 8 bits, 16 bits, 24 bits, or 32 bits output cmd d at a dout/rd y 1 1773-043 rev. 0 | page 20 of 64
data sheet ad7173- 8 configuration overvi ew after power on - or reset , the ad7173 - 8 default configuration is as follows: ? channel configuration. ch0 is enabled, ain 0 is selected as the positive input, and ain 1 is selected as the negative input . setup 0 is selected . ? setup configuration. the i nput buffers are disabled , and the external reference is selected . ? adc mode. continuous conver sion mode, the internal oscillator , and single cycle settling are enabled . ? interface m ode . crc is disabled , and data + status output is disabled. note that only a few of the register setting options are shown ; this list is just an example . for full register information, see the register details section. figure 44 show s an overview of the suggested flow for changing the adc configuration , divided into the following three blocks: ? channel c onfiguration ( see box a in figure 44) ? s etup c onfiguration ( see box b in figure 44) ? adc m ode and i nterfa ce mode configuration (see box c in figure 44) channel configur ation the ad7173 - 8 has 16 independent channels and eight indepen - dent setups . the user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel , giving the user full flexibility in the channel configuration . this also allow s per channel configuration when using eight differential inputs because each channel can have it s own dedicated setup. channel register s the channel register s are used to select which of the 17 analog input pins (ain0 to ain16) are used as either the positive analog input or the negative analog input for that channel. this register also contains a channel enable/disable bit and the setup selection bits, which are used to pick which of the eight available setups are used for this channel. when the ad7173 - 8 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from channel 0 to channel 15 . if a channel is disabled, it is skipped by the sequencer. details of the channel register for channel 0 are shown in table 10. figure 44 . suggested adc configuration flow table 10 . channel 0 register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x10 ch0 [15:8] ch_en0 setup_sel [2:0] reserved ainpos0[4:3] 0x800 1 rw [7:0] ainpos0[2:0] ainneg0 adc mode and inter f ace mode configur a tion select adc oper a ting mode, clock source, enable crc, d at a + s ta tus, and more setu p configur a tion 8 possible adc setups select fi l ter order, output d at a r a te, and more channe l configur a tion select positive and neg a tive input for each adc channe l select one of 8 setups for adc channe l a b c 1 1773-044 rev. 0 | page 21 of 64
ad7173- 8 data sheet adc setups the ad7173 - 8 has eight inde pendent setups . each setup consists of the following four registers: ? setup c onfiguration r egister ? f ilter c onfiguration r egister ? offset r egister ? gain r egister for example, setup 0 consists of setup configuration register 0, filter con figuration register 0, offset register 0, and gain register 0. figure 45 show s the grouping of these registers the setup is selectable from the channel registers detailed in the channel configuration section. this allows each channel to be assigned to one of 8 separate setups. table 11 t hrough table 14 show the four registers that are associated with setup 0. this structure is repeated fo r setup 1 to setup 7. setup configuration register s the setup configuration registers allow the user to select the output coding of the adc by selecting between bipolar and unipolar. in bipolar mode, the adc accepts negative differential input voltages, and the output coding is offset binary. in unipolar mode, the adc accepts only positive differential voltages, and the coding is straight binary. in either case, the input voltage must be within the avdd1/ avss supply voltages. the user can also select the reference source using this register. f our options are available : an internal 2.5 v reference, an external reference connected between the ref+ and ref ? pins, an external reference connected between ain0/ref2 ? and ain1/ref2+, or avdd1 ? avss. the analog i nput buffers and reference input buffers for the setup can also be enabled using this register. filter configuration register s the filter configuration register select s which digital filter is used at the output of the adc modulator. the order of the filter and the output data rate is selected by setting the bits in this register. for more information, see the digital filters section. figure 45 . adc setup register grouping table 11 . setup configuration 0 register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar 0 ref_buf 0[1:0] ain _buf 0[1:0] 0x10 00 rw [7:0] burnout_en0 reserved ref_sel 0 reserved table 12. filter configuration 0 register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x28 filtcon0 sinc3_map0 reserved enhfilten0 enhfilt0 0x0000 rw order0 odr0 table 13. offset configuration 0 register bit map reg name bits bit23:0 reset rw 0x30 offset0 [23: 0 ] offset0[23:0 ] 0x800000 rw table 14. gain configuration 0 register bit map reg name bits bit23:0 reset rw 0x38 gain0 [23: 0 ] gain0[23:0 ] 0x5xxxx0 rw setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select digital filter type and output data rate ain buffers ref buffers burnout reference source sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 1 1773-045 rev. 0 | page 22 of 64
data sheet ad7173- 8 offset register s the offset register holds the offset calibration coefficient for the adc. the power - on reset value of the offset register is 0x800000. the offset register is a 24 - bit read/write register. the power - on reset value is automatically overwritten if an internal or system zero - scale calibration is initiated by the user or if the offset register is written to by the user. gain reg ister s the gain register is a 24 - bit register that holds the gain calibration coefficient for the adc. the gain registers are read/write registers. these registers are configured at power - on with factory calibrated coefficients. therefore, every device has different default coefficients. the default value is automatically overwritten if a system full - scale calibration is initiated by the user or if the gain register is written to by the user. for more information on calibration, see the operating modes sectio n. adc mode and interface mode configuration the adc mode register an d the interface mode register configure the core peripherals for use by the ad7173 - 8 and the mode for the digital interface. adc mode register the adc mode register is used primarily to set the conversion mode of the adc to either continuous or single conversion. the user can also select the standby and power - down modes , as well as any of the calibration modes. in addition, this register contains the clock source select bits and the internal reference enable bits. the reference select bits are contained in the setup configuration registers (see t he adc setups section for more information). interface mode r egister the interface mode register configure s the digital interface operation. this register allows the user to control data - word length, crc enable, data + status read and continuous read mode. the d etails of b oth register s are shown in table 15 and table 16 . for more information, see the digi tal interface section. table 15 . adc mode register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] ref_en reserved sing_cyc reserved delay 0x2 000 rw [7:0] reserved mode clocksel reserved table 16 . interface mode register bit map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16 rev. 0 | page 23 of 64
ad7173- 8 data sheet understanding configuration flexibility the most straightforward implementation of the ad7173 - 8 is to us e eight differential inputs with adjacent analog input s and run all of them with the same setup, gain correction , and offset correction register. in this case , the user select s the following differential inputs : ain0/ain1, ain2/ain3, ain4/ain5, ain6/ain7, ain8/ain9. ain10/ain11, ain12/ain13, ain14/ain15. in figure 46, the registers shown in black font must be programmed for such a co nfiguration. the registers that are shown in gra y font are redundant in this configuration. programming the gain and offset registers is optional for any use case, as indicated by the dashe d l ines between the register blocks . an alternative way to implement these eight fully differential inputs is by taking advantage of the eight available setups. motivation for doing this includes having is a different speed/noise requirement on some o f the eight differential inputs vs. other inputs, or there may be a specific offset or gain correction for particular channels. figure 47 shows how each of the differential inputs may use a separate setup, allowing full flexibility in the configuration of each channel . figure 46 . eight fully differential inputs, all using a single setup ( setup con 0; filt con 0; gain0; offset0 ) figure 47 . eight fully differential inputs with a s etup p er channel setup config registers channel registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup 0 select digital filter type and output data rate ain buffers ref buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 1 1773-046 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 0x18 ch8 0x19 ch9 0x1a ch10 0x1b ch11 0x1c ch12 0x1d ch13 0x1e ch14 0x1f ch15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15 ain16 setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup select digital filter type and output data rate ain buffers ref buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 1 1773-047 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15 ain16 channel registers 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f rev. 0 | page 24 of 64
data sheet ad7173- 8 figure 48 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. in this random example , seven differential inputs and two single - ende d inputs are required. the single - ended inputs are the ain8/ain16 and ain15/ain16 combination s . the fi rst five differential input pairs ( ain0/ain1, ain2/ain3, ain 4/ain5, ain6/ain7, ain9/ain10) use the same setup : setupcon0. the two single - ended input pairs (ain8/ain16 and ain15/ ain16) are set up as a diagnostics ; therefore, use a separate setup: setupcon1. the final two differential inputs (ain11/ain12 and ain13/ain14) also u se a separate setup: setupcon2. given that three setups are selected for use, the setupcon0, setupcon 1, and setupcon 2 registers are programmed as required , and the filtcon0, filtcon 1, and filtcon 2 registers are also programmed as desired. optiona l gain and offset correction can be employed on a per setup basis by programming the gain0, gain 1, and gain 2 registers and the offset0, offset 1, and offset 2 registers. i n th e example shown in figure 48, the c h 0 to c h 8 registers are used . setting the msb in each of these registers , the ch_en0 to ch_en8 bits enable t he nine combinations via the cross point mu x . when the ad7173 - 8 converts, the sequencer transitions in asce nding sequential order from ch0 to ch1 to ch2 , and then on to ch8 before looping back to ch0 to repeat the sequence. figure 48 . mixed differential and single - ended configuration u sing multiple shared setups setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup select digital filter type and output data rate ain buffers ref buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 1 1773-048 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15 ain16 channel registers 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f rev. 0 | page 25 of 64
ad7173- 8 data sheet circuit description analog input buffered analog input the ad7173 - 8 integrates precision unity gain buffers on the adc inputs. the output of the integrated cross point mux is connected to the adc via these precision buffers. the buffers provide the benefit of giving the user high input impedance and fully drive the internal adc swi tch capacitor sampling network. there is a buffer on both the positive and negative analog inputs to the adc. the input signals of the ain pair that is se lected via control of the cross point mux (buf+, buf ?) pass to the buffer inputs , which drive the adc sampling capacitor circuitry . each analog input buffer has an input voltage range as shown in figure 49. each buffer can operate with an input signal down to avss (analog ground) or up to an input voltage of 1.1 v from the avdd1 supply . fully differential inputs the ain0 to ain16 analog inputs are connected to a cross point m ux . any combination of s ignals can be used to create an analog input pair. this allows the user to select eight fully differential inputs or 16 single - ended inputs. if all signals to the ad7173 - 8 are fully differential , it is recommended that the traces of the inputs be of the same length . the most reliable and efficient way to do this is by u sing adjacent inpu t pins as the differential pair . all analog inputs decoupling capacitors connect to avs s. single - ended inputs the user can also choose to measure 16 different single - ended analog inputs. in this case, each of the analog inputs is converted as being the difference between the single - ended input to be measured and a set analog input common pin. because there is a cr oss point mux , the user can set any of the analog inputs as the common pin. an example of such a scenario is to connect the ain16 pin to avss or to the refout voltage (that is, avss + 2.5 v) and select this input when configuring the cross point mu x . when using the ad7173 - 8 with single - ended inputs, the inl specification is degraded. when the user requires a buffered input in either the fully d ifferential or single - ended case, the user is required to turn on the analog input buffers as a pair. this means that , even where an input pin is connected to avss , the input buffer of this channel is turned on if the other pin making up the differential input is going to be buffere d. figure 49 . analog i nput v oltage r ange with a nalog i nput b uffers enabled avdd1 analog input buffers buf+ buf? on on reference input buffers avss ref? ref+ refout ain x avdd1 avss 1.1v ain y - adc crosspoint multiplexer usable input voltage range: buffers on (avdd1 ? 1.1v) ? (avss) int ref temperature sensor serial interface and control digital filter cs sclk din dout/rdy 1 1773-049 rev. 0 | page 26 of 64
data sheet ad7173- 8 buffer chopping, noise, and input current each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the signal chain. the 1/f noise profile is shown in figure 51. the noise performance of the buffer at certain output data rates can be improved by increasing the chopping rate of the buffer, giving a corresponding increase in input current. this is done by setting the bufchopmax x bit in the setup configuration r e gister of the selected setup. running with single cycle = 0 the output data rate can be maximized when using only a single channel by setting the sing_cyc bit to 0. however, the analog input current changes in magnitude , depending on the output data rate selected. in this condition , the input current increases by approximately 32 for output data rates selected at >2.6 ksps . set the sing_cyc bit to 0 only in this specific use case. figure 52 and figure 53 show rms noise and input current vs. output data rate for various conditions. using external bu ffers the analog input buffers can be disabled. when they are disabled , the input voltage range on the analog input s is avdd1 C avss . the analog input switched capacitor input is then exposed to the user. a suitable external amplifier is required to sufficiently drive and settle the analog input in such case s . the cs1 and cs2 capacitors each have a magnitude in the order of a number of picofarads (pf) . this capacitance is the combination of both the sampling capacitance and the parasitic capacitance. figure 50 . simplfied analog input circuit the average input current to the ad7173 - 8 changes linearly with the differential input vol tage at a rate of 6 a/v. each analog input must be buffered externally, not only to provide the varying input current with differential input amplitude, but also to settle the switched capacitor input to allow accurate sampling. the simplified analog input circuit for this situation is shown in figure 50 . figure 51 . shorted input fft figure 52 . rms noise vs . output data rate (sinc5 + sinc1 filter) figure 53 . typi cal analog input current vs . output data rate ( 2.5 v c ommon m ode ) ain0 ain1 avdd1 avss avss avss avdd1 avss ain14 avdd1 ain16 avdd1 ain15 avdd1 avss ? 1 cs1 cs2 +in ?in ? 2 ? 2 ? 1 11773-050 ?250 ?200 ?150 ?100 ?50 0 0.1 1 10 100 1k 10k amplitude (db) frequenc y (hz) 1 1773-051 0 2 4 6 8 10 12 1 10 100 1k 10k rms noise (v) odr (sps) b u f c h o p m a x = 0 b u f c h o p m a x = 1 1 1773-052 ?6 ?4 ?2 0 2 4 6 8 10 12 14 1 10 100 1k 10k a verage ain current (na) odr (sps) s i n g l e c h a nn e l and s i n g _ c y c = 0 b u f c h o p m a x = 1 s i n g _ c y c = 1 1 1773-053 rev. 0 | page 27 of 64
ad7173-8 data sheet reference options the ad7173 -8 offers the user the option of either supplying an external reference to the ref+ and ref ? pins of the device or allow ing the use of the internal 2.5 v, low noise, low drift reference. select the reference source to be used by the analog input by setting the ref_sel x bits (bits [5:4] ) in the s etup c onfiguration r egisters appropriately. the struc ture of the setup configuration 0 register is shown in table 17. the ad7173 -8 defaults on power - up to use of an external reference . external reference the ad7173 -8 has a fully differential reference input applied through the ref+ and ref ? pins. standard low noise , low drift voltage references , such as the adr445 , adr444 , and adr441 , are recommended for use. apply the external reference to the ad7173 -8 reference pins as shown in figure 54. decouple t he output of any external refere nce is to avss. as shown in figure 54, the adr441 output is decoupled with a 0.1 f cap ac itor at its output for stability purposes. the output is then connected to a 4.7 f ca pacitor , which act s as a reservoir for any dynamic charge required by the adc , and followed by a 0.1 f decoupling capacitor at the ref+ input. this capacitor is placed as close as possible to the ref+ and ref ? pins. the ref ? pin is connected directly to the avss potential. internal reference the ad7173 -8 includes its own low noise, low drift voltage referen ce . on power - up, the internal reference is disabled by default and a register write is required to select it as the reference source for the adc. write to th e ref_en bit (bit 15) in the adc mode register to enable it (see table 18 ). the internal reference has a 2.5 v output and is output on the refout pin after the ref_en bit is set in the adc mode register . d ecouple the internal reference to avss with a 0.1 f capacitor. the refout signal is buffered prior to being output to the pin. the signal can be used externally in the circuit as a common - mode source for external amplifier configurations. clock source the ad7173 -8 requires a master clock of 2 mhz. the ad7173 -8 can use one of the following sources as its sampling clock : ? internal oscillator ? external crystal (use a 16 mhz c rystal, automatically divided internally to set the 2 mhz clock) ? external clock source all output data rates listed in the data sheet relate to a master clock rate of 2 mhz. using a lower clock frequency from, for example , an external source proportionally scale s any listed data rate. to achieve the specified data rates, particularly rates for rejection of 50 hz and 60 hz, a use a 2 mhz clock. the source of the master clo ck is selected by setting the clocksel bits in the adc mode register , as shown in table 25 . the default , on power - up and reset , is to o perat e with the internal oscillator . figure 54 . external reference adr441 connected to ad7173 -8 reference pins table 17 . setup configuration 0 r egister reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved reserved bi_unipolar ref_buf 0[1:0 ] ain_buf 0[1:0 ] 0x1000 rw [7:0] burnout_en reserved ref_sel0 reserved 0 table 18 . adc mode register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adc mode [15:8] int_ ref_en reserved sing_cyc reserved delay 0x 2 000 rw [7:0] reserved mode clocksel reserved 2.5v vref 0.1f 0.1f adr441 ** 3v to 18v 0.1f 4.7f ad7173-8 ref+ ref? * * * * * *all decoupling is to avss. ** any of the adr44x family references can be used. adr441 enables reuse of the 3.3v analog supply needed for avdd1 to power the reference vin. 40 39 1 1773-054 rev. 0 | page 28 of 64
data sheet ad7173- 8 internal oscillator the internal oscillator is used as the adc master clock by default. the clock used for the adc sampling is 2 mhz (this is divided down from a higher frequency in the case of the internal oscillator use) . it is the default clock source for the ad71 73 - 8 and is specified with an accuracy of 2 .5 %. there is an option to allow the internal clock oscillator to be output on the xtal2 /clkio pin . the clock output is driven to the iovdd logic level. use of this option may affect the dc performance of the ad7173 - 8 due to a disturbance that may be introduced by the output driver. the extent to which the per - formance is affected depends on the iovdd voltage supply. higher iovdd voltages create a wi der logic output swing from the driver and may affect performance to a greater extent. this effect may be further exaggerated if the io strength bit ( register 0x0 2, bit 11) is set at higher iovdd levels (see table 26 for more information ). external crystal if higher precision , lower jitter clock sources are required , the ad7173 - 8 has the abil ity to use an external crystal to generate the master clock. for the ad7173 - 8 the required crystal frequency is 16 mhz. internally this is automatically divided to create the 2 mhz needed for sampling the adc input. the crystal is connected to the xtal1 and xtal2/clkio pins. a recommended crystal for use is the fa - 20h : a 16 mh z , 10 ppm , 9 p f crystal from epson - toyocom , which is available in a surface - mounted package. as shown in figure 55, allow two capacitors to be inserted from the traces connecting the crystal to the xtal1 and xtal2/clkio pins. these capacitors enable circuit tuning. connec t these capacitors to the dgnd pin . the value for these capacitors depend s on the length and capacitance of the trace connections between the crystal and the xtal1 and xtal2/clkio pins. th erefore , the values of these capacitors differ depending on the pcb layout and the crystal employed . as a result, empirical testing of the circuit is required. figure 55 . external crystal connections external clock the ad7173 - 8 can a lso use an externally supplied clock. in systems where this is desirable , the external clock is routed to the xtal2/clkio pin. in this configuration , the xtal2/ clkio pin accepts the externally sourced clock and routes it to the modulator. the logic level of this clock input is defined by the voltage applied to the iovdd pin. 12 13 ad7173-8 xtal1 cx1 * *decouple to gnd * cx2 clkio/xtal2 1 1773-055 rev. 0 | page 29 of 64
ad7173- 8 data sheet digital filters the ad7173 - 8 provides the following three flexible filter options to allow optimization of settling time , noise, and rejection : ? sinc5 + s inc1 filter ? sinc3 filter ? enhanced 50 hz and 60 hz rejection filters figure 56 . digital filter block diagram the filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. see the register details section for more information. sinc5 + sinc1 filter the s inc5 + s inc1 filter is targeted at fast switching multiplexed applications and achieves single cycle settling at output data rates of 2.6 k sps and lower. the s inc5 block output is fixed at the maximum rate of 31.25 k sps , and the s inc1 block output data rate can be varied to control the final adc output data rate. figure 57 shows the frequency domain response of the s inc5 + s inc1 filter at a 50 sps output data rate. the s inc5 + s inc1 filter has a slow roll - off over frequency and narrow notches. figure 57 . sinc5 + sinc1 filter response at 50 sps odr the output data rates with the accompanying settling time and rms noise for the s inc5 + s inc1 filter are listed in table 19. table 19 . output data rate (odr) , settling time (t settle ) , and noise using the sinc5 + sinc1 f ilter default output data rate (sps /ch annel ) ; 1 sing_cyc = 1 or with multiple channels enabled o utput data rate (sps) ; 1 sing_cyc = 0 and single channel enabled settling time 1 notch frequency (hz) noise (v rms) noise (v p - p ) 2 effective resolution with 5 v reference (bits) peak - to - peak resolut ion with 5 v reference (bits) 6211 31,250 161 s 31250 8.0 67 20.2 17.5 5181 15,625 193 s 15625 6.9 52 20.4 17.7 4444 10,417 225 s 10417 6.0 40 20.7 17.9 3115 5208 321 s 5208 4.5 30 21.1 18.3 2597 2597 385 s 3890 3.9 27 21.3 18.5 1007 1007 993 s 1156 2.2 15 22.2 19.3 503.8 503.8 1.99 ms 539 1.5 11 22.7 19.9 381 381 2.63 ms 401 1.3 8.9 22.9 20.1 200.3 200.3 4.99 ms 206 0.99 6.6 23.3 20.5 100.5 100.5 9.95 ms 102 0.71 5.1 23.8 21 59.52 59.52 16.8 ms 60 0.57 3.3 24 21.4 49.68 49.68 20.13 ms 50 0.52 3 24 21.4 20.01 20.01 49.98 ms 20 0.32 1.7 24 22.2 16.63 16.63 60.13 ms 16.67 0.3 1.6 24 22.4 10 10 100 ms 10 0.22 1.1 24 22.7 5 5 200 ms 5 0. 15 0.75 24 23.4 2.5 2.5 400 ms 2.5 0.08 0.32 24 24 1.25 1.25 800 ms 1.25 0.07 0.32 24 24 1 the settling time ( t settle ) is rounded to the nearest microsecond (s) . this is reflected in the output data rate and switching rate. switching rate = 1 t set tle . 2 1000 samples . sinc1 sinc5 sinc3 50hz and 60hz rejection filters 1 1773-056 0 ?120 0 150 100 50 filter gain (db) frequency (hz) 11773-057 ?100 ?80 ?60 ?40 ?20 rev. 0 | page 30 of 64
data sheet ad7173-8 sinc3 filter the s inc3 filter achieves the best single - channel noise performance at lower rates and is , therefore , most suitable for single - channel applications. the sinc3 filter always ha s a settling time equal to t settle = 3/ output data rate figure 58 shows the frequency domain filter response for the s inc3 filter. the sinc3 filter has good roll - off over frequency and has wide notches for good notch frequency rejection. f igure 58 . sinc3 filter response the output data rates with the accompanying settling time and rms noise for the s inc3 filter are shown in table 20 . it is possible to fine - tun e the output data rate for the s inc3 filter by setting the sinc3_map x bit in the filter c onfiguration x register . if this bit is set, the mapping of the filter reg ister changes to directly prog ram the decimation rate of the sinc3 filter. all other options are eliminated. the data rate , when on a single channel , can be calculated using the following equation : output data rate = 4:0] filtconx[1 f mod 32 w here: f mod is the modulator rate and is equal to 1 mhz . filtcon x [14:0] is the contents o f the filter configuration register, excluding the msb. for example, an output data rate of 50 sps can be achieved with sinc3_map x enabled by setti ng the filtconx[14:0] bits to a value of 625. table 20 . output data rate (odr), settling time (t settle ), and noise using the sinc3 filter def ault output data r a te (sps/channel); 1 s i ng_c yc = 1 or with m ulti ple ch an nels e nabled output d a ta rate (sps); 1 s i ng_c yc = 0 an d single channel enabled s ettling time 1 notch frequency (hz) noise (v rms) noise (v p - p) effective resolution with 5 v reference (bits) peak - to - peak resolution with 5 v reference (bits) 10417 31,250 96 s 31,250 210 1665 15.5 12.8 5208 15,625 192 s 15,625 27 206 18.5 15.7 3472 10,417 288 s 10,417 7.8 63 20.3 17.5 1736 5208 576 s 5208 3.6 28 21.4 18.7 868 2,604 1.15 ms 2,604 2.4 20 22 19.2 336 1,008 2.98 ms 1,008 1.5 12 22.7 19.9 168 504 5.95 ms 504 1.1 8 23.1 20.4 133.53 400.6 7.49 ms 400.6 1 7.6 23.3 20.5 67.76 200.3 14.99 ms 200.3 0.73 5.1 23.8 21.2 33.5 100.5 29.85 ms 100.5 0.55 3.5 24 21.4 19.99 59.98 50.02 ms 59.98 0.44 2.5 24 21.6 16.67 50 60 ms 50 0.42 2.3 24 21.7 6.67 20.01 149.93 ms 20.01 0.25 1.2 24 22.4 5.56 16.67 179.96 ms 16.67 0.21 1.1 24 22.6 3.33 10 300 ms 10 0.16 0.83 24 22.9 1.67 5 600 ms 5 0. 11 0.56 24 23.4 0.83 2.5 1.2 s ec 2.5 0.08 0.41 24 24 0.42 1.25 2.4 s ec 1.25 0.07 0.27 24 24 1 the settling time (t settle ) is rounded to the nearest microsecond (s) . this settling time is reflected in the output data rate and switching rate. switching rate = 1 t settle . 0 C12 0 0 15 0 10 0 50 filt er g ain (db) freque nc y (hz) 11773-058 C10 0 C8 0 C6 0 C4 0 C2 0 C11 0 C9 0 C7 0 C5 0 C3 0 C1 0 rev. 0 | page 31 of 64
ad7173-8 data sheet single cycle settling by default , t he ad7173 -8 is configure d with the si n g_cyc bit in the adc m ode r egister . this means that only fully settled data is output , thus putting the adc into a single cycle settling mode. this mode achieve s single cycle settling by reducing the output data rate to be equal to the settling time of the adc for the selected output data rate. this bit has no effect with the s inc5 + s inc1 at ou tput data rates of 2.6 k sps and lower or when multiple channels are enabled. figure 59 shows the same step on the analog input but with single cycle settling enabled. a t least a single cycle is required for the output to be fully settled. t he output data rate is equal to the se ttling time of the filter at the selected output data rate. f igure 59 . step input with single cycle settling figure 60 sho ws a step on the analo g input with this mode disabled, one channel enabled an d the sinc3 filter selected. at least three cycles are required after the step change for the output to reach the final settled value. however, the adc can then output a new conversion result at the higher rate of 1/odr. f igure 60 . step input without single cycle settling enhanced 50 hz and 60 hz rejection filters the e nhanced filter s are design ed to provide rejection of 50 hz and 60 hz simultaneously and to allow the user to trade off settling time and rejection. these filters can operate up to 27.27 sps or can reject up to 90 db of 50 hz 1 hz and 60 hz 1 hz inter - ference . these filters are realized by post filter ing the ou tput of the s inc5 + s inc1 filter. for this reason, the s inc5 + s inc1 filter must be selected when using the enhanced filters. table 21 shows the output data rates with the accompanying settling time, rejection , and rms noise. figure 61 to figure 68 show the frequency domain plots of the responses from the enhanced filters. table 21 . enhanced filter output data rate (odr) , noise , settling time (t settle ) , and rejection using the enhanced filters output data rate (sps) settling time (ms) simultaneous rejection of 50 hz 1 hz and 60 hz 1 hz (db) 1 noise (v rms) noise (v p -p) effective resolution (bits) peak - to - peak resolution (bits) reference 27.27 36.67 47 0.45 3.6 24.4 21.4 see figure 61 and figure 64 25 40.0 62 0.44 3.6 24.4 21.4 see figure 62 and figure 65 20 50.0 85 0.41 3.0 24.5 21.7 see figure 63 and figure 66 16.6 7 60.0 90 0. 41 3.0 24.5 21.7 see figure 67 and figure 68 1 master clock = 2 mhz. t settle analog input fully settled adc output 1 1773-059 1/odr analog input fully settled adc output 1 1773-060 rev. 0 | page 32 of 64
data sheet ad7173- 8 50 hz and 60 hz rejection filter frequency domain plots figure 61 . 27.27 sps odr, 36.67 ms settling time figure 62 . 25 sps odr, 40 ms settling time figure 63 . 20 sps odr, 50 ms settling time figure 64 . 27.27 sps odr, 36.67 ms settling time figure 65 . 25 sps odr, 40 ms settling time figure 66 . 20 sps odr, 50 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1773-061 0 ?100 0 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 600 100 200 300 400 500 1 1773-062 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1773-063 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1773-064 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1773-065 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1773-066 rev. 0 | page 33 of 64
ad7173- 8 data sheet figure 67 . 16.667 sps odr, 60 ms settling time figure 68 . 16.667 sps odr, 60 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1773-067 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1773-068 rev. 0 | page 34 of 64
data sheet ad7173- 8 operating modes continuous conversio n mode continuous conversion (see figure 69) is the default power - up mode. the ad7173 - 8 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is complete. to read a conversio n, the user writes to the commu nications register, indicating that the next operation is a read of the data register. when the data - word has been read from the data register, dout/ rdy goes high. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next conversion. when several channels are enabled, the adc automatically sequences through the enabled channels, performing one conversion on each channel. when all channels are converted, the sequence starts again with the first channel. the channels are converted , in or der , from lowest enabled channel to highest enabled channel. the data register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is available. the user must then read the conversio n result while the adc converts the next enabled channel ; otherwise, the new conversion result is lost. if the data_stat bit in the interface mode register is set to 1, the contents of the status register , along with the conversion data, are output each ti me the data register is read. the status register indicates the channel to which the conversion corresponds. figure 69 . continuous conversion mode din sclk dout/rdy cs 0x44 0x44 data data 1 1773-069 rev. 0 | page 35 of 64
ad7173- 8 data sheet continuous read mode in continuous read mode (see figure 70) , it is not required that the communications r egister be written to before the adc data is read. instead, apply the required number of sclks after dout/ rdy goes low to indicate the end of a conversion. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode, the data can be read only once. the user must also ensure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the ad7173 - 8 to read the word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. t o use continuous r ead mode , t he adc must be configured for continuous conversion mode. to enable continuous read mode , set the cont read bit in the interface mode register. when this bit is set, the only serial interface operations possible are reads from the data register. to exit con - tinuous read mode , issue a dummy read of the adc data register command (0x44) while rdy is low. alternatively , apply a software reset , that is, 64 sclks with cs = 0 and din = 1 . this reset s the adc and all register contents. these are the only commands that the interface recognizes after it is placed in continuous read mode. hold din low in continuous read mode until an instruction is to be written to the device. if multiple adc channels are enabled, each channel is output in turn, with the status bits being appended to the data if the data_stat bit is set in the interface mode register. the status register indicates the channel to which the conversion corresponds. figure 70 . continuous read mode din sclk dout/rdy cs 0x02 data data data 0x0080 11773-070 rev. 0 | page 36 of 64
data sheet ad7173- 8 single conversion mode in single conversion mode (see figure 71) , the ad7173 - 8 performs a single conversion and is placed in standby mode after the conversion is complete. dout/ rdy goes low to indicate the completion of a conversion . after the data - word is read from the data register, dout/ rdy goes high. the data register can be read several times, if required, even when dout/ rdy is high. if several channels are enabled, the adc automatically sequences through the enabled channels and performs a conversion on each channel . when a conversion is started, dout/ rdy goes high and remains high until a valid conversion is available and cs is low. as soon as the conversion is available, dout/ rdy goes low. the adc then selects the next channel and begins a conversion. the user must read the present conv ersion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, the period in which to read the conversion is limited. after the adc performs a single conversion on each of the selec ted channels, it returns to standby mode. if the data_stat bit in the interface mode register is set to 1, the contents of the status register , along with the conversion, are output each time the data register is read . the four lsbs of the status register indicate the channel to which the conversion corresponds . figure 71 . single conversion mode din sclk dout/rdy cs 0x01 0x44 data 0x2010 11773-071 rev. 0 | page 37 of 64
ad7173- 8 data sheet standby and power - down modes in standby mode, most blocks are powered down . the ldos remain active s uch that the registers maintain their contents. the internal reference remains active , if enabled ; and the crystal oscillator remains active , if selected. to power down the reference in standby mode, set the ref_en bit in the adc mode reg is ter to 0 . to power down the clock in standby mode , set the clocksel bits in the adc mode register to 00 ( internal oscillator ) . in power - down mode, all blocks are powered down, including the ldos. all registers lose their contents , and the gpio outputs are placed in tristate. to prevent accidental entry to power - down mode, the adc must first be placed into standby mode. exiting power - down mode requires 64 sclks with cs = 0 and din = 1, that is, a serial interf ace reset. a delay of 500 s is recommended before issuing a subsequent serial interface comman d to allow the ldo to power up. calibration modes the ad7173 - 8 provides three calibration modes that can be used to eliminate the offset and gain errors on a per setup basis : ? internal zero - scale calibration mode ? system zero - scale calibration mode ? system full - scale calibration mode only one channel can be active duri ng calibration. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the default value of the offset register is 0x800000 , and the nominal value of the gain register is 0 x555555. the calibration range of the adc gain is from 0.4 v ref to 1.05 v ref . the following equations show the calculations that are used . in unipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: 2 0x400000 ) 0x800000 ( 2 75 . 0 23 ? ? ? ? ? ? ? ? = gain offset v v data ref in in ipa e te iea eatinsip tat is nt tain int aunt te dc ain e an ffset e is as fs: 0x00000 0x400000 0x00000 0 + ? ? ? ? ? ? ? ? = gain offset v v data ref in t stat a aiatin ite te eeant aue t te mode its in te dc e eiste te dot rd pin an te rd it in te status eiste i en te aiatin initiates en te aiatin is pete te ntents f te espnin ffset ain eiste ae upate te rd it in te status eiste is set te dot rd pin etuns if cs is an te d1 eets t stan e duin an intena ffset aiatin te seete psitie ana input pin is isnnete an t uat inputs ae nnete intena t te seete neatie ana input pin f tis easn it is neessa t ensue tat te tae n te seete neatie ana input pin es nt exee te ae iits an is fee f exessie nise an intefeene sste aiatins ee expet te sste e sae ffset an sste fu sae ain taes t e appie t te dc pin s efe initiatin te aiatin es s a esut es extena t te dc ae ee f an peatina pint f ie teat a aiatin ie ante dc nesin n ffset aiatin if euie ust aas e pefe efe a fu s ae aiatin set te sste sftae t nit te rd it in te status eiste te dot rd pin t eteine te en f a aiatin ia a pin seuene an inteupt ien utine ai atins euie a tie tat is eua t te settin tie f te seete fite an te utput ata ate t e pete n intena ffset aiatin sste e sae aiatin an sste fu sae aiatin an e pefe at an utput ata ate sin e utput ata ates esuts in ette aiatin aua an is auate f a utput ata ates ne aiatin is euie f a ien anne if te efeene sue f tat anne is ane te ffset e is tpia 4 0 v an an ffset aiatin eues te ffset e t te e f te nise te ain e is fat aiate at aient tepeatue fin tis aiatin te ain e is tpia 0001 te d1 pies te use it aess t te n ip aiatin eistes ain te ipess t ea te aiatin effiients f te eie an t ite its n aiatin effiients ea ite f te ffset an ain eistes an e pefe at an tie ex ept uin an intena sef aiatin rev. 0 | page 38 of 64
data sheet ad7173- 8 digital interface t he programmable functions of the ad7173 - 8 are via the spi serial interface. the serial interface of the ad7173 - 8 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on - chip registers , and dout/ rdy is used to access data from the on - chip regi sters. sclk is the serial clock input for the device, and all data transfers (either on din or on dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin also functions as a data - ready signal, with t he line going low if cs is low when a new data - word is available in the data register. the pin is reset high when a read operation from the data register is complete. the dout/ rdy pin also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. take care to avoid reading from the data register when dout/ rdy is about to go low. the best method to ensure that no data read occurs is to always monitor the dout/ rdy line; start reading the data register as soon as dout/ rdy goes low ; and ensure a sufficient sclk rate , such that the read is completed before the next conversion result . cs is used to select a device. it can be used to decode the ad7173 - 8 in systems where several components are connect ed to the serial bus. figure 2 and figure 3 show timing diagrams for interfacing to the ad7173 - 8 using cs to decode the part. figure 2 shows the timing for a read operation from the ad7173 - 8 , and figure 3 shows the timing for a write operation to the ad7173 - 8 . it is possible to read from the data register several times , even though the dout/ rdy line returns high after the first read operation. however, take care to ensure that the read operations are completed before the next output update occurs. in continuous read mode, the data register ca n be read only once. the serial interface can operate in 3 - wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7173 - 8 . the end of the conversion can also be monitored using the rdy bit in the status register . the serial interface can be reset by writing 64 sclks with cs = 0 and din = 1. a r eset returns the interface to the state in which it expects a write to the communications register. this operation resets the contents of all registers to their power - on values. following a reset, allow a period of 500 s before addressing the serial interface. c hecksum protection the ad7173 - 8 has a checksum mode that can be used to improve interface robustness. using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. if an error occurs during a register write, the crc_error bit is set in the status register. however, to ensure that the register write was successful , it is important to read back the register and verify the checksum. for crc che cksum calculations during a write operation, the following polynomial is always used : x 8 + x 2 + x + 1 during read operations, the user can select between this polynomial and a similar xor function. the xor function requires less time to process on the host microcontroller than the polynomial - based checksum . the crc _ en bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple xor check. the checksum is a ppended to the end of each read and write transaction. the checksum calculation for the write transaction is calculated using the 8 - bit command word and the 8 - to 24 - bit data. for a read transaction , the checksum is calculated using the command word and the 8 - to 32 - bit data output. figure 72 and figure 73 show spi write and read transaction s, respectively. figure 72 . spi write transaction with crc figure 73 . spi read transaction with crc if checksum protection is enabled when continuous read mode is active , there is an implied read data command of 0x44 before every data transmission that must be accounted for when calculating the checksum value. this ensures a non zero checksum value even i f the adc data equals 0x000000. 8-bit command 8-bit crc u p t o 24-bit input cmd data crc cs din sclk 1 1773-072 8-bit command 8-bit crc up t o 32-bit output cmd data crc cs din sclk dout/ rd y 1 1337-073 rev. 0 | page 39 of 64
ad7173- 8 data sheet crc calculation polynomial the checksum , which is eight bits wide , is generated using the following polynomial : x 8 + x 2 + x + 1 to generate the checksum , the data is left shifted by eight bits to create a number ending in eight logic 0s. the polynomial is aligned s uch that its msb is adjacent to the leftmost logic 1 of the data . an exclusive or (xor) function is applied to the data to produce a new , shorter number. the polynomial is again aligned so that its msb is adjacent to the left most logic 1 of the new result , and the procedure is repeated. this process is repeated until the original data is reduced to a value less than the polynomi al. this is the 8 - bit checksum. exam ple of a polynomial crc calculation 24- bit word: 0x654321 (eight command bits and 16 - bit data) an example of generating the 8 - bit checksum using the polynomial based checksum is as follows: initial value 011001010100001100100001 01100101010000110010000100000000 left shifted eight bits x 8 + x 2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 xor result 100000111 polynomial 100011000110010000100000000 xor result 100000111 polynomial 11111110010000100000000 xor result 100000111 polynomial value 1111101110000100000000 xor result 100000111 polynomial value 111100000000100000000 xor result 100000111 polynomial value 11100111000100000000 xor result 100000111 polynomial value 1100100100100000000 xor result 100000111 polynomial value 100101010100000000 xor result 100000111 polynomial value 101101100000000 xor result 100000111 polynomial value 1101011000000 xor result 100000111 polynomial value 101010110000 x or result 100000111 polynomial value 1010001000 xor result 100000111 polynomial value 10000110 checksum = 0x86. rev. 0 | page 40 of 64
data sheet ad7173- 8 xor calculation the checksum, which is 8 - bits wide, is generated by splitting the data into bytes and then performing an xor of the bytes. example of an xor calculation 24 - bit word: 0x654321 (eight command bits and 16 - bit data) using the previous example, divide into three bytes : 0x65, 0x43, and 0x21 01100101 0 x 65 01000011 0x43 00100110 xor result 00100001 0x21 00000111 crc rev. 0 | page 41 of 64
ad7173- 8 data sheet diagnostics the ad7173 - 8 has a number of features that can be used for diagnostic purposes in safety conscious applications as well as to increase functionality and improve usefulness in a number of other applications. general - purpose i/o the ad7173 - 8 has two general - purpose digital input/ output pi ns (gpio0, gpio1) and two general - purpose digital output pins ( gpo2, gpo3 ) . as the naming convention suggests , the gpio0 and gpio1 pins can be configured as inputs or outputs, but gpo2 and gpo3 are outputs only. the gpio and gpo pins are enabled using the following bits in the gpiocon register: ip_en0 , ip_en1 ( or op_en0 , op_en1 ) for gpio0 and gpio1 , and op_en2_3 for gpo2 and gpo3 . when the gpio0 or gpio1 pin is enabled as an input, the logic level at the pin is contained in the gp_data0 or gp_data1 bit, respectively. when the gpio0 , gpio1, gp o2, or gp o3 pin is enabled as an output, the gp_data0, gp_data1, gp_data2, or gp_data3 bit, respecti vely, determines the logic level output at the pin. the logic levels for these pins are referenced to avdd1 and avss; therefore, outputs have an amplitude of either 5 v or 3.3 v depending on the avdd1 ? avss voltage. if an external mux is used to increase the channel count, the mux logic pins can be controlled using the ad7173 - 8 gpio and gpo pins. when the mux_io bit is set in the gpiocon register (address 0x06, bit 12), th e timing of the gpio pins is controlled by the adc; therefore, the channel change is synchronized with the adc, eliminating any need for external synchronization. the error pin can also be used as a general - purpose output if the err_en b its in the gpiocon register are set to 11. in this configuration, the err_dat bit in the gpiocon register determines the logic level output at the error pin. the logic level for the pin is referenced to iovdd and dgnd, and the error pin has an active pull - up. 16- bit /24 - bit conversions by default, the ad7173 - 8 generates 24 - bit conversions. however, the width of the conversions can be reduced to 16 bit s . setting bit wl16 in the interface mode register to 1 rounds all data conversions to 16 bits. clearing this bit sets the width of the data conversions to 24 bit s. serial interface res et (dout_reset) the serial interface is reset when each read operation i s complete. the instant at which the serial interface is reset is programmable. by default, the serial interface is reset after a short period of time following the last sclk rising edge, the sclk edge on which the lsb is read by the processor. by setting the dout_reset bit to 1 in the interface mode register , the instant at which the interface is reset is controlled by the cs rising edge. in this case, the dout/ rdy pin continues to output the lsb of the register being r ead until cs is taken high. only on the cs rising edge is the interface reset. this configuration is useful if the cs signal is used to frame all read operations. if cs is not used to frame all read operation s, dout_reset must be set to 0 so that the interface is reset following the last sclk edge in the read operation. synchronization normal synchroni z ation when the sync_en bit i n the gp iocon register is set to 1 , the sync pin functions as a synchronization pin. the sync input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . this pin must be low for at least one master clock cycle to ensure that synchronization occurs. if multiple channels are enabled, the sequencer is reset to the first enabled channel. if multiple ad7173 - 8 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. this is normally done after each ad7173 - 8 has performed its own calibration or has calibration coefficients loaded into its calibration registers. a falling edge on the sync pin resets the digital filter and the analog modulator and places the ad7173 - 8 into a consistent known state. while the sync pin is low, the ad7173 - 8 is maintained in this state. on the sync rising edge, the modulator and filter are taken out of this reset state , and on the next master clock edge, the part starts to gather input samples again. t he part is taken out of reset on the master clock falling edge following the sync low - to - high transition. therefore, when multiple devices are being synchronized, take the sync pin high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle betw een the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. the sync pin can also be used as a start conversion command. in this mode, the rising edge of sync starts a conversion, and the falling edge of rdy indicates when the conversion is complete. the settling time of the filter must be allowed for each data register update. rev. 0 | page 42 of 64
data sheet ad7173- 8 alternate synchroni z ation setting bit alt_sync in the interface mode register to 1 enables an alternate synchronization scheme . t he sync_en bit in the gp iocon register must be set to 1 to enable this alternate scheme. in this mode, the sync pin operates as a start conversion com - mand when several channels of the ad7173 - 8 are enabled. when sync is taken low, the adc completes the conversion on the current channel, selects the next channel in the s equence , and then waits until sync is taken high to commence the conversion. the rdy pin goes low when the conversion is complete on the current channel , and the data register is updated with the corresponding conversio n. therefore, the sync command does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. th is mode can be used only when several channels are enabled. it is not recommended to use this mode when a single channel is enabled. error flags the status register contains three error bits adc_error, crc_error, and reg_error that flag errors with the adc conversion, errors with the crc check, and errors due to changes in the registers, respectively. in addition, the error pin can indicate that an error has occurred. adc_ err or the adc_ error bit in the status register flags any errors that occur during the conversion process. the flag is set when an over - range or underrange occurs at the output of the adc . w hen an underrange or overrange occurs, t he adc also outputs all 0s or all 1s , respectively . this flag is reset only when the underrange or overrange is removed. it is not reset by a read of the data register. crc_error if the crc value that accompanies a write operation does not correspond with the information sent, the crc_error flag is set. the flag is reset as soon as the statu s register is explici tly read. reg_error this flag is used i n conjunction with the reg_ch ec k bit in the interface mode register. when the reg_ch ec k bit is set, the ad7173 - 8 monitors the values in the on - chip registers. if a bit changes, the reg_error bit is set. therefore, for writes to the on - chip regis ters, ensure that reg_ch ec k is set to 0. when the registers have been updated, t he ref_chk bit can be set to 1 . the ad7173 - 8 calculates a check sum o f the on - chip registers. if one of the register values has changed , the reg_error bit is set. if an error is flagged, the reg_ch ec k bit must be set to 0 to clear the reg_error bit in the status register. the register check function does not monitor the data register, status register , or interface mode register. error pin t he error pin functions as a n error input/output pin or a general - purpose output pin. the err_en bits in the gp iocon register determine the function of the pin. when the err_en bits are set to 1 0, the pin functions as an open - drain error output pin. the three error bits in the status register ( adc_ error, crc_error , and reg_error) are or ed, inverted , and mapped to the error pin. therefore, the error pin indicates that an error has occurred. t o identify the error source , read t he status register . when err_en bits are set to 0 1 , the error pin functions as an error input pin. the error pin of another component can be connected to the ad7173 - 8 error pin so that the ad7173 - 8 indicates when an error occurs on either itself or the external component. the value on the error pin is inverted and or ed with the errors from the adc conversion , and the result is indicate d via the adc_ error bit in the status register. the value o f the error pin is reflected in the err _ dat bit in the status register. the error pin is disabled when the err_en bits are set to 0 0 . when the err_en1 bits are set to 1 1, the error pin operates as a general - purpose output. d ata_s tat the contents of the status register can be appended to each conversion on the ad7173 - 8 . this is a useful function if several channels are enabled. each time a conversion is output, the contents of the status register are appended. the four lsbs of the status register indicate to which channel the conversion corresponds. in addition, the user can determine if any errors are being flagged by the error bits . io s treng th bit the serial interface can operate with a power supply as low as 2 v. at higher speeds ( from 10 mhz to 15 mhz upw ard ) , the dout/ rdy pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board . the io strength bit in the interface mode register increases the drive strength of the dout/ rdy pin. it is recommended that this bit be kept to it s default value unless a high frequency spi sclk (that is, ~15 mhz upward) is being used . rev. 0 | page 43 of 64
ad7173- 8 data sheet grounding and layout the analog inputs and reference inputs are differential and , therefore, most of the voltages in the analog modulator are common - mode voltages. the high common - mode rejection of the part removes common - mode noise on these inputs. the analog and digital supplies to the ad7173 - 8 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. the digital filter also removes noise from the analog and reference inputs , provided that these nois e sources do not saturate the analog modulator. as a result, the ad7173 - 8 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the ad7173 - 8 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. the printed circuit board (pcb) that houses the adc must be designed so that the analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it results in the best shielding. in any layout, the user must keep in mind the flow of cur rents in the system, ensuring that the paths for all return currents are as close as possible to the p aths the currents took to reach their destinations . avoid running digital lines under the device because this couples noise onto the die and allow s the an alog ground plane to run under the ad7173 - 8 to prevent noise coupling. the power supply lines to the ad7173 - 8 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this reduces the effects of feed through on the board. a microstrip technique is by far the best but is n ot always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs. the ad7173 - 8 has three power supply pins: av dd1, av dd2, and iovdd. the avdd1 and avdd2 pins are referenced to avss, and the iovdd pin is referenced to dgnd. decouple avdd1 and avdd2 with a 10 f tantalum capacit or in parallel with a 0.1 f capacitor to avss on each pin. place t he 0.1 f capacitor as near as possible to the device on each supply, ideally right up against the device. decouple iovdd with a 10 f tantalum capacitor , in parallel w ith a 0.1 f capacito r to dgnd. decouple a ll analog inputs to avss. if an external reference is us ed, decouple the ref+ and ref ? pins to avss. the ad7173 - 8 also has two on - board ldo regulators one that regulates the avdd2 supply and one that regulates the iovdd supply. for t he regcapa pin , it is recommended that 1 f and 0.1 f capacitor s to avss be used. similarly, for the regcapd pin , it is recommended that 1 f and 0.1 f capacitor s to dgnd be used . if using the ad7173 - 8 for split supply operation , a separate plane must be used for avss. as an example, the e va l - ad7173 - 8 sdz c ustomer evaluation board uses a 4 - layer pcb , with the largest central section of l ayer 3 used as the avss plane. figure 74 shows the pcb layout of this layer. figure 74 . eval - ad7173 - 8sdz , pcb laye r 3 1 1773-074 rev. 0 | page 44 of 64
data sheet ad7173- 8 register summary table 22. register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w 0x00 status [7:0] rdy adc_error crc_error reg_error channel 0x80 r 0x01 adcmode [15:8] ref_en reserved sing_cyc reserved delay 0x2000 rw [7:0] reserved mode clocksel reserved 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16 0x03 regcheck [23:16] register_check[23:16] 0x000000 r [15:8] register_check[15:8] [7:0] register_check[7:0] 0x04 data [23: 0 ] data[23: 0 ] 0x000000 r 0x06 gpiocon [15:8] reserved pdsw op_en2_3 mux_io sync_en err_en err_dat 0x0800 rw [7:0] gp_data3 gp_data2 ip_en1 ip_en0 op_en1 op_en0 gp_data1 gp_data0 0x07 id [15:8] id[15:8] 0x 30d x 1 r [7:0] id[7:0] 0x10 ch 0 [15:8] ch_en0 setup_sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0 0x11 ch 1 [15:8] ch_en1 setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch 2 [15:8] ch_en2 setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch 3 [15:8] ch_en3 setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x14 ch 4 [15:8] ch_en4 setup_sel4 reserved ainpos4[4:3] 0x0001 rw [7:0] ainpos4[2:0] ainneg4 0x15 ch 5 [15:8] ch_en5 setup_sel5 reserved ainpos5[4:3] 0x0001 rw [7:0] ainpos5[2:0] ainneg5 0x16 ch 6 [15:8] ch_en6 setup_sel6 reserved ainpos6[4:3] 0x0001 rw [7:0] ainpos6[2:0] ainneg6 0x17 ch 7 [15:8] ch_en7 setup_sel7 reserved ainpos7[4:3] 0x0001 rw [7:0] ainpos7[2:0] ainneg7 0x18 ch 8 [15:8] ch_en8 setup_sel8 reserved ainpos8[4:3] 0x0001 rw [7:0] ainpos8[2:0] ainneg8 0x19 ch 9 [15:8] ch_en9 setup_sel9 reserved ainpos9[4:3] 0x0001 rw [7:0] ainpos9[2:0] ainneg9 0x1a ch 10 [15:8] ch_en10 setup_sel10 reserved ainpos10[4:3] 0x0001 rw [7:0] ainpos10[2:0] ainneg10 0x1b ch 11 [15:8] ch_en11 setup_sel11 reserved ainpos11[4:3] 0x0001 rw [7:0] ainpos11[2:0] ainneg11 0x1c ch 12 [15:8] ch_en12 setup_sel12 reserved ainpos12[4:3] 0x0001 rw [7:0] ainpos12[2:0] ainneg12 0x1d ch 13 [15:8] ch_en13 setup_sel13 reserved ainpos13[4:3] 0x0001 rw [7:0] ainpos13[2:0] ainneg13 0x1e ch 14 [15:8] ch_en14 setup_sel14 reserved ainpos14[4:3] 0x0001 rw [7:0] ainpos14[2:0] ainneg14 0x1f ch 15 [15:8] ch_en15 setup_sel15 reserved ainpos15[4:3] 0x0001 rw [7:0] ainpos15[2:0] ainneg15 0x20 setupcon0 [15:8] reserved bi_ unipolar0 ref_buf 0 [1:0] ain_buf 0 [1:0] 0x1000 rw [7:0] burnout_ en 0 bufchopmax 0 ref_sel0 reserved 0x21 setupcon1 [15:8] reserved bi_unipolar1 ref_buf 1 [1:0] ain_buf 1 [1:0] 0x1000 rw [7:0] burnout_ en1 bufchopmax 1 refsel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 ref_buf 2 [1:0] ain_buf 2 [1:0] 0x1000 rw [7:0] burnout_ en2 bufchopmax 2 refsel2 reserved rev. 0 page 45 of 64
ad7173- 8 data sheet reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x23 setupcon3 [15:8] reserved bi_unipolar3 ref_buf 3 [1:0] ain_buf 3 [1:0] 0x1000 rw [7:0] burnout_ en3 bufchopmax 3 refsel3 reserved 0x24 setupcon4 [15:8] reserved bi_unipolar4 ref_buf 4 [1:0] ain_buf 4 [1:0] 0x1000 rw [7:0] burnout_ en4 bufchopmax 4 refsel4 reserved 0x25 setupcon5 [15:8] reserved bi_unipolar5 ref_buf 5 [1:0] ain_buf 5 [1:0] 0x1000 rw [7:0] burnout_ en5 bufchopmax 5 refsel5 reserved 0x26 setupcon6 [15:8] reserved bi_unipolar6 ref_buf 6 [1:0] ain_buf 6 [1:0] 0x1000 rw [7:0] burnout_ en6 bufchopmax 6 refsel6 reserved 0x27 setupcon7 [15:8] reserved bi_unipolar7 ref_buf 7 [1:0] ain_buf 7 [1:0] 0x1000 rw [7:0] burnout_ en7 bufchopmax 7 refsel7 reserved 0x28 filtcon0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x000 0 rw [7:0] reserved order0 odr0 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x000 0 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x000 0 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x000 0 rw [7:0] reserved order3 odr3 0x2c filtcon4 [15:8] sinc3_map4 reserved enhfilten4 enhfilt4 0x000 0 rw [7:0] reserved order4 odr4 0x2d filtcon5 [15:8] sinc3_map5 reserved enhfilten5 enhfilt5 0x000 0 rw [7:0] reserved order5 odr5 0x2e filtcon6 [15:8] sinc3_map6 reserved enhfilten6 enhfilt6 0x000 0 rw [7:0] reserved order6 odr6 0x2f filtcon7 [15:8] sinc3_map7 reserved enhfilten7 enhfilt7 0x000 0 rw [7:0] reserved order7 odr7 0x30 offset0 [23: 0 ] offset0[23:0 ] 0x800000 rw 0x31 offset1 [23:0] offset1[23:0 ] 0x800000 rw 0x32 offset2 [23:0] offset2[23:0] 0x800000 rw 0x33 offset3 [23:0] offset3[23:0] 0x800000 rw 0x34 offset4 [23:0] offset4[23:0] 0x800000 rw 0x35 offset5 [23:0] offset5[23:0] 0x800000 rw 0x36 offset6 [23:0] offset6[23:0] 0x800000 rw 0x37 offset7 [23:0] offset7[23:0] 0x800000 rw 0x38 gain0 [23:0] gain0[23:0] 0x5xxxx0 2 rw 0x39 gain1 [23:0] gain1[23:0] 0x5xxxx0 2 rw 0x3a gain2 [23:0] gain2[23:0] 0x5xxxx0 2 rw 0x3b gain3 [23:0] gain3[23:0] 0x5xxxx0 2 rw 0x3c gain4 [23:0] gain4[23:0] 0x5xxxx0 2 rw 0x3d gain5 [23:0] gain5[23:0] 0x5xxxx0 2 rw 0x3e gain6 [23:0] gain6[23:0] 0x5xxxx0 2 rw 0x3f gain7 [23:0] gain7[23:0] 0x5xxxx0 2 rw 1 x = dont care. the value of x is specific to the adc. 2 the value of x varies, depending on the ic that is used. rev. 0 | page 46 of 64
data sheet ad7173- 8 register details communications regis ter address: 0x00, reset: 0x00, name: comms table 23 . bit descriptions for comms bits bit name settings description reset access 7 wen this bit must be low to begin communications with the adc. 0x0 w 6 r/ w this bit determines if the command is a read or write operation. 0x0 w 0 write c ommand 1 read c ommand [5:0] ra the register address bits determine which register is to be read from or written to as part of the current communication. 0x00 w 000000 status r egister 000001 adc mode r egister 000010 interface mode r egister 000011 register checksum r egister 000100 data r egister 000110 gpio configuration r egister 000111 id r egister 010000 channel 0 r egister 010001 channel 1 r egister 010010 channel 2 r egister 010011 channel 3 r egister 010 100 channel 4 r egister 010 101 channel 5 r egister 010 110 channel 6 r egister 010 111 channel 7 r egister 01 1000 channel 8 r egister 01 1001 channel 9 r egister 01 1010 channel 10 r egister 01 1011 channel 11 r egister 01 1100 channel 12 r egister 01 1101 channel 13 r egister 01 1110 channel 14 r egister 011111 channel 15 r egister 100000 setup configuration 0 r egister 100001 setup configuration 1 r egister 100010 setup configuration 2 r egister 100011 setup configuration 3 r egister 100 100 setup configuration 4 r egister 100 101 setup configuration 5 r egister 100 110 setup configuration 6 r egister 100 111 setup configuration 7 r egister 101000 filter configuration 0 r egister 101001 filter configuration 1 r egister 101010 filter configuration 2 r egister 101011 filter configuration 3 r egister 101 100 filter configuration 4 r egister 101 101 filter configuration 5 r egister 101 1 1 0 filter configuration 6 r egister 101 1 11 filter configuration 7 r egister 110000 offset 0 r egister 110001 offset 1 r egister rev. 0 | page 47 of 64
ad7173- 8 data sheet bits bit name settings description reset access 110010 offset 2 r egister 110011 offset 3 r egister 110100 offset 4 r egister 110101 offset 5 r egister 110110 offset 6 r egister 110111 offset 7 r egister 111000 gain 0 r egister 111001 gain 1 r egister 111010 gain 2 r egister 111011 gain 3 r egister 111 100 gain 4 r egister 111 101 gain 5 r egister 111 110 gain 6 r egister 1111 11 gain 7 r egister rev. 0 | page 48 of 64
data sheet ad7173- 8 status register address: 0x00, reset: 0x80, name: status the status r egister is an 8 - bit register that contains adc and serial interface status information. it can optionally be appended to the data r egister by setting the data_stat bit in the i nterface m ode r egister (bit 6, register 0x02) . table 24 . bit descriptions for status bits bit name se ttings description reset access 7 rdy the status of rdy is output to the dout/ rdy pin whenever cs is low and a register is not being read. this bit goes low when the adc has written a new result to the data r egister. in adc calibration modes, this bit goes low when the adc has written the calibration result. rdy is brought high automatically by a read of the d ata r egister. 0x1 r 0 new data result a vailable 1 awaiting new data result 6 adc_error this bit , by default , indicates if an adc overrange or underrange has occurred. the adc result is clamped to full scale if an overrange or underrange occurs . this bit is updated when the adc result is written and is cleared by removing the overrange or underrange condition on the analog inputs. 0x0 r 0 no e rror 1 error 5 crc_error this bit indicates if a crc error has occurred during a register write. for register reads, the host microcontroller determines if a crc error has occurred. this bit is cleared by a read of this register. 0x0 r 0 no e rror 1 crc e rror 4 reg_error this bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. the check is activated by se tting the reg_check bit in the interface mode r egister. this bit is cleared by clearing the reg_check bit. 0x0 r 0 no e rror 1 error [3: 0 ] channel these bits indicate which channel was active for the adc conversion wh ose result is currently in the data r egister. this may be different from the channel currently being converted. the bits are a direct map ping from the c hannel x r egister s ; therefore, channel 0 results in 0x0 and channel 15 results in 0x 1f . 0x0 r 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 channel 4 0101 channel 5 0110 channel 6 01 11 channel 7 1000 channel 8 1001 channel 9 1010 channel 10 1011 channel 11 1100 channel 12 1101 channel 13 1110 channel 14 1111 channel 15 rev. 0 | page 49 of 64
ad7173- 8 data sheet adc mode register address: 0x01, reset: 0x 2 000, name: adcmode the adc mode r egister controls the operating mode of the adc and the master clock selection. a write to the adc m ode r egister resets the filter and the rdy bits and starts a new conversion or calibration. table 25 . bit descriptions for adcmode bits bit name settings description reset access 15 ref_en enables internal reference and outputs a buffered 2.5 v to the refout pin. 0x 0 rw 0 disabled 1 enabled 14 reserved this bit is reserved. s et to 0. 0x0 r 13 sing_cyc this bit can be used when only a single channel is active to set the adc to output only at the settled filter data rate. 0x 1 rw 0 disabled 1 enabled [12:11] reserved these bits are reserved . s et to 0. 0x0 r [10:8] delay these bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the adc starts processing its input . 0x0 rw 000 0 s 001 32 s 010 128 s 011 320 s 100 800 s 101 1.6 ms 110 4 ms 111 8 ms 7 reserved this bit is reserved. s et to 0. 0x0 r [6:4] mode these bits control the operating mode of the adc. details can be found in the operating modes section. 0x0 rw 000 continuous conversion m ode 001 single conversion m ode 010 standby m ode 011 power - d own m ode 100 internal offset c alibration 110 system offset c alibration 111 system g ain c alibration [3:2] clocksel this bit is used to select the adc clock source. selecting the internal oscillator also enables the internal oscillator. 0x0 rw 00 internal oscillator 01 internal oscillator output on xtal2 /clkio pin 10 external clock input on xtal2 /clkio pin 11 external crystal on xtal1 and xtal2 /clkio pins [1:0] reserved these bit s are reserved. s et to 0. 0x0 r rev. 0 | page 50 of 64
data sheet ad7173- 8 interface mode regis ter address: 0x02, reset: 0x0000, name: ifmode the interface mode register configures various serial interface options. table 26 . bit descriptions for ifmode bits bit name settings description reset access [15:13] reserved these bit s are reserved . set to 0. 0x0 r 12 a lt_ sync this bit enables a different behavior of the sync pin to allow the use of sync as a control for conversions when cycling channels . ( f or details , see the description of the sync _en bit in the gpio configuration register . ) 0x0 rw 0 disabled 1 enabled 11 iostreng t h this bit controls the drive strength of the dout ( dout/ rdy ) pin and the xtal2/clkio pin . set t his bit to 1 when reading from the serial interface at high speed with low iovdd supply and moderate capacitance. 0x0 rw 0 disabled (default) 1 enabled [10:9] reserved these bit s are reserved . s et to 0. 0x0 r 8 dout_reset this bit prevents the dout/ rdy pin from switching from outputting dout to outputting rdy soon after the la st rising edge of sclk during a read operation. instead, the dout/ rdy pin continue s to output the lsb of the data until cs goes high, providing longer hold times for the spi master to sample the lsb of the data. when this bit is set, cs must not be tied low. 0x0 rw 0 disabled 1 enabled 7 contread this bit enables continuous read of the adc data register. to use continuous read , configure t he adc in continuous conversion mode. for more details, see the operating modes section. 0x0 rw 0 disabled 1 enabled 6 data_stat this bit enables the status register to be appended to the data r egister when read so that channel and status information is transmitted with the data. this is the only way to en sure that the channel bits read from the status r egister correspond to the data in the d ata r egister. 0x0 rw 0 disabled 1 enabled 5 reg_check this bit enable s a register integrity checker that can be used to monitor any change in the value of the user registers. to use this feature, configure all other registers as desired, with this bit cleared. then write to this register to set the reg_check bit to 1. if the contents of any of the registers change, the reg_error bit is set in the s tatus r egister. to clear the error, set the reg_check bit to 0. neither the interface mode register nor the adc data or status r egister is included in the registers that are checked. if a register must have a new value written, clear this bit first; otherwise, an error is flagged when the new register contents are written. 0x0 rw 0 disabled 1 enabled 4 reserved this bit is reserved . s et to 0. 0x0 r [ 3 :2] crc_en en ables crc protection of register reads/writes. crc increases the number of bytes in a serial interface transfer by one. see the crc calculation section for more details. 0x0 0 rw 0 0 disabled . 01 xor checksum e nabled for register read transactions. register writes still use crc with th ese bit s set. 1 0 crc c hecksum e nabled for read and write transactions. 1 reserved this bit is reserved . s et to 0. 0x0 r rev. 0 | page 51 of 64
ad7173- 8 data sheet bits bit name settings description reset access 0 wl16 changes the adc d ata r egister to 16 bits. the adc is not reset by a write to the i nterface m ode r egister; therefore, the adc result is not rounded to the correct word length immediately after writing to these bits. the first new adc result is correct. 0x0 rw 0 24 - bit data 1 16 - bit data register check address: 0x03, reset: 0x000000, name: regcheck the register check r egister is a 24 - bit checksum calculated by x or'ing the contents of the user regis ters and some nonaccessible registers . the reg_check bit in the interface mode r egister must be set for this to operate; otherwise, the register reads 0. table 27 . bit descriptions for regcheck bits bit name settings description reset access [23:0] register_check this register contains the 24 - bit checksum of user registers when the reg_check bit is set in the interface mode r egister . 0x000000 r data register address: 0x04, reset: 0x000000, name: data the d ata r egister contains the adc conversion result . the encoding is offset binary; however, it can be changed to unipolar by the bi_unipolar bit in the s etup c onfiguration r egister. reading the d ata r eg ister brings the rdy bit and pin high if they are low. the adc result can be read multiple times; however, because rdy has been brought high, it is not possible to know if another adc result is imminent. the adc does not write a new result into the data register if the register is currently being read. table 28 . bit descriptions for data bits bit name settings description reset access [23:0] data this register contains the adc conversion result. if the data_stat bit is set in the interface mode register, the status r egister is appended to this register when read, making this a 32 - bit register. if wl16 is set in the interface mode register , this register is set to a length of 16 bits. 0x000000 r rev. 0 | page 52 of 64
data sheet ad7173- 8 gpio configuration r egister address: 0x06, reset: 0x0800, name: gpiocon the gpio c onfiguration r egister controls the general - purpose i/o pins of the adc. table 29 . bit descriptions for gpiocon bits bit name settings description reset access 15 reserved this bit is reserved . s et to 0. 0x0 r 14 pdsw this bit e nables /disables the power - down switch function. setting the bit allows the pin to sink current. this function can be used for bridge s ensor applications where the switch controls the power - up/ power - down of the bridge . 0x0 r w 13 op_en2_3 this bit enables the gpo2 and gpo3 pins . outputs are referenced between avdd1 and avss. 0x0 rw 12 mux_io this bit allows the adc to control an external multiplexer , using gpio0/gpio1 / gpo2/gpo3 in sync with the internal channel sequencing. the analog inpu t pins used for a channel can still be selected on a per channel basis. therefore, it is possible to have a 16- channel multiplexer in front of each analog input pair (ain0/ain1 to ain14/ain15) , giving a total of 128 differential channels. however, only 16 channels at a time can be automatically sequenced . f ollowing the sequence of 16 channels , the user changes the analog input to the next pair of input channels , and it se quences through the next 16 channels. there is a delay function that allows extra time for the analog input to settle , in conjunction with any switching an external m ultiplexer (see the delay bits in the adc mode register ). 0x0 rw 11 sync_en this bit enables the sync pin as a sync input. when set low, the sync pin holds the adc and filter in reset until sync goes high. an alternative operation of the sync pin is available when the alt_sync bit in the i nterface m ode r egister is set. this mode works only when multiple channels are enabled. in such case s , a low on the sync pin does not immediately reset the filter/modulator. instead, if the sync pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. bringing sync high begins the next conversion. this alternative sync mode allo ws sync to be used while cycling through channels. 0x1 rw 0 disabled 1 enabled [10:9] err_en these bits enable the error pin as an error input/output. 0x0 rw 00 disabled 01 error is an error input. the (inverted) readback state is or'ed with other error sources and is availab le in the adc_error bit in the status r egister. the error pin state can also be read from the err_dat bit i n this register . 10 error is an open - drain error output. the s tatus r egister error bits are or'ed, inverted, and mapped to the error pin. error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. 11 error is a general - purpose output. the status of the pin is controlled by the err_dat bit in this register. this is referenced between iovd d and dgnd, as opposed to the avdd1 and avss levels used by the general - purpose i/o pins. it has an active pull - up in this case. 8 err_dat this bit determines the logic level at the error pin if the pin is enabled as a general - purpose output. it reflects the readback status of the pin if the pin is enabled as an input. 0x0 rw 7 gp_data3 this bit is the write data for gpo3 . 0x0 w 6 gp_data2 this bit is the write data for gpo2 . 0x0 w 5 ip_en1 this bit turns gpio1 into an input. input should equal avdd 1 or avss. 0x0 rw 0 disabled 1 enabled rev. 0 | page 53 of 64
ad7173- 8 data sheet bits bit name settings description reset access 4 ip_en0 this bit turns gpio0 into an input. input should equal avdd 1 or avss. 0x0 rw 0 disabled 1 enabled 3 op_en1 this bit turns gpio1 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled 1 enabled 2 op_en0 this bit turns gpio0 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled 1 enabled 1 gp_data1 this bit is the readback or write data for gpio1. 0x0 rw 0 gp_data0 this bit is the readback or write data for gpio0. 0x0 rw id register address: 0x07, reset: 0x30dx , name: id the id register returns a 16 - bit id. for the ad7173 - 8 , this is 0x30dx . table 30 . bit descriptions for id bits bit name settings description reset access [15:0] id the id register returns a 16 - bit id code that is specific to the adc. 0x30dx 1 r 0x30dx ad7173 -8 1 x = dont care. channel register 0 address: 0x10, reset: 0x8001, name: ch 0 the c hannel r egisters are 16 - bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the adc for that channel. table 31 . bit descriptions for ch0 bits bit name settings description reset access 15 ch_en0 this bit enables channel 0. if more than one channel is enabled, the adc automatically sequence s between them. 0x1 rw 0 disabled 1 enabled (default) [1 4 :12] setup_sel0 these bits identify which of the eight setups are used to configure the adc for this channel. a setup comprises a set of four registers: the setup c onfiguration r egister, the filter configuration r egister, the offset r egister, and the gain r egister. all channels can use the same setup, in whic h case the same 3 - bit value is written to th ese bits on all active channels; alternatively, up to eight channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 1 00 setup 4 1 01 setup 5 1 10 setup 6 1 11 setup 7 [11:10] reserved these bits are reserved . s et to 0. 0x0 r rev. 0 | page 54 of 64
data sheet ad7173- 8 bits bit name settings description reset access [9:5] ainpos0 these bits select which of the analog inputs is connected to the positive input of the adc for this channel. temp sensor is an internal tempera - ture sensor. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 0010 1 ain 5 001 1 0 ain 6 001 11 ain 7 0 10 00 ain 8 0 10 0 1 ain 9 0 101 0 ain 10 0 1011 ain 11 0 1 1 00 ain 12 0 1 1 0 1 ain 13 0 1 1 1 0 ain 1 4 0 1 1 1 1 ain 1 5 10000 ain1 6 10001 temp sensor + 10010 temp sensor ? 10101 ref+ 10110 ref? [4:0] ainneg0 these bits select which of the analog inputs is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1(default) 00010 ain2 00011 ain3 00100 ain4 0010 1 ain 5 001 1 0 ain 6 001 11 ain 7 0 10 00 ain 8 0 10 0 1 ain 9 0 101 0 ain 10 0 1011 ain 11 0 11 00 ain 12 0 11 0 1 ain 13 0 111 0 ain 14 0 1111 ain 15 10000 ain16 10001 temp sensor + 10010 temp sensor ? 10101 ref+ 10110 ref? rev. 0 | page 55 of 64
ad7173- 8 data sheet channel registe r 1 to channel register 15 address range : 0x11 to 0x1f , reset: 0x0001, name: ch 1 to ch 15 subsequen t channel r egisters , ch 1 to ch15, use the same structure as the ch0 register. they are disabled by default (msb = 0). each channel created can be refe rred to one of eight set ups. the sequencer progresses through each of the enable d channels in order. table 32 shows the summary of these registers, their address es , and their r eset values . table 32. summary of ch1 to ch15 reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x11 ch1 [15:8] ch_en1 setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch2 [15:8] ch_en2 setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch3 [15:8] ch_en3 setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x14 ch4 [15:8] ch_en4 setup_sel4 reserved ainpos4[4:3] 0x0001 rw [7:0] ainpos4[2:0] ainneg4 0x15 ch5 [15:8] ch_en5 setup_sel5 reserved ainpos5[4:3] 0x0001 rw [7:0] ainpos5[2:0] ainneg5 0x16 ch6 [15:8] ch_en6 setup_sel6 reserved ainpos6[4:3] 0x0001 rw [7:0] ainpos6[2:0] ainneg6 0x17 ch7 [15:8] ch_en7 setup_sel7 reserved ainpos7[4:3] 0x0001 rw [7:0] ainpos7[2:0] ainneg7 0x18 ch8 [15:8] ch_en8 setup_sel8 reserved ainpos8[4:3] 0x 0 001 rw [7:0] ainpos8[2:0] ainneg8 0x19 ch9 [15:8] ch_en9 setup_sel9 reserved ainpos9[4:3] 0x0001 rw [7:0] ainpos9[2:0] ainneg9 0x1a ch10 [15:8] ch_en10 setup_sel10 reserved ainpos10[4:3] 0x0001 rw [7:0] ainpos10[2:0] ainneg10 0x1b ch11 [15:8] ch_en11 setup_sel11 reserved ainpos11[4:3] 0x0001 rw [7:0] ainpos11[2:0] ainneg11 0x1c ch12 [15:8] ch_en12 setup_sel12 reserved ainpos12[4:3] 0x0001 rw [7:0] ainpos12[2:0] ainneg12 0x1d ch13 [15:8] ch_en13 setup_sel13 reserved ainpos13[4:3] 0x0001 rw [7:0] ainpos13[2:0] ainneg13 0x1e ch14 [15:8] ch_en14 setup_sel14 reserved ainpos14[4:3] 0x0001 rw [7:0] ainpos14[2:0] ainneg14 0x1f ch15 [15:8] ch_en15 setup_sel15 reserved ainpos15[4:3] 0x0001 rw [7:0] ainpos15[2:0] ainneg15 rev. 0 | page 56 of 64
data sheet ad7173- 8 setup configuration register 0 address: 0x20, reset: 0x10 00 , name: setupcon0 the setup configuration r egisters are 16 - bit registers that configure the reference selection , input buffers, burnout currents , and output coding of the adc. table 33 . bit descriptions for setupcon0 bits bit name settings description reset access [15:13] reserved these bits are reserved . s et to 0. 0x0 r 12 bi_unipolar0 this bit sets the output coding of the adc for setup 0. 0x1 rw 0 unipolar coded output 1 offset binary coded output [11:10] ref_buf_0[1:0] reference input buffer enable. these bits turn on the buffers o f the positive and negative reference inputs. this offers a high impedance input for an externa l reference source and isolates it from the switch capacitor reference sampling input of the adc. use both reference buffers together. 0x0 rw 00 reference input buffers disabled 11 reference input buffers enabled [9:8] ain_buf_0[1:0] analog input buffer enable. t hese bits turn on the buffers o f the positive and negative analog inputs. this offers a high impedance input to the device and isolates the sensor/signal for measurement from the switch capacitor sampling input of the adc. use both analog input buffers together. 0x0 rw 00 analog input buffers disabled 11 analog input buffers enabled 7 burnout_en0 this bit e nables a 10 a current source on the positive analog input selected and a 10 a current sink on the negative analog input selected. the burnout currents are useful in diagnosis of an open wire, where by the adc result go es to full scale. enabling the burnout c urrents during measurement result s in an offset voltage on the adc reading of approximately 1 v. this means the strategy for diagnosing an open wire operate s best by turning on the burnout currents at intervals, before or after precision measurements. 0x0 rw 6 bufchopmax 0 this bit e nables the maximum buffer chop frequency, increasing ain input current and reducing buffer noise. 0x0 r w [5:4] ref_sel0 these bits allow select ion of the reference source for adc conversion on setup 0. 0x 0 rw 00 external r eference supplied to ref+ and ref ? pins 01 external r eference 2 supplied to ain1/ref2+ and ain0/ref2 ? pins 10 internal 2.5 v r eference; t his reference must also be enabled in the adc m ode r egister 11 avdd1 C avss; t his setting can be used to as a diagnostic to validate other reference values [3:0] reserved these bits are reserved . s et to 0. 0x0 r rev. 0 | page 57 of 64
ad7173- 8 data sheet setup configuration register 1 to setup configuration register 7 address: 0x2 1 to 0x27 , reset: 0x10 00 , name: setupcon 1 to setupcon7 the remaining seven setup configuration r egisters share the same 16 - bit register layout as setupcon 0. they configure the reference selection, input buffers, burnout currents , and output coding of the adc. table 34. summary of setupcon1 to setupcon7 reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x21 setupcon1 [15:8] reserved bi_unipolar1 ref_buf 1 [1:0] ain_buf 1 [1:0] 0x1000 rw [7:0] burnout_ en1 bufchopmax1 refsel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 ref_buf 2 [1:0] ain_buf 2 [1:0] 0x1000 rw [7:0] burnout_ en2 bufchopmax2 refsel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 ref_buf 3 [1:0] ain_buf 3 [1:0] 0x1000 rw [7:0] burnout_ en3 bufchopmax3 refsel3 reserved 0x24 setupcon4 [15:8] reserved bi_unipolar4 ref_buf 4 [1:0] ain_buf 4 [1:0] 0x1000 rw [7:0] burnout_ en4 bufchopmax4 refsel4 reserved 0x25 setupcon5 [15:8] reserved bi_unipolar5 ref_buf 5 [1:0] ain_buf 5 [1:0] 0x1000 rw [7:0] burnout_ en5 bufchopmax5 refsel5 reserved 0x26 setupcon6 [15:8] reserved bi_unipolar6 ref_buf 6 [1:0] ain_buf 6 [1:0] 0x1000 rw [7:0] burnout_ en6 bufchopmax6 refsel6 reserved 0x27 setupcon7 [15:8] reserved bi_unipolar7 ref_buf 7 [1:0] ain_buf 7 [1:0] 0x1000 rw [7:0] burnout_ en7 bufchopmax7 refsel7 reserved rev. 0 | page 58 of 64
data sheet ad7173- 8 filter configuration register 0 address: 0x28, reset: 0x0000, name: filtcon0 the filter configuration registers are 16- bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 35 . bit descriptions for fil tcon0 bits bit name settings description reset access 15 sinc3_map0 if this bit is set, the mapping of the f ilter configuration r egister changes to directly prog ram the decimation rate of the s inc3 filter for setup 0. all other options are eliminated. this allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a single channel , with single cycle settling disabled, equals fmod/(32 filtcon0[14:0]). 0x0 rw [14:12] reserved these bits are reserved . s et to 0. 0x0 r 11 enhfilten0 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 0. for this setting to function, t he order x bits must also be set to 00 to select the sinc5 + s inc1 filter. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt0 these bits select between various post filters for enhanced 50 hz/60 hz rejection for setup 0. 0x0 rw 010 27 .27 sps, 47 db rejection, 36. 6 7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved . s et to 0 . 0x0 r [6:5] order0 these bits control the order of the digital filter that processes the modulator data for setup 0. 0x0 rw 00 sinc5 + s inc1 (default) 11 sinc3 [4:0] odr0 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 0. 0x0 rw 00000 31,250 sps 00001 31,250 sps 00010 31,250 sps 00011 31,250 sps 00100 31,250 sps 00101 31, 25 0 sps 00110 15,625 sps 00111 10, 417 sps 01000 5 208 sps 01001 25 97 sps (2604 sps for sinc3) 01010 1007 sps (1008 sps for sinc3) 01011 503 .8 sps (504 sps for sinc3) 01100 381 sps (400.6 sps for sinc3) 01101 200 .3 sps 01110 100 .5 sps 01111 59.52 sps (59.98 sps for sinc3) 10000 49.68 sps (50 sps for sinc3) 10001 20 .01 sps 10010 16.6 3 sps (16.6 7 sps for sinc3) 10011 10 sps 10100 5 sps 10101 2. 5 sps 1011 0 1.2 5 sps rev. 0 | page 59 of 64
ad7173- 8 data sheet filter configuration register 1 to filter configuration register 7 address range : 0x2 9 to 0x2f , reset: 0x0000, name: filtcon 1 to filtcon7 the remaining seve n filter configuration r egisters share the same 16 - bit register layout as filtcon0. they configure the adc data rate and filter options and map as per their number. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the seque nce. table 36. summary of filtcon1 to filtcon7 reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0000 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x0000 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x0000 rw [7:0] reserved order3 odr3 0x2c filtcon4 [15:8] sinc3_map4 reserved enhfilten4 enhfilt4 0x0000 rw [7:0] reserved order4 odr4 0x2d filtcon5 [15:8] sinc3_map5 reserved enhfilten5 enhfilt5 0x0000 rw [7:0] reserved order5 odr5 0x2e filtcon6 [15:8] sinc3_map6 reserved enhfilten6 enhfilt6 0x0000 rw [7:0] reserved order6 odr6 0x2f filtcon7 [15:8] sinc3_map7 reserved enhfilten7 enhfilt7 0x0000 rw [7:0] reserved order7 odr7 rev. 0 | page 60 of 64
data sheet ad7173- 8 offset register 0 address: 0x30, reset: 0x800000, name: offset0 the o ffset ( z ero - s cale) r egisters are 24 - bit registers that can be used to compensate for any offset error in the adc or in the system. table 37 . bit descriptions for offset0 bits bit name settings description reset access [23:0] offset0 offset calibration coefficient for setup 0. 0x800000 rw offset register 1 to of fset register 7 address range : 0x31 to 0x37 , reset: 0x800000, name: offset1 to offset7 the o ffset ( z ero - s cale) r egisters , offset1 to offset7, share the same structure ( 24- bit ) as offset0 . they can be used individually to compensate for any offset er ror in the adc or in the system . table 38. summary of offset1 to offset7 reg name bits bit[23:0] reset rw 0x31 offset1 [23:0] offset1[23:0] 0x800000 rw 0x32 offset2 [23:0] offset2[23:0] 0x800000 rw 0x33 offset3 [23:0] offset3[23:0] 0x800000 rw 0x34 offset4 [23:0] offset4[23:0] 0x800000 rw 0x35 offset5 [23:0] offset5[23:0] 0x800000 rw 0x36 offset6 [23:0] offset6[23:0] 0x800000 rw 0x37 offset7 [23:0] offset7[23:0] 0x800000 rw gain register 0 address: 0x38, reset: 0x5xxxx 0, name: gain0 the g ain ( f ull - s cale) r egisters are 24 - bit registers that can be used to compensate for any gain error in the adc or in the system. table 39 . bit descriptions for gain0 bits bit name settings description reset 1 access [23:0] gain0 gain calibration coefficient for setup 0. 0x5xxxx0 rw 1 the value of x varies, depending on the ic that is used. gain register 1 to gain register 7 address range : 0x3 9 to 0x3f , reset: 0x5xxxx 0 , name: gain 1 to gain7 the g ain ( f ull - s cale) r egisters for gain1 to gain7 share the same 24 - bit structure as that shown by gain0 register. they can be used to compensate for any gain er ror in the adc or in the system and are assigned as per their number to a given setup. table 40. summary of gain1 to gain7 reg name bits bit[23:0] reset 1 rw 0x39 gain1 [23:0] gain1[23:0] 0x5xxxx0 rw 0x3a gain2 [23:0] gain2[23:0] 0x5xxxx0 rw 0x3b gain3 [23:0] gain3[[23:0] 0x5xxxx0 rw 0x3c gain4 [23:0] gain4[23:0] 0x5xxxx0 rw 0x3d gain5 [23:0] gain5[23:0] 0x5xxxx0 rw 0x3e gain6 [23:0] gain6[23:0] 0x5xxxx0 rw 0x3f gain7 [23:0] gain7[23:0] 0x5xxxx0 rw 1 the value of x varies, depending on the ic that is used. rev. 0 | page 61 of 64
ad7173- 8 data sheet outline dimensions figure 75 . 40 - lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp - 40 - 14) dimensions shown in millimeters ordering guide models 1 temperature range package description package option ad7173 -8b cpz ?40c to +105c 40 - lead lfcsp_wq cp -40 -14 ad7173 - 8bcpz -rl ?40c to +105c 40 - lead lfcsp_wq cp -40 -14 eval - ad7173 -8 sdz evaluation board eval - sdp - cb1z evaluation controller board 1 z = rohs compliant part. 0.50 bsc bot t om view top view pin 1 indic a t or exposed pa d pin 1 indic a t or se a ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 4.05 3.90 sq 3.75 compliant to jedec standards mo-220- wjjd . 40 1 11 20 21 30 31 10 05-06-20 1 1- a rev. 0 | page 62 of 64
data sheet ad7173- 8 notes rev. 0 | page 63 of 64
ad7173- 8 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11773 - 0- 10/13(0) rev. 0 | page 64 of 64

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