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fedl610q411-02 issue date: mar.23 2011 ML610Q411/q412/q415 8-bit microcontroller with a built-in lcd driver 1/36 general description ML610Q411/q412/q415 is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i 2 c bus interface (master), buzzer driver, battery level detect circuit, rc oscillation type a/d converter, 12-bit successive approximation type a/d converter, an d lcd driver, are incorporated around lapis semiconductor -original 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. the flash rom that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask rom and is most suitable for battery-driven applications. the on-chip debug function that is installed enables program debugging and programming. m l610q411/q412 has a dual clock, runs at 32.768khz crystal oscillation clock or a built-in 500khz rc oscillation clock, used for a system requires the accurate clock or timer. ml610q415 wo rks with the built-in rc oscillation clock and does not need an external crystal oscillator, can lower a system cost and shrink the production board. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time 30.5 ? s (@32.768 khz system clock) 2 ? s (@500khz system clock) ? internal memory ? internal 16kbbyte flash rom (8k ? 16 bits) (including unusable 1kbyte test area) ? internal 1kbyte data ram (1024 ? 8 bits) ? interrupt controller ? 2 non-maskable interrupt sources internal source: 1 (watch dog timer) external source: 1 (nmi) ? 19 maskable interrupt sources internal sources: 15 (ssio, sa-a/d converter, i2c, timer0, timer1, timer2, timer3, 1khz timer, uart, rc-a/d converter, pwm, tbc128hz, tbc32hz, tbc16hz, tbc2hz) external sources: 4 (p00, p01, p02, p03) ? time base counter ? low-speed time base counter ? 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter ? 1 channel
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 2/36 ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable ML610Q411/q412: 125ms, 500ms, 2s, and 8s ml610q415: approx. 131ms, 524ms, 2.1s, 8.4s ? timers ? 8 bits ? 4 channels (timer0-3: 16-bit x 2 configuration available by using timer0-1 or timer2-3) ? clock frequency measurement mode (in one channel of 16-bit configuration using timer2-3, ml610q415 does not have this mode) ? 1 khz timer ? interrupt function ML610Q411/q412: 10 hz/1 hz interrupt ml610q415: 9.5hz/0.95hz interrupt ? capture ? time base capture ? 2 channels ML610Q411/q412: 4096 hz to 32 hz ml610q415: 3906hz 30.5h ? pwm ? resolution 16 bits ? 1 channel ? synchronous serial port ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? txd/rxd ? 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? standard mode (50kbps) ? buzzer driver ? 4 output modes, 8 frequencies, 16 duty levels ? rc oscillation type a/d converter ? 24-bit counter ? time division ? 2 channels ? successive approximation type a/d converter ? 12-bit a/d converter ? input ? 2 channels ? conversion time: 46us/1ch@500khz ? general-purpose ports ? non-maskable interrupt input port ? 1 channel ? input-only port ? 6 channels (including secondary functions) ? output-only port ? 3 channels (including secondary functions) ? input/output port ML610Q411: 22 channels (including secondary functions) ml610q412: 14 channels (including secondary functions) ml610q415: 22 channels (including secondary functions)
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 3/36 ? lcd driver ? the number of segments ML610Q411: 144 dots max. (36 seg ? 4 com) ml610q412: 176 dots max. (44 seg ? 4 com) ml610q415: 144 dots max. (36 seg ? 4 com) ? 1/1 to 1/4 duty ? 1/3 bias (built-in bias generation circuit) ? frame frequency selecable ML610Q411/q412: approx. 64 hz, 73 hz, 85 hz, and 102 hz ml610q415: approx. 6 hz, 70hz, 81hz, 97hz ? bias voltage multiplying clock selectable (8 types) ? contrast adjustment (32 steps) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset when oscillation stop of the low-speed clock is detected (ML610Q411pc and ml610q415 does not have this function) ? reset by the watchdog timer (wdt) overflow ? battery level detector ? threshold voltages: one of 16 levels ? accuracy: ? 2% (typ.) ? clock ? low-speed clock ML610Q411/ml610q412: crystal oscillation (32.768 khz) (this lsi can not guarantee the operation withoug low-speed crystal oscillation clock) ml610q415: 1/16 of built-in rc oscillation 500 khz (31.25khz)* (this lsi does not have low-speed crystal oscillation clock) * this clock is not used for cpu operating clock. ? high-speed clock: built-in rc oscillation (500 khz) external clock (500kh or less) ? high-speed clock gear: 1/2(250khz), 1/4(125khz), 1/8(62.5khz: default) ? selection of high-speed clock mode by software: built-in rc oscillation, external clock ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the oscillation clock) ? block control function: resets and completely turns circuits of unused peripherals off.
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 4/36 ? shipment ? chip ML610Q411-xxxwa (blank product: ML610Q411-nnnwa) ML610Q411p- xxxwa (blank product: ml 610q411p-nnnwa) ML610Q411pa-xxxwa (blank product: ML610Q411pa-nnnwa) ML610Q411pc-xxxwa (blank product: ML610Q411pc-nnnwa) ml610q412-xxxwa (blank product: ml610q412-nnnwa) ml610q412p- xxxwa (blank product: ml 610q412p-nnnwa) ml610q415-xxxwa (blank product: ml610q415-nnnwa) ? 120-pin plastic tqfp ML610Q411-xxxtbz03a (blank product: ML610Q411-nnntbz03a) ML610Q411p- xxxtbz03a (blank product: ml 610q411p-nnntbz03a) ML610Q411pa-xxxtbz03a (blank product: ML610Q411pa-nnntbz03a) ML610Q411pc-xxxtbz03a (blank product: ML610Q411pc-nnntbz03a) ml610q412-xxxtbz03a (blank product: ml610q412-nnntbz03a) ml610q412p- xxxtbz03a (blank product: ml 610q412p-nnntbz03a) ml610q415-xxxtbz03a (blank product: ml610q415-nnntbz03a) xxx: rom code number p: wide range temperature version a: low-speed clock oscillation stop detection reset is selectable to disable always (see chapter3 and chapter4 in the user?s manual for more detail). c: ems tolerance improved version/hardware-inactive low-sp eed clock oscillation stop detection reset (see chapter3 and chapter4 in the user?s manual for more detail) wa: chip tb: tqfp ? guaranteed operating range ? operating temperature: ? 20? c to +70 ? c (p version: ???? c to +85 ? c) ? operating voltage: v dd = 1.1v to 3.6v, av dd = 2.2v to 3.6v
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 5/36 block diagram ML610Q411/ml610q415 block diagram figure 1 show the block diagram of the ML610Q411. "*" indicates the secondary function of each port. "*" indicates ml610q415 does not have the crystal oscillation. figure 1 ML610Q411/ml610q415 block diagram program memory (flash) 16kbyte ssio sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 1 ram 1024byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 capture 2 int 1 pwm gpio p00 to p03 p10 to p11 p20 to p22 int 5 nmi p30 to p35 p40 to p47 pa0 to pa7 data-bus pwm0* buzzer int 1 bz0* test reset_n osc xt0** xt1** osc0* lsclk* outclk* bld power av dd av ss v ddl lcd driver com0 to com3 seg0 to seg35 lcd bias v l1 , v l2 , v l3 c1 , c2 12bit-adc ain0 , ain1 v ref rc-adc 2 cs0* in0* rs0* rt0* rct0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v pp v dd v ss v ddx 1khztc int 1 int 1 int 1 display register 144bit
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 6/36 ml610q412 block diagram figure 2 show the block diagram of the ml610q412. "*" indicates the secondary function of each port. figure 2 ml610q412 block diagram program memory (flash) 16kbyte ssio sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 1 ram 1024byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 capture 2 int 1 pwm gpio p00 to p03 p10 to p11 p20 to p22 int 5 nmi p30 to p35 p40 to p47 data-bus pwm0* melody int 1 md0* test reset_n osc xt0 xt1 osc0* lsclk* outclk* bld power av dd av ss v ddl lcd driver com0 to com3 seg0 to seg43 lcd bias v l1 , v l2 , v l3 c1 , c2 12bit-adc ain0 , ain1 v ref rc-adc 2 rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v pp v dd v ss v ddx 1khztc int 1 int 1 int 1 display register 176bit cs0* in0* rs0* rt0* rct0*
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 7/36 pin configuration ML610Q411/ml610q415 tqfp120 pin layout (nc): no connection note: the assignment of the p30 to p35 are not in order. figure 3 ML610Q411/ml610q415 tqfp120 pin configuration seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl1 vl2 vl3 c1 seg20 seg19 seg18 seg17 seg16 seg15 seg14 ( nc ) vss vdd vss p03 p02 p01 p00 nmi p11 p10 (nc) a in1 a in0 (nc) ( nc ) ( nc ) (nc) pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 seg35 vss p20 p21 p22 p40 p41 p42 p43 p44 p45 p46 p47 p30 p31 p34 p32 p33 p35 vddx xt0 xt1 vss vddl vdd a vss vref a vdd reset_n seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 (nc) ( nc ) ( nc ) (nc) ( nc ) ( nc ) ( nc ) c2 vpp test ( nc ) ( nc ) ( nc ) (nc) ( nc ) ( nc ) ( nc ) (nc) ( nc ) ( nc ) (nc) ( nc ) 1pin 120pin 30pin 31pin 60pin 61pin 91pin 90pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 71 70 69 68 67 65 64 63 62 61 81 80 79 78 77 76 75 74 73 72 90 89 88 87 86 85 84 83 82 66 100 99 98 97 96 95 94 93 92 91 110 109 108 107 106 105 104 103 102 101 120 119 118 117 116 115 114 113 112 111
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 8/36 ml610q412 tqfp120 pin layout (nc): no connection note: the assignment of the p30 to p35 are not in order. figure 4 ml610q412 tqfp120 pin configuration seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl1 vl2 vl3 c1 seg20 seg19 seg18 seg17 seg16 seg15 seg14 (nc) vss vdd vss p03 p02 p01 p00 nmi p11 p10 ( nc ) a in1 a in0 ( nc ) (nc) ( nc ) ( nc ) seg43 seg35 vss p20 p21 p22 p40 p41 p42 p43 p44 p45 p46 p47 p30 p31 p34 p32 p33 p35 vddx xt0 xt1 vss vddl vdd avss vref avdd reset_n seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 ( nc ) ( nc ) (nc) ( nc ) ( nc ) ( nc ) ( nc ) c2 vpp test ( nc ) (nc) ( nc ) ( nc ) (nc) ( nc ) ( nc ) ( nc ) (nc) ( nc ) ( nc ) (nc) 1pin 120pin 30pin 31pin 60pin 61pin 91pin 90pin seg42 seg41 seg40 seg39 seg38 seg37 seg36 100 99 98 97 96 95 94 93 92 91 110 109 108 107 106 105 104 103 102 101 120 119 118 117 116 115 114 113 112 111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 71 70 69 68 67 65 64 63 62 61 81 80 79 78 77 76 75 74 73 72 90 89 88 87 86 85 84 83 82 66 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 9/36 ML610Q411/ml610q415 chip pin layout & dimension seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl1 vl2 vl3 c1 c2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 seg21 91 seg22 92 seg23 93 seg24 94 seg25 95 seg26 96 47 vss seg27 97 46 vdd seg28 98 45 vss seg29 99 44 p03 seg30 100 43 p02 seg31 101 42 p01 seg32 102 41 p00 seg33 103 40 nmi seg34 104 39 p11 seg35 105 38 p10 pa0 106 37 ( nc ) pa1 107 36 a in1 pa2 108 35 a in0 pa3 109 pa4 110 pa5 111 pa6 112 pa7 113 * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 * 27 28 29 30 vpp vss p20 p21 p22 p40 p41 reset_n p42 p43 p44 p45 p46 p47 p30 p31 p34 p32 p33 p35 test vdd vddl vss vddx xt1 xt0 avss vref avdd 2.836mm 2.636m m * dummy pad note: these dummy pads are visible and do have any f unction, they are placed for a mechanical evaluation in lapis semiconductor. please do not implement wire-bonding to the dummy pad. chip size: 2.836mm x 2.636mm pad count: 95 pins minimum pad pitch: 80 ? m pad aperture: 70 ? m ? 70 ? m chip thickness: 350 ? m voltage of the rear side of chip: v ss level figure 5 ML610Q411/ml610q415 chip layout & dimension
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 10/36 ml610q412 chip pin layout & dimension seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com0 com1 com2 com3 vl1 vl2 vl3 c1 c2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 seg21 91 seg22 92 seg23 93 seg24 94 seg25 95 seg26 96 47 vss seg27 97 46 vdd seg28 98 45 vss seg29 99 44 p03 seg30 100 43 p02 seg31 101 42 p01 seg32 102 41 p00 seg33 103 40 nmi seg34 104 39 p11 seg35 105 38 p10 seg43 106 37 ( nc ) seg42 107 36 a in1 seg41 108 35 a in0 seg40 109 seg39 110 seg38 111 seg37 112 seg36 113 * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 * 27 28 29 30 vpp vss p20 p21 p22 p40 p41 reset_n p42 p43 p44 p45 p46 p47 p30 p31 p34 p32 p33 p35 test vdd vddl vss vddx xt1 xt0 avss vref avdd 2.836mm 2.636m m * dummy pad note: these dummy pads are visible and do have any f unction, they are placed for a mechanical evaluation in lapis semiconductor. please do not implement wire-bonding to the dummy pad. chip size: 2.836mm x 2.636mm pad count: 95 pins minimum pad pitch: 80 ? m pad aperture: 70 ? m ? 70 ? m chip thickness: 350 ? m voltage of the rear side of chip: v ss level figure 6 ml610q412 chip layout & dimension
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 11/36 ML610Q411/ml610q415 pad coordinates t able 1 ML610Q411 pad coordinates chip center: x=0,y=0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 vpp -1230 -1212 51 (nc) - - 101 seg31 -1312 160 2 vss -1150 -1212 52 (nc) - - 102 seg32 -1312 80 3 p20 -1070 -1212 53 (nc) - - 103 seg33 -1312 0 4 p21 -990 -1212 54 (nc) - - 104 seg34 -1312 -80 5 p22 -910 -1212 55 (nc) - - 105 seg35 -1312 -160 6 p40 -830 -1212 56 (nc) - - 106 pa0 -1312 -240 7 p41 -750 -1212 57 (nc) - - 107 pa1 -1312 -320 8 reset_n -670 -1212 58 (nc) - - 108 pa2 -1312 -400 9 p42 -590 -1212 59 (nc) - - 109 pa3 -1312 -480 10 p43 -510 -1212 60 (nc) - - 110 pa4 -1312 -560 11 p44 -430 -1212 61 c2 1220 1212 111 pa5 -1312 -640 12 p45 -350 -1212 62 c1 1140 1212 112 pa6 -1312 -720 13 p46 -270 -1212 63 vl3 1060 1212 113 pa7 -1312 -800 14 p47 -190 -1212 64 vl2 980 1212 -- dummy -1312 -908 15 p30 -110 -1212 65 vl1 900 1212 16 p31 -30 -1212 66 com3 820 1212 17 p34 50 -1212 67 com2 740 1212 18 p32 130 -1212 68 com1 660 1212 19 p33 210 -1212 69 com0 580 1212 20 p35 290 -1212 70 seg0 500 1212 21 test 370 -1212 71 seg1 420 1212 22 vdd 450 -1212 72 seg2 340 1212 23 vddl 530 -1212 73 seg3 260 1212 24 vss 610 -1212 74 seg4 180 1212 25 vddx 690 -1212 75 seg5 100 1212 26 xt1 770 -1212 76 seg6 20 1212 - dummy 850 -1212 77 seg7 -60 1212 27 xt0 930 -1212 78 seg8 -140 1212 28 avss 1030 -1212 79 seg9 -220 1212 29 vref 1110 -1212 80 seg10 -300 1212 30 avdd 1190 -1212 81 seg11 -380 1212 31 (nc) - - 82 seg12 -460 1212 32 (nc) - - 83 seg13 -540 1212 33 (nc) - - 84 seg14 -620 1212 34 (nc) - - 85 seg15 -700 1212 35 ain0 1312 -522 86 seg16 -780 1212 36 ain1 1312 -350 87 seg17 -860 1212 37 (nc) - - 88 seg18 -940 1212 38 p10 1312 -210 89 seg19 -1020 1212 39 p11 1312 -130 90 seg20 -1100 1212 40 nmi 1312 -50 91 seg21 -1312 960 41 p00 1312 30 92 seg22 -1312 880 42 p01 1312 110 93 seg23 -1312 800 43 p02 1312 190 94 seg24 -1312 720 44 p03 1312 270 95 seg25 -1312 640 45 vss 1312 350 96 seg26 -1312 560 46 vdd 1312 430 97 seg27 -1312 480 47 vss 1312 510 98 seg28 -1312 400 48 (nc) - - 99 seg29 -1312 320 49 (nc) - - 100 seg30 -1312 240 50 (nc) - -
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 12/36 ml610q412 pad coordinates table 2 ml610q412 pad coordinates chip center: x=0,y=0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 vpp -1230 -1212 51 (nc) - - 101 seg31 -1312 160 2 vss -1150 -1212 52 (nc) - - 102 seg32 -1312 80 3 p20 -1070 -1212 53 (nc) - - 103 seg33 -1312 0 4 p21 -990 -1212 54 (nc) - - 104 seg34 -1312 -80 5 p22 -910 -1212 55 (nc) - - 105 seg35 -1312 -160 6 p40 -830 -1212 56 (nc) - - 106 seg43 -1312 -240 7 p41 -750 -1212 57 (nc) - - 107 seg42 -1312 -320 8 reset_n -670 -1212 58 (nc) - - 108 seg41 -1312 -400 9 p42 -590 -1212 59 (nc) - - 109 seg40 -1312 -480 10 p43 -510 -1212 60 (nc) - - 110 seg39 -1312 -560 11 p44 -430 -1212 61 c2 1220 1212 111 seg38 -1312 -640 12 p45 -350 -1212 62 c1 1140 1212 112 seg37 -1312 -720 13 p46 -270 -1212 63 vl3 1060 1212 113 seg36 -1312 -800 14 p47 -190 -1212 64 vl2 980 1212 - dummy -1312 -908 15 p30 -110 -1212 65 vl1 900 1212 16 p31 -30 -1212 66 com3 820 1212 17 p34 50 -1212 67 com2 740 1212 18 p32 130 -1212 68 com1 660 1212 19 p33 210 -1212 69 com0 580 1212 20 p35 290 -1212 70 seg0 500 1212 21 test 370 -1212 71 seg1 420 1212 22 vdd 450 -1212 72 seg2 340 1212 23 vddl 530 -1212 73 seg3 260 1212 24 vss 610 -1212 74 seg4 180 1212 25 vddx 690 -1212 75 seg5 100 1212 26 xt1 770 -1212 76 seg6 20 1212 - dummy 850 -1212 77 seg7 -60 1212 27 xt0 930 -1212 78 seg8 -140 1212 28 avss 1030 -1212 79 seg9 -220 1212 29 vref 1110 -1212 80 seg10 -300 1212 30 avdd 1190 -1212 81 seg11 -380 1212 31 (nc) - - 82 seg12 -460 1212 32 (nc) - - 83 seg13 -540 1212 33 (nc) - - 84 seg14 -620 1212 34 (nc) - - 85 seg15 -700 1212 35 ain0 1312 -522 86 seg16 -780 1212 36 ain1 1312 -350 87 seg17 -860 1212 37 (nc) - - 88 seg18 -940 1212 38 p10 1312 -210 89 seg19 -1020 1212 39 p11 1312 -130 90 seg20 -1100 1212 40 nmi 1312 -50 91 seg21 -1312 960 41 p00 1312 30 92 seg22 -1312 880 42 p01 1312 110 93 seg23 -1312 800 43 p02 1312 190 94 seg24 -1312 720 44 p03 1312 270 95 seg25 -1312 640 45 vss 1312 350 96 seg26 -1312 560 46 vdd 1312 430 97 seg27 -1312 480 47 vss 1312 510 98 seg28 -1312 400 48 (nc) - - 99 seg29 -1312 320 49 (nc) - - 100 seg30 -1312 240 50 (nc) - -
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 13/36 pin list pad no. primary function secondary function tertiary function 415 pin name i/o function pin name i/o function pin name i/o function 2, 24,45,47 v ss ? negative power supply pin ? ? ? ? ? ? 22, 46 v dd ? positive power supply pin ? ? ? ? ? ? 23 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? ? ? 25 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? ? ? ? 1 v pp ? power supply pin for flash rom ? ? ? ? ? ? 28 av ss ? negative power supply pin for successive approximation type adc ? ? ? ? ? ? 30 av dd ? positive power supply pin for successive approximation type adc ? ? ? ? ? ? 65 v l1 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 64 v l2 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 63 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 62 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 61 c2 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 21 test i/o input/output pin for testing ? ? ? ? ? ? 8 reset_n i reset input pin ? ? ? ? ? ? 27 xt0(* 3 ) i low-speed clock oscillation pin ? ? ? ? ? ? 26 xt1(* 3 ) o low-speed clock oscillation pin ? ? ? ? ? ? 29 v ref ? reference power supply pin for successive approximation type adc ? ? ? ? ? ?
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 14/36 pad no. primary function secondary function tertiary function 415 pin name i/o function pin name i/o function pin name i/o function 36 ain0 i successive approximation type adc input ? ? ? ? ? ? 37 ain1 i successive approximation type adc input ? ? ? ? ? ? 40 nmi i non-maskable interrupt pin ? ? ? ? ? ? 41 p00/exi0/ cap0 i input port, external interrupt 0, capture 0 input ? ? ? ? ? ? 42 p01/exi1/ cap1 i input port, external interrupt 1, capture 1 input ? ? ? ? ? ? 43 p02/exi2/ rxd0 i input port, external interrupt 2, uart0 receive ? ? ? ? ? ? 44 p03/exi3 i input port, external interrupt 3 ? ? ? ? ? ? 38 p10 osc0 i input port external clock input ? ? ? ? ? ? 39 p11 i input port ? ? ? ? ? ? 3 p20/led0 o output port lsclk o low-speed clock output ? ? ? 4 p21led1 o output port outclk o high-speed clock output ? ? ? 5 p22/led2 o output port md0 o melody output ? ? ? 15 p30 i/o input/output port in0 i rc type adc0 oscillation input pin ? ? ? 16 p31 i/o input/output port cs0 o rc type adc0 reference capacitor connection pin ? ? ? 17 p34 i/o input/output port rct0 o rc type adc0 resistor/capacitor sensor connection pin pwm0 o pwm output 18 p32 i/o input/output port rs0 o rc type adc0 reference resistor connection pin ? ? ? 19 p33 i/o input/output port rt0 o rc type adc0 resistor sensor connection pin ? ? ? 20 p35 i/o input/output port rcm o rc type adc oscillation monitor ? ? ? 6 p40 i/o input/output port sda i/o i 2 c data input/output sin0 i ssio data input 7 p41 i/o input/output port scl i/o i 2 c clock input/output sck0 i/o ssio synchronous clock 9 p42 i/o input/output port rxd0 i uart data input sout0 i ssio data output 10 p43 i/o input/output port txd0 o uart data output pwm0 o pwm output 11 p44/t02p0 ck i/o input/output port, timer 0/timer 2/pwm0 external clock input in1 i rc type adc1 oscillation input pin sin0 i ssio0 data input 12 p45/t13p1 ck i/o input/output port, timer 1/timer 3 external clock input cs1 o rc type adc1 reference capacitor connection pin sck0 i/o ssio0 synchronous clock 13 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin sout0 o ssio0 data output 14 p47 i/o input/output port rt1 o rc type adc1 resistor sensor connection pin ? ? ? pa0(* 1 ) i/o input/output port ? ? ? ? ? ? 106 seg43(* 2 ) o lcd segment pin ? ? ? ? ? ? pa1(* 1 ) i/o input/output port ? ? ? ? ? ? 107 seg42(* 2 ) o lcd segment pin ? ? ? ? ? ?? pa2(* 1 ) i/o input/output port ? ? ? ? ? ? 108 seg41(* 2 ) o lcd segment pin ? ? ? ? ? ?? 109 pa3(* 1 ) i/o input/output port ? ? ? ? ? ?
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 15/36 pad no. primary function secondary function tertiary function 415 pin name i/o function pin name i/o function pin name i/o function seg40(* 2 ) o lcd segment pin ? ? ? ? ? ?? pa4(* 1 ) i/o input/output port ? ? ? ? ? ? 110 seg39(* 2 ) o lcd segment pin ? ? ? ? ? ?? pa5(* 1 ) i/o input/output port ? ? ? ? ? ? 111 seg38(* 2 ) o lcd segment pin ? ? ? ? ? ?? pa6(* 1 ) i/o input/output port ? ? ? ? ? ? 112 seg37(* 2 ) o lcd segment pin ? ? ? ? ? ?? pa7(* 1 ) i/o input/output port ? ? ? ? ? ? 113 seg36(* 2 ) o lcd segment pin ? ? ? ? ? ?? 69 com0 o lcd common pin ? ? ? ? ? ? 68 com1 o lcd common pin ? ? ? ? ? ? 67 com2 o lcd common pin ? ? ? ? ? ? 66 com3 o lcd common pin ? ? ? ? ? ? 70 seg0 o lcd segment pin ? ? ? ? ? ? 71 seg1 o lcd segment pin ? ? ? ? ? ? 72 seg2 o lcd segment pin ? ? ? ? ? ? 73 seg3 o lcd segment pin ? ? ? ? ? ? 74 seg4 o lcd segment pin ? ? ? ? ? ? 75 seg5 o lcd segment pin ? ? ? ? ? ? 76 seg6 o lcd segment pin ? ? ? ? ? ? 77 seg7 o lcd segment pin ? ? ? ? ? ? 78 seg8 o lcd segment pin ? ? ? ? ? ? 79 seg9 o lcd segment pin ? ? ? ? ? ? 80 seg10 o lcd segment pin ? ? ? ? ? ? 81 seg11 o lcd segment pin ? ? ? ? ? ? 82 seg12 o lcd segment pin ? ? ? ? ? ? 83 seg13 o lcd segment pin ? ? ? ? ? ? 84 seg14 o lcd segment pin ? ? ? ? ? ? 85 seg15 o lcd segment pin ? ? ? ? ? ? 86 seg16 o lcd segment pin ? ? ? ? ? ? 87 seg17 o lcd segment pin ? ? ? ? ? ? 88 seg18 o lcd segment pin ? ? ? ? ? ? 89 seg19 o lcd segment pin ? ? ? ? ? ? 90 seg20 o lcd segment pin ? ? ? ? ? ? 91 seg21 o lcd segment pin ? ? ? ? ? ? 92 seg22 o lcd segment pin ? ? ? ? ? ? 93 seg23 o lcd segment pin ? ? ? ? ? ? 94 seg24 o lcd segment pin ? ? ? ? ? ? 95 seg25 o lcd segment pin ? ? ? ? ? ? 96 seg26 o lcd segment pin ? ? ? ? ? ? 97 seg27 o lcd segment pin ? ? ? ? ? ? 98 seg28 o lcd segment pin ? ? ? ? ? ? 99 seg29 o lcd segment pin ? ? ? ? ? ? 100 seg30 o lcd segment pin ? ? ? ? ? ? 101 seg31 o lcd segment pin ? ? ? ? ? ? 102 seg32 o lcd segment pin ? ? ? ? ? ? 103 seg33 o lcd segment pin ? ? ? ? ? ? 104 seg34 o lcd segment pin ? ? ? ? ? ? 105 seg35 o lcd segment pin ? ? ? ? ? ? (* 1 ) pins on ML610Q411 and ml610q415. (* 2 ) pins on ml610q412. (* 3 ) ml610q415 does not have the low-speed crystal oscillation function, but xt pin must be tied to v ss .
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 16/36 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and v ss as required. ml610q415 does not have the crystal oscillation function, but connect xt0 to vss and non-connect xt1 on ml610q415. ? ? osc0 i high-speed external clock input pin. this pin is used as the secondary function of the p10. secondary ? lsclk o low-speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00-p03 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p10-p11 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose output port p20-p22 o general-purpose output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose input/output port p30-p35 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p40-p47 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive pa0-pa7 i/o general-purpose input/output port. these pins are for the ML610Q411 and ml610q415, but are not provided in the ml610q412. primary positive
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 17/36 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/se condary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the tertiary function of the p43 or p34 pin. tertiary positive t02p0ck o pwm0 external clock input pin. this pin is used as the primary function of the p44 pin. primary ? external interrupt nmi i external non-maskable interrupt input pin. an interrupt is generated on both edges. primary positive/ negative exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00-p03 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02p0ck i external clock input pin used for both timer 0 and timer 2. the clocks for these timers are selected by software. this pin is used as the primary function of the p44 pin. primary ? t13p1ck i external clock input pin used for both timer 1 and timer 3. the clocks for these timers are selected by software. this pin is used as the primary function of the p45 pin. primary ? buzzer bz0 o buzzer signal output pin. this pin is used as the secondary function of the p22 pin. secondary positive/ negative led drive led0-2 o nch open drain output pins to drive led. primary positive/ negative
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 18/36 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rct0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? successive approximation type a/d converter av ss ? negative power supply pin for successive approximation type a/d converter. ? ? av dd ? positive power supply pin for successive approximation type a/d converter. ? ? v ref ? reference power supply pin for successive approximation type a/d converter. ? ? ain0 i channel 0 analog input for successive approximation type a/d converter. ? ? ain1 i channel 1 analog input for successive approximation type a/d converter. ? ? lcd drive signal com0-3 o common output pins. ? ? seg0-35 o segment output pins. ? ? seg36-43 o segment output pin. these pins are for the ml610q412, but are not provided in the ML610Q411 and ml610q415. ? ? lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pins for lcd bias (internally generated). capacitors ca, cb, and cc (see measuring circuit 1) are connected between v ss and v l1 , v l2 , and v l3 , respectively. ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitors c12 is connected between c1 and c2. ? ? for testing test i/o input/output pin for testing. a pull-down resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin for i/o, internal regulator, battery low detector, and power-on reset. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors cl0 and cl1 (see measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? positive power supply pin (internally generated) for low-speed oscillation. when using ML610Q411 and ml610q412, connect capacitor cx (see measuring circuit 1) between this pin and v ss . connect this pin to vss directly when using ml610q415. ? ? v pp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. ? ?
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 19/36 termination of unused pins table 3 shows methods of terminating the unused pins. table 3 termination of unused pins pin recommended pin termination v pp open av dd v ss av ss v ss v ddx v ss (ml610q415) v ref v ss xt0 v ss (ml610q415) xt1 open(ml610q415) ain0, ain1 open v l1 , v l2 , v l3 open c1, c2 open reset_n open test open nmi open p00 to p03 v dd or v ss p10 to p11 v dd p20 to p22 open p30 to p35 open p40 to p47 open pa0 to pa7 open com0 to 3 open seg0 to 43 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 20/36 electrical characteristics absolute maximum ratings (v ss = av ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 ?c ? 0.3 to +4.6 v power supply voltage 2 av dd ta = 25 ?c ? 0.3 to +4.6 v power supply voltage 3 v pp ta = 25 ?c ? 0.3 to +9.5 v power supply voltage 4 v ddl ta = 25 ?c ? 0.3 to +3.6 v power supply voltage 5 v ddx ta = 25 ?c ? 0.3 to +3.6 v power supply voltage 6 v l1 ta = 25 ?c ? 0.3 to +1.75 v power supply voltage 7 v l2 ta = 25 ?c ? 0.3 to +3.5 v power supply voltage 8 v l3 ta = 25 ?c ? 0.3 to +5.25 v input voltage v in ta = 25 ?c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 ?c ? 0.3 to v dd +0.3 v output current 1 i out1 port3?a, ta = 25 ?c ? 12 to +11 ma output current 2 i out2 port2, ta = 25 ?c ? 12 to +20 ma power dissipation pd ta = 25 ? c 1.25 w storage temperature t stg ?? ? 55 to +150 ?c recommended operating conditions (v ss = av ss = 0v) parameter symbol condition range unit ML610Q411, ml610q412, ml610q415 ? ? 20 to +70 operating temperature t op ML610Q411p, ML610Q411pa, ml610q412p ? ? 40 to +85 ? ?c v dd ?? 1.1 to 3.6 operating voltage av dd ?? 2.2 to 3.6 v v dd = 1.1 to 3.6v 30k to 36k 46.9k to 78.1k ML610Q411, ml610q412 v dd = 1.3 to 3.6v 30k to 625k v dd = 1.1 to 3.6v 46.9k to 78.1k operating frequency (cpu) f op ml610q415 v dd = 1.3 to 3.6v 23k to 625k hz low-speed crystal oscillation frequency f xtl ML610Q411/ml610q412 ? 32.768k hz c dl ?? 0 to 12 low-speed crystal oscillation external capacitor c gl ?? 0 to 12 pf c l0 ?? 1.0 ? 30% capacitor externally connected to v ddl pin c l1 ?? 0.1 ? 30% ? f capacitor externally connected to v ddx pin c x ML610Q411/ml610q412 ? 0.1 ? 30% ? f capacitors externally connected to v l1, 2, 3 pins c 1, 2, 3 ?? 1.0 ? 30% ? f capacitors externally connected across c1 and c2 pins c 12 ?? 1.0 ? 30% ? f
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 21/36 operating conditions of flash rom (v ss = av ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 ?c v dd at write/erase *1 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase *1 7.7 to 8.3 v write cycles c ep ?? 80 cycles data retention y dr ?? 10 years *1 : those voltages must be supplied to v ddl pin and v pp pin when programming and eraseing flash rom. v pp pin has an internal pulldown resister. dc characteristics (1/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (1/5) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 ?c typ. ? 10% 500 typ. ? 10% khz 500khz rc oscillation frequency f rc v dd = 1.3 to 3.6v * 3 typ. ? 25% 500 typ. ? 25% khz low-speed crystal oscillation start time* 2 t xtl ?? ?? 0.3 2 s 500khz rc oscillation start time t rc ?? ?? 50 500 ? s low-speed oscillation stop detect time *1 t stop ?? 0.2 3 20 ms reset pulse width p rst ?? 200 ?? ?? reset noise elimination pulse width p nrst ?? ?? ?? 0.3 ? s power-on reset activation power rise time t por ?? ?? ?? 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. ML610Q411pc and ml610q415 does not have this characteristic. * 2 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 3 : recommended operating temperature :w (ta = ? 40 to +85 ? c for p version, ta = ? 20 to +70 ? c for non-p version) reset reset_n reset_n pin reset vdd 0.9xv dd 0.1xv dd t por power on reset p rst vil1 vil1
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 22/36 dc characteristics (2/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (2/5) rating parameter symbol condition min. typ. max. unit measuring circuit cn4?0 = 00h 0.89 0.94 0.99 cn4?0 = 01h 0.91 0.96 1.01 cn4?0 = 02h 0.93 0.98 1.03 cn4?0 = 03h 0.95 1.00 1.05 cn4?0 = 04h 0.97 1.02 1.07 cn4?0 = 05h 0.99 1.04 1.09 cn4?0 = 06h 1.01 1.06 1.11 cn4?0 = 07h 1.03 1.08 1.13 cn4?0 = 08h 1.05 1.10 1.15 cn4?0 = 09h 1.07 1.12 1.17 cn4?0 = 0ah 1.09 1.14 1.19 cn4?0 = 0bh 1.11 1.16 1.21 cn4?0 = 0ch 1.13 1.18 1.23 cn4?0 = 0dh 1.15 1.20 1.25 cn4?0 = 0eh 1.17 1.22 1.27 cn4?0 = 0fh 1.19 1.24 1.29 cn4?0 = 10h 1.21 1.26 1.31 cn4?0 = 11h 1.23 1.28 1.33 cn4?0 = 12h 1.25 1.30 1.35 cn4?0 = 13h 1.27 1.32 1.37 cn4?0 = 14h 1.29 1.34 1.39 cn4?0 = 15h 1.31 1.36 1.41 cn4?0 = 16h 1.33 1.38 1.43 cn4?0 = 17h 1.35 1.40 1.45 cn4?0 = 18h 1.37 1.42 1.47 cn4?0 = 19h 1.39 1.44 1.49 cn4?0 = 1ah 1.41 1.46 1.51 cn4?0 = 1bh 1.43 1.48 1.53 cn4?0 = 1ch 1.45 1.50 1.55 cn4?0 = 1dh 1.47 1.52 1.57 cn4?0 = 1eh 1.49 1.54 1.59 v l1 voltage v l1 v dd = 3.0v, tj = 25 ?c cn4?0 = 1fh 1.51 1.56 1.61 v v l1 temperature deviation * 1 ? v l1 v dd = 3.0v ? ????? ? mv/ ?c v l1 voltage dependency * 1 ? v l1 v dd = 1.3 to 3.6v ?? 5 20 mv/v v l2 voltage v l2 typ. ? 10% v l1 ? 2 typ. +4% v l3 voltage v l3 v dd = 3.0v, tj = 25 ?c 1m ? load (v l3 ? v ss ) typ. ? 10% v l1 ? 3 typ. +4% v lcd bias voltage generation time t bias ?? ?? ?? 600 ms 1 * 1 :v l1 can not exceed v dd level. the maximum v l1 becomes v dd level when the v l1 calculated by the temperature deviation and voltage dependency is going to exceed the v dd level.
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 23/36 dc characteristics (3/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (3/5) rating parameter symbol condition min. typ. max. unit measuring circuit ld3?0 = 0h 1.35 ld3?0 = 1h 1.4 ld3?0 = 2h 1.45 ld3?0 = 3h 1.5 ld3?0 = 4h 1.6 ld3?0 = 5h 1.7 ld3?0 = 6h 1.8 ld3?0 = 7h 1.9 ld3?0 = 8h 2.0 ld3?0 = 9h 2.1 ld3?0 = 0ah 2.2 ld3?0 = 0bh 2.3 ld3?0 = 0ch 2.4 ld3?0 = 0dh 2.5 ld3?0 = 0eh 2.7 bld threshold voltage v bld v dd = 1.35 to 3.6v ld3?0 = 0fh typ. ? 2% 2.9 typ. +2% v bld threshold voltage temperature deviation ? v bld v dd = 1.35 to 3.6v ?? ?? ? %/ ?c 1 ta= 25 ?c ?? 0.15 0.5 supply current 1 idd1 cpu: in stop state. low-speed/high-speed rc500khz oscillation: stopped. * 7 ?? ? 2.5 ? a ta= 25 ?c ?? 0.5 1.3 supply current 2-1* 5 idd2-1 cpu: in halt state (ltbc and wdt are operating. low speed oscillation stop detector is stopped).* 3 * 4 high-speed 500khz oscillation: stopped. lcd and bias circuits: stopped. * 7 ?? ? 3.5 ? a ta= 25 ?c ?? 5.5 12 supply current 2-2* 6 idd2-2 cpu: in halt state (ltbc and wdt are operating. low speed oscillation stop detector is stopped).* 3 * 4 high-speed oscillation: oscillating. lcd and bias circuits: stopped. * 7 ?? ? 16 ? a ta= 25 ?c ?? 1.28 1.6 supply current 3-1* 5 idd3-1 cpu: in halt state (ltbc and wdt are operating. low speed oscillation stop detector is stopped).* 3 high-speed 500khz oscillation: stopped. lcd and bias circuits: operating. * 2 * 7 ?? ? 11 ? a ta= 25 ?c ?? 6.28 18 supply current 3-2* 6 idd3-2 cpu: in halt state (ltbc and wdt are operating. low speed oscillation stop detector is stopped).* 3 high-speed 500khz oscillation: oscillating. lcd and bias circuits: operating. * 2 * 7 ?? ? 23.5 ? a ta= 25 ?c ?? 5.5 7 supply current 4* 5 idd4 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz oscillation: stopped. lcd and bias circuits: operating. * 2 * 7 ?? ? 12 ? a 1
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 24/36 ta= 25 ?c ?? 80 90 supply current 5 idd5 cpu: in rc 500khz operating state. lcd and bias circuits: operating. * 2 * 7 ?? ? 100 ? a ta= 25 ?c ?? 0.4 0.5 supply current 6 idd6 cpu: in rc 500khz operating state.* 2 lcd and bias circuits: operating. * 2 a/d: in operating state. v dd = av dd = 3.0v * 7 ?? ? 0.6 ma 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 4 : significant bits of blkcon0~blkcon4 registers are all ?1?. * 5 : ML610Q411 and ml610q412 * 6 : ml610q415 * 7 : recommended operating temperature :w (ta = ? 40 to +85 ? c for p version, ta = ? 20 to +70 ? c for non-p version) dc characteristics (4/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (4/5) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ?? ?? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ?? ?? voh1 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 ?? ?? iol1 = +0.5ma, v dd = 1.8 to 3.6v ?? ?? 0.5 iol1 = +0.1ma, v dd = 1.3 to 3.6v ?? ?? 0.5 output voltage 1 (p20?p22/2 nd function is selected) (p30?p36) (p40?p47) (pb0?pb7) *1 vol1 iol1 = +0.03ma, v dd = 1.1 to 3.6v ?? ?? 0.3 ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ?? ? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ? ?? ? voh1 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 ? ?? ? output voltage 2 (p20?p22/2 nd function is not selected) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ?? ?? 0.5 output voltage 3 (p40?p41) vol3 iol3 = +3ma, v dd = 2.0 to 3.6v (when i 2 c mode is selected) ?? ?? 0.4 voh4 ioh4 = ? 0.2ma, vl1=1.2v v l3 ? 0.2 ?? ?? vomh4 iomh4 = +0.2ma, vl1=1.2v ?? ?? v l2 +0.2 vom4s iom4s = ? 0.2ma, vl1=1.2v v l2 ? 0.2 ?? ?? voml4 ioml4 = +0.2ma, vl1=1.2v ?? ?? v l1 +0.2 voml4s ioml4s = ? 0.2ma, vl1=1.2v v l1 ? 0.2 ?? ?? output voltage 4 (com0?3) (seg0?35) *1 (seg0?43) *2 vol4 iol4 = +0.2ma, vl1=1.2v ?? ?? 0.2 v 2 iooh voh = v dd (in high-impedance state) ?? ?? 1 output leakage (p20?p22) (p30?p35) (p40?p47) (pa0?pa7) *1 iool vol = v ss (in high-impedance state) ? 1 ?? ?? ? a 3
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 25/36 iih1 vih1 = v dd 0 ?? 1 v dd = 1.3 to 3.6v ? 600 ? 300 -10 input current 1 (reset_n) iil1 vil1 = v ss v dd = 1.1 to 3.6v ? 600 ? ? 300 ? -2 v dd = 1.3 to 3.6v 10 ? 300 ? 600 iih1 vih1 = v dd v dd = 1.1 to 3.6v 2 ? 300 ? 600 input current 1 (test) iil1 vil1 = v ss -1 ???? v dd = 1.3 to 3.6v 0.2 30 200 iih2 vih2 = v dd (when pulled-down) v dd = 1.1 to 3.6v 0.01 30 200 v dd = 1.3 to 3.6v ? 200 ? 30 -0.2 iil2 vil2 = v ss (when pulled-up) v dd = 1.1 to 3.6v ? 200 ? ? 30? -0.01 iih2z vih2 = v dd (in high-impedance state) ?? ?? 1 input current 2 (nmi) (p00-p03) (p10-p11) (p30-p35) (p40-p47) (pa0-pa7) *1 iil2z vil2 = v ss (in high-impedance state) ? 1 ?? ?? ? a 4 *1: ML610Q411 and ml610q415 *2: ml610q412 dc characteristics (5/5) ) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (5/5) rating parameter symbol condition min. typ. max. unit measuring circuit v dd = 1.3 to 3.6v ?? 0.7 ? v dd ?? v dd vih1 v dd = 1.1 to 3.6v ? 0.7 ? v dd ?? v dd v dd = 1.3 to 3.6v ?? 0 ?? 0.3 ? v dd input voltage 1 (reset_n) (test) (nmi) (p00?p03) (p10?p11) (p31?p35) (p40?p43) (p45?p47) (pa0?pa7) *1 vil1 v dd = 1.1 to 3.6v ? 0 ?? 0.2 ? v dd v dd = 2.0 to 3.6v 0.05 ? v dd 0.18 ? v dd 0.4 ? v dd hysteresis width (reset_n) (test_n) (nmi) (p00?p03) (p10?p11) (p31?p35) (p40?p43) (p45?p47) (pa0?pa7) *1 ? vt v dd = 1.1 to 3.6v 0.02 ? v dd 0.18 ? v dd 0.4 ? v dd vih2 ? 0.7 ? v dd ? v dd input voltage 2 (p30, p44) vil2 ?? 0 ?? 0.3 ? v dd v 5 input pin capacitance (nmi) (p00?p03) (p10?p11) (p30?p35) (p40?p47) (pa0?pa7) *1 cin f = 10khz v rms = 50mv ta = 25 ?c ?? ?? 5 pf ?? *1: ML610Q411 and ml610q415
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 26/36 hysteresis width ? v t input signal internal signal v dd v ss v ss v ddl
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 27/36 measuring circuits measuring circuit 1 measuring circuit 2 input pins v v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v ss av ss vih vil output pins (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. (*2) (*1) c v : 1 ? f c l0 : 1 ? f c l1 : 0.1 ? f c x : 0.1 ? f c a ,c b ,c c ,c d : 1 ? f c 12 ,c 34 : 1 ? f 32.768khz crystal: c-001r (epson toyocom) xt0 xt1 p10/osc0 32.768khz crystal a v dd av dd v ref v ddl v ddx c l1 c l0 c x v l1 c a v l2 c b v l3 c c v ss av ss c2 c1 c 12 c v xt0 xt1 p10/osc0 a v dd av dd v ref v ddl v ddx c l1 c l0 c x v l1 c a v l2 c b v l3 c c v ss av ss c2 c1 c 12 c v ML610Q411 and ml610q412 ml610q415
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 28/36 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pins a v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v ss av ss output pins *3: measured at the specified output pins. (*3) input pins v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v ss av ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring input pins a v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v ss av ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) rs1
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 29/36 ac characteristics (external interrupt) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ?? 106.8 ? s ac characteristics (serial port) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ?? ?? brt* 1 ?? s receive baud rate t rbrt ?? brt* 1 ? 3% brt* 1 brt* 1 +3% s *1: baud rate period (including the error of the clock freq uency selected) set with the serial port baud rate register (siobrtl,h) and the serial port mode register 0 (siomod0). t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) nmi, p00?p03 (both-edge interrupt) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 30/36 ac characteristics (synchronous serial port) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit sclk input cycle (slave mode) t scyc when high-speed oscillation is not active 10 ?? ?? ? s sclk output cycle (master mode) t scyc ?? ?? sclk* 1 ?? s sclk input pulse width (slave mode) t sw when high-speed oscillation is not active 4 ?? ?? ? s sclk output pulse width (master mode) t sw ?? sclk* 1 ? 0.4 sclk* 1 ? 0.5 sclk* 1 ? 0.6 s sout output delay time (slave mode) t sd ?? ?? ?? 500 ns sout output delay time (master mode) t sd ?? ?? ?? 500 ns sin input setup time (slave mode) t ss ?? 80 ?? ?? ns sin input setup time (master mode) t ss ?? 500 ?? ?? ns sin input hold time t sh ?? 300 ?? ?? ns *1: clock period selected with s0ck3?0 of the serial port 0 mode register (sio0mod1) t sd sclk0* sin0* sout0* *: indicates the secondar y function of the p ort. t sd t ss t sh t sw t sw t scyc
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 31/36 ac characteristics (i 2 c bus interface: standard mode) (v dd = 1.8 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ?? ? 50?? khz scl hold time (start/restart condition) t hd:sta ?? 4.0 ?? ?? ? s scl ?l? level time t low ?? 4.7 ?? ?? ? s scl ?h? level time t high ?? 4.0 ?? ?? ? s scl setup time (restart condition) t su:sta ?? 4.7 ?? ?? ? s sda hold time t hd:dat ?? 0 ?? ? ? s sda setup time t su:dat ?? 0.25 ?? ?? ? s sda setup time (stop condition) t su:sto ?? 4.0 ?? ?? ? s bus-free time t buf ?? 4.7 ?? ?? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 32/36 ac characteristics (rc oscillation a/d converter) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resistors for oscillation rs0, rs1, rt0, rt0-1,rt1 cs0, ct0, cs1 ? 740pf 1 ?? ?? k ? f osc1 resistor for oscillation = 1k ? 209.4 330.6 435.1 khz f osc2 resistor for oscillation = 10k ? 41.29 55.27 64.16 khz oscillation frequency vdd = 1.5v f osc3 resistor for oscillation = 100k ? 4.71 5.97 7.06 khz kf1 rt0, rt0-1, rt1 = 1khz 5.567 5.982 6.225 ? ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? ? rs to rt oscillation frequency ratio *1 vdd = 1.5v kf3 rt0, rt0-1, rt1 = 100khz 0.104 0.108 0.118 ? ? f osc1 resistor for oscillation = 1k ? 407.3 486.7 594.6 khz ? f osc2 resistor for oscillation = 10k ? 49.76 59.28 72.76 khz ? oscillation frequency vdd = 3.0v f osc3 resistor for oscillation = 100k ? 5.04 5.993 7.04 khz ? kf1 rt0, rt0-1, rt1 = 1khz 8.006 8.210 8.416 ? ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? ? rs to rt oscillation frequency ratio *1 vdd = 3.0v kf3 rt0, rt0-1, rt1 = 100khz 0.100 0.108 0.115 ? ? *1: kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. f oscx (rt0 ? cs0 oscillation) f oscx (rt0-1 ? cs0 oscillation) f oscx (rt1 ? cs1 oscillation) kfx = f oscx (rs0 ? cs0 oscillation) , f oscx (rs0 ? cs0 oscillation) , f oscx (rs1 ? cs1 oscillation) (x = 1, 2, 3) note: - please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. - please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. v dd av dd v ref v ddl v ddx c l1 c l0 c x v ss av ss c v rt0, rt0-1, rt1: 1k ? /10k ? /100k ? rs0, rs1: 10k ? cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pins vih vil *1: input logic circuit to determine the specified measuring conditions. (*1) cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 33/36 electrical characteristics of successive approximation type a/d converter (v dd = 1.8 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n ?? ?? ?? 12 bit 2.7v ? v ref ? 3.6v ? 4 ?? +4 integral non-linearity error idl 2.2v ? v ref ? 2.7v ? 6 ?? +6 2.7v ? v ref ? 3.6v ? 3 ?? +3 differential non-linearity error dnl 2.2v ? v ref ? 2.7v ? 5 ?? +5 zero-scale error v off ?? ? 6 ?? +6 full-scale error fse ?? ? 6 ?? +6 lsb reference voltage v ref ?? 2.2 ?? av dd v conversion time t conv ? ?? 23* 1 ?? ? /ch ? : period of high-speed clock (hsclk) * 1 : 2 ??? ch is required as an interval time for each conversion in the case of consecutive a/d conversion. a v dd av dd v ref v ddl v ddx v ss av ss analog input 1 ? f ?? ri ? 5k ? 0.1 ? f 0.1 ? f ain0, ain1 10 ? f 0.1 ? f + 1 ? f reference voltage
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 34/36 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 35/36 revision history page document no. date previous edition current edition description fedl610q411-01 jul.17,2010 ? ? formally edition 1 3, 4, 21 3, 4, 21 add the explanation of ML610Q411pc. fedl610q411-02 mar.23,2011 34 34 replace the package dimension (only the format is changed. package size and material are not changed.)
fedl610q411-02 lapis semiconductor ML610Q411/ml610q412/ml610q415 36/36 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such in formation, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be us ed with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the pr oducts safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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