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ltc4352 1 4352fa typical a pplica t ion descrip t ion low voltage ideal diode controller with monitoring the ltc ? 4352 creates a near-ideal diode using an external n-channel mosfet. it replaces a high power schottky diode and the associated heat sink, saving power and board area. the ideal diode function permits low loss power oring and supply holdup applications. the ltc4352 regulates the forward voltage drop across the mosfet to ensure smooth current transfer in diode- or applications. a fast turn-on reduces the load voltage droop during supply switch-over. if the input supply fails or is shorted, a fast turn-off minimizes reverse currents. the controller operates with supplies from 2.9v to 18v. for lower voltages, an external supply is needed at the v cc pin. power passage is disabled during undervoltage or overvoltage conditions. the controller also features an open mosfet detect circuit that flags excessive voltage drop across the pass transistor in the on state. a rev pin enables reverse current, overriding the diode behavior when desired. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 2.9v to 18v ideal diode fea t ures a pplica t ions n low loss replacement for power diode n controls n-channel mosfet n 0v to 18v supply oring or holdup n 0.5s turn-on and turn-off time n undervoltage and overvoltage protection n open mosfet detect n status and fault outputs n hot swappable n reverse current enable input n 12-pin msop and dfn (3mm 3mm) packages n redundant power supplies n supply holdup n telecom infrastructure n computer systems and servers v cc uv ov rev ltc4352 status fault mosfet on status 0.1f* to load 2.9v to 18v si7336adp *optional fault 0.1f 4352 ta01 cpo v in source gate gnd out power dissipation vs load current load current (a) 0 0 power dissipation (w) 2.5 2.0 1.5 1.0 0.5 4.0 3.0 3.5 2 4 6 8 4352 ta01b 10 diode (sbg1025l) mosfet (si7336adp) power saved
ltc4352 2 4352fa a bsolu t e maxi m u m r a t ings v in , source voltages ................................... C2v t o 24v v cc voltage .................................................. C 0.3v to 7v out voltage ................................................... C2 v to 24v cpo, gate voltages (note 3) ..................... C 0.3v to 30v cpo d.c. current ................................................... 10 ma uv, ov, rev voltages ................................ C 0.3v to 24v fa u lt , status voltages ............................ C 0.3v to 24v (notes 1, 2) o r d er i n f or m a t ion fa u lt , status currents .......................................... 5m a operating ambient temperature range ltc4352c ................................................ 0 c to 70c ltc4352i ............................................. C 40c to 85c ltc4352h .......................................... C4 0c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ms package ...................................................... 3 00c p in c on f igura t ion lead free finish tape and reel part marking* package description temperature range ltc4352cdd#pbf ltc4352cdd#trpbf ldpj 12-pin (3mm 3mm) plastic dfn 0c to 70c ltc4352idd#pbf ltc4352idd#trpbf ldpj 12-pin (3mm 3mm) plastic dfn C40c to 85c ltc4352hdd#pbf ltc4352hdd#trpbf ldpj 12-pin (3mm 3mm) plastic dfn C40c to 150c ltc4352cms#pbf ltc4352cms#trpbf 4352 12-lead plastic msop 0c to 70c ltc4352ims#pbf ltc4352ims#trpbf 4352 12-lead plastic msop C40c to 85c ltc4352hms#pbf ltc4352hms#trpbf 4352 12-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ top view dd package 12-pin (3mm 3mm) plastic dfn 12 13 11 8 9 10 4 5 3 2 1 source gate cpo gnd out rev v in v cc uv ov status fault 6 7 1 2 3 4 5 6 v in v cc uv ov status fault 12 11 10 9 8 7 source gate cpo gnd out rev top view ms package 12-lead plastic msop t jmax = 150c, ja = 43c/w exposed pad (pin 13) pcb gnd connection optional t jmax = 150c, ja = 164c/w
ltc4352 3 4352fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, v source = v in , v out = v in , v cc open, unless otherwise noted. symbol parameter conditions min typ max units supplies v in input operating range with external 2.9v to 4.7v v cc supply with external 4.7v to 6v v cc supply l l l 2.9 0 0 18 v cc 18 v v v v cc(ext) v cc external supply range l 2.9 6 v v cc(int) v cc internal regulator voltage l 3.5 4.1 4.7 v i in v in supply current v in = 0v, v cc = 5v, v out = 18v v in = 0v, v cc = 5v, v out = 18v (ltc4352h) l l l 1.4 C10 C10 3 C13 C25 ma a a i cc external v cc supply current v cc = 5v, v in = 0v l 1.25 2.5 ma v cc(uvlo) v cc undervoltage lockout threshold v cc rising l 2.45 2.57 2.7 v v cc(hyst) v cc undervoltage lockout hysteresis l 50 70 90 mv ideal diode control v fwd(reg) forward regulation voltage (v in ? v out ) l 10 25 40 mv v gate mosfet gate drive (v gate C v source ) v fwd = 0.1v, i = 0 and C1a l 5 6.1 7.5 v t on(gate) gate turn-on delay c gate = 10nf, v fwd = 0.2v l 0.25 0.5 s t off(gate) gate turn-off delay c gate = 10nf, v fwd = ?0.2v l 0.2 0.5 s input/output pins v uv,ov(th) uv, ov threshold voltage v uv falling, v ov rising l 490 500 510 mv v uv,ov(hyst) uv, ov threshold hysteresis l 2.5 5 8.5 mv v rev(th) rev threshold voltage (ltc4352h) l l 0.8 0.8 1.0 1.0 1.2 1.25 v v i uv,ov uv, ov current v = 0.5v l 0 1 a i rev rev current v rev = 1v l 7 10 13 a i out out current v out = 0v, 12v l C13 200 a i source source current v source = 0v l C85 C130 a i cpo(up) cpo pull-up current v cpo = v in = 2.9v v cpo = v in = 18v l l C60 C50 C90 C75 C115 C100 a a i gate gate fast pull-up current gate fast pull-down current gate off pull-down current v fwd = 0.2v, v gate = 0v, v cpo = 17v v fwd = C0.2v, v gate = 5v v uv = 0v, v gate = 2.5v l 60 C1.5 1.5 100 145 a a a i flt,stat(in) status , fault leakage current v = 18v l 0 1 a i flt,stat(up) status , fault pull-up current v = 0v l C8 C10 C12 a v ol status , fault output low voltage i = 1.25ma l 0.2 0.4 v v oh status , fault output high voltage i = C1a l v cc C 1 v cc C 0.5 v v gate(st) mosfet on detect threshold status pulls low, v fwd = 50mv sta tus pulls low, v fwd = 50mv (ltc4352h) l l 0.3 0.28 0.7 0.7 1.1 1.1 v v v fwd(flt) open mosfet threshold (v in C v out ) fault pulls low l 200 250 300 mv note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. note 3: internal clamps limit the gate and cpo pins to a minimum of 5v above, and a diode below source. driving these pins to voltages beyond the clamp may damage the device.
ltc4352 4 4352fa typical p er f or m ance c harac t eris t ics out current vs voltage cpo voltage vs current gate voltage vs current status , fault output low voltage vs current status , fault output high voltage vs current v in current vs voltage v in current vs voltage with external v cc v cc current vs voltage t a = 25c, v in = 12v, v source = v in , v out = v in , v cc open, unless otherwise noted. v in (v) 0 0 i in (ma) 0.4 0.8 1.6 3 6 9 12 4352 g01 15 18 1.2 v in (v) 0 ?50 i in (a) 50 0 100 150 300 1 2 3 4 4352 g02 5 250 200 v cc = 5v v cc (v) 0 0 i cc (ma) 0.50 0.25 0.75 1.00 1.50 1 2 3 4 4352 g03 65 1.25 v in = 0v v out (v) 0 ?50 i out (a) 100 50 0 150 200 300 3 6 9 12 4352 g04 1815 250 i cpo (a) 0 ?1 v cpo ?v source (v) 2 1 0 3 4 7 ?20 ?40 ?60 ?80 4352 g05 ?120 ?100 5 6 v in = 2.9v v in = 18v i gate (a) 0 ?1 v gate ?v source (v) 2 1 0 3 4 7 ?20 ?40 ?60 ?80 4352 g06 ?120 ?100 5 6 v in = 2.9v v in = 18v v out = v in ? 0.1v current (ma) 0 0 v ol (v) 0.6 0.4 0.2 1 0.8 1 2 3 4 4352 g07 5 current (a) 0 0 v oh (v) 2.5 2.0 1.5 1.0 0.5 4.0 3.0 3.5 ?2 ?4 ?6 ?8 4352 g08 ?10 ?12
ltc4352 5 4352fa p in func t ions v in (pin 1): voltage sense and supply input. connect this pin to the power input side of the mosfet. the low voltage supply v cc is generated from v in . the voltage sensed at this pin is used to control the mosfet gate. v cc (pin 2): low voltage supply. connect a 0.1f capacitor from this pin to ground. when v in 2.9v, this pin provides decoupling for an internal regulator that generates a 4.1v supply. for applications where v in < 2.9v, connect an external supply voltage in the range 2.9v to 6v to this pin. uv (pin 3): undervoltage comparator input. connect this pin to an external resistive divider from v in . if the volt- age at this pin falls below 0.5v, an undervoltage fault is detected and the mosfet is turned off. the comparator has a built-in hysteresis of 5mv. tie to v cc if unused. ov (pin 4): overvoltage comparator input. connect this pin to an external resistive divider from v in . if the volt- age at this pin rises above 0.5v, an overvoltage fault is detected and the mosfet is turned off. the comparator has a built-in hysteresis of 5mv. tie to gnd if unused. status (pin 5): mosfet status output. this pin is pulled low by an open-drain output when the external mosfet is on. an internal 10a current source pulls this pin up to a diode below v cc . it may be pulled above v cc using an external pull-up. tie to gnd or leave open if unused. fault (pin 6): fault output. this pin is pulled low by an open-drain output when a fault occurs. this fault could either be an undervoltage fault, an overvoltage fault, or an open mosfet fault. the external mosfet is turned off for undervoltage and overvoltage faults, while it is left on for open mosfet fault. an internal 10a current source pulls this pin up to a diode below v cc . it may be pulled above v cc using an external pull-up. tie to gnd or leave open if unused. rev (pin 7): reverse current enable input. connect this pin to gnd for normal diode operation that blocks reverse current. driving this pin above 1v fully turns on the mosfet gate to allow reverse current. an internal 10a current source pulls this pin to gnd. out (pin 8): output voltage sense input. connect this pin to the output side of the mosfet. the voltage sensed at this pin is used to control the mosfet gate. gnd (pin 9): device ground. cpo (pin 10): charge pump output. connect a capacitor from this pin to the source pin. the value of this capaci- tor is approximately 10x the gate capacitance (c iss ) of the mosfet switch. the charge stored on this capacitor is used to pull-up the gate during a fast turn-on. leave this pin open if fast turn-on is not needed. gate (pin 11): mosfet gate drive output. connect this pin to the gate of the external n-channel mosfet switch. an internal clamp limits the gate voltage to 6.1v above, and a diode below source. during fast turn-on a 1.5a pull-up charges gate to cpo. during fast turn-off a 1.5a pull-down discharges gate to source. source (pin 12): mosfet gate drive return. connect this pin to the source of the external n-channel mosfet switch. exposed pad (pin 13, dd package only): exposed pad may be left open or connected to device ground.
ltc4352 6 4352fa ? + cp4 disable ldo v in 0.5v cp2 cp1 cp3 ov fault *dd package only gnd m2 10a v cc exposed pad* fault status rev out source gate cpo 100a uv fault z v cc low 2.57v uv ov ? + ? + ? + ? + open mosfet detect m1 10a v cc cp6 cp5 enable reverse current 0.7v 1v source gate gate off ? + + ? ? + ? + + ? charge pump f = 3mhz v cc v in v cc 25mv amp ldo 4352 fd 10a 1 2 10 11 12 8 7 5 13 9 4 3 6 4.1v func t ional diagra m
ltc4352 7 4352fa o pera t ion the ltc4352 controls either single or back-to-back n-channel mosfets in order to emulate an ideal diode. dual mosfets eliminate current flow from the input to the output in an input undervoltage or overvoltage condition. when enabled, an amplifier (amp) monitors the voltage between the v in and out pins, and drives the gate pin. the amplifier controls the gate of the external mosfet to servo its forward voltage drop (v in C out) to 25mv. the gate voltage rises to enhance the mosfet if the load current causes more than 25mv of drop. for large output currents the mosfet gate is driven fully on and the voltage drop is equal to i load ? r ds(on) . in the case of an input supply short-circuit, when the mosfet is conducting, a large reverse current starts flowing from the load towards the input. the amp detects this failure condition as soon as it appears, and turns off the mosfet by pulling down the gate pin. the rev pin can be used to allow reverse current, overriding the diode behavior. the amp quickly pulls-up the gate pin whenever it senses a large forward voltage drop. an external capacitor between the cpo and source pins is needed for fast gate pull-up. this capacitor is charged up, at device power-up, by the internal charge-pump. this stored charge is used for the fast gate pull-up. the gate pin sources current from the cpo pin, and sinks current to the source and gnd pins. internal clamps limit the gate to source voltage to 6.1v, and the cpo to source voltage to 6.7v. the same clamps also limit the cpo and gate pins to a diode voltage below the source pin. ov, uv, and v cc comparators, cp1 to cp3, control power passage. the mosfet is held off whenever the ov pin is above 0.5v, the uv pin is below 0.5v, or the v cc pin is below 2.57v. there is a 40s delay from all three condi - tions becoming good to gate being allowed to turn on. overvoltage causes a fast turn-off, while undervoltage activates a 100a pull-down on gate after a 7s delay. open-drain pull-down, m1, pulls the status pin low when the gate to source voltage exceeds 0.7v, to indicate that power is passing through the mosfet. the fault output, m2, pulls low during an undervoltage or overvoltage fault condition. it also pulls low when gate is fully on and the forward voltage drop exceeds 250mv, indicating the mosfet has too much current or has failed open circuit. note that this open mosfet fault does not turn off the mosfet unlike the undervoltage and overvoltage faults. ldo is a low dropout regulator that generates a 4.1v supply at the v cc pin from the v in input. when a supply below 2.9v is being ored, an external supply in the 2.9v to 6v range is required at the v cc pin. comparator cp4 will disable ldo when v in is below v cc .
ltc4352 8 4352fa high availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. oring diodes have been a popular means of connecting these supplies at the point of load. diodes with storage capacitors also hold up supply voltages when an input voltage sags or has a brownout. the disadvantage of these approaches is the diodes significant forward voltage drop and the resulting power loss. additionally, diodes provide no information concerning the status of the sourcing supply. separate control must therefore be added to ensure that a supply that is out of range is not allowed to affect the load. the ltc4352 solves these problems by using an external n-channel mosfet as the pass element (see figure 1). the mosfet is turned on when power is being passed, allowing for a low voltage drop from the supply to the load. when the input source voltage drops below the output common supply voltage it turns off the mosfet, thereby matching the function and performance of an ideal diode. power supply configuration the ltc4352 can operate with supplies down to 0v. this requires powering the v cc pin with an always present external supply in the 2.9v to 6v range. if not always present, a series 470 resistor or schottky diode limits device power dissipation and backfeeding of low v cc supply when v in is high. for a 2.9v to 4.7v v cc supply, v in should be lower than v cc . a 0.1f bypass capacitor should also be connected between the v cc and gnd pins, close to the device. figure 2 illustrates this. if v in operates above 2.9v then the external supply at v cc is not needed. the 0.1f capacitor is still required for bypassing. a pplica t ions i n f or m a t ion figure 1. 12v ideal diode with status and fault indicators v cc uv ov rev ltc4352 status fault 0.1f c2 r4 2.7k d1 d1: green led ln1351c d2: red led ln1261cal mosfet on fault d2 r5 2.7k c1 to load 12v q1 si7336adp 0.1f 4352 f01 cpo v in source gate gnd out figure 2. power supply configurations v cc ltc4352 to load 0v to v cc v in gate out 0.1f 2.9v to 4.7v gnd v cc ltc4352 to load 0v to 18v 4352 f02 v in gate out gnd v cc ltc4352 to load 2.9v to 18v v in gate out 0.1f gnd 0.1f 4.7v to 6v
ltc4352 9 4352fa figure 3. start-up waveform for single mosfet application voltage (5v/div) time (2.5ms/div) 4352 fo3 cpo gate out v in , source v cc v in = 5v c2 = 0.1f applica t ions in f or m a t ion n-channel mosfets. the maximum allowable drain-source voltage, bv dss , must be higher than the supply voltages as the full supply voltage can appear across the mosfet when the input falls to 0v. the fault pin pulls low to signal an open mosfet fault whenever the forward voltage drop across the enhanced mosfet exceeds 250mv. the r ds(on) should be small enough to conduct the maximum load current while not triggering such a fault (when using fault ), and to stay within the mosfets power rating at the maximum load current. cpo capacitor selection the recommended value of the capacitor between the cpo and source pins is approximately 10x the input capacitance, c iss , of the mosfet. a larger capacitor takes a correspondingly longer time to charge up by the internal charge pump. a smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the mosfet gate capacitance. cpo and gate start-up in single mosfet applications, cpo is initially pulled up to a diode below the source pin (figure 3). in back-to- back mosfet applications, cpo starts off at 0v, since source is near ground (figure 4). cpo starts ramping up 10s after v cc clears its undervoltage lockout level. another 40s later, gate will also start ramping up with cpo if uv, ov and v in C out conditions allow it to. the ramp rate is decided by the cpo pull-up current into the combined cpo and gate pin capacitances. an internal clamp limits the cpo voltage to 6.7v above source, while the final gate voltage is determined by the forward drop servo amplifier. mosfet selection the ltc4352 drives n-channel mosfets to conduct the load current. the important features of the mosfet are its threshold voltage, the maximum drain-source voltage bv dss , and the on-resistance r ds(on) . the gate drive for the mosfet is guaranteed to be between 5v and 7.5v. this allows the use of logic level threshold figure 4. start-up waveform for back-to-back mosfet application voltage (5v/div) time (2.5ms/div) 4352 fo4 cpo gate out v in v cc v in = 5v c2 = 0.1f
ltc4352 10 4352fa a pplica t ions i n f or m a t ion figure 6. inrush and ideal diode control on a hot swap card ltc4352 plug-in card connectors backplane q2 si7336adp q1 si7336adp to load nc 4352 f06 v in uv cpo ov source gate out gnd 12v gnd 105k 0.1f c g 10k r6 10 r g 5.11k r2 r3 z1 z1: diodes inc. smaj12a inrush control the ltc4352 can be used for inrush control in applications where the input supply is hot-plugged. see figure 6. the cpo capacitor is omitted, since fast turn-on with stored charge is not desired here. undervoltage holds the gate off till the short pin makes contact. 40s after the uv level is satisfied, the mosfet gate ramps up due to the cpo pull-up current. a rc network on the gate further slows down the output dv/dt, while allowing fast turn-off during reverse current or overvoltage conditions. resistor r g prevents high frequency oscillations in q2. a dedicated hot swap controller may be needed if overcurrent protec - tion is also desired. undervoltage and overvoltage protection unlike a regular diode, the ltc4352 can prevent out of range input voltages from affecting the load voltage. this requires back-to-back mosfets, and resistive dividers from the input to the uv and ov pins. for an example, see figure 5. mosfet q2 is required to block conduction through the body diode of q1 when its gate is held off. the resistive dividers set up the input voltage range where the ideal diode control is allowed to operate. outside this range, the gate is held off and the fault pin pulls low. when using a cpo capacitor in circuit with back-to-back mosfets, there will be a large inrush current to the load capacitance due to the fast gate turn-on after uv, ov levels are met. without the capacitor, the inrush will depend on the cpo pull-up current charging up the gate capacitance. figure 5. 5v ideal diode with uv and ov protection uv ltc4352 fault status v cc 31.6k 1% 1k 1% 3.09k 1% c1 to load 5v q2 si7336adp q1 si7336adp 0.1f 4352 f05 cpo v in source gate out 0.15f c2 rev gnd r2 r1 r3 ov
ltc4352 11 4352fa source ltc4352 to load 5v q1 si7336adp 4352 f07 v in gate out c2 0.1f r7 1k gnd 12v cpo figure 7. 5v ideal diode with external 12v powering cpo for faster start-up and refresh a pplica t ions in f or m a t ion external cpo supply the internal charge pump takes milliseconds to charge up the cpo pin capacitor especially during device power up. this time can be shortened by connecting an external supply to the cpo pin. a series resistor is needed to limit the current into the internal clamp between the cpo and source pins. the cpo supply should also be higher than the main input supply to meet the gate drive requirements of the mosfet. figure 7 shows such a 5v ideal diode ap - plication, where a 12v supply is connected to the cpo pin through a 1k resistor. the 1k limits the current into the cpo pin to 5.3ma, when the source pin is grounded. input transient protection when the capacitances at the input and output are very small, rapid changes in current can cause transients that exceed the 24v absolute maximum rating of the v in and out pins. in oring applications using a single mosfet, one surge suppressor connected from out to ground clamps all the inputs. in the absence of a surge suppressor, an output capacitance of 10f is sufficient in most applications to prevent the transient from exceeding 24v. back-to-back mosfet applications, depending on voltage levels, may require a surge suppressor on each supply input. design example the following design example demonstrates the calcula- tions involved for selecting components in a 12v system with 10a maximum load current (see figure 1). first, calculate the r ds(on) of the mosfet to achieve the desired forward drop at full load. assuming a v fwd of 50mv (which is comfortably below the 200mv minimum open mosfet fault threshold): r ds on ( ) v fwd i load = 50mv 10a = 5m the si7336adp offers a good solution, in a so-8 sized package, with a maximum r ds(on) of 4m and bv dss of 30v. the maximum power dissipation in the mosfet is: p = i 2 load ? r ds(on) = (10a) 2 ? 4m = 0.4w with a maximum steady-state thermal resistance, ja , of 65c/w, 0.4w causes a modest 26c rise in junction temperature of the si7336adp above the ambient. the input capacitance, c iss , of the si7336adp is about 6500pf. slightly exceeding the 10x recommendation, a 0.1f capacitor is selected for c2.
ltc4352 12 4352fa figure 8. recommended pcb layout for power mosfet 1 2 3 4 5 6 12 11 10 9 8 7 c1 s s s g d d d d drawing is not to scale! via to ground plane source gate ltc4352 msop-12 gnd out v in v cc via to ground plane current flow current flow w w track width w: 0.03? per ampere on 1oz cu foil from input supply to load q1 so-8 4352 f08 a pplica t ions in f or m a t ion leds, d1 and d2, require around 3ma for good luminous intensity. accounting for a 2v diode drop and 0.5v v ol , r1 and r2 are set to 2.7k. pcb layout considerations connect the v in and out pin traces as close as possible to the mosfets terminals. keep the traces to the mosfet wide and short to minimize resistive losses. the pcb traces associated with the power path through the mosfet should have low resistance. see figure 8. it is also important to put c1, the bypass capacitor for the v cc pin, as close as possible between v cc and gnd. also place c2 near the cpo and source pins. surge suppres- sors, when used, should be mounted close to the ltc4352 using short lead lengths.
ltc4352 13 4352fa typical a pplica t ions plug-in card supply holdup using ideal diode at input ideal diode with reverse input protection ltc4352 plug-in card connectors backplane q1 si7336adp 4352 ta02 v in source gate out gnd gnd to load 12v gnd + c holdup hot swap controller v cc uv ov rev ltc4352 status fault 0.1f 10a load d5 smaj17a d3 1n4148 or bat85 d4 bat85 3.5v to 9v q1 si4438dy c1 0.1f 4352 ta04 cpo v in source gate gnd out
ltc4352 14 4352fa dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd12) dfn 0106 rev a 0.23 0.05 pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline 0.45 bsc p ackage descrip t ion ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?) msop (ms12) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006)
ltc4352 15 4352fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 12/10 added h-grade information revised fault pin description in pin functions revised functional diagram added text to operation section revised figures 2, 5, 6 in applications information added new typical application revised typical application and related parts list 2,3 5 6 7 8, 10 13 16
ltc4352 16 4352fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 1210 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1473/ltc1473l dual powerpath? switch driver n-channel, 4.75v to 30v/3.3v to 10v, ssop-16 ltc1479 powerpath controller for dual battery systems three n-channel drivers, 6v to 28v, ssop-36 ltc4350 hot swappable load share controller n-channel, 1.5v to 12v, share bus, ssop-16 ltc4354 negative voltage diode-or controller and monitor dual n-channel, C4.5v to C80v, so-8, dfn-8 ltc4355 positive high voltage ideal diode-or and monitor dual n-channel, 9v to 80v, so-16, dfn-14 ltc4357 positive high voltage ideal diode controller n-channel, 9v to 80v, msop-8, dfn-6 ltc4358 5a ideal diode internal n-channel, 9v to 26.5v, tssop-16, dfn-14 ltc4411 2.6a low loss ideal diode in thinsot? internal p-channel, 2.6v to 5.5v, 40a i q , sot-23 ltc4412/ltc4412hv low loss powerpath controller in thinsot p-channel, 2.5v to 28v/36v, 11a i q , tsot-23 ltc4413/ltc4413-1 dual 2.6a, 2.5v to 5.5v, ideal diodes in dfn-10 dual internal p-channel, 2.5v to 5.5v, dfn-10 ltc4414 36v low loss powerpath controller for large pfets p-channel, 3v to 36v, 30a i q , msop-8 ltc4416/ltc4416-1 36v low loss dual powerpath controller for large pfets dual p-channel, 3.6v to 36v, 70a i q , msop-10 v cc uv ov rev ltc4352 status fault 0.1f v in1 0v to 18v 5v si7336adp to load 0.1f cpo v in source gate gnd out v cc uv ov rev ltc4352 status fault 0.1f v in2 0v to 18v 5v si7336adp 0.1f cpo v in source gate gnd out 4352 ta03 0v to 18v ideal diode-or

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