View LSM6DB0_7561112.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. november 2013 docid025603 rev 1 1/66 LSM6DB0 inemo advanced inertial module: 3d accelerometer, 3d gyroscope and signal processor datasheet - target specification features ? motion sensors: ? 2/4/8 g full scale ? 245/500/2000 dps full scale ? 6-axis eco power mode down to 1.8 ma ? 3 independent acceleration channels and 3 angular rate channels ? embedded temperature sensor ? 20 kbyte data batching ? 6-axis and 9-axis quaternions ? self-test ? ecopack ? , rohs and ?green? compliant ? signal processor: ? brain: arm-based, 32-bit cortex-m0 core ? flash memory and sram including a bank with error code correction (ecc) ?i 2 c master port ?i 2 c slave port ? spi master/slave ? 4-wire uart ? 11 programmable gpios ? low-power features ? 8 x 32-bit dual timers, watchdog timer (wdg), cortex-m0 system tick (systick) timer ? standard 4-wire jtag and 2-wire swd ? 80 mhz / 32 khz rc / up to 80 mhz from single-ended external clock applications ? sensor hubs and sensor fusion ? significant motion-detection and gesture recognition ? gaming and geomagnetic rotation vectors ? pedometers, step counters and step detectors ? calibrated compasses ? enhanced navigation and motion tracking description the LSM6DB0 is an advanced low-power high- performance smart sensor system available in a plastic 3x3x1 mm lga (land grid array) package. the module includes a three-axis accelerometer, 3-axis gyroscope and cortex-m0 core with flash, sram, dual timers, 2 i 2 c (master/slave), 1 spi (master/slave) and 1 uart (transmitter/receiver). the LSM6DB0 has a full-scale acceleration range of 2/4/8 g and an angular rate range of 245/500/2000 dps. the LSM6DB0 has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same odr or the accelerometer can be enabled while the gyroscope is in power-down. the module collects inputs from the accelerometer, gyroscope, compass and several other sensors and elaborates/fuses together 9 or 10 axes (inemo engine software) which are provided to the main application processor. for example, quaternions achieve the best compromise in terms of power saving for the overall system. the LSM6DB0 is fully compliant with the android kitkat os. lga-22 (3x3x1 mm) table 1. device summary order codes temp. range [ c] package packaging LSM6DB0 -40 to +85 lga-22 tray LSM6DB0tr -40 to +85 lga-22 tape and reel www.st.com
contents LSM6DB0 2/66 docid025603 rev 1 contents 1 block diagrams and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 LSM6DB0 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 accelerometer and gyroscope mechanical characteristics . . . . . . . . . . . . 15 3.2 accelerometer and gyroscope electrical characteristics . . . . . . . . . . . . . . 16 3.3 microprocessor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 motion sensor communication interface characteristics . . . . . . . . . . 19 4.1 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 accelerometer and gyroscope operating modes . . . . . . . . . . . . . . . . . . . 21 6.2 gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 microprocessor operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 accelerometer and gyroscope functionality . . . . . . . . . . . . . . . . . . . . . 25 7.1 multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.3 continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.4 continuous-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.5 bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
docid025603 rev 1 3/66 LSM6DB0 contents 66 8 microprocessor functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 arm cortex-m0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 30 8.2 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.4 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.8 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8.1 dual timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8.2 watchdog (wdg) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8.3 system tick (systick) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.11 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . . 35 8.12 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.13 jtag and sw debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.1 int_gen_cfg2_xl (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2 int_gen_ths2_xl (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3 int_gen_dur2_xl (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.4 act_ths (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.5 act_dur (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.6 int_gen_cfg1_xl (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.7 int_gen_ths1_x_xl (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.8 int_gen_ths1_y_xl (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
contents LSM6DB0 4/66 docid025603 rev 1 11.9 int_gen_ths1_z_xl (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.10 int_gen_dur1_xl (0ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.11 reference_g (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.12 int1_ctrl (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.13 int2_ctrl (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.14 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.15 ctrl_reg1_g (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.16 ctrl_reg2_g (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.17 ctrl_reg3_g (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.18 orient_cfg_g (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.19 int_gen_src_g (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.20 out_temp_l (15h), out_temp_h (16h) . . . . . . . . . . . . . . . . . . . . . . . 50 11.21 status_reg (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.22 out_x_g (18h - 19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.23 out_y_g (1ah - 1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.24 out_z_g (1ch - 1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.25 ctrl_reg4 (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.26 ctrl_reg5_xl (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.27 ctrl_reg6_xl (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.28 ctrl_reg7_xl (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.29 ctrl_reg8 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.30 ctrl_reg9 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.31 ctrl_reg10 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.32 int_gen_src_xl (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.33 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.34 out_x_xl (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.35 out_y_xl (2ah - 2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.36 out_z_xl (2ch - 2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.37 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.38 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.39 int_gen_cfg_g (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.40 int_gen_ths_x_g (31h - 32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.41 int_gen_ths_y_g (33h - 34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
docid025603 rev 1 5/66 LSM6DB0 contents 66 11.42 int_gen_ths_z_g (35h - 36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.43 int_gen_dur_g (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
list of tables LSM6DB0 6/66 docid025603 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. gyroscope operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9. operating mode current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. gyroscope turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. accelerometer turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. LSM6DB0 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 13. alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. debug mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. absolute maximum ratings for microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. motion sensor registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 18. int_gen_cfg2_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 19. int_gen_cfg2_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. int_gen_ths2_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. int_gen_ths2_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 22. int_gen_dur2_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 23. int_gen_dur2_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. act_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 25. act_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 26. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 27. act_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 28. int_gen_cfg1_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 29. int_gen_cfg1_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 30. int_gen_ths1_x_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 31. int_gen_ths1_x_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 32. int_gen_ths1_y_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 33. int_gen_ths1_y_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 34. int_gen_ths1_z_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 35. int_gen_ths_z_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 36. int_gen_dur1_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 37. int_gen_dur1_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 38. reference_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 39. reference_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 40. int1_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 41. int1_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 42. int2_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43. int2_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 44. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 45. ctrl_reg1_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 46. ctrl_reg1_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 47. odr and bw configuration setting (after lpf1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 48. odr and bw configuration setting (after lpf2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
docid025603 rev 1 7/66 LSM6DB0 list of tables 66 table 49. ctrl_reg2_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 50. ctrl_reg2_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 51. ctrl_reg3_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 52. ctrl_reg3_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 53. gyroscope high-pass filter cutoff frequency configuration [hz]. . . . . . . . . . . . . . . . . . . . . . 49 table 54. orient_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 55. orient_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 56. int_gen_src_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 57. int_gen_src_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 58. out_temp_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 59. out_temp_h register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 60. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 61. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 62. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 63. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 64. ctrl_reg4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 table 65. ctrl_reg5_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 66. ctrl_reg5_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 67. ctrl_reg6_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 68. ctrl_reg6_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 69. odr register setting (accelerometer only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 70. ctrl_reg7_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 71. ctrl_reg7_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 72. low-pass cutoff frequency in high resolution mode (hr = 1) . . . . . . . . . . . . . . . . . . . . . . . 54 table 73. ctrl_reg8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 74. ctrl_reg8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 table 75. ctrl_reg9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 76. ctrl_reg9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 table 77. ctrl_reg10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 78. ctrl_reg10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 79. int_gen_src_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 80. int_gen_src_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 81. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 82. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 83. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 84. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 85. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 86. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 87. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 88. fifo_src example: ovr/fss details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 89. int_gen_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 90. int_gen_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 91. int_gen_ths_xh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 92. int_gen_ths_xl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 93. int_gen_ths_x_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 94. int_gen_ths_yh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 95. int_gen_ths_yl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 96. int_gen_ths_y_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 97. int_gen_ths_zh_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 98. int_gen_ths_zl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 99. int_gen_ths_z_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 100. int_gen_dur_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
list of tables LSM6DB0 8/66 docid025603 rev 1 table 101. int_gen_dur_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 102. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
docid025603 rev 1 9/66 LSM6DB0 list of figures 66 list of figures figure 1. LSM6DB0 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. accelerometer and gyroscope block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. microprocessor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 4. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. i 2 c slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. switching operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. multiple reads: accelerometer only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 8. multiple reads: accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. continuous-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. bypass-to-continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. LSM6DB0 digital power supply generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. debug mode selection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. int_sel and out_sel configuration gyroscope block diagram . . . . . . . . . . . . . . . . . . . 48 figure 18. wait bit disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 19. wait bit enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 20. lga-22: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
block diagrams and pin description LSM6DB0 10/66 docid025603 rev 1 1 block diagrams and pin description 1.1 block diagrams the LSM6DB0 includes a 3-axis accelerometer and 3-axis gyroscope combined with a low- power microprocessor arm-based cortex-m0. the reference block diagram is described in figure 1 while the motion sensor and microprocessor block diagrams are described in figure 2 and figure 3 , respectively. figure 1. LSM6DB0 application block diagram magnetometer pressure sensor other sensors accelerometer and gyroscope fifos brain arm cortex-m0 ram data fusion algorithms application processor i 2 c i 2 c i 2 c int int LSM6DB0 int1 int2 dio7 dio8 dio12 dio11
docid025603 rev 1 11/66 LSM6DB0 block diagrams and pin description 66 figure 2. accelerometer and gyroscope block diagram figure 3. microprocessor block diagram legend: nvic = nested vectored interrupt controller, gpio = general-purpose input/output charge amplifier y+ z+ y- z- a x+ x- mux x,y,z y+ z+ y- z- x+ x- m u x adc lpf1 1 0 hp_en lpf2 hpf data reg interrupt generator i2c spi out_sel int_sel src registers cfg registers gyro fifo lpf1 adc 1 0 hpf hpis1 fds xl gyro lpf2 hr interrupt generator xl 0 0 1 1 xl xl xl gyro gyro gyro +
block diagrams and pin description LSM6DB0 12/66 docid025603 rev 1 1.2 pin description figure 4. pin connections table 2. pin description pin# name function i/o level 1 vdd1.8 power supply for i/o pins 2 dio0 gpio0 / sw_tdio / jtag tms / uart_cts vdd1.8 3 dio1 gpio1 / sw_tck / jtag tck / uart_rts vdd1.8 4 dio2 gpio2 / i 2 c2_scl (slave) / uart_txd vdd1.8 5 reset microcontroller reset vdd 6 dio3 gpio3 / i 2 c2_sda (slave) / uart_rxd vdd1.8 7 dio4 gpio4 / jtag tdo vdd1.8 8 dio5 gpio5 / jtag tdi / clock input vdd1.8 9 dio8 gpio8 / i 2 c1_sda (master) / spi_out vdd 10 dio6 gpio6 / 16 mhz clock output / clock 32khz vdd 11 dio7 gpio7 / i 2 c1_scl (master) / spi_clock vdd 12 gnd 0 v supply 13 ld01.2 connect to decoupling capacitor for 1.2 v digital regulator to gnd 14 vdd (1) analog and i/o pins power supply (top view) directions of the detectable angular rates x z x y (top view) direction of the detectable accelerations vdd1.8 dio0 dio1 dio2 gnd dio8 dio4 reset dio6 1 10 7 5 16 ldo1.2 vdd dio10 dio9 6 dio5 11 17 20 res cap res res bottom view 21 22 dio3 dio7 res res + + + y x z
docid025603 rev 1 13/66 LSM6DB0 block diagrams and pin description 66 15 dio10 gpio10 / spi_input vdd 16 dio9 gpio9 / spi_cs vdd 17 res connect to gnd 18 res connect to gnd 19 res connect to vdd 20 cap connect to gnd with ceramic capacitor (2) 21 res leave unconnected 22 res leave unconnected 1. recommended 100 nf filter capacitor. 2. 10 nf (10%), 16 v. 1 nf minimum value has to be guaranteed under 12 v bias condition. the int1 and int2 pins of the motion sensor are internally connected to the dio12 and dio11 pins of the microcontroller, refer to figure 1 . table 2. pin description (continued) pin# name function i/o level
LSM6DB0 features LSM6DB0 14/66 docid025603 rev 1 2 LSM6DB0 features in the LSM6DB0 a complete sensor networking has been created with three additional external sensor connections supported by the i 2 c bus (eg. compass, pressure sensors, others). external data acquisition is totally configurable with a different data rate selection and different data reads for each slave sensor. to minimize the core?s (brain) power consumption, dedicated fifo buffers are available in the inertial sensors to maximize the temporary data storage. the LSM6DB0 can manage standard hub functionalities together with the implementation of complex algorithms for the following applications: ? sensor batching with combination of sensors based on different odr and related time-stamp information; ? sensor fusion with the support of quaternions, gravity, linear acceleration and orientation data; ? pedometers; ? game rotation vectors; ? geomagnetic rotation vectors (3-axis accelerometer and 3-axis magnetometer); ? compass calibration; ? gyroscope bias estimation and offset compensation; ? accelerometer background calibration; ? significant motion; ? gesture recognition; the device provides optimal flexibility, modularity and scalability in the customization of software routines for the customer. the LSM6DB0 completely offloads the application processor from the computation of sensor fusion, delivering unparalleled low-power consumption at the system level. owing to the embedded core (brain) in the device, there is no need for an external processing unit nor storage. the LSM6DB0 is compliant with android kitkat os.
docid025603 rev 1 15/66 LSM6DB0 mechanical characteristics 66 3 mechanical characteristics 3.1 accelerometer and gyroscope mechanical characteristics t = 25 c unless otherwise noted (a) a. the operational power supply range is from 1.71 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range 2 g 4 8 g_fs angular rate measurement range 245 dps 500 2000 la_so linear acceleration sensitivity fs = 2 g 0.061 mg/lsb fs = 4 g 0.122 fs = 8 g 0.244 g_so angular rate sensitivity fs = 245 dps 8.75 mdps/lsb fs = 500 dps 17.50 fs = 2000 dps 70 la_tyoff linear acceleration typical zero- g level offset accuracy (2) fs = 8 g 90 m g g_tyoff angular rate typical zero-rate level (3) fs = 2000 dps 30 dps la_odr linear acceleration output data rate gyro on 952 476 238 119 59.5 14.9 hz gyro off 952 476 238 119 50 10 hz
mechanical characteristics LSM6DB0 16/66 docid025603 rev 1 3.2 accelerometer and gyroscope electrical characteristics t = 25 c unless otherwise noted table 4. electrical characteristics g_odr angular digital output data rate 952 476 238 119 59.5 14.9 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. typical zero-g level offset value after soldering. 3. typical zero-rate level offset value after msl3 preconditioning. table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit symbol parameter test conditions min. typ. (1) max. unit vdd core and i/o pins supply voltage 1.71 3.6 v la_idd accelerometer current consumption in normal mode odr = 10 hz 60 a odr = 50 hz 160 odr ? 119 hz 330 g_idd gyroscope current consumption in eco power mode 1.8 ma top operating temperature range -40 +85 c 1. typical specifications are not guaranteed.
docid025603 rev 1 17/66 LSM6DB0 mechanical characteristics 66 3.3 microprocessor electrical characteristics characteristics measured in table 5 are for recommended operating conditions unless otherwise specified. typical values are in reference to t a = 25 ? c, v dd =1.8 v. table 5. dc and ac parameters symbol parameter test conditions min. typ. max. unit vdd operating supply voltage master serial port (dio6 to dio10) 1.71 3.6 v vdd1.8 operating supply voltage (dio0 to dio5) 1.75 1.8 1.95 v power consumption (dhrystone without compiler options) i supply supply current reset 50 na active (cpu, flash, and ram) 20 ma from ram 80 mhz (0.79 dmips/mhz) 40 mhz (0.79 dmips/mhz) 20 mhz (0.79 dmips/mhz) 16 mhz (0.79 dmips/mhz) 10 mhz (0.79 dmips/mhz) 10.3 5.95 3.85 3.48 2.9 from flash 80 mhz (0.3 dmips/mhz) 40 mhz (0.43 dmips/mhz) 20 mhz (0.56 dmips/mhz) 16 mhz (0.79 dmips/mhz) 10 mhz (0.79 dmips/mhz) 7.5 5.5 4.74 4.34 3.7 digital input and output (1.8 v supply) c in (1) port i/o capacitance 1.3 1.4 1.7 pf r pd (1) pull-down value 117 211 334 kw t rise (1) rise time 0.1*v dd to 0.9*v dd , c l = 50 pf 10.3 19 ns t fall (1) fall time 0.9*v dd to 0.1*v dd , c l = 50 pf 11 22 v ih (1) logic high-level input voltage 0.65 v dd v v il (1) logic low-level input voltage 0.35 v dd digital input and output (3.3 v supply) c in (1) port i/o capacitance 1.3 1.4 1.7 pf r pd (1) pull-down value 53 84 144 kw r pu (1) pull-up value 57 81 122 t rise (1) rise time 0.1*v dd to 0.9*v dd , c l = 50 pf 1.4 12 ns t fall (1) fall time 0.9*v dd to 0.1*v dd , c l = 50 pf 1.5 12.5
mechanical characteristics LSM6DB0 18/66 docid025603 rev 1 3.4 temperature sensor characteristics @ vdd = 3v, t = 25 c unless otherwise noted (b) v ih (1) logic high-level input voltage 0.65 v dd v v il (1) logic low-level input voltage 0.35 v dd t a operating ambient temperature range -40 85 c 1. guaranteed by design b. the product is factory calibrated at 3.0 v. table 6. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit todr temperature refresh rate gyro off (2) 50 hz gyro on 59.5 tsen temperature sensitivity (3) 16 lsb/c top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. when the accelerometer odr is set to 10 hz and the gyroscope block is turned off, the todr value is 10 hz. 3. the output of the temperature sensor is 0 (typ.) at 25 c
docid025603 rev 1 19/66 LSM6DB0 motion sensor communication interface characteristics 66 4 motion sensor communication interface characteristics 4.1 i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 5. i 2 c slave timing diagram note: measurement points are done at 0.2vdd and 0.8vdd, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. sd a scl t su(sp) t w(scll) t su(sda) t su(sr) t h(st) t w(sclh) t h(sda) t w(sp:sr) start repea ted sta rt stop sta rt
terminology LSM6DB0 20/66 docid025603 rev 1 5 terminology 5.1 sensitivity linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. an angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 5.2 zero- g and zero rate level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x-axis and y-axis, whereas the z-axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?linear acceleration zero- g level change vs. temperature? in table 3 . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. zero-rate level describes the actual output signal if there is no angular rate present. the zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time.
docid025603 rev 1 21/66 LSM6DB0 device operating modes 66 6 device operating modes 6.1 accelerometer and gyroscope operating modes the LSM6DB0 has two operating modes available: only accelerometer active and gyroscope in power down or both accelerometer and gyroscope sensors active at the same odr. switching from one mode to the other requires one write operation: writing to ctrl_reg6_xl (20h) the accelerometer operates in normal mode and the gyroscope is powered down, writing to ctrl_reg1_g (10h) both the accelerometer and gyroscope are activated at the same odr. figure 6 depicts both modes of operation from power down. figure 6. switching operating modes 6.2 gyroscope power modes in the LSM6DB0, the gyroscope can be configured in three different operating modes: power-down, low-power and normal mode. low-power mode is available for lower odr (14.9, 59.5, 119 hz) while for greater odr (238, 476, 952 hz), the device is automatically in normal mode. table 8 summarizes the odr configuration (odr_g[2:0] bits set in ctrl_reg1_g (10h) ) and corresponding power modes. to enable low-power mode, the lp_mode bit in ctrl_reg3_g (12h) has to be set to ?1?. low-power mode allows reaching low power consumption while maintaining the device always on, refer to table 9 . the turn-on time to change from all operating modes for the gyroscope and accelerometer is indicated in table 10 and table 11 . accelerometer only accelerometer + gyro power down write ctrl_reg1_g write ctrl_reg1_g with ctrl_reg6_xl = pd write ctrl_reg6_xl
device operating modes LSM6DB0 22/66 docid025603 rev 1 table 8. gyroscope operating mode odr_g [2:0] odr [hz] power mode (1) 1. gyroscope low-power mode is available for g_fs = 2000 dps. 000 power-down power-down 001 14.9 low-power 010 59.5 low-power 011 119 low-power 100 238 normal mode 101 476 normal mode 110 952 normal mode table 9. operating mode current consumption odr [hz] power mode current consumption (1) [ma] 1. gyroscope and accelerometer current consumption typical values based on characterization data. 14.9 low-power 1.8 59.5 low-power 2.3 119 low-power 2.9 238 normal mode 4.3 476 normal mode 4.3 952 normal mode 4.3 table 10. gyroscope turn-on time odr [hz] lpf1 only (1) 1. the table contains the number of samples to be discarded after switching between low-power mode and normal mode. lpf1 and lpf2 (1) 14.9 2 lpf2 not available 59.5 or 119 3 13 238 4 14 476 5 15 952 8 18
docid025603 rev 1 23/66 LSM6DB0 device operating modes 66 6.3 microprocessor operating modes several microprocessor operating modes are defined for the LSM6DB0: ? reset mode ? two low-power modes: low-power wait-for-interrupt (wfi) mode and high-power wait- for-interrupt (wfi) mode ? active mode in reset mode the LSM6DB0 is in ultra-low-power consumption: no voltage regulators, nor clocks are powered. the LSM6DB0 enters reset mode by asserting the external reset signal. while in low-power wfi mode, the LSM6DB0 cpu is stopped and the high-frequency 80 mhz rc oscillator is powered down. all peripherals, apart from one timer, are disabled. the power consumption is about 800 a with a 1 khz clock. in high-power wfi mode, the cpu is stopped and the high-frequency 80 mhz rc oscillator is powered up. this mode allows a faster response time for an interrupt to wake up the cpu. all peripherals are enabled and can wake up the cpu with an interrupt. the power consumption in this mode is around 2 ma with an 80 mhz clock. in active mode the LSM6DB0 is fully operational: all interfaces, including spi, i 2 c, jtag and uart, are active as well as all internal power supplies together with the high-speed frequency oscillator. the mcu core is also running. table 11. accelerometer turn-on time odr [hz] bw = 400 hz (1) 1. the table contains the number of samples to be discarded after switching between power-down mode and normal mode. bw = 200 hz (1) bw = 100 hz (1) bw = 50 hz (1) 14.9 0 0 0 0 59.5 0 0 0 0 119 1 1 1 2 238 1 1 2 4 476 1 2 4 7 952 2 4 7 14
device operating modes LSM6DB0 24/66 docid025603 rev 1 table 12 summarizes the modes of operation and transition times. table 12. LSM6DB0 operating modes ip active mode high-power wfi mode low-power wfi mode cpu yes yes yes flash sram bor yes por high-speed internal osc. no low-speed internal osc. yes timer yes spi no i2c uart wdg yes gpios yes wake-up time to active mode 0 s 50 ns 300 s consumption (typ) 10 ma 3 ma 800 a
docid025603 rev 1 25/66 LSM6DB0 accelerometer and gyroscope functionality 66 7 accelerometer and gyroscope functionality 7.1 multiple reads (burst) when only the accelerometer is activated and the gyroscope is in power down, starting from out_x_xl (28h - 29h) multiple reads can be performed. once out_z_xl (2ch - 2dh) is read, the system automatically restarts from out_x_xl (28h - 29h) (see figure 7 ). figure 7. multiple reads: accelerometer only when both accelerometer and gyroscope sensors are activated at the same odr, starting from out_x_g (18h - 19h) multiple reads can be performed. once out_z_xl (2ch - 2dh) is read, the system automatically restarts from out_x_g (18h - 19h) (see figure 8 ). figure 8. multiple reads: accelerometer and gyroscope 7.2 fifo the LSM6DB0 embeds a 32 slots of 16-bit data fifo for each of the gyroscope?s three output channels, yaw, pitch and roll, and 16-bit data fifo for each of the accelerometer?s three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly to five different modes: bypass mode, fifo-mode, continuous mode, continuous-to-fifo mode and bypass-to-continuous. each mode is selected by the fmode [2:0] bits in the fifo_ctrl (2eh) register. programmable fifo threshold status, fifo overrun events and the number of unread samples stored are available in the fifo_src (2fh) register and can be set to generate dedicated interrupts on the int1 pin using the int1_ctrl (0ch) register. x,y,z out_z_xl read #1 (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl x,y,z read #n out_z_xl (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl (15-16) out_temp x,y,z out_z_xl read #1 (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl x,y,z read #n out_z_g (1c-1d) (1a-1b) out_y_g (18-19) out_x_g out_z_xl (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl out_z_g (1c-1d) (1a-1b) out_y_g (18-19) out_x_g (15-16) out_temp
accelerometer and gyroscope functionality LSM6DB0 26/66 docid025603 rev 1 fifo_src (2fh) (fth) goes to '1' when the number of unread samples ( fifo_src (2fh) (fss5:0)) is greater than or equal to fth [4:0] in fifo_ctrl (2eh) . if fifo_ctrl (2eh) (fth[4:0]) is equal to 0, fifo_src (2fh) (fth) goes to ?0?. fifo_src (2fh) (ovrn) is equal to '1' if a fifo slot is overwritten. fifo_src (2fh) (fss [5:0]) contains stored data levels of unread samples. when fss [5:0] is equal to ?000000?, fifo is empty, when fss [5:0] is equal to ?100000?, fifo is full and the unread samples are 32. the fifo feature is enabled by writing '1' in ctrl_reg9 (23h) (fifo_en). to guarantee the correct acquisition of data during the switching into and out of fifo mode, the first sample acquired must be discarded. 7.2.1 bypass mode in bypass mode ( fifo_ctrl (2eh) (fmode [2:0]= 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode. as described in figure 9 , for each channel only the first address is used. when a new data is available the old data is overwritten. figure 9. bypass mode 7.2.2 fifo mode in fifo mode ( fifo_ctrl (2eh) (fmode [2:0] = 001) data from the output channels are stored in the fifo until it is overwritten. to reset fifo content, bypass mode should be selected by writing fifo_ctrl (2eh) (fmode [2:0]) to '000'. after this reset command, it is possible to restart fifo mode, writing fifo_ctrl (2eh) (fmode [2:0]) to '001'. the fifo buffer memorizes 32 levels of data but the depth of the fifo can be resized by setting the stop_on_fth bit in ctrl_reg9 (23h) . if the stop_on_fth bit is set to '1', fifo depth is limited to fifo_ctrl (2eh) (fth [4:0]) + 1 data. a fifo threshold interrupt can be enabled (int_ovr bit in int1_ctrl (0ch) ) in order to be raised when the fifo is filled to the level specified by the fth[4:0] bits of fifo_ctrl (2eh) . when a fifo threshold interrupt occurs, the first data has been overwritten and the fifo stops collecting data from the input channels. x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty
docid025603 rev 1 27/66 LSM6DB0 accelerometer and gyroscope functionality 66 figure 10. fifo mode 7.2.3 continuous mode continuous mode ( fifo_ctrl (2eh) (fmode[2:0] = 110) provides a continuous fifo update: as new data arrives, the older is discarded. a fifo threshold flag fifo_src (2fh) (fth) is asserted when the number of unread samples in fifo is greater than or equal to fifo_ctrl (2eh) (fth4:0). it is possible to route fifo_src (2fh) (fth) to the int1 pin by writing the int_fth bit to ?1? in register int1_ctrl (0ch) . a full-flag interrupt can be enabled, int1_ctrl (0ch) (int_ fss5)= '1', when the fifo becomes saturated and in order to read the contents all at once. if an overrun occurs, the oldest sample in fifo is overwritten and the ovrn flag in fifo_src (2fh) is asserted. in order to empty the fifo before it is full, it is also possible to pull from fifo the number of unread samples available in fifo_src (2fh) (fss[5:0]). figure 11. continuous mode x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30
accelerometer and gyroscope functionality LSM6DB0 28/66 docid025603 rev 1 7.2.4 continuous-to-fifo mode in continuous-to-fifo mode ( fifo_ctrl (2eh) (fmode [2:0] = 011), fifo behavior changes according to the int_gen_src_xl (26h) (ia_xl) bit. when int_gen_src_xl (26h) (ia_xl) bit is equal to '1' fifo operates in fifo mode, when int_gen_src_xl (26h) (ia_xl) bit is equal to '0' fifo operates in continuous mode. the interrupt generator should be set to the desired configuration by means of int_gen_cfg1_xl (06h) , int_gen_ths1_x_xl (07h) , int_gen_ths1_y_xl (08h) and int_gen_ths1_z_xl (09h) . the ctrl_reg4 (1eh) (lir_xl) bit should be set to '1' in order to have latched interrupt. figure 12. continuous-to-fifo mode x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i continuous mode fifo mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30
docid025603 rev 1 29/66 LSM6DB0 accelerometer and gyroscope functionality 66 7.2.5 bypass-to-continuous mode in bypass-to-continuous mode ( fifo_ctrl (2eh) (fmode[2:0] = '100'), data measurement storage inside fifo operates in continuous mode when int_gen_src_xl (26h) (ia_xl) is equal to '1', otherwise fifo content is reset (bypass mode). the interrupt generator should be set to the desired configuration by means of int_gen_cfg1_xl (06h) , int_gen_ths1_x_xl (07h) , int_gen_ths1_y_xl (08h) and int_gen_ths1_z_xl (09h) . the ctrl_reg4 (1eh) (lir_xl) bit should be set to '1' in order to have latched interrupt. figure 13. bypass-to-continuous mode x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty bypass mode continuous mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30
microprocessor functionality LSM6DB0 30/66 docid025603 rev 1 8 microprocessor functionality 8.1 arm cortex-m0 core the arm cortex-m0 processor is a very low gate count, energy-efficient processor. it has been developed to provide an energy-efficient processor for microcontrollers and embedded applications requiring an area-optimized processor. the arm cortex-m0 32-bit risc processor uses thumb-2 ? technology, providing a blend of 16/32-bit instructions delivering a smaller code size to 8-bit and 16-bit architectures. owing to its embedded arm core, the LSM6DB0 is compatible with all arm tools and software. 8.1.1 nested vectored interrupt controller (nvic) the arm cortex-m0 processor supports up to 32 interrupt requests (irq), a non-maskable interrupt (nmi), and various system exceptions. the nvic and the arm cortex-m0 processor core are closely coupled and provide: ? low-latency interrupt processing ? four interrupt priority levels ? efficient processing of late-arriving interrupts and higher priority interrupts ? support for tail-chaining 8.2 power supply scheme ? vdd (c) = 1.8 v to 3.3 v: external power supply for master serial port (dio6 to dio10). provided through vdd pin. ? vdd1.8 (c) = 1.8 v: external power supply for internal regulator. provided through vdd1.8 pin. the LSM6DB0 integrates an ldo regulator which is used to generate the power supply for the internal digital circuitry. the ldo supplies 1.2 v for the digital blocks and requires a decoupling capacitor for stable operation. figure 14. LSM6DB0 digital power supply generation c. for minimum and maximum operating conditions of vdd and vdd1.8 refer to table 5 . ldo digital logic 1.2v vdd1.8 (pin#1) ldo1.2 (pin#13) gnd 220 nf external decoupling capacitor 1.8 v supply gnd (pin#12)
docid025603 rev 1 31/66 LSM6DB0 microprocessor functionality 66 8.3 reset management the device has an integrated brownout reset (bor) circuit and an integrated power-on reset (por). in the LSM6DB0, the bor threshold is 1.5 v. when v dd is below this threshold, the device is in reset. the bor is always active in the LSM6DB0 at power-on. the por circuit is activated when the ldo has stabilized. the startup time of the LSM6DB0 at power-on is typically 1 ms with the bor active. 8.4 boot mode at startup, the LSM6DB0 boots from a reserved section of the flash memory programmed by st during production. it is used to adjust accurately the oscillator frequencies and contains manufacturing information. any interference with this initialization sequence can degrade the performance of the device. at the end of this sequence, the system boots from the main flash which contains the user?s program. 8.5 clock management figure 15. clock tree 1. same clock supply for both i 2 c
microprocessor functionality LSM6DB0 32/66 docid025603 rev 1 the clock management block distributes clocks from various clock sources to the cpu and peripherals. the clock management block is comprised of the following circuitry and switches: ? clock divider: the system contains various clock dividers which allow the frequency of the peripherals and cpu clock sources to be changed. ? glitch-free clock switching: the clock sources can be changed dynamically and securely in active mode. ? clock gating: the peripherals can have their clocks gated off to reduce their power consumption. ? three system clock sources: ? rc80m 80 mhz internal rc oscillator which is trimmed at 1% accuracy with factory settings ? rc32k 32 khz internal rc oscillator which is trimmed at 1% accuracy with factory settings ? extclk external clock up to 80 mhz ? watchdog clock sources: the rc32k or extclk. ? i 2 c clock source: system clock divided by 3. ? uart clock source: system clock divided by a programmable division factor between 1 and 127. ? spi clock source: clock synchronous to the processor. ? dual timers: four timers clocked by 32 khz clock pulses synchronous to the system clock sources and four timers clocked on a clock synchronous to the processor clock. ? clock-out capability: either the 32 khz clock or the output of the divide-by-5 clock can be output on a gpio for external use.
docid025603 rev 1 33/66 LSM6DB0 microprocessor functionality 66 8.6 general-purpose inputs/outputs (gpios) the LSM6DB0 contains up to 11 gpio pins each of which can be configured by software as output, as input (either pull-up or pull-down), or as an alternate function in serial mode 0 or serial mode1 (see table 13 ). each of the gpios can also be used as an external interrupt source. 8.7 memories the LSM6DB0 has the following memory features: ? flash memory with 0 wait states at 26.66 mhz and 2 wait states at 80 mhz ? sram with ecc for data and program access (read/write) referred to as ram bank0 ? sram for data and program access (read/write) referred to as ram bank1 ? memory protection: the flash and ram memory banks cannot be read from or written to by the jtag link if the debug features are connected. table 13. alternate function input/output pin name serial mode 0 serial mode 1 gpio mode direction function direction function direction function io0 input/output jtag tms / sw_tdio input uart cts input/output gpio io1 input jtag tck / sw_tck output uart rts io2 input/output i 2 c2_scl uart txd io3 i 2 c2_sda input uart rxd io4 output jtag tdo none io5 input jtag tdi clock input io6 output 16 mhz clock output 32 khz clock io7 input/output i 2 c1_scl input/output spi sclk io8 i 2 c1_sda output spi output io9 input irq input input spi cs io10 spi input
microprocessor functionality LSM6DB0 34/66 docid025603 rev 1 8.8 timers and watchdogs the LSM6DB0 includes eight dual timers, one wdg timer, and a systick timer. 8.8.1 dual timer the dual-timer features are listed below. they consist of two identical programmable free- running counters (frcs) that can be configured for 32-bit or 16-bit operations. the frcs operate from a common timer clock which must be synchronous to the cpu clock. ? 16/32-bit down counter ? interrupt generation when the counter reaches zero ? free-running mode: the counter operates continuously and wraps around to its maximum value each time it reaches zero. ? periodic mode: the counter operates continuously by reloading the programmed value each time it reaches zero. ? one-shot mode: the counter decrements to zero and then halts until it is reprogrammed ? the timer clock prescaler factors are 1, 16, or 256 8.8.2 watchdog (wdg) timer the wdg timer is a 32-bit down counter which operates on either the rc32k clock or the extclk clock. it can generate an interrupt and/or a reset when the counter reaches zero. 8.8.3 system tick (systick) timer the systick timer provides a 24-bit clear-on-write, decrementing counter which wraps around when it reaches zero. it operates on the cpu clock.
docid025603 rev 1 35/66 LSM6DB0 microprocessor functionality 66 8.9 communication interfaces 8.10 i2c bus the LSM6DB0 provides two i2c interfaces which can operate in master and slave modes. they can support standard mode and fast mode. 8.11 universal asynchronous receiver transmitter (uart) the uart interface (io0, io1, io2, io3 pins) of the LSM6DB0 supports the following maximum baud rates: ? 921600 bps in uart mode ? 460800 bps in infrared data association (irda) mode ? 115200 bps in low-power irda mode the interface supports the irda serial infrared (sir) endec and also provides flow control capabilities through the hardware management of the clear-to-send (cts) and request-to- send (rts) signals. for more details, refer to the arm document ?ddio83g_uart_pl011_trm.pdf?. 8.12 serial peripheral interface (spi) the spi interface operates as a master or slave interface. this interface supports 6 mhz bit rate max in slave mode and 16 mhz bit rate max in master mode due to the limitation of the ios. a programmable clock prescaler inside the spi allows the input clock to be divided by a factor of 2 to 254 in steps of two to provide the serial output clock. the spi interface provides data frames between 4 and 16 bits long. for more details, refer to the arm document ?ddio94c_ssp_pl022_trm.pdf?.
microprocessor functionality LSM6DB0 36/66 docid025603 rev 1 8.13 jtag and sw debug support the arm jtag debug port is embedded which enables debug using a standard jtag connection. the arm serial wire debug port is also embedded which enables serial wire debug to be connected to the cpu. the jtag tms and tck pins are shared with the sw_tdio and sw_tck respectively. there are two mechanisms to select the debug mode. jtag debug mode is selected by setting the io9 pin to zero. during reset, the sw debug mode is selected by default. figure 16. debug mode selection timing 1. resetn needs an external pull-up if not driven 1. default option depending on software configuration table 14. debug mode selection por io9 debug mode 0 0 jtag: soc (1) + cpu tap (2) selected 1. soc = chip and processor 2. tap = test access port 0 1 sw: cpu tap (2) selected 1x (3) 3. x = don?t care jtag or sw available a?v ,2 5(6(71 325 *$06&%
docid025603 rev 1 37/66 LSM6DB0 absolute maximum ratings 66 9 absolute maximum ratings 9.1 accelerometer and gyroscope stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v 9.2 microprocessor absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are in reference to gnd. table 16. absolute maximum ratings for microprocessor table 15. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection (hbm) 2 kv vin input voltage on any control pin (including cs, scl/spc, sda/sdi/sdo, sdo/sa0) 0.3 to vdd_io +0.3 v this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part. pin parameter value (min to max) unit 13 dc voltage on linear voltage regulator -0.3 to +1.8 v 9, 10, 11, 15, 16 dc voltage on digital output pins -0.3 to +3.6 2, 3, 4, 6, 7, 8 -0.3 to +1.8 5 dc voltage on analog pins -0.3 to +1.8 7, 8 dc voltage on rf/xtal pins -0.3 to +1.8 t stg storage temperature range -40 to +125 c v esd - hbm electrostatic discharge voltage 2.0 kv
register mapping LSM6DB0 38/66 docid025603 rev 1 10 register mapping the table given below provides a list of the 8/16 bit registers of the motion sensors and the corresponding addresses. table 17. motion sensor registers name type register address default note hex binary reserved 00 00000000 -- reserved int_gen_cfg2_xl r/w 01 00000001 00000000 int_gen_ths2_xl r/w 02 00000010 00000000 int_gen_dur2_xl r/w 03 00000011 00000000 act_ths r/w 04 00000100 00000000 act_dur r/w 05 00000101 00000000 int_gen_cfg1_xl r/w 06 00000110 00000000 int_gen_ths1_x_xl r/w 07 00000111 00000000 int_gen_ths1_y_xl r/w 08 00001000 00000000 int_gen_ths1_z_xl r/w 09 00001001 00000000 int_gen_dur1_xl r/w 0a 00001010 00000000 reference_g r/w 0b 00001011 00000000 int1_ctrl r/w 0c 00001100 00000000 int2_ctrl r/w 0d 00001101 00000000 reserved -- 0e -- -- reserved who_am_i r 0f 00001111 01101000 ctrl_reg1_g r/w 10 00010000 00000000 ctrl_reg2_g r/w 11 00010001 00000000 ctrl_reg3_g r/w 12 00010010 00000000 orient_cfg_g r/w 13 00010011 00000000 int_gen_src_g r 14 00010100 output out_temp_l r 15 00010101 output out_temp_h r 16 00010110 output status_reg r 17 00010111 output out_x_l_g r 18 00011000 output out_x_h_g r 19 00011001 output out_y_l_g r 1a 00011010 output out_y_h_g r 1b 00011011 output out_z_l_g r 1c 00011100 output out_z_h_g r 1d 00011101 output
docid025603 rev 1 39/66 LSM6DB0 register mapping 66 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. to guarantee proper behavior of the device, all registers addresses not listed in the above table must not be accessed and the content stored on those registers must not be changed. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ctrl_reg4 r/w 1e 00011110 00111000 ctrl_reg5_xl r/w 1f 0001 1111 0011 1000 ctrl_reg6_xl r/w 20 00100000 00000000 ctrl_reg7_xl r/w 21 00100001 00000000 ctrl_reg8 r/w 22 00100010 00000100 ctrl_reg9 r/w 23 00100011 00000000 ctrl_reg10 r/w 24 00100100 00000000 reserved -- 25 -- -- reserved int_gen_src_xl r 26 00100110 output status_reg r 27 00100111 output out_x_l_xl r 28 00101000 output out_x_h_xl r 29 00101001 output out_y_l_xl r 2a 00101010 output out_y_h_xl r 2b 00101011 output out_z_l_xl r 2c 00101100 output out_z_h_xl r 2d 00101101 output fifo_ctrl r/w 2e 00101110 00000000 fifo_src r 2f 00101111 output int_gen_cfg_g r/w 30 00110000 00000000 int_gen_ths_xh_g r/w 31 00110001 00000000 int_gen_ths_xl_g r/w 32 00110010 00000000 int_gen_ths_yh_g r/w 33 00110011 00000000 int_gen_ths_yl_g r/w 34 00110100 00000000 int_gen_ths_zh_g r/w 35 00110101 00000000 int_gen_ths_zl_g r/w 36 00110110 00000000 int_gen_dur_g r/w 37 00110111 00000000 reserved r 38-7f -- -- reserved table 17. motion sensor registers (continued) name type register address default note hex binary
register description LSM6DB0 40/66 docid025603 rev 1 11 register description the device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. the register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 11.1 int_gen_cfg2_xl (01h) linear acceleration sensor interrupt generator 2 configuration register (r/w). table 19. int_gen_cfg2_xl register description table 18. int_gen_cfg2_xl register aoi2_xl 6d2 zhie2_xl zlie2_xl yhie2_xl ylie2_xl xhie2_xl xlie2_xl aoi2_xl and/or combination of accelerometer?s interrupt 2 events. default value: 0. (0: or combination; 1: and combination) 6d2 6 direction detection function for interrupt 2. default value: 0. (0: disabled; 1: enabled) zhie2_xl enable interrupt 2 generation on accelerometer?s z-axis high event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request) zlie2_xl enable interrupt 2 generation on accelerometer?s z-axis low event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request) yhie2_xl enable interrupt 2 generation on accelerometer?s y-axis high event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request) ylie2_xl enable interrupt 2 generation on accelerometer?s y-axis low event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request) xhie2_xl enable interrupt 2 generation on accelerometer?s x-axis high event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request) xlie2_xl enable interrupt 2 generation on accelerometer?s x-axis low event or on direction recognition. default value: 0. (0: disable interrupt request; 1: enable interrupt request)
docid025603 rev 1 41/66 LSM6DB0 register description 66 11.2 int_gen_ths2_xl (02h) linear acceleration sensor interrupt 2 threshold register (r/w). table 21. int_gen_ths2_xl register description 11.3 int_gen_dur2_xl (03h) linear acceleration sensor interrupt 2 duration register (r/w). table 23. int_gen_dur2_xl register description 11.4 act_ths (04h) activity threshold register. table 25. act_ths register description 11.5 act_dur (05h) inactivity duration register. table 27. act_dur register description table 20. int_gen_ths2_xl register ths2_xl7 ths2_xl6 ths2_xl5 ths2_xl4 ths2_xl3 ths2_xl2 ths2_xl1 ths2_xl0 ths2_xl [7:0] interrupt 2 thresholds . default value: 0000 0000 table 22. int_gen_dur2_xl register wait2_xl dur2_xl6 dur2_xl5 dur2_xl4 dur2_xl3 dur2_xl2 dur2_xl1 dur2_xl0 wait2_xl wait function enable on duration counter. default value: 0. (0: wait function off; 1: wait for dur2_xl [6:0] samples before exiting interrupt 2) dur2_xl [6:0] enter/exit interrupt 2 duration value. default value: 000 0000 table 24. act_ths register sleep_on_i nact_en act_ths6 act_ths5 act_ths4 act_ths3 act_ths2 act_ths1 act_ths0 sleep_on_ inact_en gyroscope operating mode during inactivity. default value: 0 (0: gyroscope in power-down; 1: gyroscope in sleep mode) act_ths [6:0] inactivity threshold. default value: 000 0000. table 26. act_dur register act_dur7 act_dur6 act_dur5 act_dur4 act_dur3 act_dur2 act_dur1 act_dur0 act_dur [7:0] inactivity duration. default value: 0000 0000
register description LSM6DB0 42/66 docid025603 rev 1 11.6 int_gen_cfg1_xl (06h) linear acceleration sensor interrupt 1 generator configuration register. table 29. int_gen_cfg1_xl register description 11.7 int_gen_ths1_x_xl (07h) linear acceleration sensor interrupt 1 threshold register. table 31. int_gen_ths1_x_xl register description table 28. int_gen_cfg1_xl register aoi_xl 6d zhie_xl zlie_xl yhie_xl ylie_xl xhie_xl xlie_xl aoi_xl and/or combination of accelerometer?s interrupt 1 events. default value: 0 (0: or combination; 1: and combination) 6d 6-direction detection function for interrupt 1. default value: 0 (0: disabled; 1: enabled) zhie_xl enable interrupt 1 generation on accelerometer?s z-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) zlie_xl enable interrupt 1 generation on accelerometer?s z-axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) yhie_xl enable interrupt 1 generation on accelerometer?s y-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) ylie_xl enable interrupt 1 generation on accelerometer?s y-axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) xhie_xl enable interrupt 1 generation on accelerometer?s x-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) xlie_xl enable interrupt 1 generation on accelerometer?s xaxis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) table 30. int_gen_ths1_x_xl register ths1_xl_ x7 ths1_xl_ x6 ths1_xl_ x5 ths1_xl_ x4 ths1_xl_ x3 ths1_xl_ x2 ths1_xl_ x1 ths1_xl_ x0 ths1_xl_x [7:0] x-axis interrupt threshold. default value: 0000 0000
docid025603 rev 1 43/66 LSM6DB0 register description 66 11.8 int_gen_ths1_y_xl (08h) linear acceleration sensor interrupt 1 threshold register. table 33. int_gen_ths1_y_xl register description 11.9 int_gen_ths1_z_xl (09h) linear acceleration sensor interrupt 1 threshold register. table 35. int_gen_ths_z_xl register description 11.10 int_gen_dur1_xl (0ah) linear acceleration sensor interrupt 1 duration register. table 36. int_gen_dur1_xl register table 37. int_gen_dur1_xl register description 11.11 reference_g (0bh) angular rate sensor reference value register for digital high-pass filter (r/w) table 38. reference_g register table 39. reference_g register description table 32. int_gen_ths1_y_xl register ths1_xl_y 7 ths1_xl_y 6 ths1_xl_y 5 ths1_xl_y 4 ths1_xl_y 3 ths1_xl_y 2 ths1_xl_y 1 ths1_xl_y 0 ths1_xl_y [7:0] y-axis interrupt threshold. default value: 0000 0000 table 34. int_gen_ths1_z_xl register ths1_xl_z 7 ths1_xl_z 6 ths1_xl_z 5 ths1_xl_z 4 ths1_xl_z 3 ths1_xl_z 2 ths1_xl_z 1 ths1_xl_z 0 ths1_xl_z [7:0] z-axis interrupt threshold. default value: 0000 0000 wait_xl dur1_xl6 dur1_xl5 dur1_xl4 dur1_xl3 dur1_xl2 dur1_xl1 dur1_xl0 wait_xl wait function enabled on duration counter. default value: 0 (0: wait function off; 1: wait for dur_xl [6:0] samples before exiting interrupt) dur1_xl [6:0] enter/exit interrupt duration value. default value: 000 0000 ref7_g ref6_g ref5_g ref4_g ref3_g ref2_g ref1_g ref0_g ref_g [7:0] reference value for gyroscope?s digital high-pass filter (r/w). default value: 0000 0000
register description LSM6DB0 44/66 docid025603 rev 1 11.12 int1_ctrl (0ch) int1 pin control register. table 40. int1_ctrl register table 41. int1_ctrl register description 11.13 int2_ctrl (0dh) int2 pin control registrer. table 42. int2_ctrl register int1_ig _g int1_ig_ xl int1_ fss5 int1_ovr int1_fth int1_ boot int1_ drdy_g int1_ drdy_xl int1_ig_g gyroscope interrupt enable on int1 pin. default value: 0 (0: disabled; 1: enabled) int_ ig_xl accelerometer interrupt generator on int1 pin. default value: 0 (0: disabled; 1: enabled) int_ fss5 fss5 interrupt enable on int1 pin. default value: 0 (0: disabled; 1: enabled) int_ovr overrun interrupt on int1 pin. default value: 0 (0: disabled; 1: enabled) int_fth fifo threshold interrupt on int1 pin. default value: 0 (0: disabled; 1: enabled) int_ boot boot status available on int1 pin. default value: 0 (0: disabled; 1: enabled) int_drdy_g gyroscope data ready on int1 pin. default value: 0 (0: disabled; 1: enabled) int_drdy_xl accelerometer data ready on int1 pin. default value: 0 (0: disabled; 1: enabled) int2_in act int2_ig2 _xl int2_ fss5 int2_ovr int2_fth int2_drd y_temp int2_ drdy_g int2_ drdy_xl
docid025603 rev 1 45/66 LSM6DB0 register description 66 table 43. int2_ctrl register description 11.14 who_am_i (0fh) who_am_i register. 11.15 ctrl_reg1_g (10h) angular rate sensor control register 1. table 45. ctrl_reg1_g register table 46. ctrl_reg1_g register description int2_inact gyroscope interrupt enable on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_ ig2_xl accelerometer interrupt 2 generator on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_ fss5 fss5 interrupt enable on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_ovr overrun interrupt on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_fth fifo threshold interrupt on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_drdy_te mp temperature sensor data ready on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_drdy_g gyroscope data ready on int2 pin. default value: 0 (0: disabled; 1: enabled) int2_drdy_xl accelerometer data ready on int2 pin. default value: 0 (0: disabled; 1: enabled) table 44. who_am_i register 01101000 odr_g2 odr_g1 odr_g0 fs_g1 fs_g0 0 (1) 1. this bit must be set to ?0? for the correct operation of the device bw_g1 bw_g0 odr_g [2:0] gyroscope output data rate selection . default value: 000 (refer to table 47 and table 48 ) fs_g [1:0] gyroscope full-scale selection. default value: 00 (00: 245 dps; 01: 500 dps; 10: not available; 11: 2000 dps) bw_g [1:0] gyroscope bandwidth selection. default value: 00
register description LSM6DB0 46/66 docid025603 rev 1 odr_g [2:0] are used to set odr selection when both the accelerometer and gyroscope are activated. bw_g [1:0] are used to set the bandwidth selection of the gyroscope bandwidth. the following table summarizes all frequencies available for each combination of the odr_g / bw_g bits after lpf1 (see table 47 ) and lpf2 (see table 48 ) when both the accelerometer and gyroscope are activated. for more details regarding signal processing please refer to figure 17 . table 47. odr and bw configuration setting (after lpf1) odr_g2 odr_g1 odr_g0 odr [hz] cutoff [hz] (1) 1. values in the table are indicative and can vary proportionally with the specific odr value. 0 0 0 power-down n.a. 0 0 1 14.9 5 0 1 0 59.5 19 0 1 1 119 38 1 0 0 238 76 1 0 1 476 100 1 1 0 952 100 1 1 1 n.a. n.a.
docid025603 rev 1 47/66 LSM6DB0 register description 66 table 48. odr and bw configuration setting (after lpf2) odr_g [2:0] bw_g [1:0] odr [hz] cutoff [hz] (1) 1. values in the table are indicative and can vary proportionally with the specific odr value. 000 00 power-down n.a. 000 01 power-down n.a. 000 10 power-down n.a. 000 11 power-down n.a. 001 00 14.9 n.a. 001 01 14.9 n.a. 001 10 14.9 n.a. 001 11 14.9 n.a. 010 00 59.5 16 010 01 59.5 16 010 10 59.5 16 010 11 59.5 16 011 00 119 14 011 01 119 31 011 10 119 31 011 11 119 31 100 00 238 14 100 01 238 29 100 10 238 63 100 11 238 78 101 00 476 21 101 01 476 28 101 10 476 57 101 11 476 100 110 00 952 33 110 01 952 40 110 10 952 58 110 11 952 100 111 00 n.a. n.a. 111 01 n.a. n.a. 111 10 n.a. n.a. 111 11 n.a. n.a.
register description LSM6DB0 48/66 docid025603 rev 1 11.16 ctrl_reg2_g (11h) angular rate sensor control register 2. figure 17. int_sel and out_sel configuration gyroscope block diagram 11.17 ctrl_reg3_g (12h) angular rate sensor control register 3. table 49. ctrl_reg2_g register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) 0 (1) int_sel1 int_sel0 out_sel1 out_sel0 table 50. ctrl_reg2_g register description int_sel [1:0] int selection configuration. default value: 00 (refer to figure 17 ) out_sel [1:0] out selection configuration. default value: 00 (refer to figure 17 ) adc lpf1 hpf lpf2 datareg fifo interrupt generator table 51. ctrl_reg3_g register lp_mode hp_en 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) hpcf3_g hpcf2_g hpcf1_g hpcf0_g table 52. ctrl_reg3_g register description lp_mode low-power mode enable. default value: 0 (0: low-power disable; 1:low-power enable) hp_en high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled, refer to figure 17 ) hpcf_g [3:0] gyroscope high-pass filter cutoff frequency selection. default value: 0000 refer to table 53 .
docid025603 rev 1 49/66 LSM6DB0 register description 66 11.18 orient_cfg_g (13h) angular rate sensor sign and orientation register. table 54. orient_cfg_g register table 55. orient_cfg_g register description 11.19 int_gen_src_g (14h) angular rate sensor interrupt source register. table 53. gyroscope high-pass filter cutoff frequency configuration [hz] (1) hpcf_g [3:0] odr= 14.9 hz odr= 59.5 hz odr= 119 hz odr= 238 hz odr= 476 hz odr= 952 hz 0000 1 4 8 15 30 57 0001 0.5 2 4 8 15 30 0010 0.2 1 2 4 8 15 0011 0.1 0.5 1 2 4 8 0100 0.05 0.2 0.5 1 2 4 0101 0.02 0.1 0.2 0.5 1 2 0110 0.01 0.05 0.1 0.2 0.5 1 0111 0.005 0.02 0.05 0.1 0.2 0.5 1000 0.002 0.01 0.02 0.05 0.1 0.2 1001 0.001 0.005 0.01 0.02 0.05 0.1 1. values in the table are indicative and can vary proportionally with the specific odr value. 0 (1) 0 (1) signx_g signy_g signz_g orient_2 orient_1 orient_0 1. these bits must be set to ?0? for the correct operation of the device signx_g pitch axis (x) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) signy_g roll axis (y) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) signz_g yaw axis (z) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) orient [2:0] directional user-orientation selection. default value: 000 table 56. int_gen_src_g register 0 ia_g zh_g zl_g yh_g yl_g xh_g xl_g
register description LSM6DB0 50/66 docid025603 rev 1 11.20 out_temp_l (15h), out_temp_h (16h) temperature data output register. l and h registers together express a 16-bit word in two?s complement right-justified. 11.21 status_reg (17h) status register. table 61. status_reg register table 57. int_gen_src_g register description ia_g interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh_g yaw (z) high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl_g yaw (z) low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh_g roll (y) high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl_g roll (y) low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh_g pitch (x) high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl_g pitch (x) low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 58. out_temp_l register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 59. out_temp_h register temp11 temp11 temp11 temp11 temp11 temp10 temp9 temp8 table 60. out_temp register description temp [11:0] temperature sensor output data. the value is expressed as two?s complement sign extended on the msb. 0 ig_xl ig_g inact boot_ status tda gda xlda
docid025603 rev 1 51/66 LSM6DB0 register description 66 11.22 out_x_g (18h - 19h) angular rate sensor pitch axis (x) angular rate output register. the value is expressed as a 16-bit word in two?s complement. 11.23 out_y_g (1ah - 1bh) angular rate sensor roll axis (y) angular rate output register. the value is expressed as a 16-bit word in two?s complement. 11.24 out_z_g (1ch - 1dh) angular rate sensor yaw axis (z) angular rate output register. the value is expressed as a 16-bit word in two?s complement. 11.25 ctrl_reg4 (1eh) control register 4. table 62. status_reg register description ig_xl accelerometer interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ig_g gyroscope interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) inact inactivity interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) boot_ status boot running flag signal. default value: 0 (0: no boot running; 1: boot running) tda temperature sensor new data available. default value: 0 (0:a new data is not yet available; 1: new data is available) gda gyroscope new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) xlda accelerometer new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) table 63. ctrl_reg4 register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) zen_g yen_g xen_g 0 (1) lir_xl1 4d_xl1
register description LSM6DB0 52/66 docid025603 rev 1 11.26 ctrl_reg5_xl (1fh) linear acceleration sensor control register 5. 11.27 ctrl_reg6_xl (20h) linear acceleration sensor control register 6. table 67. ctrl_reg6_xl register table 64. ctrl_reg4 register description zen_g gyroscope?s yaw axis (z) output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_g gyroscope?s roll axis (y) output enable. default value: 1 (0: y-axis output disabled; 1: y axis output enabled) xen_g gyroscope?s pitch axis (x) output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled) lir_xl1 latched interrupt. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) 4d_xl1 4d option enabled on interrupt. default value: 0 (0: interrupt generator uses 6d for position recognition; 1: interrupt generator uses 4d for position recognition) table 65. ctrl_reg5_xl register dec_1 dec_0 zen_xl yen_xl xen_xl 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) table 66. ctrl_reg5_xl register description dec_ [0:1] decimation of acceleration data on out reg and fifo. default value: 00 (00: no decimation; 01: update every 2 samples; 10: update every 4 samples; 11: update every 8 samples) zen_xl accelerometer?s z-axis output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_xl accelerometer?s y-axis output enable. default value: 1 (0: y-axis output disabled; 1: y-axis output enabled) xen_xl accelerometer?s x axis output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled) odr_xl2 odr_xl1 odr_xl0 fs1_xl fs0_xl bw_scal _odr bw_xl1 bw_xl0
docid025603 rev 1 53/66 LSM6DB0 register description 66 table 68. ctrl_reg6_xl register description odr_xl [2:0] is used to set power mode and odr selection. table 69 indicates all available frequencies when only the accelerometer is activated. 11.28 ctrl_reg7_xl (21h) linear acceleration sensor control register 7. odr_xl [2:0] output data rate and power mode selection . default value: 000 (see table 69 ). fs_xl [1:0] accelerometer full scale selection. default value: 00. (00: 2g; 01: not available; 10: 4g; 11: 8g) bw_scal_ odr bandwidth selection. default value: 0. (0: bandwidth determined by odr selection: - bw = 408 hz when odr = 952 hz, 50 hz, 10 hz; - bw = 211 hz when odr = 476 hz; - bw = 105 hz when odr = 238 hz; - bw = 50 hz when odr = 119 hz; 1: bandwidth selected according to bw_xl [2:1] selection) bw_xl [1:0] anti-aliasing filter bandwidth selection. default value: 00. (00: 408 hz; 01: 211 hz; 10: 105 hz; 11: 50 hz) table 69. odr register setting (accelerometer only mode) odr_xl2 odr_xl1 odr_xl0 odr selection [hz] 0 0 0 power-down 0 0 1 10 hz 0 1 0 50 hz 0 1 1 119 hz 1 0 0 238 hz 1 0 1 476 hz 1 1 0 952 hz 1 1 1 n.a. table 70. ctrl_reg7_xl register hr dcf1 dcf0 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) fds 0 (1) hpis1
register description LSM6DB0 54/66 docid025603 rev 1 11.29 ctrl_reg8 (22h) control register 8. table 71. ctrl_reg7_xl register description hr high resolution mode for accelerometer enable. default value: 0 (0: disabled; 1: enabled). refer to table 72 . dcf[1:0] accelerometer digital filter (high-pass and low-pass) cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected odr. refer to table 72 . fds filtered data selection. default value: 0. (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpis1 high pass filter enabled for acceleration sensor interrupt function on interrupt. default value: 0. (0: filter bypassed; 1: filter enabled) table 72. low-pass cutoff frequency in high resolution mode (hr = 1) hr ctrl_reg7 (dcf [1:0]) lp cutoff freq. [hz] 1 00 odr/50 1 01 odr/100 1 10 odr/9 1 11 odr/400 table 73. ctrl_reg8 register boot bdu h_lactive 0 (1) sim if_add_inc ble sw_reset 1. this bit must be set to ?0? for the correct operation of the device. table 74. ctrl_reg8 register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content (1) ) bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb read) h_lactive interrupt activation level. default value: 0 (0: interrupt output pins active high; 1: interrupt output pins active low) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) if_add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). default value: 1 (0: disabled; 1: enabled) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) sw_reset software reset. default value: 0 (0: normal mode; 1: reset device) this bit is cleared by hardware after next flash boot. 1. boot request is executed as soon as the internal oscillator is turned-on. it is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode or sleep mode.
docid025603 rev 1 55/66 LSM6DB0 register description 66 11.30 ctrl_reg9 (23h) control register 9. 11.31 ctrl_reg10 (24h) control register 10. table 77. ctrl_reg10 register table 75. ctrl_reg9 register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device sleep_g 0 (1) fifo_ temp_en drdy_ mask_bit i2c_disable fifo_en stop_on _fth table 76. ctrl_reg9 register description sleep_g gyroscope sleep mode enable. default value: 0 (0: disabled; 1: enabled) fifo_temp_en temperature data storage in fifo enable. default value: 0 (0: temperature data not stored in fifo; 1: temperature data stored in fifo) drdy_mask_bit data available enable bit. default value: 0 (0: da timer disabled; 1: da timer enabled) i2c_disable disable i 2 c interface. default value: 0 (0: both i 2 c and spi enabled; 1: i 2 c disabled, spi only) fifo_en fifo memory enable. default value: 0 (0: disabled; 1: enabled) stop_on_fth enable fifo threshold level use. default value: 0 (0: fifo depth is not limited; 1: fifo depth is limited to threshold level) 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) 0 (1) 0 (1) st_g 0 (1) st_xl table 78. ctrl_reg10 register description st_g angular rate sensor self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled;) st_xl linear acceleration sensor self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled;)
register description LSM6DB0 56/66 docid025603 rev 1 11.32 int_gen_src_xl (26h) linear acceleration sensor interrupt source register. 11.33 status_reg (27h) status register. table 79. int_gen_src_xl register 0 ia_xl zh_xl zl_xl yh_xl yl_xl xh_xl xl_xl table 80. int_gen_src_xl register description ia_xl interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh_xl accelerometer?s z high event. default value: 0 (0: no interrupt, 1: z high event has occurred) zl_xl accelerometer?s z low event. default value: 0 (0: no interrupt; 1: z low event has occurred) yh_xl accelerometer?s y high event. default value: 0 (0: no interrupt, 1: y high event has occurred) yl_xl accelerometer?s y low event. default value: 0 (0: no interrupt, 1: y low event has occurred) xh_xl accelerometer?s x high event. default value: 0 (0: no interrupt, 1: x high event has occurred) xl_xl accelerometer?s x low. event. default value: 0 (0: no interrupt, 1: x low event has occurred) table 81. status_reg register 0 ig_xl ig_g inact boot_ status tda gda xlda table 82. status_reg register description ig_xl accelerometer interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ig_g gyroscope interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) inact inactivity interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) boot_ status boot running flag signal. default value: 0 (0: no boot running; 1: boot running) tda temperature sensor new data available. default value: 0 (0: a new data is not yet available; 1: a new data is available) gda gyroscope new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) xlda accelerometer new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available)
docid025603 rev 1 57/66 LSM6DB0 register description 66 11.34 out_x_xl (28h - 29h) linear acceleration sensor x-axis output register. the value is expressed as a 16-bit word in two?s complement. 11.35 out_y_xl (2ah - 2bh) linear acceleration sensor y-axis output register. the value is expressed as a 16-bit word in two?s complement. 11.36 out_z_xl (2ch - 2dh) linear acceleration sensor z-axis output register. the value is expressed as a 16-bit word in two?s complement. 11.37 fifo_ctrl (2eh) fifo control register. table 83. fifo_ctrl register fmode2 fmode1 fmode0 fth4 fth3 fth2 fth1 fth0 table 84. fifo_ctrl register description fmode [2:0] fifo mode selection bits. default value: 000 for further details refer to table 85 . fth [4:0] fifo threshold level setting. default value: 0 0000 table 85. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stop collecting data when fifo is full. 0 1 0 reserved 0 1 1 continuous mode until trigger is deasserted, then fifo mode. 1 0 0 bypass mode until trigger is deasserted, then continuous mode. 1 1 0 continuous mode. if the fifo is full, the new sample over- writes the older one.
register description LSM6DB0 58/66 docid025603 rev 1 11.38 fifo_src (2fh) fifo status control register. table 86. fifo_src register table 87. fifo_src register description 11.39 int_gen_cfg_g (30h) angular rate sensor interrupt generator configuration register. fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 fth fifo threshold status. (0: fifo filling is lower than threshold level; 1: fifo filling is equal or higher than threshold level ovrn fifo overrun status. (0: fifo is not completely filled; 1: fifo is completely filled and at least one sample has been overwritten) for further details refer to table 88 . fss [5:0] number of unread samples stored into fifo. (000000: fifo empty; 100000: fifo full, 32 unread samples) for further details refer to table 88 . table 88. fifo_src example: ovr/fss details fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 description 00000000 fifo empty -- (1) 1. when the number of unread samples in fifo is greater than the threshold level set in register fifo_ctrl (2eh) , fth value is ?1?. 00000011 unread sample ... -- (1) 010000032 unread samples 11100000at least one sample has been overwritten table 89. int_gen_cfg_g register aoi_g lir_g zhie_g zlie_g yhie_g ylie_g xhie_g xlie_g
docid025603 rev 1 59/66 LSM6DB0 register description 66 table 90. int_gen_cfg_g register description 11.40 int_gen_ths_x_g (31h - 32h) angular rate sensor interrupt generator threshold registers. the value is expressed as a 15- bit word in two?s complement. table 93. int_gen_ths_x_g register description aoi_g and/or combination of gyroscope?s interrupt events. default value: 0 (0: or combination; 1: and combination) lir_g latch gyroscope interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) zhie_g enable interrupt generation on gyroscope?s yaw (z) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) zlie_g enable interrupt generation on gyroscope?s yaw (z) axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) yhie_g enable interrupt generation on gyroscope?s roll (y) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) ylie_g enable interrupt generation on gyroscope?s roll (y) axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) xhie_g enable interrupt generation on gyroscope?s pitch (x) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) xlie_g enable interrupt generation on gyroscope?s pitch (x) axis low event. default value: 0. (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) table 91. int_gen_ths_xh_g register dcrm_g ths_g_ x14 ths_g_ x13 ths_g_ x12 ths_g_ x11 ths_g_ x10 ths_g_ x9 ths_g_ x8 table 92. int_gen_ths_xl_g register ths_g_ x7 ths_g_ x6 ths_g_ x5 ths_g_ x4 ths_g_ x3 ths_g_ x2 ths_g_ x1 ths_g_ x0 dcrm_g decrement or reset counter mode selection. default value: 0 (0: reset; 1: decrement, as per counter behavior in figure 18 and figure 19 ) ths_g_x [14:0] angular rate sensor interrupt threshold on pitch (x) axis. default value: 0000000 00000000.
register description LSM6DB0 60/66 docid025603 rev 1 11.41 int_gen_ths_y_g (33h - 34h) angular rate sensor interrupt generator threshold registers. the value is expressed as a 15- bit word in two?s complement. table 96. int_gen_ths_y_g register description 11.42 int_gen_ths_z_g (35h - 36h) angular rate sensor interrupt generator threshold registers. the value is expressed as a 15- bit word in two?s complement. table 99. int_gen_ths_z_g register description 11.43 int_gen_dur_g (37h) angular rate sensor interrupt generator duration register. table 100. int_gen_dur_g register table 94. int_gen_ths_yh_g register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device ths_g_ y14 ths_g_ y13 ths_g_ y12 ths_g_ y11 ths_g_ y10 ths_g_ y9 ths_g_ y8 table 95. int_gen_ths_yl_g register ths_g_ y7 ths_g_ y6 ths_g_ y5 ths_g_ y4 ths_g_ y3 ths_g_ y2 ths_g_ y1 ths_g_ y0 ths_g_y [14:0] angular rate sensor interrupt threshold on roll (y) axis. default value: 0000000 00000000. table 97. int_gen_ths_zh_g register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device ths_g_ z14 ths_g_ z13 ths_g_ z12 ths_g_ z11 ths_g_ z10 ths_g_ z9 ths_g_ z8 table 98. int_gen_ths_zl_g register ths_g_ z7 ths_g_ z6 ths_g_ z5 ths_g_ z4 ths_g_ z3 ths_g_ z2 ths_g_ z1 ths_g_ z0 ths_g_z [14:0] angular rate sensor interrupt thresholds on yaw (z) axis. default value: 0000000 00000000. wait_g dur_g6 dur_g5 dur_g4 dur_g3 dur_g2 dur_g1 dur_g0
docid025603 rev 1 61/66 LSM6DB0 register description 66 table 101. int_gen_dur_g register description the dur_g [6:0] bits set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. the wait_g bit has the following meaning: ?0?: the interrupt falls immediately if the signal crosses the selected threshold ?1?: if the signal crosses the selected threshold, the interrupt falls after a number of samples equal to the value of the duration counter register. for further details refer to figure 18 and figure 19 . figure 18. wait bit disabled wait_g exit from interrupt wait function enable. default value: 0 (0: wait function off; 1: wait for dur_g [6:0] samples before exiting interrupt) dur_g [6:0] enter/exit interrupt duration value. default value: 000 0000 ? wait bit = ?0? interrupt disabled as soon as condition is no longer valid (ex: ra te value below threshold) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? disabled
register description LSM6DB0 62/66 docid025603 rev 1 figure 19. wait bit enabled ? wait bit = ?1? interrupt disabled after duration sample (sort of hysteresis) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? enabled duration value is the same used to validate interrupt
docid025603 rev 1 63/66 LSM6DB0 soldering information 66 12 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com/mems .
package information LSM6DB0 64/66 docid025603 rev 1 13 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 20. lga-22: mechanical data and package dimensions dimensions are in millimeter unless otherwise specified general tolerance is +/-0.1mm unless otherwise specified outer dimensions item dimension [mm] tolerance [mm] 1 . 0 0 0 . 3 ] l [ h t g n e l 1 . 0 0 0 . 3 ] w [ h t d i w x a m 3 0 . 1 ] h [ t h g i e h 8514415_a
docid025603 rev 1 65/66 LSM6DB0 revision history 66 14 revision history table 102. document revision history date revision changes 28-nov-2013 1 initial release
LSM6DB0 66/66 docid025603 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of LSM6DB0

	To Download LSM6DB0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .