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| june 2012 doc id 023133 rev 2 1/55 1 stm8l052r8 value line, 8-bit ultralow power mcu, 64-kb flash, 256-bytes data eeprom, rtc, lcd, timers,usart, i2c, spi, adc data brief features operating conditions ? operating power supply: 1.8 v to 3.6 v ? temperature range: -40 c to 85 c low power features ? 5 low power modes: wait, low power run (5.9 a), low power wait (3 a), active-halt with full rtc (1.4 a), halt (400 na) ? dynamic power consumption: 200 a/mhz + 330 a ? ultra-low leakage per i/0: 50 na ? fast wakeup from halt: 4.7 s advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq. 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultra-safe bor reset with 5 programmable thresholds ? ultra low power por/pdr ? programmable voltage detector (pvd) clock management ? 32 khz and 1 to 16 mhz crystal oscillators ? internal 16 mhz factory-trimmed rc ? 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt ? digital calibration with +/- 0.5ppm accuracy ? advanced anti-tamper detection lcd: 8x24 or 4x28 w/ step-up converter memories ? 64 kb flash program memory and 256 bytes data eeprom with ecc, rww ? flexible write and read protection modes ? 4 kb of ram dma ? 4 channels supporting adc, spis, i2c, usarts, timers ? 1 channel for memory-to-memory 12-bit adc up to 1 msps/28 channels ? internal reference voltage timers ? three 16-bit timers with 2 channels (used as ic, oc, pwm), quadrature encoder ? one 16-bit advanced control timer with 3 channels, supporting motor control ? one 8-bit timer with 7-bit prescaler ? 2 watchdogs: 1 window, 1 independent ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? two synchronous serial interfaces (spi) ?fast i 2 c 400 khz smbus and pmbus ? three usarts (iso 7816 interface + irda) up to 54 i/os, all mappab le on interrupt vectors development support ? fast on-chip programming and non- intrusive debugging with swim ? bootloader using usart lqfp64 www.st.com
contents stm8l052r8 2/55 doc id 023133 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 17 3.11 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11.1 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 stm8l052r8 contents doc id 023133 rev 2 3/55 3.14.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 system configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 list of tables stm8l052r8 4/55 doc id 023133 rev 2 list of tables table 1. high density value line stm8l05xxx low power device features and peripheral counts . . . 8 table 2. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. high density value line stm8l05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 51 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 stm8l052r8 list of figures doc id 023133 rev 2 5/55 list of figures figure 1. high density value line stm8l05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. high density value line stm8l05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. stm8l052r8 64-pin lqfp64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 51 figure 6. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 introduction stm8l052r8 6/55 doc id 023133 rev 2 1 introduction this document describes the features, pinout, mechanical data and ordering information of the high density value line stm8l052r8 microcontroller with a flash memory density of 64 kbytes. for further details on the whole stmicroelectronics high density family please refer to section 2.2: ultra low power continuum . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). high density value line devices provide the following benefits: integrated system ? 64 kbytes of high density embedded flash program memory ? 256 bytes of data eeprom ? 4 kbytes of ram ? internal high speed and low-power low speed rc ? embedded reset ultra low power consumption ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for low power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals ? wide choice of development tools these features make the value line stm8l05xxx ultra low power microcontroller family suitable for a wide range of consumer and mass market applications. refer to table 1: high density value line stm8l05xxx low power device features and peripheral counts and section 3: functional overview for an overview of the complete range of peripherals proposed in this family. figure 1 shows the block diagram of the high density value line stm8l05xxx family. stm8l052r8 description doc id 023133 rev 2 7/55 2 description the high density value line stm8l05xxx devices are members of the stm8l ultra low power 8-bit family. the value line stm8l05xxx ultra low power fam ily features the enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debug ging and ultra-fast flash programming. high density value line stm8l0 5xxx microcontrolle rs feature embedded data eeprom and low-power, low-voltage, single- supply program flash memory. all devices offer 12-bit adc, real-time clock, four 16-bit timers, one 8-bit timer as well as standard communication interface such as two spis, i2c, three usarts and 8x24 or 4x28- segment lcd. the 8x24 or 4x 28-segment lcd is available on the high density value line stm8l05xxx. the stm8l05xxx family operates from 1.8 v to 3.6 v and is available in the - 40 to +85 c temperature range. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families includ ing 32-bit families. this make s any transition to a different family very easy, and simplified even more by the use of a common set of development tools. all value line stm8l ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout. description stm8l052r8 8/55 doc id 023133 rev 2 2.1 device overview table 1. high density value line stm8l05xxx low power device features and peripheral counts features stm8l052r8 flash (kbytes) 64 data eeprom (bytes) 256 ram (kbytes) 4 lcd 8x24 or 4x28 timers basic 1 (8-bit) general purpose 3 (16-bit) advanced control 1 (16-bit) communication interfaces spi 2 i2c 1 usart 3 gpios 54 (1) 1. the number of gpios given in this table includes the nrst/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). 12-bit synchronized adc (number of channels) 1 (28) others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 v to 3.6 v operating temperature -40 to +85 c package lqfp64 stm8l052r8 description doc id 023133 rev 2 9/55 2.2 ultra low power continuum the ultra low power value line stm8l05xxx and stm8l15xxx are fully pin-to-pin, software and feature compatible. besides the full comp atibility within the stm8l family, the devices are part of stmicroelectronics microcontrollers ul tra low power strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultra-low leakage process. note: 1 the stm8l05xxx is pin-to-pin compatible with stm8l101xx devices. 2 the stm32l family is pin-to-pin compatible with the general purpose stm32f family. please refer to stm32l15x documentation for more information on these devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultra low power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l05x, stm8l15x and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripheral: adc1 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and opti mize performance, the stm8 l and stm32l devices use a common architecture: same power supply range from 1.8 to 3.6 v architecture optimized to reach ultra-low consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultra-safe reset: same reset strategy for both stm8l and stm32l including power-on reset, power-down reset, brownout reset and programmable voltage detector features st ultra low power continuum al so lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes functional overview stm8l052r8 10/55 doc id 023133 rev 2 3 functional overview figure 1. high density value line stm8l05xxx device block diagram 1. legend : adc: analog-to-digital converter bor: brownout reset dma: direct memory access i2c: inter-integrated circuit multimaster interface lcd: liquid crystal display por/pdr: power on reset / power down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous asyn chronous receiver transmitter wwdg: window watchdog iwdg: independent watchdog - 3 6 # l o c k c o n t r o l l e r a n d # 3 3 # l o c k s ! d d r e s s c o n t r o l a n d d a t a b u s e s + b y t e + b y t e 2 ! - t o c o r e a n d p e r i p h e r a l s ) 7 $ ' k ( z c l o c k 0 o r t ! 0 o r t " 0 o r t # 0 o w e r 6 / , 4 2 % ' , # $ d r i v e r 7 7 $ ' b y t e s 0 o r t $ 0 o r t % " e e p e r 2 4 # 0 r o g r a m m e m o r y $ a t a % % 0 2 / - 6 $ $ 6 $ $ 6 $ $ 6 6 3 3 3 7 ) - 3 # , 3 $ ! 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + ! $ # ? ) . x 6 $ $ ! 6 3 3 ! 3 - " 6 $ $ ! 6 3 3 ! b i t ! $ # 6 2 % & 6 . 2 3 4 0 ! ; = 0 " ; = 0 # ; = 0 $ ; = 0 % ; = 0 & ; = " % % 0 ! , ! 2 - # ! , ) " 4 ! - 0 3 % ' x # / - x 0 / 2 0 $ 2 / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 t o " / 2 0 6 $ 0 6 $ ? ) . 2 % 3 % 4 $ - ! c h a n n e l s c h a n n e l s c h a n n e l s c h a n n e l s 6 , # $ t o 6 , # $ b o o s t e r ) n t e r n a l r e f e r e n c e v o l t a g e 6 2 % & ) . 4 o u t ) 2 ? 4 ) - - ( z o s c i l l a t o r - ( z i n t e r n a l 2 # k ( z o s c i l l a t o r 3 4 - # o r e b i t 4 i m e r b i t 4 i m e r k ( z i n t e r n a l 2 # ) n t e r r u p t c o n t r o l l e r b i t 4 i m e r $ e b u g m o d u l e 3 7 ) - b i t 4 i m e r ) n f r a r e d i n t e r f a c e 3 0 ) ) # 5 3 ! 2 4 6 2 % & 0 o r t & b i t 4 i m e r c h a n n e l s 3 0 ) 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + 5 3 ! 2 4 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + 5 3 ! 2 4 0 ' ; = 0 o r t ' y p s y u p t o u p t o stm8l052r8 functional overview doc id 023133 rev 2 11/55 3.1 low power modes the high density value line stm8l05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: wait mode : the cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt, event or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). low power run mode : the cpu and the selected peripherals are running. execution is done from ram with a low speed oscilla tor (lsi or lse). fl ash memory and data eeprom are stopped and the vo ltage regulator is configur ed in ultra low power mode. the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low power run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, dma controller (dma1) and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. halt mode : cpu and peripheral clocks are stopped, the device remains powered on. the wakeup is triggered by an external interrupt or reset. a few peripherals have also a wakeup from halt capability. switching off th e internal reference voltage reduces power consumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s. functional overview stm8l052r8 12/55 doc id 023133 rev 2 3.2 central processing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - si ngle cycle fetching most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-mbyte linear memory space 16-bit stack pointer - access to a 64-kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for lookup tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the high density value line stm8l05xxx devices feature a nested vectored interrupt controller: nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 40 external interrupt sources on 11 vectors trap and reset interrupts stm8l052r8 functional overview doc id 023133 rev 2 13/55 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.8 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: v ss1 , v dd1 , v ss2 , v dd2 , v ss3 , v dd3 = 1.8 to 3.6 v: external power supply for i/os and for the internal regulator. provided externally through v dd pins, the corresponding ground pin is vss. v ss1 /v ss2 /v ss3 /v ss4 and v dd1 /v dd2 /v dd3 must not be left unconnected. v ssa ; v dda = 1.8 to 3.6 v: external power supplies for analog peripherals. v dda and v ssa must be connected to v dd and v ss , respectively. v ref+ ; v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr), coupled with a brownout reset (bor) circ uitry that ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains under reset when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the high density value line stm8l05xxx embeds an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mv r) for run, wait for interrupt (wfi) and wait for event (wfe) modes low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption. functional overview stm8l052r8 14/55 doc id 023133 rev 2 3.4 clock management the clock controller distributes the system clock (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cp u and peripherals can be adjusted by a programmable prescaler. safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. system clock sources: 4 different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 khz low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) rtc and lcd clock sources: the above four sources can be chosen to clock the rtc and the lcd, whatever the system clock. startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the system clock is automatically switched to hsi. configurable main clock output (cco): this outputs an external clock for use by the application. stm8l052r8 functional overview doc id 023133 rev 2 15/55 figure 2. high density value line stm8l05xxx clock tree diagram 1. the hse clock source can be either an external crystal/ceramic res onator or an external source (hse bypass). refer to section hse clock in the stm8l15x and stm8l16x reference manual (rm0031). 2. the lse clock source can be either an external crystal/ceramic resonat or or a external source (lse bypass). refer to section lse clock in the stm8l15x and stm8l16x reference manual (rm0031). 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically.the subsecond field can also be read in binary format. the calendar can be corrected from 1 to 32767 rtc clock pulses. this allows to make a synchronization to a master clock. the rtc offers a digital calibration which allows an accuracy of +/-0.5ppm. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a different resolution, the wakeup time can reach 36 hours. periodic alarms based on the calendar can also be generated from every second to every year. a clock security system detects a failure on lse, and can provide an interrupt with wakeup capability. the rtc clock can automatically switch to lsi in case of lse failure. the rtc also provides 3 anti-tamper detection pins. this detection embeds aprogrammable filter and can wakeup the mcu. ( 3 % / 3 # - ( z ( 3 ) 2 # - ( z , 3 ) 2 # k ( z , 3 % / 3 # k ( z ( 3 ) , 3 ) 2 4 # p r e s c a l e r 0 # , + t o p e r i p h e r a l s 2 4 # # , + t o , # $ t o ) 7 $ ' 3 9 3 # , + ( 3 % , 3 ) , 3 % / 3 # ? / 5 4 / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? ) . c l o c k o u t p u t # # / p r e s c a l e r ( 3 ) , 3 ) ( 3 % , 3 % # # / t o c o r e a n d m e m o r y 3 9 3 # , + 0 r e s c a l e r ) 7 $ ' # , + 2 4 # 3 % , ; = , 3 % # , + " % % 0 3 % , ; = t o " % % 0 " % % 0 # , + - 3 6 # 3 3 c o n f i g u r a b l e 0 e r i p h e r a l # l o c k e n a b l e b i t s t o 2 4 # 2 4 # # , + c l o c k e n a b l e b i t , # $ # , + t o , # $ 3 9 3 # , + ( a l t c l o c k e n a b l e b i t , # $ p e r i p h e r a l 2 4 # # , + , # $ p e r i p h e r a l # 3 3 ? , 3 % functional overview stm8l052r8 16/55 doc id 023133 rev 2 3.6 lcd (liquid crystal display) the lcd is only availabl e on stm8l052xx devices. the liquid crystal display drives up to 8 common terminals and up to 24 segment terminals to drive up to 192 pixels. it can also be configured to drive up to 4 common and 28 segments (up to 112 pixels). internal step-up converter to guarantee contrast control whatever v dd . static 1/2, 1/3, 1/4, 1/8 duty supported. static 1/2, 1/3, 1/4 bias supported. phase inversion to reduce power consumption and emi. up to 8 pixels which ca n be programmed to blink. the lcd controller can operate in halt mode. note: unnecessary segments and common pins can be used as general i/o pins. 3.7 memories the high density value line stm8l05xxx devices have the following main features: 4 kbytes of ram the non-volatile memory is divided into three arrays: ? 64 kbytes of high density embedded flash program memory ? 256 bytes of data eeprom ?option bytes the eeprom embeds the error correction code (e cc) feature. it supp orts the read-while- write (rww): it is possible to execute the code from the program matrix while programming/erasing the data matrix. the option byte protects part of the flash program memory from write and readout piracy. 3.8 dma a 4-channel direct memory access controlle r (dma1) offers a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 chann els are shared between the following ips with dma capability: adc1, i2c1 , spi1, spi 2, usart1, usart2, usart3 and the five timers. stm8l052r8 functional overview doc id 023133 rev 2 17/55 3.9 analog-to-digital converter 12-bit analog-to-digital converter (adc1) with 28 channels (including 4 fast channels), temperature sensor and internal reference voltage conversion time down to 1 s with f sysclk = 16 mhz programmable resolution programmable sampling time single and continuous mode of conversion scan capability: automatic conversion perfor med on a selected gr oup of anal og inputs analog watchdog: interrupt generation when the converted voltage is outside the programmed threshold triggered by timer note: adc1 can be served by dma1. 3.10 system configuration cont roller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing interface allows application software to control the routing of different i/os to the tim1 timer input captures. it also controls the routing of internal analog signals to adc1 and the internal reference voltage v refint . 3.11 timers the high density value line stm8l05xxx devices contain one advanced control timer (tim1), three 16-bit general purpose timers (tim2, tim3 and tim5) and one 8-bit basic timer (tim4). all the timers can be served by dma1. ta bl e 2 compares the features of the advanced control, general-purpose and basic timers. table 2. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim1 16-bit up/down any integer from 1 to 65536 ye s 3 + 1 3 tim2 any power of 2 from 1 to 128 2 none tim3 tim5 tim4 8-bit up any power of 2 from 1 to 32768 0 functional overview stm8l052r8 18/55 doc id 023133 rev 2 3.11.1 tim1 - 16-bit ad vanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external i/o synchronization module to control the timer with external signals break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time encoder mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) 3.11.2 16-bit general purpose timers 16-bit autoreload (ar) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) 2 individually configurable capture/compare channels pwm mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.11.3 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow. 3.12 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. 3.12.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.12.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. stm8l052r8 functional overview doc id 023133 rev 2 19/55 3.13 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 3.14 communication interfaces 3.14.1 spi the serial peripheral interfaces (spi1 and spi2) provide half/ full duplex synchronous serial communication with external devices. maximum speed: 8 mbit/s (f sysclk /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software hardware crc calculation slave/master selection input pin note: spi1 and spi2 can be served by the dma1 controller. 3.14.2 i2c the i 2 c bus interface (i 2 c1) provides multi-master capab ility, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. master, slave and multi-master capability standard mode up to 100 khz and fast speed modes up to 400 khz 7-bit and 10-bit addressing modes smbus 2.0 and pmbus support hardware crc calculation note: i 2 c1 can be served by the dma1 controller. 3.14.3 usart the usart interfaces (usart1, usart2 and usart3) allow full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 1 mbit/s full duplex sci spi1 emulation high precision baud rate generator smartcard emulation irda sir encoder decoder single wire half duplex mode note: usart1 , usart2 and usart3 can be served by the dma1 controller. functional overview stm8l052r8 20/55 doc id 023133 rev 2 3.15 infrared (ir) interface the high density value line st m8l05xxx devices contain an infr ared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.16 development support development tools development tools for the stm8 microcontrollers include: the stice emulation system offe ring tracing and code profiling the stvd high-level language debugger including c compiler, assembler and integrated development environment the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers. bootloader a bootloader is available to reprogram the flash memory using the usart1, usart2, usart3 (usarts in asynchronous mode), spi1 or spi2 interfaces. the reference document for the bootloader is um0560: stm8 bootloader user manual . the bootloader is used to download application software into the device memories, including ram, program and data memory, using standard serial interfaces. it is a complementary solution to programming via the swim debugging interface. stm8l052r8 pin description doc id 023133 rev 2 21/55 4 pin description figure 3. stm8l052r8 64-pin lqfp64 package pinout . 2 3 4 0 ! 0 ! 0 ! 0 ! 6 , # $ 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 6 $ $ 6 3 3 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 ' 0 ' 0 ' 0 ' 0 " 0 " 0 & 0 & 0 & 0 & 0 & 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ a i pin description stm8l052r8 22/55 doc id 023133 rev 2 table 3. legend/abbreviation for table 4 type i= input, o = output, s = power supply level ft five-volt tolerant tt 3.6 v tolerant output hs = high sink/source (20 ma) port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state a fter reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 4. high density value line stm8l05xxx pin description pin number pin name type i/o level input output main function (after reset) default alternate function lqfp64 floating wpu ext. interrupt high sink/source od pp 2 nrst/pa1 (1) i/o x hs x x reset pa 1 3 pa2/osc_in/ [usart1_tx] (8) / [spi1_miso] (8) i/o x x x hs x x port a2 hse oscillator input / [usart1 transmit] / [spi1 master in- slave out] 4 pa3/osc_out/ [usart1_ rx] (8) /[spi1_mosi] (8) i/o x x x hs x x port a3 hse oscillator output / [usart1 receive]/ [spi1 master out/slave in] / 5 pa4/tim2_bkin/ [tim2_etr] (8) / lcd_com0/adc1_in2 i/o ft (2) xxxhsxx port a4 timer 2 - break input /[timer 2 - trigger] / lcd com 0 / adc1 input 2 6 pa5/tim3_bkin/ [tim3_etr] (8) / lcd_com1/adc1_in1 i/o ft (2) xxxhsxx port a5 timer 3 - break input /[timer 3 - trigger] / lcd_com 1 / adc1 input 1 7 pa 6 / [adc1_trig] / lcd_com2/adc1_in0 i/o ft (2) xxxhsxx port a6 [adc1 - trigger] / lcd_com2 / adc1 input 0 8 pa7/lcd_seg0 (2) /tim5_ch1 i/o ft (2) xxxhsxx port a7 lcd segment 0/ tim5 channel 1 31 pb0 (3) /tim2_ch1/ lcd_seg10/adc1_in18 i/o ft (2) xxxhsxx port b0 timer 2 - channel 1 / lcd segment 10 / adc1_in18 32 pb1/tim3_ch1/ lcd_seg11/ adc1_in17 i/o ft (2) xxxhsxx port b1 timer 3 - channel 1 / lcd segment 11 / adc1_in17 stm8l052r8 pin description doc id 023133 rev 2 23/55 33 pb2/ tim2_ch2/ lcd_seg12/ adc1_in16 i/o ft (2) xxxhsxx port b2 timer 2 - channel 2 / lcd segment 12 / adc1_in16 34 pb3/tim2_etr/ lcd_seg13/ adc1_in15 i/o ft (2) xxxhsxx port b3 timer 2 - trigger / lcd segment 13 /adc1_in15 35 pb4 (3) / [spi1_nss] (8) / lcd_seg14/ adc1_in14 i/o ft (2) x (3) x (3) xhsx x port b4 [spi1 master/slave select] / lcd segment 14 / adc1_in14 36 pb5/ [spi1_sck] (8) / lcd_seg15/ adc1_in13 i/o ft (2) xxxhsxx port b5 [spi1 clock] / lcd segment 15 / adc1_in13 37 pb6/[ spi1_mosi] (8) / lcd_seg16/ adc1_in12 i/o ft (2) xxxhsxx port b6 [spi1 master out/slave in] / lcd segment 16 / adc1_in12 38 pb7/ [spi1_miso] (8) / lcd_seg17/ adc1_in11 i/o ft (2) xxxhsxx port b7 [spi1 master in- slave out] /lcd segment 17 / adc1_in11 53 pc0 (2) /i2c1_sda i/o ft (2) xxt (4) port c0 i2c1 data 54 pc1 (2) /i2c1_scl i/o ft (2) xxt (4) port c1 i2c1 clock 57 pc2/usart1_rx/ lcd_seg22/adc1_in6/ vrefint i/o ft (2) xxxhsxx port c2 usart1 receive / lcd segment 22 / adc1_in6 /internal voltage reference output 58 pc3/usart1_tx/ lcd_seg23/ adc1_in5 i/o ft (2) xxxhsxx port c3 usart1 transmit / lcd segment 23 / adc1_in5 59 pc4/usart1_ck/ i2c1_smb/cco/ adc1_in4 i/o ft (2) xxxhsxx port c4 usart1 synchronous clock / i2c1_smb / configurable clock output / adc1_in4 60 pc5/osc32_in / [spi1_nss] (8) / [usart1_tx] (8) i/o ft (2) xxxhsxx port c5 lse oscillator input / [spi1 master/slave select] / [usart1 transmit] 61 pc6/osc32_out/ [spi1_sck] (8) / [usart1_rx] (8) i/o ft (2) xxxhsxx port c6 lse oscillator output / [spi1 clock] / [usart1 receive] 62 pc7/adc1_in3 i/o ft (2) xxxhsxx port c7 adc1_in3 table 4. high density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp64 floating wpu ext. interrupt high sink/source od pp pin description stm8l052r8 24/55 doc id 023133 rev 2 25 pd0/tim3_ch2/ [adc1_trig] (8) / lcd_seg7/adc1_in22/ i/o ft (2) xxxhsxx port d0 timer 3 - channel 2 / [adc1_trigger] / lcd segment 7 / adc1_in22 26 pd1/tim3_etr/ lcd_com3/ adc1_in21 i/o ft (2) xxxhsxx port d1 timer 3 - trigger / lcd_com3 / adc1_in21 27 pd2/tim1_ch1 /lcd_seg8/ adc1_in20 i/o ft (2) xxxhsxx port d2 timer 1 - channel 1 / lcd segment 8 / adc1_in20 28 pd3/ tim1_etr/ lcd_seg9/adc1_in19 i/o ft (2) xxxhsxx port d3 timer 1 - trigger / lcd segment 9 / adc1_in19 45 pd4/tim1_ch2 /lcd_seg18/ adc1_in10 i/o ft (2) xxxhsxx port d4 timer 1 - channel 2 / lcd segment 18 / adc1_in10 46 pd5/tim1_ch3 /lcd_seg19/ adc1_in9 i/o ft (2) xxxhsxx port d5 timer 1 - channel 3 / lcd segment 19 / adc1_in9 47 pd6/tim1_bkin /lcd_seg20/ adc1_in8/rtc_calib/ /vrefint i/o ft (2) xxxhsxx port d6 timer 1 - break input / lcd segment 20 / adc1_in8 / rtc calibration / internal voltage reference output 48 pd7/tim1_ch1n /lcd_seg21/ adc1_in7/rtc_alarm/v refint i/o ft (2) xxxhsxx port d7 timer 1 - inverted channel 1/ lcd segment 21 / adc1_in7 / rtc alarm / internal voltage reference output 49 pg4/spi2_nss i/o ft (2) x xxhsxx port g4 spi2 master/slave select 50 pg5/spi2_sck i/o ft (2) x xxhsxx port g5 spi2 clock 51 pg6/spi2_mosi i/o ft (2) x xxhsxx port g6 spi2 master out- slave in 52 pg7/spi2_miso i/o ft (2) x xxhsxx port g7 spi2 master in- slave out 19 pe0 (2) /lcd_seg1/tim5_c h2/rtc_tamp1 i/o ft (2) xxxhsxx port e0 lcd segment 1/timer 5 channel 2/rtc tamper 1 20 pe1/tim1_ch2n/ lcd_seg2/rtc_tamp2 i/o ft (2) xxxhsxx port e1 timer 1 - inverted channel 2 / lcd segment 2/ rtc tamper 2 table 4. high density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp64 floating wpu ext. interrupt high sink/source od pp stm8l052r8 pin description doc id 023133 rev 2 25/55 21 pe2/tim1_ch3n/ lcd_seg3/rtc_tamp3 i/o ft (2) xxxhsxx port e2 timer 1 - inverted channel 3 / lcd segment 3/ rtc tamper 3 22 pe3/lcd_seg4 /usart2_rx i/o ft (2) xxxhsxx port e3 lcd segment 4 /usart2 receive 23 pe4/lcd_seg5 /usart2_tx i/o ft (2) xxxhsxx port e4 lcd segment 5 /usart2 transmit 24 pe5/lcd_seg6/ adc1_in23/usart2_ck i/o ft (2) xxxhsxx port e5 lcd segment 6 / adc1_in23/usart2 synchronous clock 63 pe6/pvd_in/tim5_bkin i/o ft (2) xxxhsxx port e6 pvd_in /tim5 break input 64 pe7 /tim5_etr i/o ft (2) xxxhsxx port e7 tim5 trigger 39 pf0/adc1_in24 / [usart3_tx] i/o x x x hs x x port f0 adc1_in24/ [ usart3 transmit ] 40 pf1/adc1_in25/ [usart3_rx] i/o x xxhsxx port f1 adc1_in25/ [ usart3 receive] 41 pf4/lcd_seg36 /lcd_com4 (5) i/o ft (2) x xxhsxx port f4 lcd_seg36/ lcd com4 (5) 42 pf5/lcd_seg37/ lcd_com5 (5) i/o ft (2) x xxhsxx port f5 lcd_seg37/ lcd com5 (5) 43 pf6/lcd_seg38/ lcd_com6 (5) i/o ft (2) x xxhsxx port f6 lcd_seg38/ lcd com6 (5) 44 pf7/lcd_seg39/ lcd_com7 (5) i/o ft (2) x xxhsxx port f7 lcd_seg39/ lcd com7 (5) 18 vlcd s lcd booster external capacitor 11 v dd1 s digital power supply 10 v ss1 i/o ground 12 v dda s analog supply voltage 13 v ref+ s adc1 positive voltage reference 14 pg0/usart3_rx/ [tim2_bkin] i/o ft (2) x xxhsxx port g0 usart3 receive / [timer 2 - break input] 15 pg1/usart3_tx/ [tim3_bkin] i/o ft (2) x xxhsxx port g1 usart3 transmit / [timer 3 -break input] table 4. high density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp64 floating wpu ext. interrupt high sink/source od pp pin description stm8l052r8 26/55 doc id 023133 rev 2 16 pg2/usart3_ck i/o ft (2) x xxhsxx port g2 usart 3 synchronous clock 17 pg3 [tim3_etr] i/o ft (2) x xxhsxx port g3 [timer 3 - trigger] 9v ssa/ v ref- s analog ground voltage / adc1 negative voltage reference 55 v dd2 s ios supply voltage 56 v ss2 s ios ground voltage 1 pa 0 (6) / [usart1_ck] (8) / swim/beep/ir_tim (7) i/o x x x hs xx port a0 [usart1 synchronous clock] (8) / swim input and output /beep output / infrared timer output 29 v dd3 s ios supply voltage 30 v ss3 s ios ground voltage 1. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as output open-drai n or push-pull, not as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l15x and stm8l16x reference manual (rm0031). 2. in the 5 v tolerant i/os, protection diode to v dd is not implemented. 3. a pull-up is applied to pb0 and pb4 during the reset phase . these two pins are input floating after reset release. 4. in the open-drain output column, ?t? de fines a true open-drain i/o (p -buffer, weak pull-up and protection diode to v dd are not implemented). 5. seg/com multiplexing available on m edium+ and high density devices. seg signals are available by default (see reference manual for details). 6. the pa0 pin is in input pull-up during the reset phase and after reset release. 7. high sink led driver capability available on pa0. 8. [ ] alternate function remapping option (if the same alternate func tion is shown twice, it indi cates an exclusive choice not aduplication of the function). table 4. high density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp64 floating wpu ext. interrupt high sink/source od pp stm8l052r8 pin description doc id 023133 rev 2 27/55 4.1 system configuration options as shown in table 4: high density value line stm8l05xxx pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ? routing interface (ri) and system configuration controller? section in the stm8l15x and stm8l16x reference manual (rm0031). memory and register map stm8l052r8 28/55 doc id 023133 rev 2 5 memory and register map 5.1 memory mapping the memory map is shown in figure 4 . figure 4. memory map 1. table 5 lists the boundary addresses for each memory si ze. the top of the stack is at the ram end address. 2. refer to table 7 for an overview of hardware register mapping, to table 6 for details on i/o port hardware registers, and to table 8 for information on cpu/swim/debug module controller registers. gpio and peripheral registers 0x00 0000 reserved high density (64 kbytes) reset and interrupt vectors 0x00 1000 0x00 10ff 0x00 07ff ram (4 kbytes) (1) (513 bytes) (1) 0x00 1100 data eeprom 0x00 4800 0x00 48ff 0x00 4900 0x00 7fff 0x00 8000 0x00 ffff 0x00 0800 0x00 0fff 0x00 47ff 0x00 7eff 0x00 8080 0x00 807f 0x00 7f00 reserved including stack (256 bytes) option bytes 0x00 4fff 0x00 5000 0x00 57ff 0x00 5800 reserved 0x00 5fff boot rom 0x00 6000 0x00 67ff (2 kbytes) 0x00 6800 reserved cpu/swim/debug/itc registers 0x00 5000 gpio ports 0x00 5050 flash 0x00 50c0 itc-exti 0x00 50d3 rst 0x00 50e0 clk 0x00 50f0 wwdg 0x00 5210 iwdg 0x00 5230 beep 0x00 5250 rtc 0x00 5280 spi1 0x00 52e0 i2c1 0x00 52ff usart1 tim2 tim3 tim1 tim4 irtim adc1 0x00 5070 dma1 syscfg spi2 usart2 0x00 509d 0x00 50a0 0x00 50b0 0x00 5140 0x00 5200 0x00 5300 0x00 5340 0x00 5380 0x00 53f0 0x00 5430 0x00 5440 flash program memory wfe 0x00 50a6 0x00 50b2 pwr reserved reserved 0x00 53c0 reserved ri lcd usart3 0x00 53e0 0x00 5400 0x00 5444 tim5 0x00 52b0 stm8l052r8 memory and register map doc id 023133 rev 2 29/55 5.2 register map table 5. flash and ram boundary addresses memory area size start address end address ram 4 kbytes 0x00 0000 0x00 0fff flash program memory 64 kbytes 0x00 8000 0x01 7fff table 6. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x01 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pc_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 memory and register map stm8l052r8 30/55 doc id 023133 rev 2 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 0x00 501e port g pg_odr port f data output latch register 0x00 0x00 501f pg_idr port g input pin value register 0xxx 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 0x00 5023 to 0x00 502c reserved area (10 bytes) table 6. i/o port hardware register map (continued) address block register label register name reset status table 7. general hardware register map address block register label register name reset status 0x00 502e to 0x00 5049 reserved area (27 bytes) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr data eeprom unprotection key register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 0x00 5055 to 0x00 506f reserved area (27 bytes) stm8l052r8 memory and register map doc id 023133 rev 2 31/55 0x00 5070 dma1 dma1_gcsr dma1 global configuration & status register 0xfc 0x00 5071 dma1_gir1 dma1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 bytes) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00 0x00 507d 0x00 507e reserved area (2 bytes) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 0x00 5083 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 32/55 doc id 023133 rev 2 0x00 5084 dma1 reserved area (1 byte) 0x00 5085 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 bytes) 0x00 5089 dma1_c2cr dma1 channel 2 configuration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 bytes) 0x00 5093 dma1_c3cr dma1 channel 3 configuration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 0x00 5098 reserved area (1 byte) 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509c reserved area (2 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 33/55 0x00 509d syscfg syscfg syscfg_rmpcr3 remapping register 3 0x00 0x00 509e syscfg_rmpcr1 remapping register 1 0x00 0x00 509f syscfg_rmpcr2 remapping register 2 0x00 0x00 50a0 itc - exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf1 external interrupt port select register 1 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50a9 wfe_cr4 wfe control register 4 0x00 0x00 50aa itc - exti exti_cr4 external interrupt control register 4 0x00 0x00 50ab exti_conf2 external interrupt port select register 2 0x00 0x00 50a9 to 0x00 50af reserved area (7 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power contro l and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 34/55 doc id 023133 rev 2 0x00 50c0 clk clk_ckdivr clock master divider register 0x03 0x00 50c1 clk_crtcr clock rtc register 0x00 (1) 0x00 50c2 clk_ickr internal clock control register 0x11 0x00 50c3 clk_pckenr1 peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 peripheral clock gating register 2 0x00 0x00 50c5 clk_ccor configurable clock control register 0x00 0x00 50c6 clk_eckr external clock control register 0x00 0x00 50c7 clk_scsr system clock status register 0x01 0x00 50c8 clk_swr system clock switch register 0x01 0x00 50c9 clk_swcr clock switch control register 0xx0 0x00 50ca clk_cssr clock se curity system register 0x00 0x00 50cb clk_cbeepr clock beep register 0x00 0x00 50cc clk_hsicalr hsi calibration register 0xxx 0x00 50cd clk_hsitrimr hsi clock ca libration trimming register 0x00 0x00 50ce clk_hsiunlckr hsi unlock register 0x00 0x00 50cf clk_regcsr main regulator control status register 0bxx11100x 0x00 50d0 clk_pckenr3 peripheral clock gating register 3 0x00 0x00 50d1 to 0x00 50d2 reserved area (2 bytes) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 beep beep_csr1 beep control/status register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 bytes) 0x00 50f3 beep_csr2 beep control/status register 2 0x1f 0x00 50f4 to 0x00 513f reserved area (76 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 35/55 0x00 5140 rtc rtc_tr1 time register 1 0x00 0x00 5141 rtc_tr2 time register 2 0x00 0x00 5142 rtc_tr3 time register 3 0x00 0x00 5143 reserved area (1 byte) 0x00 5144 rtc_dr1 date register 1 0x01 0x00 5145 rtc_dr2 date register 2 0x21 0x00 5146 rtc_dr3 date register 3 0x00 0x00 5147 reserved area (1 byte) 0x00 5148 rtc_cr1 control register 1 0x00 (1) 0x00 5149 rtc_cr2 control register 2 0x00 (1) 0x00 514a rtc_cr3 control register 3 0x00 (1) 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 initialization and status register 1 0x01 0x00 514d rtc_isr2 initializatio n and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 bytes) 0x00 5150 rtc_sprerh (1) synchronous prescaler register high 0x00 (1) 0x00 5151 rtc_sprerl (1) synchronous prescaler register low 0xff (1) 0x00 5152 rtc_aprer (1) asynchronous prescaler register 0x7f (1) 0x00 5153 reserved area (1 byte) 0x00 5154 rtc_wutrh (1) wakeup timer register high 0xff (1) 0x00 5155 rtc_wutrl (1) wakeup timer register low 0xff (1) 0x00 5156 reserved area (1 bytes) 0x00 5157 rtc_ssrl subsecond register low 0x00 0x00 5158 rtc_ssrh subsecond register high 0x00 0x00 5159 rtc_wpr write protection register 0x00 0x00 515a rtc_shiftrh shift register high 0x00 0x00 515b rtc_shiftrl shift register low 0x00 0x00 515c rtc_alrmar1 alarm a register 1 0x00 (1) 0x00 515d rtc_alrmar2 alarm a register 2 0x00 (1) 0x00 515e rtc_alrmar3 alarm a register 3 0x00 (1) 0x00 515f rtc_alrmar4 alarm a register 4 0x00 (1) 0x00 5160 to 0x00 5163 reserved area (4 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 36/55 doc id 023133 rev 2 0x00 5164 rtc rtc_alrmassrh alarm a subsecond register high 0x00 (1) 0x00 5165 rtc_alrmassrl alarm a subsecond register low 0x00 (1) 0x00 5166 rtc_alrmassms kr alarm a masking register 0x00 (1) 0x00 5167 to 0x00 5169 reserved area (3 bytes) 0x00 516a rtc rtc_calrh calibration register high 0x00 (1) 0x00 516b rtc_calrl calibration register low 0x00 (1) 0x00 516c rtc_tcr1 tamper control register 1 0x00 (1) 0x00 516d rtc_tcr2 tamper control register 2 0x00 (1) 0x00 516e to 0x00 518a reserved area 0x00 5190 csslse csslse_csr css on lse control and status register 0x00 (1) 0x00 519a to 0x00 51ff reserved area 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 interrupt control register 0x00 0x00 5203 spi1_sr spi1 st atus register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 37/55 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 i2c1_oarh i2c1 own address register for dual mode 0x00 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 0x00 521d i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register 0xxx 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 38/55 doc id 023133 rev 2 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 interrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 st atus register 1 0x00 0x00 5257 tim2_sr2 tim2 st atus register 2 0x00 0x00 5258 tim2_egr tim2 event generation register 0x00 0x00 5259 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl tim2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 auto-reload register high 0xff 0x00 5260 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 capture/ compare register 1 high 0x00 0x00 5262 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 capture/ compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 outpu t idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 39/55 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 interrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 st atus register 1 0x00 0x00 5287 tim3_sr2 tim3 st atus register 2 0x00 0x00 5288 tim3_egr tim3 event generation register 0x00 0x00 5289 tim3_ccmr1 tim3 captur e/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl tim3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 capture/ compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 captur e/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 capture/ compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 captur e/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 outpu t idle state register 0x00 0x00 5297 to 0x00 52af reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 40/55 doc id 023133 rev 2 0x00 52b0 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 52b1 tim1_cr2 tim1 control register 2 0x00 0x00 52b2 tim1_smcr tim1 slave mode control register 0x00 0x00 52b3 tim1_etr tim1 external trigger register 0x00 0x00 52b4 tim1_der tim1 dma1 request enable register 0x00 0x00 52b5 tim1_ier tim1 interrupt enable register 0x00 0x00 52b6 tim1_sr1 tim1 status register 1 0x00 0x00 52b7 tim1_sr2 tim1 status register 2 0x00 0x00 52b8 tim1_egr tim1 event generation register 0x00 0x00 52b9 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 52ba tim1_ccmr2 tim1 captur e/compare mode register 2 0x00 0x00 52bb tim1_ccmr3 tim1 captur e/compare mode register 3 0x00 0x00 52bc tim1_ccmr4 tim1 captur e/compare mode register 4 0x00 0x00 52bd tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 52be tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 52bf tim1_cntrh tim1 counter high 0x00 0x00 52c0 tim1_cntrl tim1 counter low 0x00 0x00 52c1 tim1_pscrh tim1 prescaler register high 0x00 0x00 52c2 tim1_pscrl tim1 prescaler register low 0x00 0x00 52c3 tim1_arrh tim1 auto-reload register high 0xff 0x00 52c4 tim1_arrl tim1 auto-reload register low 0xff 0x00 52c5 tim1_rcr tim1 repetition counter register 0x00 0x00 52c6 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 52c7 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 52c8 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 52c9 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 52ca tim1_ccr3h tim1 captur e/compare register 3 high 0x00 0x00 52cb tim1_ccr3l tim1 captur e/compare register 3 low 0x00 0x00 52cc tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 52cd tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 52ce tim1_bkr tim1 break register 0x00 0x00 52cf tim1_dtr tim1 dead-time register 0x00 0x00 52d0 tim1_oisr tim1 outpu t idle state register 0x00 0x00 52d1 tim1_dcr1 dma1 control register 1 0x00 table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 41/55 0x00 52d2 tim1 tim1_dcr2 tim1 dma1 control register 2 0x00 0x00 52d3 tim1_dma1r tim1 dma1 address for burst mode 0x00 0x00 52d4 to 0x00 52df reserved area (12 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interrupt enable register 0x00 0x00 52e5 tim4_sr1 tim4 status register 1 0x00 0x00 52e6 tim4_egr tim4 event generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 auto-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 bytes) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5300 tim5 tim5_cr1 tim5 control register 1 0x00 0x00 5301 tim5_cr2 tim5 control register 2 0x00 0x00 5302 tim5_smcr tim5 slave mode control register 0x00 0x00 5303 tim5_etr tim5 external trigger register 0x00 0x00 5304 tim5_der tim5 dma1 request enable register 0x00 0x00 5305 tim5_ier tim5 interrupt enable register 0x00 0x00 5306 tim5_sr1 tim5 st atus register 1 0x00 0x00 5307 tim5_sr2 tim5 st atus register 2 0x00 0x00 5308 tim5_egr tim5 event generation register 0x00 0x00 5309 tim5_ccmr1 tim5 captur e/compare mode register 1 0x00 0x00 530a tim5_ccmr2 tim5 capture/compare mode register 2 0x00 0x00 530b tim5_ccer1 tim5 capture/compare enable register 1 0x00 0x00 530c tim5_cntrh tim5 counter high 0x00 0x00 530d tim5_cntrl tim5 counter low 0x00 0x00 530e tim5_pscr tim5 prescaler register 0x00 0x00 530f tim5_arrh tim5 auto-reload register high 0xff 0x00 5310 tim5_arrl tim5 auto-reload register low 0xff table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 42/55 doc id 023133 rev 2 0x00 5311 tim5 tim5_ccr1h tim5 capture/compare register 1 high 0x00 0x00 5312 tim5_ccr1l tim5 captur e/compare register 1 low 0x00 0x00 5313 tim5_ccr2h tim5 capture/ compare register 2 high 0x00 0x00 5314 tim5_ccr2l tim5 captur e/compare register 2 low 0x00 0x00 5315 tim5_bkr tim5 break register 0x00 0x00 5316 tim5_oisr tim5 outpu t idle state register 0x00 0x00 5317 to 0x00 533f reserved area 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 0x00 534e adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 0x00 5352 to 0x00 53bf reserved area (110 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 43/55 0x00 53c0 spi2 spi2_cr1 spi2 control register 1 0x00 0x00 53c1 spi2_cr2 spi2 control register 2 0x00 0x00 53c2 spi2_icr spi2 interrupt control register 0x00 0x00 53c3 spi2_sr spi2 status register 0x02 0x00 53c4 spi2_dr spi2 data register 0x00 0x00 53c5 spi2_crcpr spi2 crc polynomial register 0x07 0x00 53c6 spi2_rxcrcr spi2 rx crc register 0x00 0x00 53c7 spi2_txcrcr spi2 tx crc register 0x00 0x00 53c8 to 0x00 53df reserved area 0x00 53e0 usart2 usart2_sr usart2 status register 0xc0 0x00 53e1 usart2_dr usart2 data register 0xxx 0x00 53e2 usart2_brr1 usart2 baud rate register 1 0x00 0x00 53e3 usart2_brr2 usart2 baud rate register 2 0x00 0x00 53e4 usart2_cr1 usart2 control register 1 0x00 0x00 53e5 usart2_cr2 usart2 control register 2 0x00 0x00 53e6 usart2_cr3 usart2 control register 3 0x00 0x00 53e7 usart2_cr4 usart2 control register 4 0x00 0x00 53e8 usart2_cr5 usart2 control register 5 0x00 0x00 53e9 usart2_gtr usart2 guard time register 0x00 0x00 53ea usart2_pscr usart2 prescaler register 0x00 0x00 53eb to 0x00 53ef reserved area 0x00 53f0 usart3 usart3_sr usart3 status register 0xc0 0x00 53f1 usart3_dr usart3 data register 0xxx 0x00 53f2 usart3_brr1 usart3 baud rate register 1 0x00 0x00 53f3 usart3_brr2 usart3 baud rate register 2 0x00 0x00 53f4 usart3_cr1 usart3 control register 1 0x00 0x00 53f5 usart3_cr2 usart3 control register 2 0x00 0x00 53f6 usart3_cr3 usart3 control register 3 0x00 0x00 53f7 usart3_cr4 usart3 control register 4 0x00 0x00 53f8 usart3_cr5 usart3 control register 5 0x00 0x00 53f9 usart3_gtr usart3 g uard time register 0x00 0x00 53fa usart3_pscr usart3 prescaler register 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 44/55 doc id 023133 rev 2 0x00 53fb to 0x00 53ff reserved area 0x00 5400 lcd lcd_cr1 lcd control register 1 0x00 0x00 5401 lcd_cr2 lcd control register 2 0x00 0x00 5402 lcd_cr3 lcd control register 3 0x00 0x00 5403 lcd_frq lcd frequency selection register 0x00 0x00 5404 lcd_pm0 lcd port mask register 0 0x00 0x00 5405 lcd_pm1 lcd port mask register 1 0x00 0x00 5406 lcd_pm2 lcd port mask register 2 0x00 0x00 5407 reserved area 0x00 5408 lcd_pm4 lcd port mask register 4 0x00 0x00 5409 to 0x00 540b lcd reserved area (3 bytes) 0x00 540c lcd_ram0 lcd display memory 0 0x00 0x00 540d lcd_ram1 lcd display memory 1 0x00 0x00 540e lcd_ram2 lcd display memory 2 0x00 0x00 540f lcd_ram3 lcd display memory 3 0x00 0x00 5410 lcd_ram4 lcd display memory 4 0x00 0x00 5411 lcd_ram5 lcd display memory 5 0x00 0x00 5412 lcd_ram6 lcd display memory 6 0x00 0x00 5413 lcd_ram7 lcd display memory 7 0x00 0x00 5414 lcd_ram8 lcd display memory 8 0x00 0x00 5415 lcd_ram9 lcd display memory 9 0x00 0x00 5416 lcd_ram10 lcd display memory 10 0x00 0x00 5417 lcd_ram11 lcd display memory 11 0x00 0x00 5418 lcd_ram12 lcd display memory 12 0x00 0x00 5419 lcd_ram13 lcd display memory 13 0x00 0x00 541a reserved area 0x00 541b lcd_ram15 lcd display memory 15 0x00 0x00 541c reserved area 0x00 541d lcd_ram17 lcd display memory 17 0x00 0x00 541e reserved area 0x00 541f lcd_ram19 lcd display memory 19 0x00 0x00 5420 reserved area 0x00 5421 lcd_ram21 lcd display memory 21 0x00 table 7. general hardware register map (continued) address block register label register name reset status stm8l052r8 memory and register map doc id 023133 rev 2 45/55 0x00 5422 to 0x00 542e reserved area 0x00 542f lcd lcd_cr4 lcd control register 4 0x00 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 timer input capt ure routing register 1 0x00 0x00 5432 ri_icr2 timer input capt ure routing register 2 0x00 0x00 5433 ri_ioir1 i/o input register 1 0xxx 0x00 5434 ri_ioir2 i/o input register 2 0xxx 0x00 5435 ri_ioir3 i/o input register 3 0xxx 0x00 5436 ri_iocmr1 i/o control mode register 1 0x00 0x00 5437 ri_iocmr2 i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 i/o control mode register 3 0x00 0x00 5439 ri_iosr1 i/o switch register 1 0x00 0x00 543a ri_iosr2 i/o switch register 2 0x00 0x00 543b ri_iosr3 i/o switch register 3 0x00 0x00 543c ri_iogcr i/o group control register 0x3f 0x00 543d ri_ascr1 analog switch register 1 0x00 0x00 543e ri_ascr2 analog switch register 2 0x00 0x00 543f ri_rcr resistor co ntrol register 1 0x00 0x00 5440 to 0x00 5444 reserved area (5 bytes) 1. these registers are not impacted by a sy stem reset. they are reset at power-on. table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052r8 46/55 doc id 023133 rev 2 table 8. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f cpu reserved area (85 bytes) 0x00 7f60 cfg_gcr global configuration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) stm8l052r8 memory and register map doc id 023133 rev 2 47/55 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only table 8. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status interrupt vector mapping stm8l052r8 48/55 doc id 023133 rev 2 6 interrupt vector mapping table 9. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active- halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 0tli (2) external top level interrupt - - - - 0x00 8008 1 flash eop/wr_pg_dis - - yes yes (5) 0x00 800c 2 dma1 0/1 dma1 channels 0/1 - - yes yes (5) 0x00 8010 3 dma1 2/3 dma1 channels 2/3 - - yes yes (5) 0x00 8014 4 rtc/lse_ css rtc alarminterrupt/lse css interrupt yes yes yes yes 0x00 8018 5 exti e/f/ pvd (3) porte/f interrupt/pvd interrupt ye s ye s ye s ye s (5) 0x00 801c 6 extib/g external interrupt port b/g yes yes yes yes (5) 0x00 8020 7 extid/h external interrupt port d yes yes yes yes (5) 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes (5) 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes (5) 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes (5) 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes (5) 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes (5) 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes (5) 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes (5) 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes (5) 0x00 8044 16 lcd lcd interrupt - - yes yes 0x00 8048 17 clk/tim1 system clock switch/ css interrupt/ tim 1 break --yesyes (5) 0x00 804c 18 adc1 acd1 yes yes yes yes (5) 0x00 8050 19 tim2/usart2 tim2 update/overflow/ trigger/break usart2 transmission complete/transmit data register empty interrupt --yesyes (5) 0x00 8054 20 tim2/usart2 capture/ compare/usart2 interrupt --yesyes (5) 0x00 8058 stm8l052r8 interrupt vector mapping doc id 023133 rev 2 49/55 21 tim3/usart3 tim3 update/overflow/ trigger/break usart3 transmission complete/transmit data register empty interrupt --yesyes (5) 0x00 805c 22 tim3/usart3 tim3 capture/compareusart3 receive register data full/overrun/idle line detected/parity error/ interrupt --yesyes (5) 0x00 8060 23 tim1 update /overflow/trigger/ com ---yes (5) 0x00 8064 24 tim1 capture/compare - - - yes (5) 0x00 8068 25 tim4 tim4 update/overflow/ trigger --yesyes (5) 0x00 806c 26 spi1 end of transfer yes yes yes yes (5) 0x00 8070 27 usart1/tim5 usart1 transmission complete/transmit data register empty/ tim5 update/overflow/ trigger/break --yesyes (5) 0x00 8074 28 usart1/tim5 usart1 received data ready/overrun error/ idle line detected/parity error/tim5 capture/compare --yesyes (5) 0x00 8078 29 i 2 c1/spi2 i 2 c1 interrupt (4) / s p i 2 ye s ye s ye s ye s (5) 0x00 807c 1. the low power wait mode is entered when executing a wfe instruction in low power run mode. 2. the tli interrupt is the logic or between tim2 overflow interrupt, and tim4 overflow interrupts. 3. the interrupt from pvd is logically or- ed with port e and f interrupts. register exti_conf allows to select between port e and port f interrupt (see external interrupt port sele ct register (exti_conf) in the rm0031). 4. the device is woken up from halt or active-halt mode only when the address received matches the interface address. 5. in wfe mode, this interrupt is served if it has been previ ously enabled. after processing t he interrupt, the processor goes back to wfe mode. when this interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. table 9. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active- halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address package characteristics stm8l052r8 50/55 doc id 023133 rev 2 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. stm8l052r8 package characteristics doc id 023133 rev 2 51/55 figure 5. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline 1. drawing is not to scale. , ! , d " " c c c $ $ $ % % % b 0 i n - 3 6 $ table 10. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0. 0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n64 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm8l052r8 52/55 doc id 023133 rev 2 figure 6. recommended footprint 1. dimensions are in millimeters. 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 stm8l052r8 ordering information scheme doc id 023133 rev 2 53/55 8 ordering information scheme for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you . figure 7. ordering information scheme example: stm8 l 052 r 8 t 6 device family stm8 microcontroller product type l = low power device subfamily 052: devices with lcd pin count r = 64 pins program memory size 8 = 64 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c revision history stm8l052r8 54/55 doc id 023133 rev 2 9 revision history table 11. document revision history date revision changes 20-apr-2012 1 initial release. 05-jun-2012 2 modified lcd in features , section 3.6: lcd (liquid crystal display) , table 1: high density value line stm8l05xxx low power device features and peripheral counts , figure 1: high density value line stm8l05xxx de vice block diagram , table 4: high density value lin e stm8l05xxx pin description , figure 4: memory map , table 4: high density value lin e stm8l05xxx pin description , and table 7: general hardware register map modified section 2.2: ultra low power continuum ?compatibility with stm8l15x family? stm8l052r8 doc id 023133 rev 2 55/55 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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