S1C63004 cmos 4-bit single chip microcontroller z high performance 4-bit core cpu s1c63000 z segment lcd driver (max:36seg x 8com) z r/f converter to measure temperature and humidity z low current consumption z low voltage operation descriptions the S1C63004 is a microcontroller features low voltage operations and low current consum ption. it consists of a 4-bit core cpu s1c63000 as the core cpu, rom (4k words x 13 bits), ram (512 words x 4 bits), supply voltage detection (svd) circuit, serial interface, timers, and sound generator. it also incorporates a segment lcd controller/driver that can drive a maximum 36-segment x 8-common lcd panel , and an r/f converter that can meas ure temperature and humidity using sensors such as a thermistor. the S1C63004 is suitable for battery driven clocks and watches with temperature and humid ity measurement functions. ? features z cpu 4-bit cmos core cpu s1c63000 z osc1 oscillation circuit 32.768khz (typ.) crystal oscillation circuit z osc3 oscillation circuit 4.0mhz (typ., 3v model) / 1.0mhz (typ., 1.5v model) ceramic oscillation circuit 1.8mhz (typ., 3v model) / 500khz (typ., 1.5v model) cr oscillation circuit (extenal r), or 500khz (typ., 3v model / 1.5v model) cr oscillation circuit (built-in r) (*1) z instruction set 47 types of basic inst ructions (411 instructions with all), 8 types of addressing modes z instruction execution time during operation at 32.768khz: 61sec 122sec 183sec during operation at 4mhz: 0. 5sec 1sec 1.3sec z rom capacity code rom: 4,096 words x 13 bits data rom: 1,024 words x 4 bits z ram capacity data memory: 512 words x 4 bits display memory: 288 bits z lcd driver 36 segments (max., *1) x 3 to 8 commons (*2) z i/o ports 20 bits z serial interface 1 port (8-bit clo ck synchronous system with spi supported) z time base counters clock timer 1/1000-second stopwatch timer with direct key input function z programmable timer 8-bit timer x 3 channels (can be used as 16-bit timer x 1 + 8-bit timer x 1) (*2) z watchdog timer built-in z sound generator with envel ope and 1-shot output functions z r/f converter 2 channels, cr oscillation type r/f converter with 20-bit counters, supports resistive humidity sensors z supply voltage detection (svd) circuit programmable 29 detection voltage levels (*2) z external interrupt key input 8 systems z internal interrupt watchdog timer (nmi) 1 systems clock timer 8 systems stopwatch timer 4 systems programmable timer 6 systems serial interface 1 systems r/f converter 3 systems z power supply voltage 1.8 to 5.5v (3v normal type) or 1.1 to 1.7v (1.5v low-voltage type) (*1) z operation temperat ure range -40 to 85c z current consumption (typ.) sleep (32k hz) 0.1a (3v model) / 0.1a (1.5v model) halt (32khz) 0.5a (3v model) / 0.5a (1.5v model) run (32khz) 2.3a (3v model) / 2.0a (1.5v model) run (4m/1mhz) 220a (4mhz, 3v model) / 60a (1mhz, 1.5v model) z shipment form qfp14-80pin, tqfp14-100pin, or die form *1: can be selected with mask option. *2: can be selected with software.
S1C63004 2 ? block diagram semiconductor operations division ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 http://www.epson.jp/device/semicon_e/ epson semiconductor website document code: 411895500 first issue feb, 2010 in j apan notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ? seiko epson corporation 2010, all rights reserved code rom 4,096 words x 13bits reset system reset control data rom 1,024 words x 4bits ram 512 words x 4bits core cpu s1c63000 osc watchdog timer clock timer power controller svd test interrupt controller clock management unit stopwatch timer programmable timer serial interface sound generator r/f converter lcd controller & driver i/o controller & driver p00 / key00 / run_stp / krst00 p01 / key01 / lap / krst01 p02 / key02 / krst02 p03 / key03 / krst03 p10 / key10 / evin_a p11 / key11 / tout_a p13 / key13 / fout p12 / key12 / bz p20 p21 p22 / evin_b p23 / tout_b p30 / sclk p31 / sout p32 / sin p33 / srdy_ss p50 / rfout p51 / sen0 p52 / ref0 p53 / rfin0 hud sen1 ref1 rfin1 seg0-19 com0-7 krst00-03 key00-03 key10-13 fout run_stp lap evin_a,b tout_a,b sclk sout sin srdy_ss bz rfout rfin0 sen0,ref0 rfin1 sen1,ref1 hud seg40-55 seg44 seg45 seg46 seg47 seg40 seg41 seg42 seg43 seg48 seg49 seg50 seg51 seg55 seg54 seg53 seg52 mask option osc1 osc2 osc3 osc4 vdd vd1 vosc vc1-3 ca, cb vss test code rom 4,096 words x 13bits reset system reset control data rom 1,024 words x 4bits data rom 1,024 words x 4bits ram 512 words x 4bits ram 512 words x 4bits core cpu s1c63000 osc watchdog timer clock timer power controller svd test interrupt controller clock management unit stopwatch timer programmable timer serial interface sound generator r/f converter lcd controller & driver i/o controller & driver p00 / key00 / run_stp / krst00 p01 / key01 / lap / krst01 p02 / key02 / krst02 p03 / key03 / krst03 p10 / key10 / evin_a p11 / key11 / tout_a p13 / key13 / fout p12 / key12 / bz p20 p21 p22 / evin_b p23 / tout_b p30 / sclk p31 / sout p32 / sin p33 / srdy_ss p50 / rfout p51 / sen0 p52 / ref0 p53 / rfin0 hud sen1 ref1 rfin1 seg0-19 com0-7 krst00-03 key00-03 key10-13 fout run_stp lap evin_a,b tout_a,b sclk sout sin srdy_ss bz rfout rfin0 sen0,ref0 rfin1 sen1,ref1 hud seg40-55 seg44 seg45 seg46 seg47 seg40 seg41 seg42 seg43 seg48 seg49 seg50 seg51 seg55 seg54 seg53 seg52 mask option osc1 osc2 osc3 osc4 vdd vd1 vosc vc1-3 ca, cb vss test
|
