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RT8082 ? ds8082-00 november 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications z lcd tv and monitor z notebook computers z distributed power systems z ip phones z digital cameras general description the RT8082 is a high efficiency synchronous, step-down dc/dc converter. its input voltage range is from 2.7v to 5.5v and provides an adjustable regulated output voltage from 1v to 5v while delivering up to 3a of output current. the internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external schottky diode. the switching ripple voltage is easily smoothed-out by small package filtering elements due to a fixed operating frequency of 2mhz. the 100% duty cycle provides low dropout operation extending battery input range in portable systems. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8082 operates in forced continuous pwm mode, which minimizes ripple voltage and reduces the noise and rf interference. 3a, 2mhz, synchronous step-down converter features z z z z z high efficiency : up to 95% z 2mhz fixed frequency pwm operation z z z z z no schottky diode required z z z z z 1v reference allows low output voltage z z z z z output current up to 3a z z z z z forced continuous mode operation z z z z z low dropout operation : 100% duty cycle z z z z z enable function z z z z z power good function z z z z z internal soft-start z z z z z rohs compliant and halogen free simplified application circuit ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. package type qw : wdfn-12e 3x3 (w-type) RT8082 lead plating system g : green (halogen free and pb free) marking information 0e=ym dnn 0e= : product code ymdnn : date code en vin RT8082 v in bias lx fb r bias l c out v out c in c ff r1 r2 c bias pgood r pgood pgnd agnd pgood enable
RT8082 2 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1, 12 lx internal power mosfet switches output. connect these pins to the inductor together. 2, 11 vin power input. decouple this pin to gnd with two 10 f capacitors. 3, 10, 13 (exposed pad) pgnd power ground. the exposed pad must be soldered to a large pcb and connected to ground for maximum power dissipation. 4 agnd analog ground. provides the return path for control circuit and internal reference. 5 bias analog power input. decouple this pin to agnd with a minimum 0.1 f ceramic capacitor. 6 fb feedback input. this pin is used to set the desired output voltage via an external resistive divider. the feedback reference voltage is 1v typically. 7 nc no internal connection. 8 en enable control input. floating this pin or connecting this pin to logic high will enable the device and pulling this pin to logic low will disable the device. 9 pgood power good indicator. this pin is an open drain logic output that is pulled to ground when the output voltage is within 7% of regulation point. pin configurations (top view) wdfn-12e 3x3 lx vin bias agnd lx vin pgnd en pgood pgnd fb nc 11 10 9 1 2 3 4 5 12 67 8 pgnd 13
RT8082 3 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram operation during normal operation, the internal high side power switch (p-mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the peak inductor current reaches the value defined by the output voltage (v comp ) of the error amplifier. the error amplifier adjusts its output voltage by comparing the feedback signal from a resistive voltage divider on the fb pin with an internal 1v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier increases its output voltage to allow the average inductor current traces the new load current. when the high side power mosfet turns off, the low side power switch (n-mosfet) turns on until the beginning of the next clock cycle. driver control logic en threshold current sense & over current protection oscillator slope compensation over temperature protection vin pgnd lx pgood shutdown control under voltage lock out en pwm comparator error amplifier soft-start voltage reference fb bias agnd
RT8082 4 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply input voltage, vin, bias ------------------------------------------------------------------------------- ? 0.3v to 6v z lx pin switch voltage --------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z other pins ------------------------------------------------------------------------------------------------------------ ? 0.3v to (v in + 0.3v) z lx pin switch current --------------------------------------------------------------------------------------------- 5a z power dissipation, p d @ t a = 25 c wd fn-12e 3x3 ----------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wdfn-12e 3x3, ja ------------------------------------------------------------------------------------------------ 60 c/w wdfn-12e 3x3, jc ----------------------------------------------------------------------------------------------- 7 c/w z junction temperature ---------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ----------------------------- ------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------------- 2kv electrical characteristics (v in = v en = 3.6v, t a = ? 40 c to 85 c, unless otherwise specified) recommended operating conditions (note 4) z supply input voltage ----------------------------------------------------------------------------------------------- 2.7v to 5.5v z junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit quiescent current i q v fb = 0.9v, not switching -- 570 900 a shutdown current i shdn v en = 0v -- 1 2 a i load = 100ma 0.98 1 1.02 feedback voltage v fb i load = 100ma, t a = 25 c 0.99 1 1.01 v feedback leakage current i fb -- 1 -- na line regulation i load = 100ma -- 0.07 -- %/v load regulation 20ma < i load < 3a -- 0.2 0.5 % switching frequency f osc 1.7 2 2.3 mhz high side switch on-resistance r ds(on)_p -- 75 150 low side switch on-resistance r ds(on)_n i lx = 0.5a -- 55 80 m peak current limit i lim 3.5 5 -- a under voltage lockout threshold v uvlo v in rising 2.35 2.45 2.6 v under voltage lockout hysteresis v uvlo -- 0.2 -- v v fb rising (good), t a = 25 c -- 93 90 power good rising threshold v fb rising (fault), t a = 25 c -- 107 110 %
RT8082 5 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit v fb falling (fault), t a = 25 c -- 93 90 power good falling threshold v fb falling (g ood), t a = 25 c -- 107 110 % power good resistance i pgood = 500 a -- 145 250 enable threshold voltage en rising 0.5 0.85 1.3 v enable voltage hysteresis -- 50 -- mv enable input current -- 0.1 2 a over temperature protection -- 160 -- c over temperature protection hysteresis -- 20 -- c
RT8082 6 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit note : using all ceramic capacitors 8 en vin 2, 11 RT8082 v in 2.7v to 5.5v bias 5 lx 1, 12 fb 6 r bias 1h c out v out c in 10f x 2 c ff r1 r2 c bias 0.1f pgood 9 r pgood 4 3, 10, 13 (exposed pad) pgood 10k 10k pgnd agnd l enable 10f x 2 v out (v) r1 (k ) r2 (k ) c ff (pf) l ( h) c out ( f) 3.3 27.6 12 82 2 10 x 2 2.5 18 12 330 1.5 10 x 2 1.8 9.6 12 150 1 10 x 2 1.5 6 12 open 1 10 x 2 1.2 6 30 open 1 10 x 2 1.0 0 open open 1 10 x 2 table 1. suggested components selection
RT8082 7 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics reference voltage vs. input voltage 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) reference voltage (v) efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current (a) efficiency (%) v out = 3.33v v out = 1.83v v in = 5v output voltage vs. output current 1.79 1.80 1.81 1.82 1.83 1.84 1.85 1.86 1.87 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) v in = 5v, v out = 1.83v output voltage vs. input voltage 1.79 1.80 1.81 1.82 1.83 1.84 1.85 1.86 1.87 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1.83v, i out = 0a output voltage vs. output current 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) v in = 5v, v out = 3.33v quiescent current vs . input voltage 300 350 400 450 500 550 600 650 700 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) quiescent current (a ) v fb = 0.9v
RT8082 8 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. reference voltage vs. temperature 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) switching frequency vs. temperature 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 -50-25 0 25 50 75100125 temperature (c) switching frequency (khz) 1 current limit vs. input voltage 1 2 3 4 5 6 7 8 9 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) current limit (a) v out = 1.83v current limit vs. temperature 1 2 3 4 5 6 7 8 9 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 5v, v out = 1.83v enable threshold vs. temperature 0.75 0.80 0.85 0.90 0.95 1.00 1.05 -50 -25 0 25 50 75 100 125 temperature ( c) enable threshold (v) 1 falling rising v in = 3.3v uvlo threshold vs. temperature 1.8 2.0 2.2 2.4 2.6 2.8 -50 -25 0 25 50 75 100 125 temperature (c) input voltage (v) v en = 3.3v falling rising
RT8082 9 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power off from vin time (10ms/div) i out (2a/div) v out (2v/div) v in (2v/div) v in = 3.3v, v out = 1.83v, i out = 3a power on from vin time (5ms/div) i out (2a/div) v out (2v/div) v in (2v/div) v in = 3.3v, v out = 1.83v, i out = 3a output voltage ripple time (250ns/div) i l (500ma/div) v out (50mv/div) v in = 3.3v, v out = 1.83v, i out = 0a v lx (2v/div) output voltage ripple time (250ns/div) i l (2a/div) v out (50mv/div) v lx (2v/div) v in = 3.3v, v out = 1.83v, i out = 3a load transient response i out (1a/div) v out (100mv/div) v in = 3.3v, v out = 1.83v, i out = 1a to 3a time (100 s/div) load transient response i out (1a/div) v out (200mv/div) v in = 3.3v, v out = 1.83v, i out = 0 to 3a time (100 s/div)
RT8082 10 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from en time (500 s/div) i out (5a/div) v out (2v/div) v en (5v/div) v in = 3.3v, v out = 1.83v, i out = 3a v pgood (5v/div) power off from en time (25 s/div) i out (5a/div) v out (2v/div) v en (5v/div) v in = 3.3v, v out = 1.83v, i out = 3a v pgood (5v/div)
RT8082 11 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information this ic is a single phase buck pwm converter. it provides single feedback loop, current mode control with fast transient response. an internal 1v reference allows the output voltage to be precisely regulated for low output voltage applications. a fixed switching frequency (2mhz) oscillator and internal compensation are integrated to minimize external component count. output voltage setting the resistive voltage divider allows the fb pin to sense the output voltage as shown in figure 1. where v ref is the feedback reference voltage (1v typ.). soft-start the ic contains an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter is turned on. soft-start automatically begins once the chip's enable control is pulled to high. during soft-start, the internal soft-start capacitor is charged and generates a linear ramping-up voltage across the capacitor. the v fb voltage tracks the internal ramping-up voltage which will induce the duty pulse width to increase slowly and in turn reduce the output surge current. finally, the internal 1v reference takes over the loop control once the internal ramping-up voltage becomes higher than 1v. the typical soft-start time is set at 1ms. power good output the power good output is an open-drain output and requires a pull up resistor. when the output voltage is 7% above or 7% below its set voltage, pgood will be pulled high. it is figure 1 . setting the output voltage out ref r1 v = v 1 + r2 ?? ?? ?? ??? ? ?? ?? ?? ??? ? out out l in vv i = 1 fl v having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high efficiency operation is achieved by reducing ripple current at low frequency, but it requires a large inductor to attain this goal. for the ripple current selection, the value of i l = 0.4(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ??? ? ? ?? ?? ??? ? out out l(max) in(max) vv l = 1 fi v in this ic, 1 h is recommended for initial design. the inductor's current rating (cause a 40 c temperature rising from 25 c ambient) must be greater than the maximum load current and ensure that the peak current will not saturate the inductor during short circuit condition. input and output capacitors selection higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step change at the output can induce ringing the output voltage is set by an external resistive voltage divider according to the following equation : held high until the output voltage returns within the allowed tolerances once more. during soft-start, pgood is actively held high and is only allowed to be low when soft-start period is over and the output voltage reaches 93% of its set voltage. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current, i l , increases with higher v in and decreases with higher inductance : RT8082 fb agnd v out r1 r2
RT8082 12 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. at the input, v in . this ringing can couple to the output and be mistaken. a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. two 10 f low esr ceramic capacitors are recommended for bypassing input and an additional 0.1 f is recommended close to the ic input side for high frequency filtering. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. for the RT8082, a separate inductor current signal is used to monitor over current condition, so this keeps the maximum output current relatively constant regardless of duty cycle. under output voltage protection (hiccup mode) a hiccup mode of under voltage protection (uvp) function is provided for the ic. when the fb voltage drops below half of the feedback reference voltage, v ref , and the peak inductor current reaches the ocp threshold. the uvp function will be triggered to auto soft-start the power stage continuously until this event is cleared. the hiccup mode uvp reduces input current in short-circuit conditions and it will not be triggered during soft-start process. under voltage lockout threshold the ic features input under voltage lockout protection (uvlo). if the input voltage exceeds the uvlo rising threshold voltage (2.45v typ.), the converter will reset and prepare the pwm for operation. if the input voltage falls below the uvlo falling threshold voltage (2.25v typ.) during normal operation, the device will stop switching. the uvlo rising and falling threshold voltage has a hysteresis (0.2v typ.) to prevent noise from causing reset. thermal shutdown the device implements an internal thermal shutdown function when the junction temperature exceeds 160 c. the thermal shutdown disables the device until the junction temperature drops below the hysteresis (20 c typ.). then, the device is re-enabled and automatically reinstates the power up sequence. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-12e 3x3, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-12e 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT8082 13 ds8082-00 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 2. derating curve of maximum power dissipation layout considerations follow the pcb layout guidelines for optimal performance of the ic. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to vin pin. ` lx node is with high frequency voltage swing and should be kept at small area. keep analog components away from the lx node to prevent stray capacitive noise pick- up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the ic. ` connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. figure 3. pcb layout guide lx should be connected to inductor by wide and short trace, and keep sensitive components away from this trace place the feedback resistors as close to the ic as possible place the input and output capacitors as close to the ic as possible lx agnd pgnd fb pgnd v out c in c in c out l r1 r2 vin bias lx vin en pgood pgnd nc 11 10 9 1 2 3 4 5 12 67 8 pgnd 13 v out 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8082 14 ds8082-00 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension w-type 12e dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options min. max. min. max. a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.280 0.007 0.011 d 2.900 3.100 0.114 0.122 d2 2.350 2.450 0.093 0.096 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e l 0.400 0.500 0.016 0.020 symbol dimensions in millimeters dimensions in inches 0.500 0.020

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