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this is information on a product in full production. february 2013 doc id 16938 rev 3 1/27 27 stmpe1600 16-bit port expander with ultra-low power consumption xpander logic? datasheet ? production data features 16 gpios which default to 16 inputs on power- up serial i 2 c interface (0 to 400 khz) to the host with noise filter operating voltage 1.65 v - 3.6 v i/o voltage 1.65 v - 3.6 v interrupt output pin internal power-on-reset wakeup feature on each i/o up to 8 devices sharing the same bus (3 address pins) 8 ma current drive/sink on each gpio at 3.3 v < 1a suspend current esd protection exceeds 2 kv hbm per jesd22-a114 latch-up testing exceeding 100 ma package: qfn24 (4 x 4 mm with 0.5 mm pitch) applications portable media players game consoles mobile phones smart phones description the stmpe1600 is a gpio (general purpose input/output) port expander able to interface a main digital asic via the two-line bidirectional bus (i2c). a separate gpio expander ic is often used in mobile multimedia platforms to solve the problems of the limited amount of gpios typically available on the digital engine. i/o expanders provide a simple solution when additional i/o are needed for several interface functions such as sensors, pushbuttons, leds, fans, etc. the stmpe1600 offers gr eat flexibility as each i/o can be configured as input or output. the device has been designed with very low quiescent current and includes a wakeup feature for each i/o, to optimize the power consumption of the device. qfn24 (4 x 4 mm) table 1. device summary order code package packing STMPE1600QTR qfn24 tape and reel www.st.com
contents stmpe1600 2/27 doc id 16938 rev 3 contents 1 stmpe1600 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin assignment (qfn24 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2i 2 c block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 i 2 c module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 i 2 c address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3i 2 c features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 turning i 2 c block off and on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 interrupt status gpio register (isgpior) . . . . . . . . . . . . . . . . . . . . . . . 16 8 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 polarity inversion regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.3 fail safe conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
stmpe1600 stmpe1600 functional overview doc id 16938 rev 3 3/27 1 stmpe1600 functional overview the stmpe1600 device consists of the following blocks: ? main fsm gpio controller ?i 2 c interface ?por ?gpios figure 1. block diagram !-6 -ain&3- '0)/ controller '0)/ '0)/ 0/2 ) # 6## '0)/ '0)/ '.$ ).4 3#,+ 3$!4 !$$2
stmpe1600 functional overview stmpe1600 4/27 doc id 16938 rev 3 1.1 pin assignment figure 2. qfn24 pin-mapping 1.2 pin assignment (qfn24 package) !-6 1&. xmm mmpitch mmmax thickness '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? '.$ '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? '0)/? ! 3#, 3$! 6## ).4 ! ! table 2. pin assignment pin number name type function 1 gpio_0 io gpio 0 2 gpio_1 io gpio 1 3 gpio_2 io gpio 2 4 gpio_3 io gpio 3 5 gpio_4 io gpio 4 6 gpio_5 io gpio 5 7 gpio_6 io gpio 6 8 gpio_7 io gpio 7 9 gnd - ground connection 10 gpio_8 io gpio 8 11 gpio_9 io gpio 9
stmpe1600 stmpe1600 functional overview doc id 16938 rev 3 5/27 12 gpio_10 io gpio 10 13 gpio_11 io gpio 11 14 gpio_12 io gpio 12 15 gpio_13 io gpio 13 16 gpio_14 io gpio 14 17 gpio_15 io gpio 15 18 a0 i i 2 c address 0. up to 8 such devices can be addressed. 19 scl i i 2 c clock. fail-safe 20 sda io i 2 c data. fail-safe 21 vcc - power supply for i 2 c and digital core and gpios 22 int o interrupt output pin. fail-safe 23 a1 i i 2 c address 1. up to 8 such devices can be addressed. 24 a2 i i 2 c address 2. up to 8 such devices can be addressed. table 2. pin assignment pin number name type function
i 2 c block stmpe1600 6/27 doc id 16938 rev 3 2 i 2 c block 2.1 i 2 c module the stmpe1600 is interfaced to the main processor using an i 2 c bus. 2.1.1 i 2 c address the addressing scheme of stmpe1600 is designed to allow up to 8 devices to be connected to the same i 2 c bus. the slave device address is a 7-bit or 10-bit address where they are 42h, 43h, 44h, 45h, 46h, 47h, 48h and 49h (equivalent values in 7-bit and 10-bit addressing). figure 3. addressing scheme !-6 $''5 6&/ 6'$ *1' 9&& 6&/ 6'$ 6703(
stmpe1600 i 2 c block doc id 16938 rev 3 7/27 for the bus master to communicate to the slave device, the bus master must initiate a start condition and followed by the slave device address. accompanying the slave device address, there is a read/write bit (r/w ). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledge on the sda during the 9th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction. figure 4. i 2 c timing table 3. eight programmable slave addresses a2 a1 a0 slave device address (7-bit or 10-bit addressing) 0 0 0 42h 0 0 1 43h 0 1 0 44h 0 1 1 45h 1 0 1 46h 1 0 1 47h 1 1 0 48h 1 1 1 49h $, 6'$ 3 w68672 w6867$ w+'67$ 65 6&/ w68'$7 w) w+''$7 w5 w+,*+ w/2: w+'67$ w%8) 6 3
i 2 c block stmpe1600 8/27 doc id 16938 rev 3 table 4. i 2 c bus timing symbol parameter min typ max uni f scl scl clock frequency 0 ? 400 khz t low clock low period 1.3 ? ? s t high clock high period 600 ? ? ns t f sda and scl fall time ? ? 300 ns t hd:sta start condition hold time (after this period the first clock is generated) 600 ? ? ns t su:sta start condition setup time (only relevant for a repeated start period) 600 ? ? ns t su:dat data setup time 100 ? ? ns t hd:dat data hold time 0 ? ? s t su:sto stop condition setup time 600 ? ? ns t buf time the bus must be free before a new transmission can start 1.3 ? ? s
stmpe1600 i2c features doc id 16938 rev 3 9/27 3 i 2 c features the features that are supported by the i 2 c interface are as below: ?i 2 c slave device ? operates from 1.65 v to 3.6 v ? compliant to philips i 2 c specification version 2.1 ? supports standard (up to 100kbps) and fast (up to 400kbps) modes ? 7-bit and 10-bit device addressing modes with up to 8 slave device addresses ? general call ? start/restart/stop ? address up to 8 stmpe1600 devices via i 2 c start condition a start condition is iden tified by a falling edge of sda while scl is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and will not respond to any transaction unless one is encountered. stop condition a stop condition is identified by a rising edge of sda while scl is stable at high state. a stop condition terminates communication between the slave device and bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is re ady to receive the next i2c transaction. a stop condition at the end of a write command stops the write operation to registers. acknowledge bit the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sda after sending eight bits of data . during the ninth bit, the receiver pulls the sda low to acknowledge the receipt of the eight bits of data. the receiver may leave the sda in high state if it would to not acknowledge the receipt of the data. data input the device samples the data input on sda on the rising edge of the scl. the sda signal must be stable during the rising edge of scl and the sda signal must change only when scl is driven low.
i2c features stmpe1600 10/27 doc id 16938 rev 3 figure 5. read and write modes (random and sequential) table 5. operating modes mode byte programming sequence read 1 start, device address, r/w = 0, register address to be read restart, device address, r/w = 1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within t he range that allows an address auto- increment, then the register addres s auto-increments internally after every byte of data being read. write 1 start, device address, r/w = 0, register address to be written, data write, stop if no stop is issued, the data writ e can be continuously performed. if the register address falls within the range that allows address auto- increment, then the register addres s auto-increments internally after every byte of data being written in. for those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write op eration. refer to the memory map table for the address ranges that are auto and non-increment. start r/w=0 ack device address reg address ack device address ack r/w=1 data read no ack stop one byte read start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read ack more than one byte read ack no ack stop data read + 1 data read + 2 start r/w=0 ack device address reg address ack data to be written ack stop one byte write more than one byte read start r/w=0 ack device address reg address ack data to write ack stop data to write + 2 ack ack data to write + 1 master slave am00775v1
stmpe1600 i2c features doc id 16938 rev 3 11/27 read operation a write is first performed to load the register address into the address counter but without sending a stop condition. then, the bus master sends a restart condition and repeats the device address with the r/w bit set to 1. the slave device acknowledges and outputs the content of the addressed byte. if no more data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a stop condition. if the bus master acknowledges the data byte, then it can continue to perform the data reading. to terminate the stream of data byte, the bus master must not acknowledge the last output byte and follow by a stop condition. if the address of the register written into the address counter falls within the range of addresses that has the auto-increment function, the data being read will be coming from cons ecutive addresses, with the inter nal address counter automatically increments after each byte output. after the last memory address, the address counter 'rolls-over' and the device continue to output data from the memory address of 0x00. similarly, for the address of register that falls within non-increment range of addresses, the output data byte comes from the same address (which is the address pointed by the address counter). acknowledgement in read operation for the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. if the bus master does not drive the sda to low state, then the slave device terminates and switches back to its idle mode, waiting for the next command. write operations a write is first performed to load the register address into the address counter without sending a stop condition. after the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (pointed by the address counter). the slave device again acknowledges and the bus master terminates the transfer with a stop condition. if the bus master would like to continue to write more data, it can just continue write operation without issuing the stop condition. whether the address counter auto increments or not after each data byte write, depends on the address of the register written into the address counter. after the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a stop condition. when the address counter reaches the last memory address, it 'rolls-over' on the next data byte write. general call a general call address is a transaction with the slave address of 0x00 and r/w = 0. when a general call address is made, the device responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. the meaning of a general call address is defined in the second byte sent by the master-transmitter.
i2c features stmpe1600 12/27 doc id 16938 rev 3 note: all other second byte values will be ignored. 3.1 turning i 2 c block off and on the stmpe1600 operates entirely on the i 2 c clock. when there is no activity on the i 2 c bus, current consumption of the device is extremely low. however, when there is activity on the i 2 c bus, current consumption increases, even if the i 2 c traffic is not directed to the assigned address. the host system may choose to shut-down the i 2 c block in the stmpe1600, if no access to the registers is required. this feature allows the current consumption to drop to the minimum. host system turns off the i 2 c block by writing '1' into the i2c_shdn bit. the i2c block will shut down on the next valid clock edge of the i 2 c clock signal. in this state, the device cannot be accessed by i 2 c, as the i 2 c has shut down completely. to turn on the i 2 c block, system host must reset the stmpe1600 in order to re-activate the i 2 c block either by removing v cc and bringing it back again. or by using gpio_0 for wake- up function. table 6. general call r/w second byte value definition 0 0x06 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 1-bit programmable part of the slave address. 0 0x04 2-byte transaction in which the second byte tells the slave device not to reset and write (or latch in) the 1-bit programmable part of the slave address. 0 0x00 not allowed as second byte.
stmpe1600 register map doc id 16938 rev 3 13/27 4 register map table 7. register map address register name size (bit) function 0x00 chip id lsb 8 0x00 0x01 chip id msb 8 0x16 0x02 version id 8 revision number (0x01) 0x03 systemcontrol 8 reset and interrupt control 0x04- 0x07 reserved reserved 0x08 iegpior 8 gpio interrupt enable register lsb 0x09 8 gpio interrupt enable register msb 0x0a isgpior 8 gpio interrupt status register lsb 0x0b 8 gpio interrupt status register msb 0x10 gpmr 8 gpio monitor pin state register lsb 0x11 8 gpio monitor pin state register msb 0x12 gpsr 8 gpio set pin state register lsb 0x13 8 gpio set pin state register msb 0x14 gpdr 8 gpio set pin direction register lsb 0x15 8 gpio set pin direction register msb 0x16 gppir 8 gpio polarity inversion register lsb 0x17 8 gpio polarity inversion register msb 0x18- 0xff reserved reserved
system control register stmpe1600 14/27 doc id 16938 rev 3 5 system control register sys_ctrl system control register address: 0x03 type: rw reset: 0x00 description: system control register. 76543 2 1 0 soft reset i2c_shdn wakeup_en reserved reserved int_enable reserved int_polarity rw rw rw ?? rw ? rw [7] soft reset: writing ?1? to this bit causes a soft reset cleared by hardware. [6] i2c_shdn: writing ?1? to this bit shuts down the i2c block on the next valid i2c clock. in shut-down mode, only 2 possible wa ys exist to re-activate the device: - remove and reconnect vcc - wake_up through the gpio_0 pin if programmed as a hot-key and if wakeup enable bit of this register is enabled all gpio states remain the same on entering shut-down mode. [5] wakeup_en: wakeup enable bit ?1? to enable gpio_0 as clock gating signal during shutdown ?0? to disable the above [4] reserved [3] reserved [2] int_enable: ?1? to enable interrupt output ?0? to disable interrupt output when the interrupt output is disabled, it is in floating condition but it does not consume current [1] reserved [0] int_polarity: interrupt polarity ?1? for active high ?0? for active low
stmpe1600 interrupt system doc id 16938 rev 3 15/27 6 interrupt system the stmpe1600 can be configured to generate an interrupt when there is a logic transition on any of the gpio configured as an input. iegpior interrupt enable gpio mask register address: 0x08, 0x09 type: rw reset: 0x00 description: interrupt enable gpio mask register (iegpior) the iegpior register is used to enable the interruption from a particular gpio interrupt source to the host. the ieg[15:0] bits are the interrupt enable mask bits corresponding to the gpio[15:0] pins. 1514131211109876543 2 1 0 ieg15 ieg14 ieg13 ieg12 ieg11 ieg10 ieg9 ieg8 ieg7 ieg6 ieg5 ieg4 ieg3 ieg2 ieg1 ieg0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [15:0] ieg[x]: interrupt enable gpio mask (where x = 15 to 0) writing a ?1? to the ie[x] bit will enable the interruption to the host.
interrupt status gpio register (isgpior) stmpe1600 16/27 doc id 16938 rev 3 7 interrupt status gpio register (isgpior) isgpior interrupt stat us gpio mask register address: 0x0a, 0x0b type: rw reset: 0 description: interrupt status gpio register (isgpior) the isgpior register monitors the status of the interruption from a particular gpio pin interrupt source to the host. regardless of the iegpior bits are enabled or not, the isgpior bits are still updated. the isg[ 15:0] bits are the interrupt status bits corresponding to the gpio[15:0] pins. 1514131211109876543 2 1 0 isg15 isg14 isg13 isg12 isg11 isg10 isg9 isg8 isg7 isg6 isg5 isg4 isg3 isg2 isg1 isg0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [15:0] isg[x]: interr upt status gpio (where x = 15 to 0) read: interrupt status of the gpio[x]. reading the regi ster will clear any bits that has been set to ?1? write: writing to this register has no effects
stmpe1600 gpio controller doc id 16938 rev 3 17/27 8 gpio controller a total of 16 gpios are available in the stmpe1600 port expander ic. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio (input or output), or into one of the alternate functions. unused gpios should be configured as outputs to minimize the power consumption. a group of registers are used to control the exact function of each of the 16 gpios. the registers and their respective address are listed in the following table. note: once the last register address 0x16-0x17 location is accessed, the locations of 0x18 to 0xff are reserved. after 0xff location, the pointer rolls over to the 0x00 register address location. all gpio registers are named as gpxx, where: xx represents the functional group. the function of each bit is shown in the following table: on power-up reset, all gpios are set as input. table 8. gpio controller registers address register name description auto-increment (during sequential r/w) 0x10 gpmr gpio monitor pin state register ye s 0x12 gpsr gpio set pin state register ye s 0x14 gpdr gpio set pin direction register ye s 0x16 gppir gpio polarity inversion register ye s 1514131211109876543 2 1 0 io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 table 9. gpio bit function register name function gpio monitor pin state reading this bit yields the current state of the bit. writing has no effect. gpio set pin state writing ?1? to this bit causes the corresponding gpio to go to ?1? state. writing ?0? to this bit causes the corresponding gpio to go to ?0? state. gpio set pin direction ?0? sets the corresponding gpio to input state, and ?1? sets it to output state. all bits are ?0? on reset. gpio polarity inversion writing a ?1? enables polarity inversion on the input port. writing a ?0?, the input port polarity is retained. the reset value is 0.
polarity inversion register stmpe1600 18/27 doc id 16938 rev 3 9 polarity inversion register pinv polarity inversion register address: 0x16, 0x17 type: rw reset: 0 description: polarity inversion register. this register allows the user to invert the polarity of the input port register data. if a bit in this register is set (written with ?1?), the inpu t port data polarity is inverted. if a bit in this register is cleared (written with a ?0?), the input port data polarity is retained. this is for active high or active low operation register. the polarity of the read register can be inverted with this register. 9.1 power supply the stmpe1600 operates with a single power supply vcc that ranges from 1.65v to 3.6v. the gpio remains valid until the v cc is removed. when the v cc is removed, the gpio is reset. 9.2 reset the stmpe1600 is equipped with an internal por circuit that holds the device in reset state, until the v cc supply input is valid. the internal por is tied to the v cc supply pin. in the duration when reset pin is asserted, all gpio are reset and default to input states. 1514131211109876543 2 1 0 pinv 15 pinv 14 pinv 13 pinv 12 pinv 11 pinv 10 pinv9 pinv8 pinv7 pinv6 pinv5 pinv4 pinv3 pinv2 pinv1 pinv0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [15:0] pinv[x]: polarity inversion register (where x = 15 to 0) writing a ?1? to the pinv[x] bit will enable polarity inversion on the input port. writing a ?0?, the input port polarity is retained. the reset value is 0.
stmpe1600 polarity inversion register doc id 16938 rev 3 19/27 9.3 fail safe conditions the stmpe1600 ios (sda, scl, int, a2, a1, a0) are fail-safe ios that support 4 ma current drive. note that ?present? state implies that the supply is present. the ?absent? state implies that the power is lost (grounded) condition. in the fail-safe condition, the leakage current flowing into the stmpe1600 device is prevented. fail safe condition when chip supply is 0 v and when v io (sda, scl, int, a2, a1, a0) is 3.6 v, this is classified as a fail-safe condition. in this case, the chip is protected and the current per i/o is limited to a very small value. overvoltage condition the second condition is the overvoltage condition which occurs when v cc = 1.65 v and v io = 3.6 v. in this condition, the current drawn by the device per io can be 10 a (typical) and 25 a (worst case). this device should not be operated under this condition. so it is recommended to operate the io at the same voltage as the supply voltage (either 1.8 v or 3.3 v). also the fail safe ios are special ios which can have a voltage present while the supply voltage v cc is 0 v. current will be limited from the fail safe ios when supply voltage v cc is 0 v. table 10. fail safe conditions v cc (core and io supply) condition present normal operating condition absent complete power-down condition
maximum rating stmpe1600 20/27 doc id 16938 rev 3 10 maximum rating stressing the device above the ratings listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect the device?s reliability. 10.1 dc electrical characteristics table 11. absolute maximum ratings symbol parameter value unit v cc supply voltage 4.5 v v io gpio supply voltage 4.5 v v esd esd protection on each gpio pin (hbm) 2 kv table 12. thermal data symbol parameter value unit ? ja thermal resistance j unction-ambient tbd c/w t opr operating temperatire -40 to 85 c t j storage temperature -65 to 155 c table 13. supplies symbol parameter test conditions value unit min typ max v cc core supply voltage 1.65 ? 3.6 v icc 400khz operating current with i 2 c clk = 400 khz with full traffic density scl running at 400 khz v cc =1.8-3.3v 100% traffic density i/o = inputs no peripheral activity or no load ? 200 500 a icc 100khz operating current with i 2 c clk = 100 khz with full traffic density scl running at 100 khz v cc =1.8-3.3v 100% traffic density i/o=inputs no peripheral activity or no load ? 135 200 a
stmpe1600 maximum rating doc id 16938 rev 3 21/27 table 14. input/outputs icc (normal) normal mode operating current scl running at 400khz vcc=1.8-3.3v 1% traffic density no peripheral activity or no load ?1015a icc (suspend) standby operating current no i 2 c activity (scl=0khz) v cc =1.8-3.3v v inputs =gnd or v cc no peripheral activity or no load i/o=inputs ?0.251 a i cc (powerdown) power down current i 2 c block off v cc =1.8 - 3.3 v ?0.251 a i io(fail safe) fail-safe io current v cc =0 v vio (fail safe)= 3.6 v ? 0.25 1 a sym bol parameter test conditions value unit min typ max v il input voltage low state v cc = 1.65 - 3.6 v ? ? 0.2vcc v v ih input voltage high state v cc =1.65-3.6v 0.8vcc ? ? v v hyst schmitt trigger hysteresis 0.2 ? v i il input low leakage current v i =gnd ? ? 1 a i ih input high leakage current v i =v cc ??-1a v ol output voltage low state v cc =1.65-3.6v, i ol =8ma ? ? 0.15vcc v v oh output voltage high state v cc =1.65-3.6v, i ol =8ma 0.85vcc ? ? v table 13. supplies (continued) symbol parameter test conditions value unit min typ max
maximum rating stmpe1600 22/27 doc id 16938 rev 3 table 15. digital inputs (a2, a1, a0 pins) table 16. interrupt (int pin) table 17. input (scl), input/output (sda) symbol parameter test conditions value unit min typ max v il low-level input voltage ? ? 0.2vcc v v ih high-level input voltage 0.8vcc ? ? v i l leakage current v i =v cc or gnd -1 ? 1 a symbol parameter test conditions value unit min typ max i ol open-drain low-level output current v ol =0.4v ? 4 ? ma v ol output voltage low state v cc = 1.8 - 3.3 v, i ol =4ma ??0.15vccv v oh output voltage high state v cc =1.8-3.3v, i ol =4ma 0.85vcc ? ? v symbol parameter test conditions value unit min typ max v il low-level input voltage ? ? 0.2vcc v v ih high-level input voltage 0.8vcc ? ? v i l leakage current v i =v cc or gnd -1 ? 1 a v ol (i 2 c) output voltage low state v cc = 1.8 - 3.3 v, i ol =4ma ??0.15vccv v oh (i 2 c) output voltage high state v cc = 1.8 - 3.3 v, i ol =4 ma 0.85vcc ? ? v
stmpe1600 package mechanical data doc id 16938 rev 3 23/27 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 6. package outline for qfn24 (4 x 4 x 1 mm) - 0.5 mm pitch 1&.?
package mechanical data stmpe1600 24/27 doc id 16938 rev 3 table 18. package mechanical data for qfn24 (4 x 4 x 1 mm) - 0.5 mm pitch figure 7. stmpe1600 top side marking information symbol millimeters min typ max a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 ? 0.20 ? b 0.18 0.25 0.30 d 3.85 4.00 4.15 d2 2.40 2.50 2.60 e 3.85 4.00 4.15 e2 2.40 2.50 2.60 e?0.50? l 0.30 0.40 0.50 ddd ? ? 0.08
stmpe1600 package mechanical data doc id 16938 rev 3 25/27 figure 8. carrier tape and reel info figure 9. pcb land pattern reel size is 13-inch with 4000 units per reel.
revision history stmpe1600 26/27 doc id 16938 rev 3 12 revision history table 19. document revision history date revision changes 26-mar-2010 1 initial release. 08-jan-2013 2 document status has been promoted from ?preliminary data? to ?datasheet?. 05-feb-2013 3 updated figure 7 .
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