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| toshiba america electronic components, inc. toshiba 1999 TC35815CF flow control 10/100mbps ethernet controller data sheet preliminary
? 1999 toshiba america electronic components, inc. published in april, 1999 toshiba products described in this document are not authorized for use as critical components in life support systems without t he written consent of the appropriate officer of toshiba america, inc. life support systems are either systems intended for surgical implant in the body or systems which sustain life. a critical component is any component of a life support system whose failure to perform may cause a malfunction or failure of the life support system, or may affect its safety or effectivene ss. the information in this document has been carefully checked and is believed to be reliable. however, no responsibility can be a ssumed for inaccuracies that may not have been caught. all information in this document is subject to change without prior notice. furthermore, toshiba cannot assume responsibility fo r the use of any license under the patent rights of toshiba or any third parties. this technical data may be controlled under u.s. export administration regulations and may be subject to the approval of the u. s. department of commerce prior to export. any export or re-export, directly or indirectly, in contravention of the u.s. export administration regulations is strictly prohibited. brand names and product names mentioned herein may be trademarks or registered trademarks of their respective companies. toshiba toshiba corporation i TC35815CF flow control 10/100mbps ethernet controller contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 document definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features and benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pci system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 controller application configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 system control models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 power management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal and power supply information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 peripheral component interconnect (pci) signals . . . . . . . . . . . . . . . . . . . . . . . . 10 pci address and data signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pci control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pci bus arbitration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pci error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pci interrupt signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pci system signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 media independent interface (mii) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 transmit mii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 receive mii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mii station management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 external 10mbps endec signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 transmit 10mbps signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 receive 10mbps signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10mbps control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 external eeprom or rom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 external cam interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 internal scan interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 chapter 3 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 overview of functional blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pci and dma overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 mac overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 media independent interface (mii). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 peripheral component interconnect (pci) bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dma functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dma transmit controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dma receive controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mac functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mac transmit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mac receive block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ii toshiba corporation contents flow control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mac control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mii station manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 prom controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 chapter 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 register address summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 vendor id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 device id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 pci command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 class code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pci control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 i/o and memory base address registers . . . . . . . . . . . . . . . . . . . . . . . . . 40 subsystem vendor id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 subsystem id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 pci interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 transmit frame pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 transmit threshold control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 transmit polling control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 buffer list frame pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 receive fragment size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 descriptor area registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupt source register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 flow control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mac layer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 mac control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 cam control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 transmit control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 receive control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 station management data access registers . . . . . . . . . . . . . . . . . . . . . . . 58 cam access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 prom control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 system error count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 frame descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 next frame descriptor field (fdnext). . . . . . . . . . . . . . . . . . . . . . . . . . . 64 frame descriptor system field (fdsystem). . . . . . . . . . . . . . . . . . . . . . . 65 frame descriptor status field (fdstat) . . . . . . . . . . . . . . . . . . . . . . . . . . 65 frame descriptor length field (fdlength) . . . . . . . . . . . . . . . . . . . . . . . 65 toshiba corporation iii contents frame descriptor control field (fdctl) . . . . . . . . . . . . . . . . . . . . . . . . . .65 buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 buffer descriptor control (bdctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 buffer descriptor status field (bdstat) . . . . . . . . . . . . . . . . . . . . . . . . . .68 chapter 6 mac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 mac frame and packet formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 destination address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 special flow control destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 mac register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 special register clear operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 transmitting a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 the ieee 802.3 csma/cd mac-layer protocols . . . . . . . . . . . . . . . . . . . . . 73 the mii transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 receiving a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 cam operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 full duplex pause operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 transmit pause operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 remote pause operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 error signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 reporting of errors in transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 reporting of errors in receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 accessing station management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 accessing an eeprom or rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 chapter 7 dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 pci initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 dma and mac initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 queue initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 transmit queue initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 buffer list initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 receive descriptor area initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 transmitting a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 transmit complete notification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 receiving a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 processing received frame descriptors . . . . . . . . . . . . . . . . . . . . . . . . . .86 freeing buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 processing interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 chapter 8 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 pci clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 detailed timing parameters for each pci operation/transaction. . . . . . .90 pci measurement and test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 detailed timing parameters for each mii operation/transaction. . . . . . . . . . . . .92 iv toshiba corporation contents chapter 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 chapter 10 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 95 appendix a implementation limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 buffer sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 appendix b glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 ethernet and networking acronyms and terms . . . . . . . . . . . . . . . . . . . . . . . . . b-1 appendix c unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 peripheral component interconnect (pci) functions . . . . . . . . . . . . . . . . . . . . . c-1 ieee 802.3 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 toshiba toshiba corporation v flow control 100/10 mbps ethernet controller figures figure 1-1 ethernet system overview ................................................................ 2 figure 1-1 pci system block diagram ............................................................... 4 figure 1-1 configuration for 100base-t showing option ............................... 5 figure 1-1 data structure overview.................................................................... 6 figure 2-1 external signals ................................................................................. 9 figure 3-1 dma functional blocks .................................................................. 23 figure 3-2 mac functional blocks .................................................................. 25 figure 4-1 address map of pci configuration registers ................................. 34 figure 4-1 address map of dma control registers ........................................ 34 figure 4-3 address map of flow control registers ......................................... 35 figure 4-4 address map of mac control and status registers ....................... 35 figure 6-1 transmission without collision ...................................................... 74 figure 6-2 transmission with collision in preamble ....................................... 75 figure 6-3 cam memory map ......................................................................... 76 figure 8-1 pci clock waveforms ..................................................................... 89 figure 8-2 output timing measurement conditions ........................................ 90 figure 8-3 input timing measurement conditions ........................................... 90 figure 8-4 transmit signal timing relationships at the mii............................... 92 figure 8-5 receive signal timing relationships at the mii ................................ 92 figure 8-6 mdio sourced by phy ................................................................... 92 figure 8-7 mdio sourced by sta .................................................................... 92 figure 10-1 lqfp144-p-2020-0.50a [144-pin lqfp (thin quad flat package C 1.4mm)] .......................................................................... 95 vi toshiba corporation figures this page left blank intentionally toshiba toshiba corporation vii flow control 100/10 mbps ethernet controller tables t able 1-1 features and benefit s ......................................................................... . 3 t able 2-1 power supply informatio n ................................................................. . 9 t able 2-2 peripheral component interconnect (pci) signal s .......................... . 10 t able 2-3 corresponding between c_be#[3:0] and ad[31:0 ] ....................... . 11 t able 2-4 big endian byte orde r .................................................................... . 11 t able 2-5 transmit mii signal s ....................................................................... . 11 t able 2-6 receive mii signal s ........................................................................ . 15 t able 2-7 mii station management signal s .................................................... . 16 t able 2-8 transmit 10mbps signal s ................................................................ . 17 t able 2-9 receive 10mbps endec interfac e .................................................... . 18 t able 2-10 10mbps control signal s .................................................................. . 18 t able 2-11 external eeprom od rom interfac e ............................................ . 19 t able 2-12 external cam interface signal s ...................................................... . 20 t able 2-13 internal scan interface signal s ........................................................ . 2 0 t able 4-1 pci configuration register s ............................................................ . 31 t able 4-2 dma control register s ................................................................... . 32 t able 4-3 flow control register s .................................................................... . 32 t able 4-4 mac control and status register s .................................................. . 33 t able 5-1 frame descriptors forma t ............................................................... . 64 t able 5-2 buffer descriptors forma t ............................................................... . 67 t able 6-1 fields of an ieee 802.2/ethernet packet (frame ) ............................ . 69 t able 8-1 5v and 3.3v timing parameter s ..................................................... . 91 t able 8-2 measurement and test condition parameter s ................................. . 91 t able 9-1 absolute maximum rating s ............................................................ . 93 t able 9-2 dc characteristics (pci pins ) ......................................................... . 93 t able 9-3 dc characteristics (other pci pins ) ............................................... . 93 t able 10-1 ethernet controller pin assignment s .............................................. . 96 t abl e a-1 cam siz e ...................................................................................... . a-1 t abl e a-2 bus latency and buffer size s ........................................................ . a-1 viii toshiba corporation tables this page left blank intentionally toshiba toshiba corporation 1 flow control 100/10mbps ethernet controller chapter 1 - introduction this speci?cation describes a ?ow control capable ethernet controller which operates at either 10-mbit/s or 100-mbit/s. in half duplex mode, the controller implements the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol. in full duplex mode, the controller implements ieee 802.3x mac control layer and the pause operation for ?ow control. the controller also supports ?ow control in half duplex mode, and includes programmable support for additional mac control functions. the controller supports direct connection to the 32-bit peripheral components interconnect (pci) local bus, and uses bus master burst transfer mode to ef?ciently move data to and from system memory. the controller has on-chip mem- ory for buffering, so there is no need for external local buffer memory. the new 100mbps implementations of ethernet increase the capacity of a net- work ten times, while using existing twisted-pair wiring. by keeping the media access control (mac) layer and the csma/cd protocol unchanged, network administrators can quickly adapt newer and faster implementations. this approach also lowers cost of deployment since it allows re-use of existing applications soft- ware. by supporting both 10- and 100mbps speeds, new products may be deployed into markets which are in transition. one recent advance in ethernet is the use of full duplex links and switching hubs to greatly increase the capacity of a local area network. these hubs are more expensive than the traditional shared media and simple repeating hubs. but the increase in throughput is signi?cant for a number of applications. products which support full duplex are well established in the market place, and the demand for such products is expected to grow. as part of the evolving support for the full duplex mode of operation, the ieee 802.3x standards group has approved a new standard for ?ow control. this standard establishes an optional "mac control" sublayer and de?nes the pause operation, which is supported by this mac control sublayer. the pause opera- tion provides an industry method of supporting ?ow control in full duplex ether- net networks. toshiba has designed its TC35815CF flow control 10/100mbps ethernet controller for use in highly integrated and cost-effective ethernet solutions. by supporting direct connection to a pci bus, the chip can be used with a media driver chip to provide a minimum-parts solution. the TC35815CF flow control 10/100mbps ethernet controller is register compatible with previous toshiba designs, insuring that investments in system and software development can be leveraged in full duplex systems with ?ow con- trol. the controller supports an optional 10mbps interface. the "7-wire interface" supports mother board applications, where systems developers wish to support older 10 mb/s phys to ensure interoperability on installed 10 mb/s networks. 2 toshiba corporation introduction document de?nition a complete ethernet circuit is divided into three sections, as shown in figure 1-1: 1. the system bus interface and direct memory access (dma) engine. 2. the media access control (mac) layer. 3. the physical or medium dependent interface (mdi) layer. the pci bus interface section contains separate ?rst-in, ?rst-out (fifo) buffers for transmit and receive, a dma controller, and a register access module. the mac layer consists of transmit and receive blocks, the ?ow control block, a content addressable memory (cam) for recognizing addresses, and a number of con- trol, status, and error counter registers. the dma-independent interface (dii) is the interface between the mac and the dma section. the TC35815CF flow control 10/100mbps ethernet controller supports the media independent interface (mii). the mii is a standard for a media-independent layer which separates physical-layer issues from the mac layer. the mii is part of the iso approved ieee 802.3 100base-t standard for 100mbps ethernet. this document speci?es a single chip which implements a pci bus interface, the dma engine, and the mac layer. it is intended as an interface speci?cation and an architectural overview of the device and its operation. figure 1-1 ethernet system overview p c i dma engine media dependent interface m i i command & status registers d i i pci bus interface & dma physical layer mac layer receive block mac rx fifo address cam transmit block mac tx fifo toshiba corporation 3 introduction features and bene?ts table 1-1 summarizes the features and bene?ts of the TC35815CF flow control 10/ 100mbps ethernet controller. table 1-1 features and bene?ts features bene?ts pci bus interface. direct connection, with no glue logic. dma engine using burst mode. ef?cient data transfers. large dma fifo buffers. no external buffer memory required. 16-byte receive fifo buffer allow dma latency during pci bursts. 80-byte transmit fifo buffer dma latency; retransmit after collision without dma action. data alignment logic. full data alignment freedom; high bus utilization. endian translation. operates with either big-endian or little-endian processors. support for old and new media. compatible with existing 10mbps networks. 100/10mbps operation. range of price/performance points. phased conversion. full ieee 802.3 compatibility. compatible with existing applications software. mii compliant interface. can be used with many 100base-t physical layers. station management signaling external physical layer con?guration and link negotiation. on-chip cam address recognition for network traf?c ?ltering. optional external cam support hub and bridge applications with many addresses. optional rom or eeprom network address and con?guration information. optional 7-wire interface allow use of old 10mps physical layer for compatibility full duplex mode doubles bandwidth. pause operation h/w support for full duplex ?ow control. flexible mac control support software can support future mac control operations. long packet mode specialized environments. short packet mode specialized environments. fast testing. pad generation ease of processing, reduced processing time. transmit polling mode minimize system overhead to initiate transmission. transmit wake-up control minimize system latency to transmission initiation. receive early-notify control minimize system latency to processing received packet. power management minimize power consumption connected to quiet network. 4 toshiba corporation introduction pci system block diagram figure 1-2 shows a typical block diagram for a computer using the TC35815CF flow control 10/100mbps ethernet controller. the implementation may integrate various functions in a slightly different way. for example, the memory controller may be implemented as a single controller, or as separate address and data controllers. also, the variety of available audio and video compression and other peripherals open up a wide range of possibilities. figure 1-2 pci system block diagram controller application con?gurations figure 1-3 shows the components that are likely to be used with the TC35815CF flow control 10/100mbps ethernet controller. the controller is normally connected to a 100base-t medium which can operate at either 100mbps or 10mbps. the mii provides transmit and receive clocks for four-bit parallel operation. the clocks oper- ate at 25mhz for 100mbps operation, or 2.5mhz for 10mbps operation. optionally, the controller can also be connected to 10base-t, to provide customer selection of either old or fast ethernet in the ?eld. the controller supports a 10-mhz clock rate for serial 10mbps operation, when connected to a 10mbps manchester encoder- decoder (endec). the system designer has additional options: (1) one or more external cams can add many ethernet addresses for the controller to receive. this is useful for applica- tions such as switching hubs, routers, and bridges, where more addresses must be matched with precision than the controller supports with its on-chip cam. (2) an data control data data cpu cpu bus 32/64 cache mem address control addr dram addr addr pci bus 32 addr i/o bus bridge slots graphics adapter lan adapter crt disk network scsi isa bus data floppy keyboard sound data buffers x bus toshiba corporation 5 introduction inexpensive serial programmable rom can provide the controller with its ethernet station address automatically upon power-up. (3) an mii connector can be provided to allow the use of alternate external 100mbps phys. figure 1-3 configuration for 100base-t showing options data structures the TC35815CF flow control 10/100mbps ethernet controller exchanges control information and data via three data structures: ? frame descriptors ? buffer descriptors ? data buffers figure 1-4 shows how these data structures are related. frame descriptors have a four-byte pointer to the next frame, a ?eld for the sys- tem or applications program to use exclusively, a frame status ?eld, a control ?eld for the entire frame, and an array of associated buffer descriptors. buffer descriptors have a pointer to a data buffer and control ?eld for the buffer. a data buffer is an array of bytes, which can be stored in either little endian or big endian order. for more details on these data structures, see chapter 5, memory organization. the dma engine supports transfer of data on byte boundaries. frame descrip- tors must be aligned on 16 byte boundaries. buffer descriptors must be aligned on eight-byte boundaries. the dma engine employs bursts of full four-byte, aligned pci bus 100/10 mbit/s ethernet controller external cam eeprom or rom 100base-t phy utp or fibre connecter endec and transceiver filters and magnetics rj-45 connector standard component optional component 10 mbit (7 wire) interface media independent interface mii connector 6 toshiba corporation introduction transfers whenever possible. alignment in data buffers does not affect performance very much. the dma engine avoids doing unaligned or partial word accesses, except at the beginning or end of block transfers. figure 1-4 data structure overview system control models the TC35815CF flow control 10/100mbps ethernet controller can be programmed for two modes of operation. ? interrupt on each packet, or group of packets, transmitted or received. ? poll continuously for new packets to transmit. post data and descriptors, but do not interrupt for packets received. an interrupt for each packet or group of packets is the traditional way that ether- net software is controlled. this is appropriate for occasional network traf?c, such as electronic mail. however, as processors increase in speed and complexity, the time to service an interrupt does not improve correspondingly. in fact, many modern processors have large amounts of state information and sophisticated caching schemes, which can slow the relative speed of interrupt processing even further. combined with a faster network, where packets may arrive more frequently, the overhead for servicing net- work interrupts can become a signi?cant burden to the system. also, some applica- tions, such as interactive conferences, require a much higher level of network traf?c. these factors lead to the design of more ef?cient network control schemes. by enabling or disabling interrupts for selected frame descriptors, the system can arrange for the controller to process multiple packets between interrupts. this data bstatus data bstatus data bstatus system control next fstatus system control next fstatus system control next fstatus data buffers buffer descri p tors head tail queue access frame descriptors data bstatus data bstatus data bstatus data bstatus data bstatus ... toshiba corporation 7 introduction reduces the overhead in servicing interrupts, and improves performance by caching code when the system processes several packets at once. it is even possible to set up the controller so that it generates no interrupts at all unless serious errors occur. this requires enabling some additional controls, to ensure that the starting and stopping of traf?c, and polling during idle times, is han- dled ef?ciently. for more details, see chapter 7, dma operation. power management the TC35815CF flow control 10/100mbps ethernet controller provides for dynamic power management. by reducing the clock rate to idle circuits, the controller consumes signi?cantly less power, while maintaining full network functionality. given the current emphasis on the green desktop, or pcs which meet govern- mental guidelines for energy ef?ciency, power management is becoming an issue that affects a broader market segment than just lap-tops and palm-tops. the TC35815CF flow control 10/100mbps ethernet controller is designed to provide a fully-functional, yet power ef?cient solution for networking. reference documents see the following documents for additional technical information: pci local bus speci?cation , revision 2.1, june 1, 1995. pci special interest group, hilsboro, oregon, (800) 433-5177. pci local bus speci?cation , production version, revision 2.0, april 30, 1993. pci special interest group, hilsboro, oregon, (800) 433-5177. international standard iso/iec 8802-3, ansi/ieee std 802.3. information technologytelecomunications and information exchange between systemslocal and metropolitan area networkspart 3: carrier sense multiple access with colli- sion detection (csma/cd) access method and physical layer speci?cations , fifth edition 1996-07-29. ieee std 802.u-1995 (supplement to international standard iso/iec 8802-3: 1993 [ansi/ieee std 802.3 , 1993 edition]). ieee standards for local and metroploitan area networks: supplement to carrier sense multiple access with collision detection (csma/cd) access method and physical layer speci?cations. "media access control (mac) parameters, physical layer, medium attachment units and repeater for 100 mb/s operation, type 100base-t. (clauses 21-30)". approved june 14, 1995. pci hardware and software , by edward solari and george willse, second edition, 1995. annabooks, san diego, ca, (619) 673-0870. pci system architecture , third edition, by tom shanley and don anderson, february 1995. mindshare, inc., published by addison-wesley. ieee std. 802.3x - 1997 supplement to carrier sense multiple access with collision detection (csma/cd) access method and physical layer speci?cations: 8 toshiba corporation introduction "speci?cation for 802.3 full duplex operation" . project 802 local & metropolitan area networks , draft guide to ansi/ieee std 802.3 (csma/cd access method & physical layer speci?cations), systag network guide, draft 5.2, january 23, 1994. the ethernet. a local area network. data link layer and physical layer speci?cations. digital equipment corporation, intel corporation, and xerox corpo- ration. version 2.0. ( "the blue book" ) november, 1982. toshiba toshiba corporation 9 TC35815CF flow control 10/100mbps ethernet controller chapter 2 - external signals signal and power supply information figure 2-1 shows the 94 external signals for the TC35815CF flow control 10/ 100mbps ethernet controller, divided into functional groups. this chapter groups the signal de?nitions by functional area, giving each signals symbolic name, full name, direction, clock domain, and brief de?nition. the groups are: ? 37 for pci address and data ? 13 for pci control, arbitration, error reporting, interrupt, and system ? 18 for mii transmit and receive ? 9 for internal scan ? 4 for an optional external ? 9 for an optional 10mbps manchester eeprom/rom encoder-decoder (endec) ? 2 for an optional external cam interface ? 5 for internal test figure 2-1 external signals table 2-1 power supply information signal pin # function vss 1, 9, 19, 25, 31, 40, 44, 49, 52, 57, 64, 67, 73, 78, 81, 85, 88, 91, 96, 102, 110, 116, 118, 123, 127, 136 ground of power supply (0v) vdd 6, 16, 18, 28, 37, 48, 55, 60, 68, 80, 82, 90, 94, 104, 109, 117, 126, 129, 140 3.3v power supply ad[31:0] par pci address and data frame# trdy# irdy# idsel devsel# stop# pci control inta# pci interrupt req# serr# perr# pci errors gnt# pci arbitration rst# clk pci system t1 t2 t3 t4 t5 test rxd[3:0] rx_clk rx_dv rx_er receive media independent interface (mii) transmit media independent interface (mii) tx_clk col crs txd[3:0] tx_en tx_er cam_load cam_hit# external cam mii station management mdc mdio transmit 10-mbit/s endec txen_10 txd_10 txc_10 rxd_10 rxc_10 crs_10 col_10 10-mbit/s control link_10 loop_10 prom_di prom_do prom_clk external eeprom/ rom prom_cs receive 10-mbit/s endec c_be#[3:0] sca scb scb2 scan sca2 stm si2 so2 si so stm 10 toshiba corporation external signals peripheral component interconnect (pci) signals table 2-2 shows the 50 peripheral component interconnect (pci) signals for the TC35815CF flow control 10/100mbps ethernet controller. these include the 49 sig- nals required for a pci master, plus the interrupt a signal. the part drives sustained tri- state signals high for one clock before returning them to the high-impedance state. sig- nals whose symbols end in # are active-low signals. all signals are referenced to the rising edge of clk, except serr#, rst# and inta#. the serr# signal is asserted synchro- nous, and deasserted asynchronous to the clk. table 2-2 peripheral component interconnect (pci) signals function symbol name type master target clock domain address and data ad[31:0] address and data bus tri-state in/out in/out pci clock c_be#[3:0] command and byte enable bus tri-state out in pci clock par parity tri-state in/out in/out pci clock interface control frame# cycle frame sustained tri-state out in pci clock trdy# target ready sustained tri-state in out pci clock irdy# initiator ready sustained tri-state out in pci clock stop# stop sustained tri-state in out pci clock devsel# device select sustained tri-state in out pci clock idsel initialization device select input -- in pci clock arbitration gnt# grant input a a. a. gnt# is a point-to-point signal. the pci specification specifies the use of a tri-state driver. b. in master mode, the controller does not signal serr#, but monitors it as an input. c. in slave mode, the controller signals serr# for address parity errors. in -- pci clock req# request tri-state out -- pci clock error reporting perr# parity error sustained tri-state in/out in/out pci clock serr# system error open drain in b b. out c c. pci clock/asynch interrupt inta# interrupt a open drain out out asynchronous system clk pci clock input in in pci clock rst# reset input in in asynchronous toshiba corporation 11 external signals pci address and data signals ad[31:0] address and data bus carries address information during the address phase, and data during the data phase. c_be#[3:0] command and byte enable during the address phase, c_be#[3:0] de?nes the type of transaction, and dur- ing the data phase, it indicates the validity of bytes carried on ad[31:0]. table 2-3 shows the correspondence between the byte-enable signals and bytes on the address and data bus during the data phase. table 2-4 shows the byte ordering of data when big endian is enabled. par parity provides even parity for the information carried on ad[31:0] and c_be#[3:0], by causing ad[31:0], c_be#[3:0], and par to contain an even number of bits equal to one. the par signal is active during the clock period after ad and c_be# contain valid data. pci control signals frame# cycle frame driven by the current master to signal how long an access lasts. in a bus transac- tion terminated by the master, the master asserts frame# beginning with the ?rst or address cycle, and holding it until the next to last cycle, when it deasserts it. (see the stop# signal for a description of target abort.) table 2-3 correspondence between c_be#[3:0] and ad[31:0] address and data bus ad[31:0] 31 30 29 28 27 26 25 24 23222120191817161514131211109876543210 byte 3 (msb) byte 2 byte 1 byte 0 (lsb) c_be#[3] c_be#[2] c_be#[1] c_be#[0] table 2-4 big endian byte order address and data bus ad[31:0] 313029282726252423222120191817161514131211109876543210 byte 0 (msb) byte 1 byte 2 byte 3 (lsb) c_be#[3] c_be#[2] c_be#[1] c_be#[0] 12 toshiba corporation external signals trdy# target ready during a read, the target asserts trdy# to indicate that it is driving valid data on ad[31:0]. during a write, the target asserts trdy# to indicate it is ready to receive data over ad[31:0]. a data transfer occurs in a cycle when both trdy# and irdy# are asserted. irdy# initiator ready during a read, the initiator asserts irdy# to indicate that it is ready to receive data on ad[31:0]. during a write, the initiator asserts irdy# to indicate it is driving valid data over ad[31:0]. a data transfer occurs in a cycle when both trdy# and irdy# are asserted. stop# stop# the target asserts stop# to request that the master terminate or abort the current transaction. devsel# device select driven by the target to con?rm that it has decoded the address as referring to itself. idsel initialization device select equivalent to chip select, idsel is a fully-decoded addressing mechanism for con?guration read and write transactions. pci bus arbitration signals gnt# grant a point-to-point signal from the arbiter to an agent, signalling to the agent that the arbiter has granted it bus ownership. req# request a point-to-point signal from an agent to the arbiter, signalling to the arbiter that toshiba corporation 13 external signals the agent desires bus ownership. in normal operation, req#, is an output, but during reset it enters a high-impedance state. pci error signals perr# parity error kept at a high-impedance state, unless an agent receives non-special cycle data with a parity error, in which case it asserts perr# two clocks later, and then, as with all sustained tri-state signals (unlike serr#), drives it high for one clock before return- ing to the high-impedance state. serr# system error the serr# signal is used to signal parity errors during an address cycle of a bus transaction, and all errors other than parity errors. pci interrupt signal inta# interrupt a requests an interrupt. pci system signals clk clock all inputs are sampled on rising edge of clock. the controller supports 100 mbps ethernet when operating at 16-33mhz frequency operation. may be held low at any time, to conserve power. may only be stopped in a low state. rst# reset causes all output signals to enter a high-impedance state, and clears all registers. does not affect on-chip ram or fifos. upon deassertion, the software drivers are responsible to check for the presence of a serial rom, and if present, to read in the station address, and other con?guration parameters. 14 toshiba corporation external signals media independent interface (mii) signals the mii is the interface between the TC35815CF flow control 10/100mbps ether- net controller and the physical layer (phy). transmit mii signals table 2-5 shows the mii signals supported by the TC35815CF flow control 10/ 100mbps ethernet controller for transmitting packets. for a detailed description of these signals, see the mii sections of the 802.3u documents listed in the reference documents section. col collision asserted asynchronously with minimum delay from the start of a collision on the medium. tx_clk transmit clock txd[3:0] and tx_en are driven off the rising edge of the tx_clk by the control- ler, and sampled by the phy on the rising edge of the tx_clk. txd[3:0] transmit data transmit data is aligned on nibble boundaries. txd[0] corresponds to the ?rst bit to transmit on the physical medium and is the lsb of the ?rst byte, followed by the ?fth bit of that byte during the next clock. tx_en transmit enable tx_en provides precise framing for the data carried on txd[3:0]. it is active during the clock periods that txd[3:0] contains valid data to be transmitted, from preamble through crc. table 2-5 transmit mii signals symbol name direction clock domain col collision input C tx_clk transmit clock input C txd[3:0] transmit data output tx_clk tx_en transmit enable output tx_clk tx_er transmit coding error output tx_clk toshiba corporation 15 external signals tx_er transmit coding error tx_er is driven synchronously to tx_clk and is sampled continuously by the physical layer entity (phy). if asserted for one or more tx_clk periods, it causes the phy to emit one or more symbols which are not part of the valid data or delimiter set somewhere in the frame being transmitted. receive mii signals table 2-6 shows the mii signals supported by the TC35815CF flow control 10/ 100mbps ethernet controller for receiving packets. for a detailed description of these signals, see the mii sections of the 802.3u documents listed in the reference docu- ments section. crs carrier sense asserted asynchronously with minimum delay from the detection of a non-idle medium. rx_clk receive clock rx_clk is a continuous clock. in four-bit mode, its frequency is 25mhz for 100mbps operation, and 2.5 mhz for 10mbps. rxd[3:0], rx_dv, and rx_er are driven by the phy off the falling edge of rx_clk, and sampled on the rising edge of rx_clk. rxd[3:0] receive data rxd is aligned on nibble boundaries. rxd[0] corresponds to the ?rst bit received on the physical medium which is the lsb of the byte in one clock period and the ?fth bit of that byte in the next clock. table 2-6 receive mii signals symbol name direction clock domain crs carrier sense input C rx_clk receive clock input C rxd[3:0] receive data input rx_clk rx_dv receive data valid input rx_clk rx_er receive error input rx_clk 16 toshiba corporation external signals rx_dv receive data valid phy asserts rx_dv synchronously and holds it active during the clock periods that rxd[3:0] contains valid received data. phy asserts rx_dv no later than the clock period when it places the ?rst nibble of the start frame delimiter (sfd) on rxd[3:0]. if phy asserts rx_dv prior to the ?rst nibble of the sfd, then rxd[3:0] carries valid preamble symbols. rx_er receive error phy asserts rx_er synchronously whenever it detects a physical medium error, e.g., a coding violation. phy asserts rx_er only when it asserts rx_dv. mii station management signals table 2-7 shows the two mii station management signals. use of these signals for con?guring a phy or negotiating a link protocol is optional. mdc management data clock timing reference for transfer of information on the mdio signal. with the pci clock at 33mhz, the mdc clock has a maximum clock frequency of 33/14 = 2.36mhz. the minimum clock period is 424 ns. mdio management data i/o transfers data to or from a phy attached to the mii interface. controller can initiate a sequence to determine whether a phy is attached. output/input is tri-state and a pull down resistor is provided in the pad. external 10mbps endec signals these signals support connection to a optional 10base-tphy. this mode of opera- tion is distinct from the 10mbps operation mode of the mii. the external endec uses a 1-bit serial signal, while the mii supports a 4-bit parallel interface. table 2-7 mii station management signals symbol name direction mdc management data clock output mdio management data input/output tri-state toshiba corporation 17 external signals transmit 10mbps signals table 2-8 shows the four signals which support transmission via an external 10mbps manchester encoder-decoder (endec). col_10 collision detect on 10mbps endec asserted when a 10mbps phy detects a collision. ignored if 10mbps phy is not enabled by the master control register. txc_10 transmit clock on 10mbps endec clock from 10mbps phy to transfer data. ignored if 10mbps phy is not enabled by the master control register. txd_10 transmit data on 10mbps endec data line for transmitting to the 10mbps phy. stays low if 10mbps phy is not enabled by the master control register. txen_10 transmit enable on 10mbps endec asserted by the controller when it is ready to transfer data. stays low if 10mbps phy is not enabled by the master control register. receive 10mbps signals table 2-9 shows the three signals which support reception via an external 10mbps endec. table 2-8 transmit 10mbps endec interface symbol name direction col_10 collision detect on 10mbps endec input txc_10 transmit clock on 10mbps endec input txd_10 transmit data on 10mbps endec output txen_10 transmit enable on 10mbps endec output 18 toshiba corporation external signals crs_10 carrier sense on 10mbps endec asserted when a 10mbps phy has data to transfer. ignored if 10mbps phy is not enabled by the master control register. rxc_10 receive clock 10mbps endec clock from 10mbps phy to receive data. ignored if 10mbps phy is not enabled by the master control register. rxd_10 receive data 10mbps endec data line for receiving from the 10mbps phy. ignored if 10mbps phy is not enabled by the master control register. 10mbps control signals table 2-10 shows the two signals provided to control 10mbps phy. use of these sig- nals is optional. loop_10 loop back at 10mbps endec output signal, driven by bit 7 of mac of control register. link_10 link status of 10mbps endec used to convey link status of the 10mbps endec. stored in bit 15 of mac of con- trol register. ignored if 10mbps phy is not enabled by the master control register. table 2-9 receive 10mbps endec interface symbol name direction crs_10 carrier sense on 10mbps endec input rxc_10 receive clock on 10mbps endec input rxd_10 receive data on 10mbps endec input table 2-10 10mbps control signals symbol name direction loop_10 loop back at 10mbps endec output link_10 link status of 10mbps endec input toshiba corporation 19 external signals external eeprom or rom interface table 2-11 shows the four signals which control an external eeprom or rom. use of these signals is optional. prom_di eeprom/rom data input data line for transmitting from external eeprom/rom to the controller. must be high with no eeprom present. an internal resistor pull-up is a solution. prom_do eeprom/rom data output transfers data from the controller to an external eeprom/rom. prom_clk eeprom/rom clock clock for transmitting to and from an external eeprom/rom. with the pci clock at 33mhz, the maximum clock frequency for prom-clk is 33/34 = 0.97mhz. this is compatible with the slowest commercial parts, which specify a maximum frequency of 1mhz. prom_cs eeprom/rom chip select used to frame transmissions to and from an external eeprom/rom. table 2-11 external eeprom or rom interface symbol name direction prom_di eeprom/ rom data input input prom_do eeprom/ rom data output output prom_clk eeprom/ rom clock output prom_cs eeprom/ rom chip select output 20 toshiba corporation external signals external cam interface signals table 2-12 shows the two external cam interface signals. use of these signals is optional. cam_load external cam address load signals the external cam to begin loading the destination address from rxd[3:0]. this signal is optional even with an external cam, as external circuitry can derive it from mii signals, just as the mac does. cam_hit# external cam hit noti?cation from the external cam that it has recognized this packets destina- tion address. held inactive by a pull-up resistor if the external cam is not present. internal scan interface signals table 2-13 lists nine scan interface signals. this group of signals is used to implement scan test vectors for automatic testing. the TC35815CF flow control 10/100mbps ethernet controller requires two scan chains. the scan test mode signal is required to be asserted during scan testing, in order to hold some internal logic elements in a testable state. these include elements related to clock muxing, power management, software reset, and memory blocks. table 2-12 external cam interface signals symbol name direction cam_load external cam address load output cam_hit# external cam hit input table 2-13 internal scan interface signals symbol name direction sca scan clock a input sca2 scan clock a-2 input scb scan clock b input scb2 scan clock b-2 input si scan data in input so scan data out tri-state si2 scan data in-2 input s02 scan data out-2 tri-state stm scan test mode input toshiba corporation 21 external signals sca scan clock a-2 the scan clock a for the second internal scan chain. scb scan clock b the scan clock b for the ?rst internal scan chain. scb2 scan clock b-2 the scan clock b for the second internal scan chain. si scan data input the scan data input is the serial input for data shifted into the ?rst internal scan chain. so scan data output the scan data output is the serial output for data shifted from the ?rst internal scan chain. si2 scan data input-2 the scan data input is the serial input for data shifted into the second internal scan chain. so2 scan data output-2 the scan data output is the serial output for data shifted from the second internal scan chain. stm scan test mode the scan test mode is asserted during scan testing, and deasserted for normal operation. it is required to place the chip in a testable state. this signal is deasserted when mounted in a user device. a pull-down resistor should be provided internally, to make this the default. toshiba corporation 2 2 external signals this page left blank intentional l y toshiba toshiba corporation 23 TC35815CF flow control 10/100mbps ethernet controller chapter 3 - functional blocks overview of functional blocks figure 3-1 gave an overview of an ethernet circuit. the functional blocks of the TC35815CF flow control 10/100mbps controller are shown in more detail in figures 3-1 and 3-2. figure 3-1 shows the dma functional blocks, while figure 3- 2 shows the mac functional blocks. figure 3-1 dma functional blocks both diagrams, refer to the dma independent interface (dii). this is an inter- nal interface with a simple handshaking protocol, which interfaces the two, small, byte-wide fifos in the mac with wider and deeper fifos in the dma block. pci and dma overview the peripheral component interconnect (pci) bus is an industry-standard bus for high performance pcs and workstations. in addition, some network hub designs use the pci bus for internal data paths, or back plane connections. figure 3-1 shows the major functional blocks in the dma for con?guring and controlling the pci bus, and for transferring data to and from the dma fifos: ? pci i/o control block, for generating and recognizing pci control signals. ? pci slave block, for recognizing and controlling transactions where the ether- net controller is the target device. ? pci master block, for controlling transactions where the ethernet controller is the initiator device. pci bus / dma fifo arbiter 32 / dma receive consumer p c i dma transmit producer dma transmit fifo pci i/o ctl pci slave pci master pipe regs / 8 addr data ctl & stat registers dma receive fifo dma transmit consumer dma receive producer / 32 8 / d i i 24 toshiba corporation functional blocks ? pci pipe registers, to provide buffering, so dma engine can sustain back-to-back (or 1-1-1-1...) performance during long burst operations. ? control and status registers, for pci configuration and mac and dma control. ? an arbiter block, for allocating access to the pci bus and dma memory. ? producer and consumer control blocks for transmit and receive data entering and leaving the dma fifos. the pci con?guration registers and dma registers provide con?guration and control information for the ethernet controller as a pci i/o device. they also provide access to data structures stored in main memory, and access to the control and status information in the mac. there are two fifo buffers controlled by the dma engine. the dma transmit fifo holds data and status information for packets being transmitted. the dma receive fifo holds data and status information for packets being received. the pci arbiter decides which of the consumer and producer state machines has highest prior- ity for accessing the fifo buffers. the priority is dynamic. during burst transfers, the state machines controlling the pci bus are given priority, if possible. but if a receive fifo is close to becoming full, or a transmit fifo is close to becoming empty during transmission, that fifo will receive priority. otherwise, the arbiter will provide round- robin fair service. the dma controller blocks provide logic for controlling bus master read and write operations across the pci bus. they include: ? burst size control, to optimize pci and system performance. ? transmit threshold control, to match transmission latency to pci bus latency. ? big endian byte swapping, to support data transfers to big endian processors. ? buffer spanning and packing controls. ? polling controls, to optionally poll for packets to transmit. ? wake-up controls, to start transmission as soon as data is ready. ? early notification, to allow processing of incoming data to begin before data end. ? interrupt enable controls, to adjust controller behavior to protocol requirements. mac overview in figure 3-2 we see that the mac consists of a transmit block, a receive block, a set of control and status registers, and two serial controllers, one for accessing the mii sta- tion management interface, and one for the external eeprom/rom. the mac also has a loopback circuit, optional support for a 10mbps interface to a manchester encode/decoder, and support for an optional external cam circuit. toshiba corporation 25 functional blocks figure 3-2 mac functional blocks the media independent interface (mii) is the interface between a 100 base-t compatible physical layer and the transmit and receive blocks, and is part of the ieee 802.3 standard. the transmit block buffers the outgoing data in the mac transmit fifo, encap- sulates it, and passes it on to the mii and the 10mbps interface. the transmit block has circuits for generating preamble and jam bytes, pad bytes, and the crc value. it also has logic to check parity, a timer for the backoff delay after a collision, and a timer for the inter-packet gap after a transmission. the receive block decapsulates the received packet from the mii and stores it in the mac receive fifo. the receive block has circuits for checking the crc value, generating parity to protect data in the fifo, and checking packet lengths. the receive block also has a content addressable memory (cam) block which provides for acceptance or rejection of a packet based on its destination address. the registers control programmable options, and specify which conditions inter- rupt the system. the status registers hold information for error handling software, and the error counters accumulate statistical information for network management soft- ware. the loopback circuit provides for mac-layer testing in isolation from the mii and physical layer. the mac blocks provide controls for network operation, including: ? controls to enable and disable transmit and receive circuit, including requests to halt at end of current packet. transmit block mac transmit fifo preamble and jam generator pad and crc generator backoff and intergap timers d i i receive block mac receive fifo address cam controller crc and cam filters parity gen. / 8 m i i mac control & status registers 10 mb i/f txd_10 rxd_10 rxd[3:0] txd[3:0] station manager serial controller external eeprom/ rom mdc mdio eeprom/rom serial controller loopback external cam cam_load cam_hit# flow control / 8 26 toshiba corporation functional blocks ? interrupt enable and disable controls for individual conditions. ? address recognition controls, for up to 21 individual addresses. ? counters and status bits for collecting network management data. ? loopback and other controls, to aid in diagnosing problems. ? controls for reading, writing, and erasing values in an eeprom or rom chip. ? pause operation enable controls, to enable pausing of transmitter on receipt of mac control packets specifying a pause operation. ? mac control packets transmit controls, to enable generation of pause and other mac control packets, even when transmitter is paused. ? mac control packets pass through controls, to enable s/w to process other forms of mac control packets. media independent interface (mii) both transmit and receive blocks operate using the mii, which was developed by the ieee 802.3 task force on 100mbps ethernet to support the following goals: 1. physical media independence. 2. multi-vendor point of interoperability. 3. data and data delimiters are synchronous to clock references. 4. provides independent four-bit wide transmit and receive data paths. 5. capable of supporting both 100 and 10mbps rates. 6. compatible with common digital cmos asic processes. 7. primarily a chip-to-chip interface with ttl signal levels. 8. provides a simple management interface for speed detection, link status, etc. 9. support connection of mac layer end physical (phy) layer devices. 10. capable of driving a limited length of shielded cable via a standard connector. the physical layer or phy encodes outgoing data and decodes incoming data. the manner of encoding (manchester for 10mbps operation, 4b/5b for 100base-x, or 8b/ 6t for 100base-t) does not affect the mii. the mii expects raw data for transmission, starting with the preamble and ending with the crc. the mac layer can also generate jam and pad bytes. the station manager block, described in this chapter on page 30, mii station manager, provides an interface for speed detection, link status, etc. chapter 2, external signals, de?nes the signals which make up the mii. chapter 8, timing, gives detailed timing information for the mii. toshiba corporation 27 functional blocks peripheral component interconnect (pci) bus the peripheral component interconnect (pci) bus is the latest in a series of local bus standards for pc- and workstation-class machines. the primary reasons for support- ing the pci bus are: ? industry standard C both pc and workstation companies are supporting it. ? high speed C fast enough to support 100mbps ethernet. ? cost effective C chip sets in high volume will ensure low costs. ? bus master mode C relieves the system of significant processing load. the pci bus features 32-bit addresses and a 32-bit data path, multiplexed over the same pins. for future growth, a 64-bit extension of the bus is also de?ned, but is not supported by this controller. in burst-mode transfers, the pci bus can, in theory, support 132mbytes transfer rates (the 64-bit version supports 264mbytes) with a 33mhz system clock. the TC35815CF flow control 10/100mbps ethernet control- ler works with both current and future higher performance bus controller chips. chapter 2, external signals, de?nes the signals which make up the pci bus. chapter 8, timing, gives detailed timing information for the pci bus. dma functional blocks pci arbiter the pci arbiter accepts as input signals status information from the dma transmit and receive controllers. the pci arbiter controls switching between transmit, receive, and noti?cation activity on the pci bus using pci in master mode access. the pci arbiter also allows slave mode access to read and write control and status registers. dma transmit controller the dma transmit controller consists of two state machines: a producer and a consumer. the dma transmit producer reads the transmit queue frame descriptor, and controls the transfer of data from the transmit queue to the transmit data fifo. it also controls the writing of transmit status information, which gives mac status information about trans- mitted packets, after transmission is complete. the dma transmit consumer controls the mac transmit engine and the movement of data from the dma transmit fifo to the smaller mac transmit fifo. 28 toshiba corporation functional blocks dma receive controller the dma receive controller consists of two state machines: a producer and a con- sumer. the dma receive producer controls the movement of data from the mac to the dma receive fifo. the dma receive consumer allocates buffers from the free buffer list, writes new frame descriptors and related buffer descriptors in the free descriptor area, and controls the transfer of bytes from the dma receive fifo into system memory via the pci bus. mac functional blocks mac transmit block the transmit block is responsible for transmitting data. it complies with the ieee 802.3 standard for carrier sense multiple access with collision detection (csma/ cd) protocol. it also supports a full-duplex mode of operation, which allows simulta- neous transmission while receiving. the transmit block consists of the following: 1. transmit fifo, fifo controller, and counters 2. preamble and jam generator 3. pad byte and crc generator 4. parity checker 5. backoff and intergap timers for more information on the transmit block see chapter 6, mac operation. mac receive block the receive block is responsible for receiving data. it complies with the ieee 802.3 standard for carrier sense multiple access with collision detection (csma/cd) protocol. it also supports a full-duplex mode of operation, which allows simultaneous transmission while receiving. the receive block consists of the following sections: 1. receive fifo, fifo controller, and counters 2. cam block for address recognition 3. crc generator and checker 4. parity generator for more information on the receive block see chapter 6, mac operation. 29 toshiba corporation functional blocks flow control block the ?ow control block provides for the following functions: ? recognition of mac control frames received by the receive block. ? transmission of mac control frames, even if transmitter is paused. ? timers and counters for pause operation. ? command and status register interface. ? options for passing mac control frames through to s/w drivers. the receive logic in the ?ow control block recognizes a mac control frame and performs the pause operation as follows: first, the length/type ?eld must have the special value speci?ed for mac control frames. second, the destination address must be recognized by the cam. third, the frame length must be 64 bytes, including crc. fourth, the crc must be good. and ?fth, the frame must contain a valid pause operation code and operand value. if the length/type ?eld does not have the special value speci?ed for mac con- trol frames, then the mac takes no action, and the packet is treated as a normal packet. if the cam does not recognize the destination address, the mac rejects the packet. if the packet length is not 64 bytes, including the crc, the mac will not per- form the operation. the packet will be marked as a mac control packet, and passed forward to the s/w drivers, if pass through is enabled. a control bit in the transmit status register can be set to generate a full duplex pause operation or other mac control function, even if the transmitter itself is paused. there are two timers and corresponding csr registers which are used during pause operation. one timer and register are used when a received packet causes the transmitter to be paused. the other pair is used to approximate the paused status of the other end of the link, after the transmitter sends a pause command. the command and status register (csr) interface provides control and status bits within the transmit and receive control registers and status registers. these allow the initiation of sending a mac control frame, enabling and disabling mac control functions, and reading of the flow control counters. control bits are provided for either processing mac control frames entirely within the controller, or for passing mac control frames on the s/w drivers. this allows flow control to be enabled by default even if s/w drivers which are not other- wise "flow control aware". 30 toshiba corporation functional blocks mac control and status registers the mac has a block of registers which provides control and status information. these registers control the transmit and receive blocks, report mac status, and pro- vide a communication interface to the cam, the mii station management interface, and the optional external eeprom/rom. these registers are available via pci memory-mapped or i/o mapped access. for more information on the mac control and status registers see the section mac layer registers in chapter 4. mii station manager the toshiba 100/10mbps ethernet mac processes the station management data (mdio and mdc) signals of the mii controller, but does not interpret the values. the mii station manager provides logic for reading and writing control and status regis- ters in a con?gured phy device through the mii de?ned serial interface. if a specialized application, such as a bridge, router, or switched hub, requires access to these values to negotiate con?gurations, they are available via mac control and status registers which trigger reads and writes across the station management data interface. for more information see the section station management data access registers in chapter4. prom controller the prom controller provides logic for reading and writing an optional external eeprom or rom device. the external devices supported are the microchip 93lc46b and the national nm93c46. timing compatible devices, smaller devices, and read-only equivalent devices are also supported. for more information see the section prom control registers in chapter 4. toshiba toshiba corporation 31 TC35815CF flow control 10/100mbps ethernet controller chapter 4 - registers overview this chapter describes user accessible registers for the TC35815CF flow control 10/100mbps ethernet controller. registers are grouped by function: ? pci configuration ? dma control and status registers ? flow control registers ? mac control and status in normal operation, most registers do not need to be accessed directly. transmit and receive operations are done using continuous cyclic queues, or rings. control and status information is communicated through data structures described in chapter 5. dma control registers need to be accessed at initialization time, in order to initiate operation. mac registers may need to be accessed for special con?guration needs, such as setting the cam to do address ?ltering. for interrupt based drivers, some of the dma and mac registers are accessed in the interrupt handler, to enable and dis- able interrupts, to determine the cause of an interrupt, and to clear interrupt condition bits. flow control registers may be accessed by drivers to monitor the progress of local and remote pause commands. table 4-1 shows the register name, symbol, address, size, and access type for each pci con?guration register. the pci con?guration registers implement a standard master/slave pci device. they provide device identi?cation, control and status information, and vari- ous setup registers, which are addressed at initialization time. pci con?guration registers can be loaded from an eeprom/rom or initial- ized by system driver code which asserts the idsel signal. table 4-1 pci con?guration registers name symbol addr bytes access vendor id vend_id 00h 2 ro device id dev_id 02h 2 ro command pci_cmd 04h 2 r/w status pci_stat 06h 2 r/w class code pci_clas 08h 4 ro pci control pci_ctl 0ch 4 r/w* i/o base address io_basea 10h 4 r/w memory base address mlo_basea 14h 4 r/w subsystem vendor id sub_vend_id 2ch 2 r/w subsystem id sub_id 2eh 2 r/w pci interrupt pci_int 3ch 4 r/w* 32 toshiba corporation registers table 4-2 shows the register name, symbol, address, size, and access type for each dma control register. these registers provide support for a transmit queue, a receive queue, free buffer list, and a free descriptor area. some registers control frag- mentation sizes or polling rates. table 4-3 shows the register name, symbol, address, size, and access type for each flow control register. these registers provide support for receiving, processing, and generating full duplex pause operations and other forms of mac control packets. table 4-4 shows the functional group, register name, symbol, address, size, and access type for each mac control and status register. these registers are generally loaded from an eeprom or rom on chip power up or chip reset. some of these reg- isters, such as the cam control and error count registers, are accessed by system soft- ware drivers while the mac is active. the mac transmit and receive control and status registers are generally controlled by the dma engine after they are setup. table 4-2 dma control registers name symbol addr bytes access dma control dma_ctl 00h 3 r/w transmit frame pointer txfrmptr 04h 4 r/w transmit threshold txthrsh 08h 2 r/w transmit polling counter txpollctr 0ch 2 r/w buffer list frame pointer blfrmptr 10h 4 r/w receive fragment size rxfragsize 14h 2 r/w interrupt enable int_en 18h 2 r/w free descriptor area base fda_bas 1ch 4 r/w free descriptor area limit fda_lim 20h 2 r/w interrupt source int_src 24h 2 r/w* table 4-3 flow control registers name symbol addr bytes access pause count pausecnt 30h 2 ro remote pause count rempaucnt 34h 4 ro transmit control frame status txconfrmstat 38h 2 r/w toshiba corporation 33 registers the mac layer control registers include a master mac control register, control registers for transmit and receive, control registers for the cam, and some error counters for network management. register access there are three basic types of register access: 1. ro - read only. writing to a ro register has no effect. 2. r/w - read and write. the user can read and write the register. the controller may also write the register, and some parts may be reserved or read only, so the user may not always be able to read what was written. 3. rclr/w - read with clear and write. reading the register clears the value. used for counters. may also be written to change the count period. the registers with access marked with * have special semantics, such as bits which are write 1 to clear, etc. as explained in the detailed descriptions. reserved bits are initialized to 0. software should leave them unchanged when writing to registers, to aid in compatibility with future uses. software should not depend on the value of reserved ?elds being 0. table 4-4 mac control and status registers group name symbol addr bytes access mac mac control mac_ctl 40h 2 r/w* cam control cam_ctl 44h 1 r/w transmit control tx_ctl 48h 2 r/w* transmit status tx_stat 4ch 2 ro receive control rx_ctl 50h 2 r/w receive status rx_stat 54h 2 ro station management data station management data md_data 58h 2 r/w station management control and address md_ca 5ch 2 r/w* cam cam address cam_adr 60h 2 r/w cam data cam_data 64h 4 r/w cam enable cam_ena 68h 3 r/w eeprom prom control prom_ctl 6ch 2 r/w* prom data prom_data 70h 2 r/w system management missed error count miss_cnt 7ch 2 rclr/w 34 toshiba corporation registers register address summary figures 4-1 through 4-4 summarize the memory addresses of the pci con?guration reg- isters, the dma control and status registers, flow control registers, and mac control and status registers. these ?gures assume a little endian layout of system memory. figure 4-1 address map of pci configuration registers figure 4-2 address map of dma control registers dev_id vend_id pci_stat pci_cmd rev_id pci_clas prog_if sub_cl base_cl 00 04 08 0c 10 14 18 1c ... 3c reserved int_line pci_int int_pin min_gnt max_lat cache_sz pci_ctl lat_timr hdr_typ bist io_basea mlo_basea reserved (mhi_basea) reserved byte 0 byte 1 byte 2 byte 3 sub_id reserved ... 2c sub_vend_id 00 04 08 reserved 0c txpollctr txfrmptr 10 14 rxfragsize reserved 1c 20 fda_bas fda_lim blfrmptr txthrsh byte 3 byte 2 byte 1 byte 0 reserved dma_ctl reserved 18 int_en reserved 24 int_src reserved toshiba corporation 35 registers figure 4-3 address map of flow control registers figure 4-4 address map of mac control and status registers the pci con?guration register addresses are effective when the idsel signal is asserted. the dma and mac control and status register addresses are effective when idsel is not asserted and when the upper bits of the address match either the i/ o base register (io_basea) or the memory base register (mlo_basea). 30 34 38 rempaucnt txconfrmstat byte 3 byte 2 byte 1 byte 0 reserved pausecnt reserved reserved 40 44 48 4c 50 54 60 64 68 5c 58 6c 70 7c miss_cnt reserved prom_ctl cam_data[3:0] cam_ena[2:0] reserved tx_ctl tx_stat mac_ctl reserved cam_ctl cam_adr reserved rx_ctl rx_stat md_data byte 0 byte 1 byte 2 byte 3 md_ca reserved reserved reserved reserved reserved reserved reserved prom_data reserved reserved reserved ... reserved 36 toshiba corporation registers pci con?guration registers there are a total of 256 con?guration address spaces reserved for a pci device. the ?rst 64 address spaces are prede?ned by the pci speci?cation. the TC35815CF flow control 10/100mbps ethernet controller uses only the ?rst 64 address spaces. vendor id register vendor id (vend_id) 00h the vendor id register identi?es toshiba as the component manufacturer. it contains a unique identi?cation number assigned by pci sig. the toshiba pci sig number is 102fh. device id register device id (dev_id) 02h the pci device id register identi?es the speci?c device. the 16-bit number is assigned by toshiba is 0030h. revisions are part of the class code register. 15 0 vendor id number 15 0 device id number toshiba corporation 37 registers pci command register pci command (pci_cmd) 04h this register describes how the controller can generate or respond to pci cycles. for a more complete description, see the pci speci?cation, section 6.2.2, device control. the following are required for the ethernet controller to operate correctly: bus- mas, and either mems or ios. the following are optional for the ethernet controller: serren, and parer. the following are always 0 and ignored by the ethernet controller: fasten, waitcc, vga_ps, mwien, and specc. the controller only contains one address comparator, which is shared between memory and i/o accesses as follows: when mems=0 and ios=1, the controller will respond to any accesses; when mems=1 the controller will respond to memory space accesses only, regardless of the value of ios. in addition to mems and ios, the cor- responding base address register must be set. hardware reset to value 000h. software reset has no effect. 15 10 9 8 7 6 5 4 3 2 1 0 reserved fasten serren waitcc parer vga_ps mwien specc busmas mems ios fasten fast back-to-back enable =0. controller cannot do fast back-to-back transactions to different devices. serren system error enable enable the system error (serr#) driver. waitcc wait cycle control =0. controller does not generate address/data stepping. parer parity error response device is to respond to parity errors. vga_ps vga palette snoop =0. no special vga palette snooping. mwien memory write & invalidate enable =0. controller does not generate memory write & invali- date commands. specc special cycles =0. controller ignores special cycle operations. busmas bus master device can behave as a bus master. mems memory space device can respond to memory accesses. ios i/o space device can respond to i/o space accesses. 38 toshiba corporation registers status register status (pci_stat) 06h this register records status information for pci bus related events. this register has some special operating characteristics. for example, individual bits are cleared by writing a 1; writing a 0 has no effect. this is necessary to support simultaneous updat- ing of status information by both the system and the pci device. for a more complete description, see the pci speci?cation, section 6.2.3, device status. software reset to value 0200h. 15 14 13 12 11 10 9 8 7 6 0 dparerr ssyserr rmasabt rtarabt starabt devsel dpard fastcap reserved dparerr detected parity error parity error was detected. set even if parity error response bit in pci command register is not set. parity errors during address cycles are included. ssyserr signaled system error set when device asserts the serr# line. rmasabt received master abort this device was master and a master transaction was termi- nated with master-abort, except for a special cycle. rtarabt received target abort this device was master and a master transaction was termi- nated with target-abort. starabt signaled target abort this device was target and a master transaction was termi- nated by asserting target-abort. devsel device selection timing =01. the controllers slowest devsel# timing as a target device is medium. the bits are encoded: 00 - fast 01 - medium 10 - slow dpard data parity detected set when (1) perr# asserted or observed by the controller, (2) agent setting perr# acted as master, and (3) parity error response bit in pci control register is set. fastcap fast back-to-back capable =0. the controller is not capable of accepting fast back-to- back transactions from different agents. toshiba corporation 39 registers class code register class code (pci_clas) 08h pci control register pci control (pci_ctl) 0ch hardware reset to value 8000_0000h. software reset has no effect. the built-in self test (bist) is used to test the on-chip buffers. the high order of bist (bit 31 of pci_ctl) is a r/o 1, indicating the controller supports bist. the next bit (bit 30 of pci_ctl) is used to start the test. writing a 1 to bit 30 invokes the test; bit 30 is cleared when the test is complete. if the test fails, the low order bits of the bist status (bits 25, 24 in pci_ctl) are set to indicate the nature of the error; bit 25 indicates a ram parity error; bit 24 indicates a ram test failure: read data did not match expected data. bits 29 to 26 are reserved. bist should be invoked by software drivers during initialization. note: invok- ing bist will overwrite the ram based registers. with a 33mhz clock, the bist test takes approximately 123s, assuming a 1k 31 24 23 16 15 8 7 0 base_cl sub_cl prog_if rev_id base_cl base class id set to 02h for network controller. sub_cl sub class id set to 00h for ethernet controller. prog_if programming interface set to 00h. no register level programming interfaces de?ned. rev_id revision id set by manufacturer to a device speci?c revision number, an extension to the device id register. 31 24 23 16 15 8 7 0 bist hdr_typ lat_timr 0 cache_sz bist built-in self test controls invocation of self test code on start up. hdr_typ header type set to 00h for single function, standard layout of bytes 10h through 3fh in con?guration space. lat_timr latency timer number of pci bus clocks for controller as bus master. cache_sz cache line size system cache line size. 40 toshiba corporation registers double-word memory. the default value of the latency timer is 0, to indicate it is programmable. on hardware reset, the cache line size is set to zero. it is the responsibility of the s/w drivers to set an appropriate default cache line size. the recommended size for most systems is eight doublewords (32 bytes). the controller can support cache line sizes up to 127 doublewords. the cache line size is used to select memory read multiple commands instead of memory read line commands for burst reads. i/o and memory base address registers these registers are used to map the dma and mac control and status registers into either i/o address space or system memory space. i/o address space and memory address space are both limited to 32 bits. in addition to setting a base address register, the corresponding control bit in the pci command register must be set. i/o base address (io_basea) 10h hardware reset to value 0000_0001h. software reset has no effect. memory base address (mlo_basea) 14h hardware reset to value 0000_0000h. software reset has no effect. 31 4 3 2 1 0 baseaddr 0 0 i/o baseaddr base address upper 28-bits of base address. i/o i/o flag 1= i/o space (read-only). 31 4 3 2 1 0 baseaddr 0 loc i/o baseaddr base address upper 28-bits of base address. loc location bits 00= locate anywhere in 32-bit address space (read-only). i/o i/o flag 0= memory space (read-only). toshiba corporation 41 registers subsystem vendor id register after hardware reset, the subsystem vendor id and subsystem id registers are ini- tialized with values read from the eeprom/rom, if present. an attempt to read these registers while they are being loaded will be terminated with a target retry. subsystem vendor id register (sub_vend_id) 2ch the subsystem vendor id register identi?es the adapter card manufacturer. it contains a unique identi?cation number assigned by pci sig. the default value is 0. if an eeprom is present, it can be used to set the value. subsystem id register subsystem id (sub_id) 2eh the subsystem id register identi?es the speci?c device. the 16-bit number is assigned by the adapter card manufacturer. vendors that produce both devices and subsystems must ensure that subsystem id values are different from device id val- ues. the default value is 0. if an eeprom is present, it is used to set the value after hardware reset. 15 0 subsystem vendor id number 15 0 subsystem id number 42 toshiba corporation registers pci interrupt register pci interrupt (pci_int) 3ch the value of 0 for max_lat and min_gnt indicate that these registers are not used for determining these values. to determine if an interrupt is being generated by this pci device, the s/w should examine the interrupt source register. for more information see chapter 4, page 49, in the section interrupt source register. dma control registers there are three queues which are jointly managed by the dma engine and the sys- tem software: 1. transmit queue - txq 2. receive queue - rxq 3. buffer list -bl_q the transmit queue is a list of frame descriptors which are ready for transmis- sion. the receive queue is a list of frame descriptors which have been received and are ready for processing by the system software. the buffer list is a list of buffer descriptors which describes areas of system memory that can be used to store received data. the free descriptor area (fda) is the memory area where the controller writes the frame descriptors and buffer descriptors for the receive queue. 31 24 23 16 15 8 7 0 max_lat min_gnt int_pin int_line max_lat maximum latency ro =0 (unit = 1/4 microsecond) desired setting for latency timer vales. min_gnt minimum grant ro = 0 (unit = 1/4 microsecond) minimum burst period, assuming 33mhz clock. int_pin interrupt pin ro set to 01h for inta#. int_line interrupt line r/w set by system. interrupt line routing information. toshiba corporation 43 registers dma control dma control (dma_ctl) 00h hardware reset to value 0000_1020h. software reset has no effect. the dma control register controls the transfer of data in master mode: burst size, big endian byte ordering, and test mode functionality. it also controls a number of other dma functions, such as power management, wake-up on transmit, and software interrupt. the dmburst ?eld controls the size of data transfers requested across the pci bus when in master mode. it is a nine-bit register, with the two low-order bits forced to zero, i.e. values must be a multiple of four. the default value after hardware reset is 32 bytes or 8 doublewords. this can be modi?ed by a value in the eeprom/rom. dmburst cannot be set to zero; an attempt to write a zero is ignored. generally, the dmburst register should indicate a multiple of the pci cache line size register. care must be used with burst sizes of 4, 8, and 12 in 100mbps full duplex mode. the power management bit controls dynamic power management. the default value is 1, or enabled. testmode enables certain test features, such as the ability to read and write all of internal dma ram. the transmit and receive big endian bits support the transmission and reception of data which has been ordered for a big endian machine. note that only data (bytes in the areas pointed to by the buffer descriptors) are affected. control information, which includes registers, frame descriptors, and buffer descriptors, are always in native pci bus, or little endian format. the transmit wake up bit supports immediate transmission of data, rather than waiting for the current polling cycle to end. if set, and if the transmitter is polling, the cur- rent polling cycle will be terminated. this bit is cleared at the end of the current polling cycle. software interrupt is provided by the controller as a service for software drivers. 31 19 18 17 16 15 14 13 12 11 9 8 2 1 0 reserved intmask swintreq txwakeup rxbige txbige testmode powrmgmnt reserved dmburst 0 0 dmburst dma burst size size of data bursts requested in master mode. powrmgmnt power management enable dynamic power management. testmode test mode enable test mode functions. txbige transmit big endian if set, treat all transmit data as big endian. rxbige receive big endian if set, treat receive data as big endian. txwakeup transmit wake up w hen set, abort the current polling cycle and begin transmission. swintreq software interrupt request when set, cause an interrupt to be signalled. intmask interrupt mask when set, causes interrupt signals to be disabled. 44 toshiba corporation registers transmit frame pointer transmit frame pointer (txfrmptr) 04h software reset to value 0000_0001h. the transmit frame pointer register contains the address of the ?rst frame descriptor to transmit. after software reset, the eol bit is set. the system must set this register to a properly initialized frame descriptor to enable transmission, or poll- ing for packets to transmit. a valid address must be aligned to a 16 byte boundary, i.e. bits 0 to 3 must be zero. for a description of how polling is controlled, see section "transmit polling control register". transmit threshold control transmit threshold (txthrsh) 08h held in internal ram, so hardware and software reset have no effect. the transmit threshold register controls the buffer latency for transmitting pack- ets. if the threshold value is non-zero, then data transfer to the mac will begin as soon as the dma transmit fifo contains this number of bytes, or as soon as a com- plete packet is in the fifo. if the threshold value is zero, data transfer to the mac starts immediately. it is the responsibility of the s/w drivers to initialize this register. the value can be speci?ed in the eeprom/rom. if the threshold value is set too low, the dma transmit fifo may run dry due to pci bus latency. if this occurs, as indicated by the mac transmit status, system soft- ware should increase the txthold value. care should be taken not to set the threshold value greater than 1700. in long packet mode, this may cause buffer memory to ?ll without enabling transmission, causing the transmitter to hang. 31 4321 0 address 0 0 0 eol eol end of list if set, address is invalid for use by the controller. must wait for system to clear. 31 16 15 11 10 0 reserved reserved txthold toshiba corporation 45 registers transmit polling control register transmit polling counter (txpollctr) 0ch held in internal ram, so hardware and software reset have no effect. the transmit polling counter controls the frequency with which the controller polls for packets to transmit. an internal counter will be set to this value, and decre- ments to zero. when the register reaches zero, a read will be done to see if a new transmit packet has arrived. with a 33mhz clock, each unit in the polling counter is equivalent to 61.44 micro-seconds. the transmit polling counter is held in internal ram, so does not have a default value. it is the responsibility of the s/w drivers to initialize this register. the value can be speci?ed in the eeprom/rom, with soft- ware driver support. this register must be set to 1 or higher, if "hot chaining" of transmit buffers is used. buffer list frame pointer buffer list frame pointer (blfrmptr) 10h software reset to value 0000_001h. the buffer list frame pointer contains the address of the ?rst frame descriptor to read for acquiring free buffer descriptors. the system must set this register to a prop- erly initialized frame descriptor to enable reception. a valid address must be aligned to a 16 byte boundary, i.e. bits 0 to 3 must be zero. 31 16 15 12 11 0 reserved reserved txpollctr 31 4321 0 address 0 0 0 eol eol end of list if set, address is invalid for use by the controller. must wait for system to clear. 46 toshiba corporation registers receive fragment size register receive fragment size (rxfragsize) 14h hardware reset to value 0000_0000h. software reset has no effect. the receive fragment size register speci?es the smallest data fragment the con- troller will generate. the size must be a multiple of four, i.e. the two low order bits are always zero. packing can be enabled globally, using the enable packing bit, or on a per buffer area basis, as explained in chapter 5, page 65 in the section frame descriptor control field (fdctl). the controller always begins storing received data on a four-byte-aligned address. there may be one to three unused bytes at the end of a frame, due to alignment. when packing is enabled, the minfrag value must be greater than zero for the con- troller to work. it is the responsibility of s/w drivers to set the minimum fragment ?eld and the enpack bit if packing is desired. when packing is not enabled, the minfrag value must be left at zero. 31 16 15 14 12 11 2 1 0 reserved enpack reserved minfrag 0 0 minfrag minimum fragment minimum number of bytes to write into a partially ?lled buffer. enpack enable packing 1= use minfrag value to pack buffers. 0= use fdctl ?eld to control packing (default). toshiba corporation 47 registers interrupt enable register interrupt enable (int_en) 18h ... 7 6 5 4 3 2 1 0 ... earnoten dparerren ssyserren rmasabten rtargabten stargabten blexen fdaexen 31 12 11 10 9 8 ... reserved nrabten txctlcmpen dmparerren dparden ... fdaexen free descriptor area exhausted enable enable an interrupt if the free descriptor area becomes exhausted, i.e. if the controller encounters a block in the fda which is still owned by the system. blexen buffer list exhausted enable enable an interrupt if the buffer list becomes exhausted, i.e. if the controller encounters a descriptor in the bl which is still owned by the system. stargabten signalled target abort enable enable an interrupt if the controller signals a target abort while act- ing as a target. rtargabten received target abort enable enable an interrupt if the controller receives a target abort while act- ing as bus master. rmasabten received master abort enable enable an interrupt if the controller receives a master abort while acting as a target. ssyserren signalled system error enable enable an interrupt if the controller signals system error. dparerren detected parity error enable enable an interrupt if the controller detects a parity error on a pci bus data transfer during a master access. earnoten early notify enable enable an interrupt after writing the ?rst buffer and buffer descriptor of a packet. dparden data parity detected enable enable an interrupt if bit 8 of pci stat register is set. dmparerren dma parity error enable enable an interrupt if a parity error is detected in reading or writing the dma internal ram. txctlcmpen transmit control complete enable enable an interrupt when transmission of a mac control packet is complete nrabten non-recoverable abort enable enable an interrupt when there is an internal non- recoverable abort condition. 48 toshiba corporation registers hardware reset to value 0000_0000h. software reset has no effect. the interrupt enable register controls the generation of interrupts in response to errors and other conditions detected by the dma engine. the early notify enable bit supports applications which want to minimize latency. note that the frame descriptor will not be valid when the early notify is pro- cessed. only the ?rst buffer descriptor is valid when this interrupt is signalled. descriptor area registers free descriptor area base register (fda_bas) 1ch hardware reset to value 0000_0000h. software reset has no effect. the free descriptor area base register contains the starting address of the area reserved for the controller to write frame and buffer descriptors for received packets. the address must be a multiple of 16 bytes, i.e. bits 0, 1, 2, and 3 are zero. free descriptor area limit register (fda_lim) 20h hardware reset to value 0000_0000h. software reset has no effect. the free descriptor area limit register contains the count of the number of 16- byte blocks in the receive descriptor area, in bits 15:4. alternatively, the low 16 bits can be viewed as a byte offset from the base. each 16-byte block holds one frame descriptor, or two eight-byte buffer descrip- tors. so the maximum size of a single descriptor area is 4095*16 or 64k - 16 bytes. note: the fda_lim register must point to the lowest offset in the fda where a new frame descriptor can be safely begun. enough space must be allowed for a maximum size packet to have enough space for a max- imum number of buffer descriptors. 31 43210 address 0000 31 16 15 43210 reserved count/offset 0000 toshiba corporation 49 registers interrupt source register interrupt source (int_src) 24h w1/clr- indicates a bit that is cleared by writing 1 to the bit. writing 0 has no effect. ro- indicates a read only bit, which is cleared by clearing the condition which sets the bit, or by resetting the controller. software reset to value 0000_0000h. the interrupt source register is read by system software, to see if there is an interrupt associated with the ethernet controller. in addition, the register provides status bits for some conditions which are not reported elsewhere. 31 15 14 13 12 11 10 9 8 7 reserved nrabt dmparerrstat blex fdaex intnrabt inttxctlcmp intexbd dmparerr 654 3 2 1 0 intearnot swint intblex intfdaex intpci intmacrx intmactx intmactx interrupt reported in mac transmit status, tx_stat. w1/clr intmacrx interrupt reported in mac receive status, rx_stat. w1/clr intpci interrupt reported in pci controller, pci_stat r/o intfdaex interrupt caused by free descriptor area exhausted r/o intblex interrupt caused by buffer list exhausted r/o swint interrupt caused by software interrupt request r/o intearnot interrupt caused by early notify w1/clr dmparerr interrupt caused by dma parity error. r/o intexbd interrupt caused by excessive (more than 28) buffer descriptors. w1/clr inttx/ctlcmp interrupt caused by mac control packet completed. w1/clr intnrabt interrupt caused by non-recoverable abort state. r/o fdaex set if fda is exhausted. cleared by writing 1. w1/clr blex set if bl is exhausted. cleared by writing 1. w1/clr dmparerrstat set if dma parity error occurs. cleared by writing 1. w1/clr nrabt set if non-recoverable abort occurs. w1/clr 50 toshiba corporation registers if an interrupt is associated with the ethernet controller, all further interrupts from the ethernet controller can be masked with the intmask bit of the dma control register. if bits 10 through 0 are all zeroes, the controller did not generate the interrupt. low order bits are set if interrupts are generated and reported in other status registers. bit 8 is set if a single frame descriptor requires more than 28 buffer descrip- tors. bit 13 is set whenever a dma ram parity error is detected. bit 7 is set an interrupt is generated, only if the dparerren bit of the interrupt enable register is set. flow control registers pause control (pausecnt) 30h remote pause control (rempaucnt) 34h software reset to value 0000_0000h. the pause count register provides the current value of a received pause counter. a value of 0 indicates the mac is not paused. the remote pause count register pro- vides an approximate current value of the remote pause counter, based on when a pause command was sent. for both counters each unit is one slot time, or 512 bit times. 31 16 15 0 reserved count pausecnt received pause count count of slot times that transmitter is being paused, as the result of receiving a mac control pause operation packet. rempaucnt remote pause count count of slot times that remote mac is being paused, as the result of sending a pause operation packet. toshiba corporation 51 registers transmit control frame status (txctlfrmstat) 38h held in internal ram, so hardware and software reset have no effect. the transmit control frame status provides the status of sending a mac con- trol packet to a remote station via the sdpause bit of the transmit control register. when the transmission is complete, the software drivers may pick up the status from this register. software can reset this register by clearing it before initiating the trans- fer of a mac control frame. the txctlcmpen bit of the interrupt enable register provides for an option to generate an interrupt on completion of mac control packet transmission. mac layer registers mac control register mac control (mac_ctl) 40h 31 16 15 0 reserved txstat value 15 14 13 12 11 10 9 8 link10 - enmissroll - - missroll - - 765 4 3 2 1 0 loop10 conn macloop fulldup reset haltimm haltreq 52 toshiba corporation registers hardware reset to value 0000h. software reset is invoked by setting bit 2, reset. bit 2 is cleared after software reset is complete. other bits are not affected by software reset. software reset is delayed for three clock cycles, to allow normal completion of the operation which writes the reset bit. software can use the tx_ctl and rx_ctl registers to request halt after current network transactions are complete before using reset. the missed roll and link status 10 mb/s are read-only status bits. all others are control bits. the missed roll bit is set when the counter rolls over and cleared when s/w reads the missed count register, as described in section, "system error count register." some phys may not support full duplex. mac loopback overrides the full duplex bit. some 10 mb/s phys may interpret loop10 to control different functions, and signal link10 to indicate a different status condition. in automatic connect mode, activity in the form of receive clock and carrier sense on the 10 mb/s interface will select the 10 mb/s endec, otherwise the mii is selected. for some full duplex operating environments, the 10 mb/s 7-wire interface may require software con?guration via the connection mode bits. haltreq halt request stop transmission and reception after completion of any current packets. haltimm halt immediate stop transmission and reception immediately. reset software reset reset all ethernet controller state machines and fifos. fulldup full duplex allow transmission to begin while reception is occurring. macloop mac loopback cause transmission signals to be presented as input to the receive circuit without leaving the controller. conn connection mode select the connection mode. 00 = automatic, (default) 01 = force 10mbps endec 10 = force mii (rate determined by mii clock) loop10 loop 10 mbps if set, assert the loop_10 external signal to the 10mbps endec. missroll missed roll missed error counter rolled over. enmissroll enable missed roll interrupt when missed error counter rolls over. link10 link status 10mbits buffered signal on the link 10 pin. toshiba corporation 53 registers cam control register cam control (cam_ctl) 44h hardware reset to value 0000h. software reset has no effect. the three accept bits override cam rejections. to place the mac in promiscuous mode, accept packets with all three types of destination address: 1. station, which has an even ?rst byte, for example, 00-00-00-00-00-00, 2. multicast-group, which has an odd ?rst byte, but which is not ff-ff-ff-ff-ff- ff, for example, 01-00-00-00-00-00, 3. broadcast, de?ned to be ff-ff-ff-ff-ff-ff. when the cam compare mode is enabled, the cam memory is read for addresses to ?lter incoming messages. the cam memory is organized as entries of six bytes each, which can be individually enabled and disabled as described in sec- tion cam access registers, on page 59. an alternative way to place the mac in promiscuous mode is to set the nega- tive cam bit, but clear the compare enable bit. this way, the cam will fail to rec- ognize all packets, and in turn the mac will accept them. to reject all packets, clear all bits in cam_ctl. 15 5 4 3 2 1 0 reserved compen negcam broadacc groupacc stationacc stationacc station accept accept any packet with a unicast station address. groupacc group accept accept any packet with a multicast-group address. broadacc broadcast accept accept any packet with a broadcast address. negcam negative cam 0 = accept packets cam recognizes, reject others. 1 = reject packets cam recognizes, accept others. compen compare enable enable compare mode. 54 toshiba corporation registers transmit control and status registers transmit control (tx_ctl) 48h hardware reset to value 0000h. software reset clears the txen and does not affect others. *sdpause is automatically cleared upon completing the transmission of the mac control packet. writing 0 to this bit has no effect. to receive an interrupt after each packet, set the enable completion and all the mac error enable bits. interrupts may also be enabled only for speci?c conditions. sqe checking is automatic over the 7-wire interface. 15 14 13 12 11 10 9 - encomp entxpar enlatecoll enexcoll enlcarr enexdefer 87654 3 210 enunder mii10 sdpause noexdef fback nocrc nopad txhalt txen txen transmit enable if zero, stop transmission immediately. txhalt transmit halt request halt transmission after completing any current packet. nopad suppress padding do not generate pad bytes for packets with less than 64 bytes. nocrc suppress crc do not add the crc at the end of a packet. fback fast back-off use faster back-off timers for testing. noexdef no excessive defer suppress the checking of excessive deferral. sdpause* mii10 send pause mii 10 mb mode send a pause command, or other mac control frame. set by s/w to enable sqe checking in mii 10 mb mode. interrupt enable flags enunder enable underrun interrupt if the mac transmit fifo becomes empty during transmission. enexdefer enable excessive deferral interrupt if the mac defers for max_deferral time: = 0.24288 ms for 100mbps. = 2.4288 ms for 10mbps. enlcarr enable lost carrier interrupt if carrier sense is not detected or is dropped during the entire transmission of a packet. enexcoll enable excessive collision interrupt if 16 collisions occur in the same packet. enlatecoll enable late collision interrupt if a collision occurs after 512 bit times (64 byte times). entxpar enable transmit parity interrupt if the mac transmit fifo has a parity error. encomp enable completion interrupt when the mac transmits or discards one packet. toshiba corporation 55 registers transmit status (tx_stat) 4ch software reset to value 00_0000h. cleared at beginning of each packet transmitted. the transmission status ?ags are set whenever the corresponding event occurs. in addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set. the low order 5 bits can be read and masked as a single collision count, i.e when excoll is 1, txcoll is 0. if txcoll is non-zero, then excoll is 0. 16 15 14 13 12 11 10 9 sqerr txhalted comp txpar latecoll tx10stat lostcrs exdefer 8 7 5 4 3210 under inttx paused txdefer excoll txcoll txcoll transmit collision count count of the collisions in transmitting a single packet. if 16 collisions occur, txcoll will be zero, and excoll is set. excoll excessive collision set if 16 collisions occur in the same packet. transmission skipped. txdefer transmit deferred set if transmission of packet was deferred and no collisions occurred. paused transmitter paused set if transmission was paused after completion of the current packet. inttx interrupt on transmit set if transmission of packet caused an interrupt condition. this includes the encomp transmission complete condition, if enabled. transmission status flags under underrun mac transmit fifo becomes empty during transmission. exdefer excessive deferral mac defers for max_deferral: (two maximum size packets) = 0. 24288 ms for 100mbps. = 2. 4288 ms for 10mbps. lostcrs lost carrier sense carrier sense is not detected or is dropped during the entire transmission of a packet (from the sfd to the crc). tx10stat transmit 10mbps status = 1 if packet was transmitted via the 10mbps interface. = 0 if packet was transmitted via mii. latecoll late collision a collision occurs after 512 bit times (64 byte times). txpar transmit parity error mac transmit fifo has detected a parity error. comp completion mac transmits or discards one packet. txhalted transmission halted transmission was halted by clearing txen or setting txhalt. sqerr signal quality error no heart beat signal observed at end of transmission. 56 toshiba corporation registers receive control and status registers receive control (rx_ctl) 50h hardware reset to value 0000h. software reset clears rxen and does not affect other values. to receive an interrupt after each packet, set the good enable and all the error enable bits. interrupts may also be enabled only for speci?c conditions. * the frame lengths above do not include preamble and start frame delimiter (sfd). see chapter 6, page 69, in the section mac frame and packet formats, for more details. 15 14 13 12 11 10 9 8 - engood enrxpar - enlongerr enover encrcerr enalign 76 5 4 3 2 10 - ignorecrc passctl stripcrc shorten longen rxhalt rxen rxen receive enable if zero, stop reception immediately. rxhalt receive halt request halt reception after completing any current packet. longen long enable allow reception of frames longer than 1518 bytes. * shorten short enable allow reception of frames shorter than 64 bytes. * stripcrc strip crc value check the crc, but strip it from the message. passctl pass control packets enable passing of received mac control packets to system. ignorecrc ignore crc value do not check the crc. interrupt enable flags enalign enable alignment interrupt upon receipt of a packet whose length in bits is not a multi- ple of eight, and whose crc is invalid. encrcerr enable crc error interrupt upon receipt of a packet whose crc is invalid or, during its reception, the phy asserts rx_er. enover enable over?ow interrupt upon receipt of a packet when the mac receive fifo is full. enlongerr enable long error interrupt upon receipt of a frame longer than 1518 bytes,* unless the long enable bit is set. enrxpar enable receive parity interrupt if the mac receive fifo detects a parity error. engood enable good interrupt upon receipt of a packet with no errors. toshiba corporation 57 registers receive status (rx_stat) 54h software reset to value 0000h. cleared at the beginning of each packet received. * the frame lengths above do not include preamble and start frame delimiter (sfd). see chapter 6, page 69, in the section mac frame and packet formats, for more details. the receive status ?ags are set whenever the corresponding event occurs. once set, a ?ag stays set until another packet arrives. in addition, an interrupt is generated if the corresponding enable bit in the receive control register is set. ctlrecd is set if the packet type is 8808h and the cam recognizes the address. software is responsible for checking the pause operation code. software is responsible for separating alignment, crc, and frame too long errors, and reporting them correctly as management information. 15 14 13 12 11 10 9 rxhalted good rxpar - longerr over?ow crcerr 8 7 6 5 43210 alignerr rx10stat intrx ctlrecd reserved receive status flags ctlrecd control received set if packet received is a mac control frame. intrx interrupt on receive set if reception of packet caused an interrupt condition. this includes good received, if the engood bit is set. rx10stat r eceive 10mbits status = 1 if packet was received via the 10mibits interface. = 0 if packet was received via mii. alignerr alignment error frame length in bits was not a multiple of eight and the crc was invalid. crcerr crc error crc at end of packet did not match computed value, or the phy asserted rx_er during packet reception. over?ow over?ow error the mac receive fifo was full when it needed to store a received byte. longerr long error received a frame longer than 1518 bytes.* not set if the long enable bit in the receive control register is set. rxpar receive party error the mac receive fifo has detected a parity error. good good received successfully received a packet with no errors. if engood = 1, an inter- rupt is generated on each packet received successfully. rxhalted reception halted reception interrupted by user clearing rxen or setting rxhalt. 58 toshiba corporation registers station management data access registers station management data register (md_data) 58h software reset to value 0000h. the mii section of the ieee 802.3 standard for 100-base-t, 100mbps ether- net, referenced in chapter 1, reference documents, de?nes the format of the sta- tion management data registers. see speci?c phy data sheets for additional hardware dependent registers. station management data control and address (md_ca) 5ch software reset to value 0000h. before attempting to access the phy control registers, software should read the md_ca register to ensure the busy bit is not set. the contoller provides support for reading and writing of station management data to the phy. setting of options in station management registers does not affect the controller. some phys may not support the option to suppress preambles after the ?rst operation. 15 0 station management data 15 14 13 12 11 10 9876543210 reserved presup busy wr phy addr addr address address inside the phy of register to read or write. phy phy address address of phy device to read or write. wr write set for write, clear for read. busy busy bit set to begin operation; controller clears when operation completes. presup preamble suppress if set, the preamble is not sent to the phy. toshiba corporation 59 registers cam access registers cam address (cam_adr) 60h software reset to value 0000h. in normal operation, the cam_adr and cam data registers can read or write the cam contents, including two double word locations immediately after the cam for flow control operation, as shown in figure 6-3. writing to other memory loca- tions in normal operation has no effect. when the testmode bit of the dma control register is set, the cam_adr can be used to read or write the entire dma_ram. cam data (cam_data) 64h four bytes are accessed each time there is a read or write of the cam address regis- ter, i.e. the pci byte enables are ignored. system software must take care to perform read, modify, and write logic when modifying only 2 bytes of a 4-byte word. the cam data register has a copy of the data stored at the cam bytes addressed by the cam address register. the register may be read more than once. when data is written to this register, the addressed cam bytes are changed. note: unlike data transferred in master mode, data transferred via this cam interface is always interpreted internally as big endian. 1514131211109876543210 reserved cam_loc 0 0 cam_loc cam address the address of the four-byte cam location to read or write. 31 24 23 16 15 8 7 0 cam_data[0] cam_data[1] cam_data[2] cam_data[3] 60 toshiba corporation registers cam enable (cam_ena) 68h hardware reset to value 00_0000h. software reset has no effect. the cam enable register indicates which entries are valid for address ?ltering. up to 21 entries, numbered 0 through 20, may be active. prom control registers the prom control register provides control and status information and buffering for the prom controller, which controls the reading and writing of an optional external eeprom or small serial rom device. prom control (prom_ctl) 6ch software reset to value 0000h. before attempting to access the eeprom/rom memory, software should read the prom_ctl register to ensure that the busy bit is not set. 31 21 20 0 reserved cam_ena 15 14 13 12 6 5 0 busy opcode reserved prom_addr busy busy bit set to begin operation. will be cleared by the serial driver when operation is complete. opcode operation code 1 0=read 0 1=write. 0 0=enable or disable writing, as speci?ed in prom_addr. [5:4] = 11, enable [5:4] = 00, disable 1 1=erase prom_addr address allows addressing of up to 64 16-bit entries. toshiba corporation 61 registers prom data (prom_data) 70h software reset to value 0000h. the prom data registers provides the 16 bits of data written to or read from prom. the current implementation supports the following devices: ? microchip 93lc46b ? national nm93c46. upon hardware reset, the subsystem vendor id register, and subsystem id register are loaded from the ?rst two locations in the eeprom or rom. software drivers are responsible for reading the station address, storing in the cam, and enabling cam operation, as part of driver intitialization. when the pci bus operates at 33mhz, the eeprom or rom is clocked at 1mhz. system error count registers missed error count (miss_cnt) 7ch hardware reset to value 0000_0000h. software reset has no effect. cleared when read. the missed error count register provides a count of packets discarded due to var- ious types of errors. together with status information for packets transmitted and received, this counter provides the information needed for station management. reading the missed error count register clears the register. it is then the responsi- bility of the system to maintain a global count with more bits of precision. the missed error counter rolling over from 0x7fff to 0x8000 sets the missed 15 0 prom_data 31 16 15 0 reserved miss_cnt miss_cnt missed error count counts the number of valid packets which are rejected by the mac unit because the mac receive fifo over?ows, a parity error occurs, or the receive enable bit (rx_en) is cleared. this count excludes packets the cam rejects. 62 toshiba corporation registers roll bit in the mac control register. it also generates an interrupt if the enable missed roll bit is set. if station management software wants more frequent interrupts, the missed error count register can be set to a value closer to the roll over value of 0x7fff. for exam- ple, setting the register to 0x7f00 would provide for an interrupt after counting 256 occurrences. locations 0x74 and 0x78 are reversed to maintain software compatibility with earlier controller designs. toshiba toshiba corporation 63 TC35815CF flow control 10/100mbps ethernet controller chapter 5 - memory organization this chapter describes the data structures used by the pci-based 100/10mbps ethernet controller to communicate with the host system. these structures are located in system memory. there are three types of basic data structures: 1. frame descriptors 2. buffer descriptors 3. data buffers these data structures are used in three ways: 1. transmit queue - a list of frame descriptors for packets to transmit. 2. receive queue - a list of frame descriptors for packets that have been received. 3. buffer list - a list of frame descriptors with unused buffers for receiving data. the general organization of each of these was shown in figure 1-4 on page 6. each section of this chapter describes one of the basic data structures. some data structures contain different information when they are used in different queues, which is described in sub-sections. in continuous polling operation, a queue does not become empty once it is active. there is always a dummy frame descriptor at the end of the list, which belongs to the producer of new descriptors. for a detailed explanation, see chapter 7, dma operation. to begin transmission, the system stores into the transmit frame pointer regis- ter the address of the ?rst frame descriptor in the transmit queue. the controller traverses the transmit queue, updating the status of transmitted packets. transmis- sion complete is indicated in the frame descriptor status ?eld and in the ownership bit of the frame descriptor control ?eld. this allows the queue to be processed by system software after transmission, e.g. to free buffers. the controller acquires buffers from the buffer list, and writes new frame descriptors and new buffer descriptors into the free descriptor area, as described in chapter 7, dma operation. frame descriptors each frame descriptor has a pointer to the next frame descriptor in the queue, a sys- tem data ?eld, a length ?eld, and control and status ?elds. table 5-1 shows the lay- out of a frame descriptor. 64 toshiba corporation memory organization the controller will preserve the contents of the frame system data ?eld, fdsys- tem. this ?eld may be used by either the system or the application programs. the ini- tial value for frame descriptors written on the receive queue is obtained from the current buffer list frame descriptor. each queue makes slightly different use of the fdnext, fdctl, fdstat, and fdlength ?elds, as explained below. next frame descriptor field (fdnext) the next frame descriptor ?eld containers either an end-of-list (eol) ?ag, or a pointer to the next frame descriptor in the same queue. frame descriptors must be aligned to 16-byte boundaries, i.e. a valid pointer must have bits 0-3 set to zero. on all the queues, the next frame descriptor ?eld is used to stop the consumer of the list, by setting the eol bit. the consumer must wait for the producer of the list to clear the eol bit, when it stores a valid pointer. on the buffer list queue, it is possi- ble to chain from one buffer pool to another using the next frame descriptor ?eld. if table 5-1 frame descriptor format byte 3 byte 2 byte 1 byte 0 offset fdnext 00 fdsystem 04 reserved fdstat 08 fdctl fdlength 0c fdnext next frame descriptor address of next frame descriptor in this queue. fdsystem frame system data for use by the system or application software. fdstat frame descriptor status status ?eld for this frame descriptor. fdctl frame descriptor control control ?eld for this frame descriptor. fdlength frame length length ?eld for this frame. 31 4321 0 pointer 0 0 0 eol pointer 28-bit pointer field if eol=0, contains upper 28 bits of address of the next frame descriptor in this queue. eol end-of-list flag =0. pointer is valid. =1. end of list. must wait for ?ag to clear. toshiba corporation 65 memory organization chaining of buffer lists is not used, the software drivers should set the fdnext ?eld to contain its own address. this would cause the controller to re-examine the same buffer area for re-use. alternatively, the eol bit can be set, causing the controller to stop. frame descriptor system field (fdsystem) the fdsystem ?eld is a 32-bit ?eld which is reserved for system software use. it could be a pointer to a table of information, a pointer to c++ virtual functions, etc. on the transmit queue, the fdsystem ?eld is not used. on the receive queue, the controller will copy the contents of the fdsystem ?eld from the current buffer list queue, where the ?rst buffer descriptor was allocated. frame descriptor status field (fdstat) on the transmit and receive queues, the fdstat ?eld is used for reporting transmis- sion and reception completion status. for a description of the status bits, see the tx_stat and rx_stat registers in chapter 4, page 47 in section mac layer regis- ters. on the receive buffer list, the fdstat ?eld is not used. frame descriptor length field (fdlength) on the transmit queue, the fdlength ?eld is not used. on the receive queue, the controller sets the fdlength ?eld to the total length of the packet. on the buffer list queue, the fdlength ?eld is used to count the number of free buffer descriptors allocated to the queue. the controller accesses the buffer list frame descriptor via the buffer list frame pointer register. if the controller encounters a buffer it does not own, it will set the bl_ex bit in the interrupt source register and wait for the system to clear it. the controller will read the buffer descriptors, using the fdlength ?eld as a limit. when the controller nears the end of the list, it will fetch the next frame descriptor pointed to by the fdnext ?eld as described in chapter 4, page 45 in section descriptor area registers. frame descriptor control field (fdctl) the table below shows the abbreviation, ?eld name, description, and usage of the fdctl ?eld. 66 toshiba corporation memory organization the ownership ?eld is used in the transmit and receive queues to synchronize processing by the controller and the system. frame options are used in the transmit queue and the buffer list. the buffer descriptor count ?eld is only used in the transmit and recieve queues. (the buffer list uses the length ?eld as a count ?eld to allow larger buffer pools). if an attempt is made to use more than 28 buffer descriptors for a single received packet, then an excess buffer descriptor error is generated. the transmit queue uses the frame options ?eld to set transmit characteristics for individual packets: ? 10000 = big endian byte ordering. ? 01000 = interrupt after transmitting. ? 00100 = no crc appended. ? 00010 = no pad bytes, if short frame. these bits can be combined to ask for combinations of characteristics. for example, 01110 would mean: little endian, interrupt after transmission, do not append crc, and do not pad a short packet. per packet big endian controls can be useful in a hub application, where packets are received for transmission from a mixture of big and little endian sources. for computer applications, it is easier to use the global big endian control bit described in chapter 4, page 43, in the section dma control. the receive buffer list queue uses the frame options ?eld to control packing and little or big endian data order, providing that the global enable bit described in chapter 4, page 46 in section receive fragment size register, has not been set: ? 10000 = big endian byte ordering. ? 00001 = enable buffer packing for the buffers in this frame, ignore the global enable bit. if packing is enabled, the rxfragsize register controls the the packing algorithm. 15 141312111098765 43210 cownsfd frmopt reserved bdcount symbol name description used by cownsfd controller owns frame descriptor =1. the controller owns the frame descrip- tor, after the system sets cownsfd. =0. the system owns the frame descriptor, after the controller clears cownsfd. tx, rx frmopt frame options per frame control options. see below. tx,bl bdcount buffer descriptor count number of bds allocated. (0 to 29) tx,rx toshiba corporation 67 memory organization buffer descriptors each buffer descriptor has a pointer to the data buffer, control and status bytes, and a two-byte length ?eld. table 5-2 shows the layout of a buffer descriptor. when buffers are on the buffer list queue, the buffdata ?eld points to the begin- ning of the buffer, and the bufflength ?eld re?ects the allocated size of the unused buffer. when buffers are in use on the transmit and receive queues, the buffdata ?eld points to the beginning of data, and the bufflength ?eld re?ects the length of the data. it is the responsibility of the system software to set the length ?eld to the allo- cated size, when buffers are placed in the buffer list queue. as with frame descriptors, each queue makes slightly different use of the bdctl and bdstat ?elds, as explained below. buffer descriptor control (bdctl) on the transmit queue, the bdctl ?eld is not used. on the receive queue, the bdctl ?eld holds the number of buffer descriptors pointing into a single buffer area. the ?rst buffer descriptor in the frame is numbered 0, the next 1, etc. table 5-2 buffer descriptor format byte 3 byte 2 byte 1 byte 0 offset buffdata 00 bdctl bdstat bufflength 04 buffdata buffer data pointer 32-bit address of storage for bytes of data. bdctl buffer descriptor control control for this buffer descriptor. bdstat buffer descriptor status status for this buffer descriptor. bufflength buffer length length ?eld for this buffer descriptor. 68 toshiba corporation memory organization on the free buffer list, the bdctl ?eld is used to record ownership of the buffer. this allows synchronizing allocation and freeing of buffer descriptors, to ensure that the controller will not wrap around and begin reusing buffers before the system can empty them. buffer descriptor status field (bdstat) on the transmit queue, the bdstat ?eld is not used by the controller. on the receive queue, the bdstat ?eld is used as a buffer id, which is copied from the free buffer queue. on the free buffer queue the bdstat ?eld is used to pass the buffer descriptor id number to the controller. note: buffer ids can only be unique if there are at most 256 buffers in a single buffer pool. 7 6543210 cownsbd rxbdseqn cownsbd controller owns buffer descriptor =1. controller owns the buffer descriptor. when the sys- tem sets cownsbd, the buffer is free for reception. =0. system owns the buffer descriptor. when the control- ler clears cownsbd, the buffer has been ?lled. rxbdseqn receive buffer descriptor sequence number after reception: the sequence number for this buffer within the current buffer area. 7 0 rxbdid rxbdid receive buffer descriptor id the buffer id value. toshiba toshiba corporation 69 TC35815CF flow control 10/100mbps ethernet controller chapter 6 - mac operation this chapter gives detailed information about the following aspects of mac operation: 1. mac frame and packet formats 2. destination address formats 3. initialization 4. mac register access 5. transmitting a frame 6. receiving a frame 7. cam operation 8. full duplex pause operation 9. error signaling and network management 10. accessing station management data 11. accessing an eeprom or rom. mac frame and packet formats table 6-1 shows the format of an ieee 802.3/ethernet frame. the standard packet has the following ?elds: table 6-1 fields of an ieee 802.3/ethernet packet (frame) packet (encoded on the medium) added by transmitter, stripped by receiver data frame (sent by user) added by transmitter data frame (delivered to user) optionally stripped by receiver preamble s f d destination address source address length or type llc data pad bytes cyclic redundancy check(crc) 7 bytes 1 6 bytes 6 bytes 2 0-1500 0-46 4 bytes high low ... . . . msb lsb 70 toshiba corporation mac operation 1. preambleCseven identical bytes. the bits in each byte are 10101010, transmitted from left to right. 2. start frame delimiter (sfd)Cone byte. the bits are 10101011, transmitted from left to right. 3. destination addressCsix bytes. may be an individual or a multicast (including broadcast) address. 4. source addressCsix bytes. mac does not interpret the bytes. however, to be a valid station address, the ?rst bit transmitted, the lsb of the ?rst byte, should be set to 0. 5. length or typeCtwo bytes. the mac only recognizes the special value of 8808h as the mac control frame type. other values are not processed. the current ieee 802.3 standard speci?es that values less than 1500 are lengths and values greater that 1535 are types. values less that or equal to 1500 indicate the number of the logical link control (llc) data bytes in the data ?eld, in bytes. the mac transmits the high-order byte of the length or type field ?rst. 6. logical link control (llc) dataC46 to 1500 bytes (including pad). 7. padC0 to 46 bytes. if the llc data is less than 46 bytes long, the mac will transmit pad bytes of zeroes. 8. cyclic redundancy check (crc)Cfour bytes. a value computed as a function of all ?elds except the preamble, the sfd, and the crc itself. the ieee 802.3 standard also refers to the crc as the frame check sequence (fcs). the preamble, sfd, pad data, and crc are added by the transmitter. padding can also be done in software, and there is a transmit control bit to suppress crc addition. the receive control register has a bit to control stripping the crc. stripping of pad data is the responsibility of the software drivers. the mac transmits the least signi?cant bit of each byte ?rst for all ?elds except the crc. throughout this document, we attempt to use packet to denote all of the bytes transmitted and received, while frame refers to the bytes delivered by the user for trans- mission, and to the user who is receiving. there are a number of factors and options which can affect this standard mac frame: ? some phys may deliver a longer or shorter preamble. ? short packet mode allows llc data fields with less than 46 bytes. there are options to suppress padding and allow reception of short packets. ? long packet mode allows llc data fields with more than 1500 bytes. there is an option to allow reception of long packets. ? no crc mode suppresses the appending of an crc field. ? ignore crc mode allows the reception of packets without valid crc fields. ? pad bytes are counted in the length field as part of the llc data. toshiba corporation 71 mac operation destination address format bit 0 of the destination address is an address type designation bit. it identi?es the address as either an individual or a group address. group addresses are also called multicast addresses. individual addresses are also called unicast addresses. the broadcast address is a special group address, namely ff-ff-ff-ff-ff-ff in hex. there is a special group address used in connection with the full duplex pause operation: 01-80-c2-01-00-01. bit 1 distinguishes between locally or globally administered addresses. for glo- bally administered (or u, universal) addresses, the bit is set to 0. if an address is to be assigned locally, this bit is set to 1. for the broadcast address, this bit is also a 1. destination address, ?rst byte: special flow control destination address the current speci?cation for full duplex flow control speci?es a special destination address for the pause operation packet. in order for the mac to receive packets which contain this special destination address, the address must be programmed into one of the cam entries, that cam entry must be enabled, and the cam must be activated. some cam entries are used when generating a flow control packet via the sdpause bit in the transmit control register, as explained later in this chapter. initialization on power up and reset, the mac control and status registers are set as described in chapter 4, registers. refer to the veri?cation test suite and software application notes for more details about order of initialization, and functional dependencies. transmit collision count, cam data, and eeprom/rom buffer registers are not set on power up or reset. the transmit collision count register is reset at the beginning of transmitting a new packet. the cam memory should be initialized before enabling usage of the cam. 76543210 rest u/l i/g i/g individual or group flag =0 individual address. =1 group address. u/l universal or local flag =0 universal address. =1 local address. rest rest of byte rest of ?rst byte of destination address. 72 toshiba corporation mac operation mac register access mac register access is controlled by the pci bus interface. for more information on register access, including mac command and status registers, see chapter 7, dma operation. special register clear operations the missed packet error count register is cleared on read. this ensures synchroniza- tion with software drivers which accumulate a total count. the transmit and receive status registers are cleared at the beginning of the next packet. for this reason, the values read from the register interface may not be stable. the value of these registers is stored in the fdstatus ?eld of the frame descriptor in memory, for each packet transmitted or received, and software should examine the status values found in system data structures. transmitting a frame 1. to transmit a frame, the transmit enable bit in the transmit control register must be set and the transmit halt request bit must be zero. in addition, the halt immediate and halt request bits in the mac control register must be cleared. these conditions are normally set after dma controller initialization has occurred, such as storing a valid frame descriptor address in the transmit frame pointer register. the mac will then signal the dma engine to transfer bytes to the mac transmit fifo. the dma transmit controller then controls the transfer of bytes to the mac transmit fifo. 2. the mac transmit block will start transmitting the data in the fifo, but will retain the ?rst 64 bytes until it has acquired the net. at that time, the mac transmit block will request more data and transmit it until the dma transmit controller signals the end of data to be transmitted. the mac transmit block generates pad bytes, if needed, appends the calculated crc to the end of the packet, and transmission ends. it sets the completion bit in the transmit status register, signaling the end of a transmission, which may in turn cause an interrupt. 3. transmission of data across the mii interface is driven by either a 25 or 2.5mhz mii transmit clock, tx_clk. transmission across the 10mbits endec is driven by a 10mhz transmit clock, txc_10. 4. the mac transmit block does not begin transmission onto the net until there are eight bytes of data in the mac transmit fifo. since the ?rst eight bytes transmitted are the preamble and the start frame delimiter, this gives an initial 16 byte times for dma latency. the dma transmit block does not begin transferring data to the mac transmit fifo, until either the entire toshiba corporation 73 mac operation packet is in the dma ram buffer, or the number of bytes in the dma ram buffer exceeds the dma transmit threshold register. if transmit underrun errors occur, the problem can be corrected by setting the dma transmit threshold register to a higher value. 5. the mac transmit block will check the parity. if there is a parity error, the mac transmit block resets the fifo, and sets the mac parity error bit in the transmit status register. the ieee 802.3 csma/cd mac-layer protocols ? the mac transmit block consists of three state machines. the main transmit state machine implements the mac-layer protocols, and controls the other two. the gap state machine tracks and counts the inter-packet gap timing between packets. and the back-off state machine implements the backoff and retry algorithm of the 802.3 csma/cd protocol. ? in half-duplex mode, the gap state machine is responsible for counting the 96 bit times from the deassertion of the carrier sense signal, which is the inter-record gap. it breaks the 96 bit times for the inter-record gap into the first 64 bits, and the last 32 bits, in order to precisely control the appropriate times for beginning trans- mission. if there is any traffic within the first 64-bit times, it resets the counter and resumes counting from zero. if there is any traffic within the last 32 bits, it contin- ues counting and signals the end at 96 bit times. ? in full-duplex mode, the gap state machine starts counting at the end of transmis- sion and signals the end at 96 bit times. ? if the main transmit state machine detects a collision, it starts the back-off state machine counters and waits for the end of the back-off slot, before retransmitting the collision-causing packet again. each time there is a collision for the same packet, the back-off state machine increments an internal attempt counter. an 11- bit pseudo-random-number generator outputs a random number by selecting a subset of the value of the generator. the subset grows by one bit for each subse- quent attempt. this implements the equation: 0 < r < 2 k k = min( n , 10) where r is the number of slot times that the mac has to wait in case of a collision, and n is the number of attempts. for example, after the ?rst collision, n is 1 and r is a random number between 0 and 1. the pseudo-random-number generator in this case is one-bit wide and gives a random number of either 0 or 1. after the sec- ond attempt, r is a random number between 0 and 3; the state machine looks at the two least signi?cant bits of the generator ( n = 2) which gives a value between 0 and 3. ? in order to improve the statistical independence between two macs using the same pseudo-random number generator, the mac uses values from the crc of previous successfully transmitted packets to modify the basic random number sequence. 74 toshiba corporation mac operation the mii transmit operation ? if there is data to be transferred, the inter-packet gap is ok, and the mii is ready (there are no collisions, and either in full-duplex mode or there is no crs), then the mac transmit block transmits the preamble followed by the sfd. after the transmission of the preamble and the sfd, it transmits 64 bytes of data regardless of the packet length, unless short transmission is enabled. this means that if the packet is less than 64 bytes, it will pad the llc data field with zeroes. at the end of the packet, it appends the crc, if crc generation is enabled. if there is any collision during this first 64 bytes (8 bytes of preamble and sfd and 56 bytes of the frame), it stops the transmission and transmits a jam pattern (32 bits of all ones). it increments the collision attempt counter, returns control to the back-off state machine , and retransmits the packet when the backoff time has elapsed and the gap time is ok. ? if there are no collisions, the mac transmit block transmits the rest of the packet, and at this time (after the first 64 bytes have been transmitted without collisions), it allows the dma engine to overwrite this packet. after transmit- ting the first 64 bytes, it transmits the rest of the packet and appends the crc to the end. fifo underrun or more than 16 collisions will cause the state machine to abort the packet (no retry) and prepare for the next packet in the queue. ? in case of any transmission errors, the mac transmit block sets the appropri- ate error bit in the transmit status register, and it may generate an interrupt, depending on the transmit control register. ? figures 6-1 and 6-2 show the timing relationships among mii signals. figure 6-1 transmission without collision l/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/ ll/hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh?hhhhhhhhhhhh\lllllllllllll xxxxspssxssrssxssessxssassxssmssxssbssxsslssxssessxss?sxsssxsssxsssxxxxxxxxxxxxx llllll///hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh?hhhhhhhhhhhhh\\\lllllllllll gllllllllllllllllllllllllllllllllllllllllllllllllllll?lllllllllllllllllllllllllll tx_clk tx_en txd[3:0] crs col toshiba corporation 75 mac operation figure 6-2 transmission with collision in preamble receiving a frame 1. to receive a frame, the receive enable bit in the receive control register must be set and the receive halt request bit must be zero. in addition, the halt immediate and halt request bits in the mac control register must be cleared. these conditions are normally set after dma controller initialization has occurred, such as storing a valid address into the buffer list frame pointer register, and initializing the free descriptor area base and registers. the dma receive controller then controls the transfer of bytes from the mac receive fifo. for more information on initializing the data structures to enable reception, see section receiving a frame in chapter 7. 2. the mac receive block, when enabled, constantly monitors a data stream coming from either the mii or the optional external 10mbits endec. if the mac is in loopback mode, the data stream will be coming from the mac transmit block via the mii or 10mbits endec lines. 3. the mac receive block receives zero to seven bytes of preamble, followed by the start frame delimiter (sfd). the mac receive block waits for the sfd pattern before receiving the packet. 4. the ?rst nibble of destination address follows the sfd. when it has received a byte, the mac receive block generates parity, stores the byte with its parity in the mac receive fifo, and signals that data is present. it combines subsequent nibbles into bytes and stores them in the fifo. the dma receive controller reads bytes from the mac receive fifo, checks parity, and moves the data into the dma receive fifo. when the mac receive fifo becomes empty, or when it drives out the last byte of a packet, the mac receive block signals these conditions. 5. if, during frame reception, the phy asserts both rx_dv and rx_er, the mac receive block reports a crc error for the current packet. l/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/hh\ll/ ll/hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh\llll xxxsp1ssxsp2ssxsp3ssxsp4ssxsp5ssxsp6ssxsp7ssxsp8ssxsj1ssxsj2ssxsj3sxsj4ssxxxxxxx llllll///hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh\\\ll gllllllllllllllllllllfsssss/sssss/ tx_clk tx_en txd[3:0] crs col 76 toshiba corporation mac operation 6. after the mac receive block receives the destination address, the cam block attempts to recognize it. if the cam block rejects the packet, the mac receive block signals this condition and the dma receive block discards the data packet. cam operation to read or write the cam, system software should ?rst set the cam address register, then read or write the cam data register. all bytes are written, without regard to par- tial word enables. when writing the upper or lower two bytes of a double word, it is the responsibility of the driver software to correctly write the adjacent two byte ?eld, as well. the controller does not support read/modify/write cycles to its internal dma ram. figure 6-3 shows how the mac reads cam entries from the cam memory. entries are assumed to be in big endian order: #0-0 is the ?rst byte of the ?rst entry, #0-5 is the sixth and last byte of the ?rst entry, and so on. there are two bytes after cam entry #20, rsv-2 and rsv-3, and two double words. mc#1 and mc#2, which are not used in cam operation, but are used in generating mac control frames, as explained in the next section entitled full duplex pause operation. figure 6-3 cam memory map 00 04 08 0c 10 14 20 ... 6c 1c 18 70 74 78 7c #0-3 #0-0 #0-1 #0-2 #1-1 #0-4 #0-5 #1-0 #1-5 #1-2 #1-3 #1-4 byte 0 byte 1 byte 2 byte 3 #2-3 #2-0 #2-1 #2-2 #3-1 #2-4 #2-5 #3-0 #3-5 #3-2 #3-3 #3-4 #4-3 #4-0 #4-1 #4-2 #5-1 #4-4 #4-5 #5-0 #5-5 #5-2 #5-3 #5-4 #18-3 #18-0 #18-1 #18-2 #19-1 #18-4 #18-5 #19-0 #19-5 #19-2 #19-3 #19-4 #20-3 #20-0 #20-1 #20-2 rsv-3 #20-4 #20-5 rsv-2 80 84 mc#1-3 mc#1-0 mc#1-1 mc#1-2 mc#2-3 mc#2-0 mc#2-1 mc#2-2 mc#3-3 mc#3-0 mc#3-1 mc#3-2 88 toshiba corporation 77 mac operation full duplex pause operation transmit pause operation to enable full duplex pause operation, the special broadcast address for mac control packets must be programmed into the cam, and the corresponding cam enable bit set. while this can be any cam location, the next section will specify how some cam locations may be preferred, to optimize cam entry utilization. the mac receive circuit recognizes the full duplex pause operation when the following conditions are met: ? the type/length field has the special value for mac control packets, 0x8808. ? the packet is recognized by the cam. ? the length of the packet is 64 bytes. ? the operation field specifies pause operation. when a full duplex pause operation is recognized, the mac receive circuit loads the operand value into the pause count register, and signals both the mac dma engine that pause should begin at the end of the current packet, if any. the pause circuit maintains the pause counter, and decrements it to zero, before signalling the end of the pause operation, and allowing the dma transmit circuit to resume. if a second full duplex pause operation is recognized while the ?rst operation is in effect, the pause counter is reset with the current operand value. note that a value of 0 may cause premature termination of a pause operation in progress. remote pause operation the toshiba TC35815CF flow control 10/100mbps ethernet stand-alone mac sup- ports full programmability of the mac control frames to support both pause oper- ation and future uses of mac control. to send a remote pause operation or other mac control frame the following steps need to be taken: ? program cam location #0 with the destination address. ? program cam location #1 with the source address. ? program cam location #20 with the mac control type field, pause opera- tion opcode, and operand value. the two reserved bytes after cam location #20 should be written with 0000h. ? program the two double word locations mc#1 and mc#2, with 0000_0000h. ? write the transmit control register, setting the sdpause bit. the destination address and source address are normally the special broadcast address for mac control frames and the local station address, respectively. these cam entries can be enabled for use in address ?ltering. cam entry #20 should not be enabled, when used as part of flow control transmission. 78 toshiba corporation mac operation upon completion, the transmit status is written to the transmit control frame status register. the dma engine generates an interrupt if the transmit control com- plete enable bit (10) of the interrupt enable control register is set. error signaling the error and abnormal operation ?ags set by the mac are arranged into transmit and receive groups, and can be found in either the transmit status register (tx_stat) or the receive status register (rx_stat). in addition, the missed packet register counts packets missed for system network management purposes. please refer to chapter 4, regis- ters, for the formats of the ?ags and counters. reporting of errors in transmit transmit operation terminates when the entire packet (preamble, sfd, data, and crc) has been successfully transmitted to the physical medium without encountering a collision. in addition, the mac transmit block detects and reports both internal and network errors. under the following conditions, transmission will be aborted and a status bit will be set. many of the bits that are set can also generate interrupts, if the corresponding interrupt enable bit has been set in the transmit control register. toshiba corporation 79 mac operation mac transmit parity error a parity bit protects data coming from the dma transmit controller via the dii into the mac transmit fifo. a parity error sets the txparerr bit of the transmit status register and generates an interrupt, if interrupt is enabled. mac transmit fifo underrun the 80-byte mac transmit fifo is capable of handling a worst case dma latency of 1.28 m s (128 bit times, or 16 byte times), because 64 bytes are retained for possible retransmission after a collision. a mac transmit fifo underrun indicates a pci bus latency problem, since the dma transmit controller has more than enough bandwidth to keep up. such an underrun sets the underrun bit in the transmit status register. lost carrier carrier sense (crs) is monitored from the beginning of the start frame delimiter (sfd) to the last byte transmitted. a lost-carrier condition indicates that crs was never present or was dropped during transmission (a possible network problem), but transmission is not aborted. during loopback mode, tx_en drives crs. during full-duplex operation, crs is not passed to the transmit block, and lost carrier will not be asserted. lost carrier sets the lostcrs bit in the transmit status register. excessive collision whenever the mac encounters a collision during transmit, it will back off, update the col- lision counter, and try again later. when the counter equals 16 (16 attempts all resulted in a collision) transmission is aborted. excessive collisions probably indicate a network problem. excessive collision sets the excoll bit in the transmit status register. late collision (transmit out-of-window collision) in a correctly operating network, the controller sees a collision (if there is one) within the ?rst 64 bytes of data being transmitted. if a collision occurs after this time a possible net- work problem is detected. late collision sets the latecoll bit in the transmit status register, and transmission of the packet is aborted. signal quality error (sqe) in 10 mb/s mode, the mac checks for a heartbeat at the end of a transmitted packet. this is a short collision signal within the ?rst 40 bit times after end of transmission. signal quality error sets the sqerr bit in the transmit status register. deferral during an attempt to send a packet, the mac may have to defer the transmission because of the pre-occupied network. this is not an error, but is used as a network activity indicator, but only when collisions do not occur. deferral sets the txdeferred bit of the transmit status register. excessive deferral during the ?rst attempt of sending a packet, the mac may have to defer the transmis- sion because of pre-occupied network. if the deferral time is longer than two maximum sized packets (2.4288ms for either of the 10mbits operation modes or 0.24288ms for the 100mbits operation mode) transmission is aborted if excessive deferral is enabled. excessive deferral indicates a possible network problem. excessive deferral sets the exdefer bit of the transmit status register. paused during an attempt to send a packet, the mac may have to defer the transmission because the transmitter has been paused by the reception of mac control packet continuing a pause operation. this is not an error, but is used as a network activity indicator. to assist software in marking packets which experience a pause, the paused bit is set on the last packet before a pause will take effect. 80 toshiba corporation mac operation reporting of errors in receive the mac receive block starts putting received data from the physical medium into the mac receive fifo after detecting the start frame delimiter (sfd). it also checks for mac receive fifo over?ow during reception. at the end of reception, the mac receive block looks for external errors (alignment, length, crc, and frame too long). mac receive parity error a parity bit protects data once it enters the mac receive fifo. a parity error sets the rxparerr bit of the receive status register and generates an interrupt, if interrupt is enabled. alignment error at the end of reception, the mac receive block checks that the incoming packet has been correctly framed on an 8-bit boundary. if it is not, and the crc is invalid, data has been disrupted through the network, and the mac receive block reports an align- ment error. a crc error is also reported. the alignerr bit and the crcerr bits are set in the receive status register. crc error at the end of reception, the mac receive block checks the crc for validity, and reports a crc error if it is invalid. crc, frame alignment, and long errors are the network errors detected by the receive unit. they might be detected in the following combinations. C crc error only. C frame alignment and crc errors only. C long and crc errors only. C frame alignment, long, and crc errors. over?ow error during reception, the incoming data are put into the mac receive fifo before they are transferred to the dma receive controller. if the mac receive fifo ?lls up because of excessive system latency or other reasons, the mac receive block rejects the received packet and sets the over?ow error bit of the receive status register. long error the mac receive block checks the length of the incoming packet at the end of recep- tion. if the length is longer than the maximum frame size of 1518 bytes, the mac receive block reports receiving a long error, unless long frame mode is enabled. mii error the phy informs the mac if it detects a media error (such as coding violation) by asserting rx_er. when the mac sees rx_er asserted, a crc error is forced at the end of the packet. toshiba corporation 81 mac operation accessing station management data the basic sequence of events in accessing the station management data are: ? system software reads the busy bit to ensure the md is not busy. ? for a write operation, the data should be written into the data register before setting the control register. ? software writes the mdc address, the read/write flag, and sets the busy bit. ? the controller completes the operation, and clears the busy bit. ? for a read operation, when system software detects the busy bit is cleared, it can read the data register. accessing an eeprom or rom the basic sequence of events in accessing an external eeprom or serial rom are: ? system software reads the busy bit to ensure the driver is not busy. ? for a write operation, the data should be written into the data register before setting the control register. ? software writes the address and the read/write flag, and sets the busy bit. ? the controller completes the operation, and clears the busy bit ? for a read operation, when system software detects the busy bit is cleared, it can read the data register. 82 toshiba corporation mac operation this page left blank intentionally toshiba toshiba corporation 83 TC35815CF flow control 10/100mbps ethernet controller chapter 7 - dma operation this chapter gives information on programming the TC35815CF flow control 10/ 100mbps ethernet contro ller. some topics will be covered later in application notes. programming details differ slightly, depending on the control mode chosen: batch processing or continuous polling. the descriptions in this chapter assume continuous polling, unless otherwise noted. the topics covered in this chapter include: 1. pci initialization 2. dma and mac initialization 3. queue initialization 4. transmitting a frame 5. receiving a frame 6. processing interrupts pci initialization at system initialization time, the idsel signal can be used to write the pci con?gu- ration registers. this is normally done by having the system map the controller into a startup memory address space, and having data transfers to those addresses gener- ate the idsel signal. alternatively, some registers can be initialized from an optional eeprom or rom, as described in the chapter 6 accessing an eeprom or rom section. the registers that must be initialized include: ? pci i/o or memory base address - to map registers into i/o or memory space. ? pci command - to customize pci capabilities. the registers that might be initialized include: ? pci interrupt - to customize latency or route interrupts. dma and mac initialization after pci initialiazation, the dma and mac control registers are normally mapped into i/o space, or memory space, and can be read or written from the mapped space. alternatively, these registers can be initialized from an optional eeprom or rom, as described in chapter 6, page 81, in the section accessing an eeprom or rom. 84 toshiba corporation dma operation the registers that must be initialized include: ? dma transmit frame pointer - to initiate transmission. ? dma buffer list frame pointer - to provide buffers for reception. ? dma free descriptor area base and limit - to initialize receive notification area. ? dma transmit polling count - to customize polling for packets to transmit. ? dma transmit threshold - to customize handling of transmit latency. ? mac transmit control - to change default transmission settings. ? mac receive control - to change default reception settings. ? mac cam control - to customize station and multicast-group address recognition. ? mac cam address and data - to provide station address and other address filtering. ? mac cam enable - to enable individual cam entries after setup. the registers that might be initialized include: ? mac control register - to customize mac configuration. ? dma transmit burst size - to customize transfer sizes. queue initialization before starting the controller, the system needs to set up the transmit queue, the buffer list queue, and the receive descriptor area. transmit queue initialization there are two modes of operation for the transmitter: batch processing and continuous polling. for batch processing, the system software sets up a linked list of frame descriptors to transmit, with the last frame descriptor containing an end-of-list (eol) indicator. when the last frame descriptor is transmitted, the transmit frame pointer register loads the eol indicator, and transmission terminates. later, the system must restart transmission by storing a new value in this register. for continuous polling, the system software sets up a linked list of frame descrip- tors to transmit, which ends with a dummy frame descriptor. the linked list may be initially empty, except for the dummy frame descriptor. the dummy frame descriptor is owned by the system, to prevent the controller from accessing it. when a new packet is to be transmitted, the dummy frame descriptor is overwritten, as described in this chapter transmitting a frame. toshiba corporation 85 dma operation buffer list initialization the buffer list queue is initialized by setting up a linked list of frame descriptors with one or more frame descriptors, each containing a list of free buffer descriptors. the list can be any one of the following: 1. a single frame descriptor, with a large number of free buffer descriptors. 2. a linked list of frame descriptors. 3. a circular queue, with the last frame descriptor pointing to the ?rst frame descriptor. for 1.) and 2.) the fdnext ?eld would have the eol bit set; for 3.) the fdnext ?eld of the last frame descriptor would point to the ?rst frame descriptor. the receive buffer fragment size register can be set to globally enable packed buffer usage. alternatively, the frame descriptor control ?eld (fdctl) can be used to select packed or unpacked buffer usage on a per buffer area basis. for packed buffer usage, the buffer id ?elds can be set, to assist in memory management. for more details on enabling buffer packing see chapter 4, page 46 in the section receive fragment size register, chapter 4, page 48 in the section descriptor area registers, and chapter 5, page 67 in the section buffer descriptor control (bdctl). receive descriptor area initialization the receive descriptor area is initialized by writing the descriptor area base and limit registers. the controller will use these registers to initiate writing of the receive queue in the receive descriptor area. transmitting a frame transmit queue initialization in chapter 7 on page 84, describes batch processing transmission. for each batch of frames to transmit, the system initializes the transmit queue, and writes the head of the queue into the transmit frame pointer register. for continuous polling transmission, the list of frame descriptors is terminated by a dummy frame descriptor, which is owned by the system. when the controller reaches the dummy record, it will enter a polling mode. in this mode, the controller periodically reads the frame descriptor control (fdctl) ?eld, waiting for the fdowner bit to be cleared by the system. the frequency of polling is controlled by the transmit polling counter register. to transmit a frame in continuous polling mode, the system writes a new frame descriptor for the frame to transmit at the tail of the transmit queue. this is done by over- writing the old dummy frame descriptor, creating a new dummy frame descriptor, and setting the next ?eld of the old frame descriptor to the new dummy frame descriptor. the last step of the overwrite is to clear the fdowner bit of the old frame descriptor, giving ownership to the controller. 86 toshiba corporation dma operation transmit complete noti?cation the system can obtain transmission completion information in a variety of ways: ? request an interrupt. ? poll the fdctl field of transmitted frame descriptors, for system ownership. ? poll the transmit frame pointer register. interrupts can be requested at the end of each frame transmitted, or at the end of selected frames. when polling the transmit frame pointer register, the system call look for an invalid value (batch processing mode), or look for the address of the dummy frame descriptor (continuous polling mode). receiving a frame to enable the mac to receive frames, system software must do the following: 1. initialize the free buffer list and free descriptor areas, as described earlier in this chapter on page 84, in the section , queue initialization. 2. write a dummy frame descriptor into the free descriptor area, setting the fdowner bit of the fdctl ?eld so the controller owns it. 3. initialize the receive frame pointer register to the address of the dummy frame descriptor in the free descriptor area. there are two ways that system software can be noti?ed about received frames: ? request an interrupt for each frame received. ? poll the dummy frame descriptor, looking for the fdowner bit to be set. interrupts are enabled by setting the completion interrupt enable bit of the receive control register. once a frame is received, the system must do the following: ? process the frame descriptor and free it for reuse at a future time. ? free buffers as they are returned, and add them to the free buffer list. processing received frame descriptors the free descriptor area is intended to be used in a fifo manner. however, different applications will take different amounts of time to process frames and return associ- ated buffers. so frame descriptors allocated by the controller are copied to another area and freed in the order in which they are received, before being passed up the pro- tocol stack. toshiba corporation 87 dma operation freeing buffers there are two ways that buffers may be allocated: ? starting a new frame in a new buffer. ? placing several frames or parts of frames in a single buffer. the allocation mode is controlled by either the buffer fragment size register, or the frame descriptor control ?eld. the single frame mode has the advantage of sim- pler memory management, but the disadvantage of less ef?cient memory utilization. the packed buffer mode has the advantage of more ef?cient memory utilization, but the disadvantage of more complex memory management. packed buffers require some additional managing, because of the possibility of multiple frames or fragments of frames in the same buffer area. the controller counts the number of buffers created in the same buffer area, and provides this count as the rxbdseqn ?eld of the bdctl ?eld in the buffer descriptor. system software can then count returned fragments, until all fragments are returned. a buffer id value, rxbdid, is copied from the buffer descriptors in free buffer queue, to the buffer descriptors in the received frame queue. up to 256 id values are available. if more are needed, several techniques are available. one alternative is to provide id extension bits in the fdsystem ?eld. another is to calculate high order bits from the buffer pointer values, which point into the buffer. processing interrupts when an interrupt occurs, it is generally on a shared interrupt line. to see if this pci device is the source of an interrupt, system software reads the interrupt source register. based on the contents of this register, the system software may need to read additional registers, such as the transmit or receive status registers. 88 toshiba corporation dma operation this page left blank intentionally toshiba toshiba corporation 89 TC35815CF flow control 10/100mbps ethernet controller chapter 8 - timing pci clock timing parameters the timing diagrams for pci bus operations can be found in the pci speci?cation. timing diagrams for the mii operations and 10mbps ethernet can be found in the ieee 802.3 standard document. timing diagrams for the supported eeprom devices can be found on the respective data sheets. this section conforms to pci local bus speci?cation, section 4.2.3, timing speci?cation. figure 8-1 shows the pci clock waveform and measurement points for both 5v and 3.3v signaling environments. figure 8-1 pci clock waveforms in order for the controller to support 100mbps transmit and receive, the pci clk should be operated at between 25 and 33mhz. clock rates of 16mhz or slower can support 10mbps operation. the controller is a fully static design, and can have its clock rate lowered or stopped, providing transmission and reception have been disabled. 2.0 v, p-to-p (minimum) 0.4 v cc , p-to-p (minimum) t_cyc t_high t_low 0.6 v cc 0.2 v cc 0.4 v 2.4 v 2.0 v 1.5 v 0.8 v 0.475 v cc 0.400 v cc 0.325 v cc 5-volt clock 3.3-volt clock 90 toshiba corporation timing detailed timing parameters for each pci operation/transaction figure 8-2 output timing measurement conditions. high levels are at v_th, low levels are at v_tl, and transitions are at v_test. figure 8-3 input timing measurement conditions. high levels are at v_th, low levels are at v_tl, and transitions are at v_test. llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh|\llllllllll | ???t_val?? ssssssssssssssssssssssssssssssssss|ssssssssss|xsssssssssssssss |???t_on?? |?????????|????t_off???? ???????????????????????????????????????????|qssssssssssss|w??? clk output delay tri-state output llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh\lllllllllll ???t_su?? | ???t_hs?? sssssssssssssssssssssssss|xssinputs|ssvalidss|xsssssssssssssssss clk input toshiba corporation 91 timing table 8-1 shows the timing parameters for 5v and 3.3v signaling environments. notes: 1. minimum times are measured with 0 pf equivalent load; maximum times are measured with 50 pf equivalent load. actual test capacitance may vary, but results should be correlated to these specifi- cations. 2. req# and gnt# are point-to-point signals, and have different output valid delay and input setup times than do bussed signals. gnt# has a setup of 10, and req#, 12. all other signals are bussed. 3. rst# is asserted and deasserted asynchronously with respect to clk. 4. all output drivers must be floated when rst# is active. pci measurement and test conditions table 8-2 shows the measurement and test condition parameters for 5v and 3.3v sig- naling environments. note: 1. the input test for the 5v environment is done with 400 mv of overdrive (over v ih and v il ); the test for the 3.3v environment is done with 0.125*v cc mv of overdrive. timing parameters must be met with no more overdrive than this. v max specifies the maximum peak-to-peak waveform allowed for testing input timing. table 8-1 5v and 3.3v timing parameters symbol parameter min. max. units figure notes t val clk-to-signal-valid delay for bussed signals 2 11 ns 8-2 1, 2 t val (ptp) clk-to-signal-valid delay for point-to-point signals 2 12 ns 8-2 1, 2 t on float-to-active delay 2 - ns 8-2 - t off active-to-?oat delay - 28 ns 8-2 - t su input setup time to clk for bussed signals 7 - ns 8-3 2 t su (ptp) input setup time to clk for point-to-point signals gnt#: 10 req#: 12 -ns8-3 2 t h input hold time from clk 0 - ns 8-3 - t rst reset active time after power stable 1 ms - 3 t rst-clk reset active time after clk stable 100 m s- 3 t rst-off reset active to output ?oat delay - 40 ns - 3, 4 t rrsu req64# to rst# setup time 10*t cyc -ns - - t rrh rst# to req64# hold time 0 50 ns - - table 8-2 measurement and test condition parameters symbol 5v signaling 3.3v signaling units note v th 2.4 0.6 v cc v1 v tl 0.4 0.2 v cc v1 v test 1.5 0.4 v cc v- v max 2.0 0.4 v cc v1 input signal edge rate 1 v/ns - 92 toshiba corporation timing detailed timing parameters for each mii operation/transaction this section conforms to draft supplement to ansi/ieee std. 802.3, section 22.3, signal characteristics. figure 8-4 transmit signal timing relationships at the mii figure 8-5 receive signal timing relationships at the mii figure 8-6 mdio sourced by phy figure 8-7 mdio sourced by sta llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh|\llllllllll | ? ???0snssmin,s25snssmax ssssssssssssssssssssssssssssssssssssssssssss|xsssssssssssssss tx_clk txd[3:0], tx_en, tx_er llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh\lllllllllll ???10snssmin?? | ???10snssmin?? ssssssssssssssssssss|xsssssssinputs|ssvalidsssssss|xssssssssssss rx_clk rxd[3:0], rx_dv, rx_er llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh|\llllllllll | ? ???0snssmin,s300snssmax ssssssssssssssssssssssssssssssssssssssssssss|xsssssssssssssss mcd mdio llll/hhhhhhhhhhhhhh\llllllllllllll|/hhhhhhhhhhhhhh\lllllllllll ???10snssmin?? | ???10snssmin?? ssssssssssssssssssss|xsssssssinputs|ssvalidsssssss|xssssssssssss mcd mdio toshiba toshiba corporation 93 TC35815CF flow control 10/100mbps ethernet controller chapter 9 - electrical specifications table 9-1 absolute maximum ratings table 9-2 dc characteristics (pci pins) table 9-3 dc characteristics (other pci pins) notes 1. with pull down resistor 2. non pull down resistor 3. with pull-up resistor 4. non pull-up resistor 5. all input pins are 5v tolerant. symbol item rating vdd supply voltage -0.5v to 4.6v vin input voltage -0.5 to 5.5 v tsolder soldering temperature(10 s) 240 c tstg storage temperature -65 c to 150 c topr operating temperature 0 c to 70 c symbol item min. typ. max. unit vih(pci) input high voltage(#5) 0.5vdd 5.25 v vil(pci) input low voltage 0.4vdd v voh output high voltage(ioh=-2.0 ma) 0.9vdd v vol output low voltage(iol=6 ma) 0.1vdd v lil input leakage -10 10 m a symbol item min. type. max unit notes vdd supply voltage 3 3.3 3.6 v iddd operating current (3.3 v, 33 mhz) 50 80 ma lih1 input high current 1 30 160 m a1 lih2 input high current 2 -10 10 m a2 lil1 input low current 1 -160 -30 m a3 lil2 input low current 2 -10 10 m a4 vih input high voltage 2 5.25 v 5 vil input low voltage 0.8 v voh output high voltage (ioh=2.5 ma) 2.4 v vol output low voltage (iol=2.5 ma) 0.4 v 94 toshiba corporation electrical specification s this page left blank intentionally toshiba toshiba corporation 95 TC35815CF flow control 10/100mbps ethernet controller chapter 10 - mechanical specifications figure 10-1 qfp144-p-2020-0.50 [144-pin quad flat package] 20.0 0.2 20.0 0.2 1.25 typ. 109 144 72 73 108 36 37 1 1.25 typ. 0.5 bsc seating plane 22.6 0.2 22.6 0.2 0.2 0.1 0.45 +0.2 ?.1 +0.1 ?.05 0.08 4.45 max 0.1 3.6 0.2 m 0 ? -10 ? 0.5 0.2 0.15 21.6 0.2 unit: mm pin no. pin name 96 toshiba corporation mechanical specifications pin no. pin name 1 vss 2 ad23 3 ad22 4 ad21 5 ad20 6 vdd 7 ad19 8 ad18 9 vss 10 ad17 11 ad16 12 c_be_l2 13 frame_l 14 irdy_l 15 trdy_l 16 vdd 17 devsel_l 18 vdd 19 vss 20 stop_l 21 perr_l 22 serr_l 23 par 24 c_be_l1 25 vss 26 ad15 27 ad14 28 vdd 29 ad13 30 ad12 31 vss 32 ad11 33 ad10 34 ad9 35 ad8 36 c_be_l0 37 vdd 38 ad7 pin no. pin name 39 ad6 40 vss 41 ad5 42 ad4 43 ad3 44 vss 45 ad2 46 ad1 47 ad0 48 vdd 49 vss 50 sca 51 scb 52 vss 53 pcam_hit_l 54 pcam_load 55 vdd 56 nc 57 vss 58 sca2 59 scb2 60 vdd 61 nc 62 pprom_di 63 pprom_do 64 vss 65 pprom_clk 66 pprom_cs 67 vss 68 vdd 69 prxc_10 70 pcrs_10 71 prxd_10 72 ploop_10 73 vss 74 plink_10 75 pcol_10 76 ptxen_10 pin no. pin name 77 ptxd_10 78 vss 79 ptxc_10 80 vdd 81 vss 82 vdd 83 crs 84 col 85 vss 86 txd3 87 txd2 88 vss 89 txd1 90 vdd 91 vss 92 txd0 93 tx_en 94 vdd 95 ptx_clk 96 vss 97 tx_er 98 prx_er 99 prx_clk 100 prx_dv 101 prxd0 102 vss 103 prxd1 104 vdd 105 prxd2 106 prxd3 107 pmdc 108 mdio 109 vdd 110 vss 111 si 112 so 113 si2 114 so2 pin assignments table 10-1 ethernet controller pin assignments 97 toshiba corporation mechanical specifications pin no. pin name 115 stm 116 vss 117 vdd 118 vss 119 t1 120 t2 121 t3 122 t4 123 vss 124 t5 pin no. pin name 125 inta_l 126 vdd 127 vss 128 prst_l 129 vdd 130 pclk 131 gnt_l 132 req_l 133 ad31 134 ad30 pin no. pin name 135 ad29 136 vss 137 ad28 138 ad27 139 ad26 140 vdd 141 ad25 142 ad24 143 c_be_l3 144 idsel table 10-1 ethernet controller pin assignments (continued) notes: 1. for a description of the active signals, see chapter 2, "external signals". 2. nc indicates a no connect. 3. a=master, e.g., sca 4. b=slave, e.g., scb 5. t1, t3, t4, t5 must be open. 6. t2 must connect to vss. 98 toshiba corporation mechanical specifications this page left blank intentionally toshiba toshiba corporation a-1 TC35815CF flow control 10/100mbps ethernet controller appendix a constants max_deferral C the maximum number of milliseconds that the mac will defer before asserting an excessive deferral signal. max_cam_entries C the maximum number of six-byte addresses that the cam can hold in direct compare mode. table a-1 shows cam size. buffer sizes toshiba has designed its TC35815CF flow control 10/100mbps ethernet control- ler to use suf?cient internal buffering so that the controller can continue to send and receive packets even when the pci local bus in not available for reasonably long periods of time. table a-2 shows the relationship between bus latency and buffer sizes. the bus latency is the maximum amount of time that the pci local bus might be tied up, or locked by other devices. the pci speci?cation uses 10-30 m s as a nominal value for bus latency. but in talking with various system designers, toshiba believes that 40-100 m s is a more realistic value for designs. certainly there is ample evidence that small buffer sizes on some 10mbps ethernet controllers leads to the high failure rate of packet transmission and reception on pc-based networks. trans- mitters running dry is now recognized as a major source of runt packets on these networks. the numbers for bytes and bits are the amount of transmit or receive data that can be sent in large packets at 100mbps. the packet numbers are calculated using the minimum packet size (64 bytes), but not taking into account the effects of inter-packet gaps or short packet mode. internal noti?cation fifos must be big enough to buffer this number of minimum- size packets for transmission and reception to continue without blocking. table a-1 cam size max_cam_entries bytes bits 21 126 1008 table a-2 bus latency and buffer sizes bus latency bytes packets transmit >140 m s 1700 1 - 20 receive >160 m s 1900 1 - 22 a-2 toshiba corporation appendix a this page left blank intentionally toshiba toshiba corporation b-1 TC35815CF flow control 10/100mbps ethernet controller appendix b glossary this glossary contains a brief explanation of technical terms, abbreviations, and acronyms used in this document. ethernet and networking acronyms and terms 10base5 C 500-meter-per-segment ethernet using half-inch diameter thick coaxial cable. up to 100 nodes. 10base2 C 185-meter-per-segment ethernet, using rg-58 50-ohm thin coaxial cable similar to that used for community-antenna television. up to 30 nodes. also, cheapernet or thinnet. 10base-t C 24-gauge, unshielded, twisted-pair 10mbps ethernet. 100base-fx C 100 mbps ethernet using ?bre optic cable. 100base-t C twisted-pair 100mbps fast ethernet, either 100base-t4 or 100base- tx. 100base-t2 C 100 mbps ethernet using two pairs of category-3, -4, or -5 generic twisted balanced cable. 100base-t4 C intels proposal for 100mbps ethernet using 8b/6t block coding over four pairs of category-3 unshielded twisted pair. the data runs on three of the four pairs; the fourth pair handles collision detection. the data wires handle a maximum frequency of 25mhz. also, 4t+ and 4t-plus. 100base-tx C 100mbps ethernet using three-level mlt-3 signaling employed by cop- per fddi (cddi) over two pairs of data-grade, category-5 unshielded twisted pair wir- ing. also, 100base-x. 100base-x C 100mbps ethernet using three-level mlt-3 signaling employed by copper fddi (cddi) over two pairs of data-grade, category-5 unshielded twisted pair wiring. also, 100base-tx. 100base-vg C 100mbps ethernet alternative. see anylan. anylan C also 100base-vg anylan. joint h-p and ibm 100mbps ethernet alterna- tive and token ring proposal. also, ieee 802.12. adsl C asymmetric digital subscriber lines. from bell communications research inc. uses as few as four-wire twisted pair. alignment erro r Cwhen the mac receives a frame that is not an integer number of bytes long, and the crc is invalid. synonym: framing error. see also, dribble. arp C address resolution protocol. maps an internet address to a physical address. not all networks need it. aui C attachment unit interface layer of lan csma/cd. connects the dte to the mau. see osi. used with thick ethernet, involving a drop cable. babble C transmit continuously for more than 1500 bytes. 1 1. project 802 local and metropolitan area networks. draft guide to ansi/ieee std. 802.3 (cs- ma/cs access method and physical layer specifications). systems topology technical advisory group (systag) network guide, draft 5.2, january 23, 1994. section 3.5 false jabber, page 13. b-2 toshiba corporation appendix b big endian C the byte at memory address 0 contains the most-signi?cant bits. used by ibm 370, motorola 68000, pyramid, and tcp/ip protocol header integers. bridge C a store-and-forward device connecting physical networks that merely passes all packets. unlike a gateway, strictly speaking, it performs no protocol conversion, and unlike a router, it does not switch packets to the appropriate network (although some bridges can learn where various hosts reside and route packets). broadcast address C a distinguished, prede?ned multicast address that always denotes the set of all stations on a given local area network. all ones in the destination address ?eld shall be prede?ned to be the broadcast address, ff-ff-ff-ff-ff-ff. bundle C a group of signals which have a common set of characteristics and differ only in their information content. capture effect C under heavy load, if at least one of the contending stations is capable of transmitting back-to-back packets continuously, that station can capture the network for long periods. this occurs because, once a station has succeeded in transmitting, it zeroes its attempts counter, so its next maxbackoff will be set to 2. other stations, however, will con- tinue to increment their attempts counters, causing their maxbackoff variables to grow exponentially. the network still carries traf?c at its full rate (except for second-order effects), but its arbitration has become unfair. ccitt C consultative committee for international telephony and telegraphy. renamed itu. cheapernet C 185-meter-per-segment ethernet. also, 10base2. csma/cd C carrier sense multiple access with collision detection. used by ethernet. cddi C copper distributed data interface. fddi without the ?ber. co C central of?ce. crc C cyclic redundancy code. called cyclic redundancy check in ieee 802.3 docu- ment. dce C data communications equipment. ds0 C 64-kbits asynchronous rate. one voice channel. ds1 C 1.544mbps asynchronous rate. 24 ds0 signals. t1 equipment and cable carry ds1 rate and format between cos. ds2 C 6.312mbps asynchronous rate. four ds1 signals. ds3 C 44.736mbps asynchronous rate. 28 ds1 signals. t3 equipment and cable carry ds3 rate and format between cos. dma C direct memory access. dribble Cwhen the mac receives a frame that is not an integer number of bytes long. dribble produces an alignment error when the crc is invalid. dte C data terminal equipment. if the aui is not exposed, this is the pls and up. see osi. efd C the end of frame delimiter toshiba corporation b-3 appendix b frame C according to 802.3 tutorial, a frame is everything in a packet except the pre- amble and the start frame delimiter: destination and source addresses, length, llc data, padding, and frame check sequence. framing error C see alignment error, dribble. gateway C a device connecting networks that performs some protocol conversion. globally administered address C an ethernet address whose second bit transmitted, used to distinguish between locally or globally administered addresses, is set to 0, indi- cating a globally administered (or u, universal) address. if an address is to be assigned locally, this bit shall be set to 1. note that for the broadcast address, this bit is also a 1. group address C an ethernet destination address whose ?rst bit transmitted, used to identify it either as an individual or as a group address, is 1, indicating that the address ?eld contains a group address that identi?es none, one or more, or all of the stations connected to the local area network. more commonly called a multicast address. the ?rst byte of a multicast address is odd, for example, 01-00-00-00-00-00. there are two kinds of multicast address: (a) multicast-group address. an address associated by higher-level convention with a group of logically-related stations. (b) broadcast address. a distinguished, prede?ned multicast address, ff-ff-ff-ff-ff-ff, that always denotes the set of all stations on a given local area network. hdlc C high-level data link control. used in x.25. heartbeat C signal quality error (sqe). iab C internet activities board. icmp C internet control message protocol. the protocol to handle error and control information between gateways and hosts. tcp/ip networking software, not user pro- cesses, generates and processes icmp messages. ieee 1149.1 C see jtag. ieee 802.12 C joint hp and ibm 100mbps proposal. also, 100base-vg or any- lan. ieee 802.3 C information technologyClocal and metropolitan area networksCpart 3: carrier sense multiple access with collision detection (csma/cd) access method and physical layer speci?cations. international standard iso/iec 8802-3: 1993(e), ansi/ ieee std. 802.3, 1993 edition, july 8, 1993. also, ethernet. ieee 802.4 C token bus. ieee 802.5 C token ring. individual address C an ethernet address whose ?rst bit transmitted, used to identify it either as an individual or as a group address, is 0, indicating that the address ?eld con- tains an individual address, and so is associated with a particular station on the network. the ?rst byte of a individual address is even, for example, 00-00-00-00-00-00. ip C internet protocol. fragments (segments), routes, delivers, and reassembles packets for tcp, udp, and icmp. connectionless and unreliable. adds a 20-byte header and a check sum. isdn C integrated services digital network. iso C international organization for standardization. jabber C in order to protect the network from babbling nodes, ieee std. 803.3 requires maus to inhibit transmission onto the network if they have been transmitting for an excessive time. the window for jabber must be between 20 and 150ms. 1 1. project 802 local and metropolitan area networks. draft guide to ansi/ieee std. 802.3 (csma/ cs access method and physical layer specifications). systag network guide, draft 5.2, january 23, 1994. section 3.5 false jabber, page 13. b-4 toshiba corporation appendix b jtag C joint test action group. a group of companies that developed what became ieee 1149.1 test access port... for board-level production test of integrated-circuit pin continuity. lan C local area network. little endian C the byte at memory address 0 contains the least-signi?cant bits. used by intel x86, dec vax, and dec pdp-11. llc C logical link control layer of lan csma/cd. the upper half of the osi (which see) reference model data link layer, between the mac and the network layer. locally administered address C an ethernet address whose second bit transmitted, used to distinguish between locally or globally administered addresses, is set to 1, indicating a locally administered address. if an address is to be assigned globally (or u, universal), this bit shall be set to 0. note that for the broadcast address, this bit is also a 1. 1 mac C media access control layer of lan csma/cd. the lower half of the osi (which see) reference model data link layer, between the llc and the pls. mau C medium attachment unit layer of lan csma/cd. see osi. mdi C medium dependent interface layer of lan csma/cd. the part of the mau that connects the pma to the medium. see osi. mii C media independent interface. a four-bit-wide interface between a reconcilia- tion layer and the pls. the reconciliation layer connects to the mac using the exist- ing 802.3 mac-pls interface. minimum frame length C 64 bytes (512 bits). note that this does not include the preamble and the start frame delimiter. multicast address C an ethernet destination address whose ?rst bit transmitted, used to identify it either as an individual or as a group address, is 1, indicating that the address ?eld contains a group address that identi?es none, one or more, or all of the sta- tions connected to the local area network. the ?rst byte of a multicast address is odd, for example, 01-00-00-00-00-00. there are two kinds of multicast address: (a) multi- cast-group address. an address associated by higher-level convention with a group of logically-related stations. (b) broadcast address. a distinguished, prede?ned multicast address that always denotes the set of all stations on a given local area network. multicast-group address C an address associated by higher-level convention with a group of logically-related stations. this is one of two kinds of multicast address, the other being the broadcast address, ff-ff-ff-ff-ff-ff. ndis C network driver interface speci?cation for a generic device driver, indepen- dent of protocol or hardware. network acquisition time C if the dte transmits for a period exceeding the net acquisition time without detecting a collision, then the dte is said to have acquired the network. the dte will send the remainder of its frame without the possibility of having a collision in a correctly operating network. by this time, all dtes in the net- work have detected network activity and are deferring to it.... for example, the net- work acquisition time on a single-segment 10base5 network of 500-meter length is approximately 108 bit times. 2 also called round trip delay. nic C network interface controller or card. also network information center, at sri international, which assigns a network a class ?eld (a, b, or c) and a unique net- work id ?eld of the 32-bit tcp/ip addresses. 1. ansi/ieee std. 802.3, 1993 edition. section 3.2.3 address fields, page 42. 2. project 802 local and metropolitan area networks. draft guide to ansi/ieee std. 802.3 (csma/ cs access method and physical layer specifications). systag network guide, draft 5.2, january 23, 1994. section 2.3.1: network acquisition time, page 4. toshiba corporation b-5 appendix b oc1 C 51.84mbps optical carrier 1, sonet synchronous transport signal sts-1. 28 ds1 signals or one ds3. oc3 C 155.52mbps optical carrier 3, sonet synchronous transport signal sts-3. three byte-interleaved sts-1 signals. oc12 C 622.08mbps optical carrier 12, sonet synchronous transport signal sts-12. twelve byte-interleaved sts-1 signals. oc48 C 2488.32mbps optical carrier 48, sonet synchronous transport signal sts-48. 48 byte-interleaved sts-1 signals. octet C byte. osi C open system interconnection reference model layers adopted by the iso C application, presentation, session, transport, network, data link (composed of llc and mac layers of lan csma/cd), and physical (composed of pls and pma lay- ers of lan csma/cd, connected by aui). packet C according to 802.3 tutorial, a packet is a frame, preceded by the preamble and the start frame delimiter ?elds. thus, it consists of (1) preamble, (2) start frame delimiter, (3) destination and (4) source addresses, (5) length, (6) llc data, (7) pad- ding, and (8) frame check sequence ?elds. pci C peripheral component interconnect. 32 or 64 bits wide, 0 to 33mhz clock rate, 132 to 264 mbyte/s (peak). intel corporation released version 1.0 of the pci speci?cation on june 22, 1992, and the pci special interest group released revision 2.0 on april 30, 1993. ping C packet internet groper. tests the reachability of another site by sending an icmp echo request message. pcmcia C personal computer memory card international association. pdu C protocol data unit in atm. phy - physical layer entity, as de?ned in the 802 architecture and overview stan- dard. the word phy is used to denote the set of functions associated with a physical layer protocol. pls C physical signaling layer of lan csma/cd. see osi. pma C physical medium attachment. see osi. pmd C physical medium dependent layer. pmd connects to mac via mii on one side, and connects to mdi on the other. ppp C point-to-point protocol. successor to slip, serial line internet protocol. pro- vides router-to-router and host-to-network connections over both synchronous and asynchronous circuits. pstn C public switched telephone network. preamble C the ?rst ?eld of a packet, up to seven bytes long. each byte has value 10101010, transmitted left to right. qam C quadrature amplitude modulation. modulation of both amplitude and phase, to increase the information capacity of a channel. rarp C reverse address resolution protocol. maps a physical address to an inter- net address. only some networks need it. repeater C connects two or more ethernet segments, with signal ampli?cation and timing and preamble regeneration, but without storing packets. rj-11 C four-wire modular telephone connector. rj-45 C eight-wire modular telephone connector. router C a store-and-forward protocol-dependent device connecting networks that switches packets to the appropriate network. b-6 toshiba corporation appendix b runt C a frame that is less than 64 bytes ( minframesize) long, exclusive of preamble and sfd. synonym: fragment. saturn C sonet-atm user network. a group to develop chips to sonet and atm forum speci?cations. scsi C small computer system interface. sdh C synchronous digital hierarchy. itus european designation for ?ber-optic transmission. see also sonet. sdlc C synchronous data link control. used in systems network architecture. sfd C start frame delimiter. a single byte with value 10101011, transmitted from left to right. it follows the preamble. signal quality erro r C sqe. also, heartbeat. slip C serial line internet protocol. predecessor to ppp. smds C switched multimegabit data service, a 45mbps cell-relay service based on ieee 802.6 distributed queue dual bus. smtp C simple mail transfer protocol. an application program provided by almost every tcp/ip implementation. snmp C simple network management protocol. allows a tcp/ip host to query other nodes for network-related statistics and error conditions. sonet C synchronous optical network. ansi u.s. ?ber-optic transmission standard. see also sdh. sonic tm C national semiconductor corporations dp83932b systems-oriented network interface controller. spanning tree C an algorithm to create a logical topology connecting all network segments, and ensures that only one path exists between any two stations. spool C simultaneous peripheral operation on-line. sqe C signal quality error. also, heartbeat. start frame delimiter C see sfd. station address C an ethernet address whose ?rst bit transmitted, used to identify it either as an individual or as a group address, is 0, indicating that the address ?eld contains an individual address, and so is associated with a particular station on the network. the ?rst byte of a multicast address is even, for example, 00-00-00-00-00-00. sts-1 C synchronous transport signals. t1 C 1.544mbps. tap C test access port. see jtag. tcp Ctransmission control protocol, a connection-oriented, reliable, full-duplex, virtual circuit byte-stream facility for a user process. uses ip. part of the tcp/ip protocol suite. tcp/ip Ctransmission control protocol/internet protocol, the darpa internet protocol suite. type 1 cable C shielded, two-pair cable. type 3 cable C unshielded, twisted-pair cable. udp C user datagram protocol, a connectionless, unreliable datagram facility for a user process. uses ip. part of the tcp/ip protocol suite. universal address C an ethernet address whose second bit transmitted, used to dis- tinguish between locally or globally administered addresses, is set to 0, indicating a globally administered (or u, universal) address. if an address is to be assigned locally, this bit shall be set to 1. note that for the broadcast address, this bit is also a 1. 1 1. ansi/ieee std. 802.3, 1993 edition. section 3.2.3 address fields, page 42. toshiba corporation b-7 appendix b v.32terbo modem C 19.2 kbits/s. v.34 modem C 28.8 kbits/s. vesa C video electronics standards association, an association of companies involved in the design and manufacture of video graphics adapters. vl C vesa local bus. b-8 toshiba corporation appendix b this page left blank intentionally toshiba toshiba corporation c-1 TC35815CF flow control 10/100mbps ethernet controller appendix c the following features are not supported by the toshiba TC35815CF flow con- trol 10/100mbps ethernet controller. peripheral component interconnect (pci) functions some optional pci functions are not supported. the controller does not support the lock# signal, which supports atomic oper- ations. nor does it support the interrupt b, c, and d signals, intb#, intc#, and intd#, for multi-function devices, or snoop backoff, sbo#, and snoop done, sdone, for cache support. the controller does not support the optional pins for a 64-bit ad data path. the controller does not support 64-bit addressing for system memory space. thus, in chapter 4, page 40, the section named i/o and memory base address registers, only 00 and 01 are supported as values for the loc ?eld. ieee 802.3 features the controller does not support the 16-bit option for destination and source addresses. c-2 toshiba corporation appendix c this page left blank intentionally toshiba t aec regional sales o f fices no r thwest san jose, ca tel: (408) 52 6 - 240 0 f ax: (408) 52 6 - 24 10 portland, or tel: (503) 629-0818 f ax: (503) 629-0827 southwest irvine, ca tel: (949) 453-0224 f ax: (949) 453-0125 dallas, tx tel: (972) 480-0470 f ax: (972) 235-4114 central chicago, il tel: (847) 945-1500 f ax: (847) 945-1044 no r theast edison, nj tel: (732) 248-8070 f ax: (732) 248-8030 boston, ma tel: (781) 224-0074 f ax: (781) 224-1096 southeast atlanta, ga tel: (770) 931-3363 f ax: (770) 931-7602 ww w .toshiba.com/taec sp31680499 |
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