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IC-NQI 13-bit sin/d converter with calibration rev a2, page 1/ 26 features ? resolution of up to 8192 angle steps per sine/cosine period ? binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis ? conversion time of just 250 ns including ampli?er settling ? count-safe vector follower principle, real-time system with a 70 mhz sampling rate ? direct sensor connection; selectable input gain ? front-end signal conditioning features offset (8 bits), amplitude ratio (5 bits) and phase (6 bits) calibration ? input frequency of up to 250 khz ? incremental a quad b outputs with a selectable minimum transition distance (e.g. 0.25 s for 1 mhz at a) ? index signal processing adjustable in position and width ? serial output of absolute angle data at clock rates of up to 10 mhz ? error monitoring: frequency, amplitude, con?guration (crc) ? multiturn counting up to 24 bits ? device setup from serial eeprom or 2-wire interface ? esd protection and ttl-/cmos-compatible outputs applications ? interpolator ic for position data acquisition from analog sine/cosine sensors ? optical linear/rotary encoders ? mr sensor systems packages tssop20 block diagram copyright ? 2011 ic-haus http://www.ichaus.com p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 2/ 26 description IC-NQI is a monolithic a/d converter which, by ap- plying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolu- tion and hysteresis into angle position data. the front-end ampli?ers are con?gured as instrumen- tation ampli?ers, permitting sensor bridges to be di- rectly connected without the need for external resis- tors. various programmable d/a converters are avail- able for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase er- rors. front-end gain can be set in stages graded to suit all common differential sensor signals from ap- proximately 20 mvpp to 1.5 vpp, and also single-end sensor signals from 40 mvpp to 3 vpp respectively. two serial interfaces have been included to permit con?guration of the device: i 2 c for the connection of an eeprom and a 2-wire interface for con?guration from a microcontroller. a low signal at pin nprg is required to release the 2-wire interface for program- ming, whereas a high signal at pin nprg preselects the serial output of measurement data. for measurement data output, the fast synchronous- serial 2-wire interface can follow an ssi protocol at clock rates of up to 4 mbit/s, or a biss unidi- rectional protocol featuring error messages and a crc-protected transmission at clock rates of up to 10 mbit/s. a con?gurable period counter can supple- ment the measurement data by a multiturn count of up to 24 bits. at the same time any changes in output data are converted into incremental a quad b encoder sig- nals. here, the minimum transition distance can be adapted to suit the system on hand (limitations due to counter input frequency, cable length, emi). a syn- chronized index signal is generated and output to z if enabled by the pzero and nzero inputs. if the eeprom is detected following a power-down reset, the crc-protected chip setup is read in auto- matically. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 3/ 26 contents packages 4 absolute maximum ratings 5 thermal data 5 electrical characteristics 6 characteristics: diagrams . . . . . . . 8 operating requirements: 2w interface 9 parameter and register 10 signal conditioning 11 converter functions 12 maximum converter frequency 13 serial data output . . . . . . . . . . . . . . . 13 incremental output to a, b and z . . . . . . . 14 incremental signals 15 signal monitoring and error messages 17 test functions 18 serial 2-wire interface 19 serial data output . . . . . . . . . . . . . . . 19 examples of data output with ssi protocol . . 20 bidirektional register communication . . . . . 21 register communication: read . . . . . . . . 21 register communication: write . . . . . . . . 21 eeprom interface 22 application hints 23 principle input circuits . . . . . . . . . . . . . 23 basic circuits . . . . . . . . . . . . . . . . . . 24 evaluation board 24 design review: notes on chip functions 25 p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 4/ 26 packages tssop20 (according to jedec standard) pin configuration tssop20 4.4 mm, lead pitch 0.65 mm pin functions no. name function 1 pcos input cosine + 2 ncos input cosine - 3 vdda +5 v supply voltage (analog) 4 gnda ground (analog) 5 vref reference voltage output 6 a incremental output a analog signal cos+ (tma mode) pwm signal for offset sine (calib.) 7 b incremental output b analog signal cos- (tma mode) pwm signal for offset cosine (calib.) 8 z output index z pwm signal for phase/ratio (calib.) 9 gnd ground 10 vdd +5 v supply voltage (digital) 11 nprg programming enable input (active low) 12 clk 2w interface, clock line 13 dat 2w interface, data output 14 sda eeprom interface, data line analog signal sin+ (tma mode) 15 scl eeprom interface, clock line analog signal sin- (tma mode) 16 nerr error input/output, active low 17 pzero input zero signal + 18 nzero input zero signal - 19 psin input sine + 20 nsin input sine - external connections linking vdda to vdd and gnd to gnda are required. p r e l i m i n a r y p r e l i m i n a r y 1 pcos 2 n cos 3 vdda 4 g nda 5 vref 6 a 7 b 8 z 9 gnd 10 vdd nsin 20 psin 19 nzero 18 pzero 17 nerr 16 scl 15 sda 14 dat 13 clk 12 nprg 11 nqi code... ...yyww
IC-NQI 13-bit sin/d converter with calibration rev a2, page 5/ 26 absolute maximum ratings these ratings do not imply operating conditions; functional operation is not guaranteed. beyond these ratings device damage may occur. item symbol parameter conditions unit no. min. max. g001 vdda voltage at vdda -0.3 6 v g002 vdd voltage at vdd -0.3 6 v g003 vpin() voltage at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, clk, dat, nprg, a, b, z v() < vdda + 0.3 v -0.3 6 v v() < vdd + 0.3 v g004 imx(vdda) current in vdda -50 50 ma g005 imx(gnda) current in gnda -50 50 ma g006 imx(vdd) current in vdd -50 50 ma g007 imx(gnd) current in gnd -50 50 ma g008 imx() current in psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, clk, dat, nprg, a, b, z -10 10 ma g009 ilu() pulse current in all pins (latch-up strength) according to jedec standard no. 78; -100 100 ma ta = 25 c, pulse duration 10 ms, vdda = vdda max , vdd = vdd max , vlu() = (-0.5...+1.5) x vpin() max g010 vd() esd susceptibility at all pins hbm 100 pf discharged through 1.5 k
2 kv g011 tj junction temperature -40 150 c g012 ts storage temperature range -40 150 c thermal data operating conditions: vdda = vdd = 5 v 10 % item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature range -25 85 c tssop20 et -40/125 -40 125 c all voltages are referenced to ground unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 6/ 26 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. total device 001 vdda, vdd permissible supply voltage 4.5 5.5 v 002 i(vdda) supply current in vdda ?n() = 200 khz; a, b, z open 15 ma 003 i(vdd) supply current in vdd ?n() = 200 khz; a, b, z open 20 ma 004 von turn-on threshold vdda, vdd 3.2 4.4 v 005 vhys turn-on threshold hysteresis 200 mv 006 vc()hi clamp voltage hi at psin, nsin, pcos, ncos, pzero, nzero, vref vc()hi = v() - vdda; 0.3 1.6 v i() = 1 ma, other pins open 007 vc()lo clamp voltage lo at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, clk, dat, nprg, a, b, z i() = -1 ma, other pins open -1.6 -0.3 v 008 vc()hi clamp voltage hi at nerr, scl, sda, clk, dat, nprg, a, b, z vc()hi = v() - vdd; 0.3 1.6 v i() = 1 ma, other pins open input ampli?ers psin, nsin, pcos, ncos 101 vin()sig permissible input voltage range 0.6 vdda 1.1 v 102 vos() input offset voltage vin() and g() in accordance with table gain; g 20 -10 10 mv g < 20 -15 15 mv 103 tcos input offset voltage temperature drift see 102 10 v/k 104 iin() input current v() = 0 v ... vdda -50 50 na 105 ga gain accuracy g() in accordance with table gain 95 102 % 106 garel gain sin/cos ratio accuracy g() in accordance with table gain 97 103 % 107 fhc cut-off frequency g = 80 230 khz g = 2.667 650 khz 108 sr slew rate g = 80 4 v/s g = 2.667 9 v/s sin/d conversion: accuracy 201 aaabs absolute angle accuracy without calibration referred to 360 input signal, g = 2.667, vin = 1.5 vpp, hys = 0 -1.0 1.0 deg 202 aaabs absolute angle accuracy after calibration referred to 360 input signal, hys = 0, internal signal amplitude of 2 ... 4 vpp -0.5 0.35 +0.5 deg 203 aarel relative angle accuracy referred to output signal period of a/b, -10 10 % g = 2.667, vin = 1.5 vpp, selres = 1024, fctr = 0x0004 ... 0x00ff, ?n < ?n max (see table 14 ) reference voltage vref 801 vref reference voltage i(vref) = -1 ma ... +1 ma 48 52 % vdda oscillator a01 fosc() oscillator frequency presented at scl with subdivision of 2048; vdda = vdd = 5 v 10 % 52 90 mhz vdda = vdd = 5 v 60 72 83 mhz a02 tcosc oscillator frequency tempera- ture drift vdda = vdd = 5 v -0.1 %/k a03 vcosc oscillator frequency power sup- ply dependance +10.6 %/v p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 7/ 26 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. zero comparator b01 vos() input offset voltage v() = vcm() -20 20 mv b02 iin() input current v() = 0 v ... vdda -50 50 na b03 vcm() common-mode input voltage range 1.4 vdda- 1.5 v b04 vdm() differential input voltage range 0 vdda v incremental outputs a, b, z and 2w interface output dat d01 vs()hi saturation voltage hi vs()hi = vdd - v(); i() = -4 ma 0.4 v d02 vs()lo saturation voltage lo i() = 4 ma 0.4 v d03 tr() rise time cl() = 50 pf 60 ns d04 tf() fall time cl() = 50 pf 60 ns d05 rl() permissible load at a, b tma = 1 (calibration mode) 1 m
2w interface: clock input clk, programming enable nprg e01 vt()hi threshold voltage hi 2 v e02 vt()lo threshold voltage lo 0.8 v e03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv e04 ipu(clk) pull-up current in clk v() = 0 ... vdd - 1 v -240 -120 -25 a e05 ipd(nprg) pull-down current in nprg v() = 1 ... vdd 20 120 300 a e06 fclk(clk) permissible clock frequency at clk ssi protocol 4 mhz biss b/c or c unidir. protocols 10 mhz register communication (nprg = lo) 0.25 mhz e07 tp(clk- dat) propagation delay: clk edge vs. dat output rl(dat) 1 k
(see fig. 4) 10 50 ns e08 tbusy() processing time 0 0 0 e09 tbusy()r processing time register com- munication (start bit delay) nprg = lo; with read access to eeprom 2 ms e10 tidle() interface blocking time nprg = lo; powering up with no eeprom 1 1.5 ms eeprom interface, control logic: inputs sda, nerr f01 vt()hi threshold voltage hi 2 v f02 vt()lo threshold voltage lo 0.8 v f03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv f04 tbusy()cfg duration of startup con?guration error free eeprom access 5 7 ms eeprom interface, control logic: outputs sda, scl, nerr g01 f() write/read clock at scl 20 100 khz g02 vs()lo saturation voltage lo i() = 4 ma 0.45 v g03 ipu() pull-up current v() = 0 ... vdd - 1 v -600 -300 -75 a g04 ft() fall time cl() = 50 pf 60 ns g05 tmin()lo error signal indication time at nerr (lo signal) clk = hi (keine datenausgabe), amplitude or frequeny error 10 ms g06 tpwm() error signal pwm cycle duration at nerr fosc() subdivided 2 22 60.7 ms g07 rl() permissible load at sda, scl tma = 1 (calibration mode) 1 m
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IC-NQI 13-bit sin/d converter with calibration rev a2, page 8/ 26 characteristics: diagrams figure 1: de?nition of relative angle error. figure 2: de?nition of minimum transition distance. figure 3: typical residual absolute angle error after calibration. p r e l i m i n a r y p r e l i m i n a r y twhi()/t aarel 10% 60% 50% 40% 0% 110% aarel 10% 90% 100% 0% $ t mtd 0 90 180 270 360 -0.15 -0.1 -0.05 0 0.05 0.1 0.15
IC-NQI 13-bit sin/d converter with calibration rev a2, page 9/ 26 operating requirements: 2w interface operating conditions: vdd = 5 v 10 %, ta = -25 ... 85 c; input levels lo = 0 ... 0.45 v, hi = 2.4 v ... vdd item symbol parameter conditions fig. unit no. min. max. serial data output: ssi (pin nprg = hi, selssi = 1) i001 t clk permissible clock period cfgtos = 0x01 4 250 2x t tos ns i002 t clkh clock signal hi level duration 4 25 t tos ns i003 t clkl clock signal lo level duration 4 25 t tos ns serial data output: biss b, biss c unidir. (pin nprg = hi, selssi = 0, bissmod = 0 resp. 1) i004 t clk permissible clock period cfgtos selected in accordance with table 31 5, 6 100 2x t tos ns i005 t clkh clock signal hi level duration 5, 6 25 t tos ns i006 t clkl clock signal lo level duration 5, 6 25 t tos ns bidirectional register communication (pin nprg = lo) i007 t clk permissible clock period cfgtor selected in accordance with table 31 7 4 s i008 t clkh clock signal hi level duration 7 t tor ns i009 t clkh clock signal hi level duration read out of register data 7 30 70 % tclk i010 t clkl clock signal lo level duration 7 inde?nite i011 t clk0h "logic 0" hi level duration 7 10 30 % tclk i012 t clk1h "logic 1" hi level duration 7 70 90 % tclk figure 4: serial ssi data output (nprg = hi). figure 5: serial biss b data output (nprg = hi). figure 6: serial biss c unidir. data output (nprg = hi). figure 7: bidirectional register communication (nprg = lo). p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 10/ 26 parameter and register register description . . . . . . . . . . . . . . . . . . . . . . . page 10 signal conditioning . . . . . . . . . . . . . . . . . . . . . . . page 11 gain: gain select sinoffs: offset calibration sine cosoffs: offset calibration cosine refoffs: offset calibration reference ratio: amplitude calibration phase: phase calibration converter function . . . . . . . . . . . . . . . . . . . . . . . . page 12 selres: resolution hys: hysteresis fctr: max. permissible converter frequency incremental signals . . . . . . . . . . . . . . . . . . . . . . . page 15 cfgabz: output a, b, z rot: direction of rotation cbz: period counter con?guration enresdel: output turn-on delay zpos: zero signal position cfgz: zero signal length cfgab: zero signal logic signal monitoring and error messages . . . . . . . . . . . . . . . . . . . . . . . page 17 selampl: amplitude monitoring, function ampl: amplitude monitoring, thresholds aerr: amplitude error ferr: frequency error test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18 tmode: test mode tma: analog test mode biss interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 cfgtos: interface timeout cfgtor: interface timeout m2s: period counter output bissmod: protocol version selssi: ssi compatibility cfgssi: ssi output rpl: register protection settings overview adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 bissmod m2s(1:0) selres(4:0) 0x01 hys(2:0) zpos(4:0) 0x02 enresdel selssi rot cbz cfgabz(1:0) cfgz(1:0) 0x03 cfgssi(1:0) cfgab(1:0) rpl(1:0) aerr ferr 0x04 fctr(7:0) 0x05 fctr(14:8) 0x06 cfgtor(1:0) cfgtos(1:0) tmode(2:0) tma 0x07 reserved address / internal use (programming to zero recommended) 0x08 gain(3:0) ratio(3:0) 0x09 sinoffs(7:0) 0x0a cosoffs(7:0) 0x0b phase(5:0) refoffs ratio(4) 0x0c selampl ampl(1:0) 0x0d 0x0e 0x0f crc(7:0) check sum over address 0-14 with crc polynomial: "100100111" (read out of eeprom) eeprom 0x10 - 0x1f 0x00 - 0xf eeprom register section for device con?guration 0x20 - 0x77 0x10 - 0x67 free eeprom registers 0x78 - 0x7f 0x68 - 0x6f eeprom: biss identi?er, rom: device id IC-NQI v3: 4e 51 56 33 {adr0} 00 69 43 as no access protections are selected all registers are accessible by read and write operations (see rpl). table 5: register layout p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 11/ 26 signal conditioning input stages sin and cos are con?gured as instru- mentation ampli?ers. the ampli?er gain must be se- lected in accordance with the sensor signal level and programmed to register gain according to the follow- ing table. half of the supply voltage is output to vref as center voltage to help dc level adaptation. gain adr 0x08, bit 7:4 sine/cosine input signal levels vin() amplitude average value (dc) code ampli?cation differential single-ended differential single-ended 0x0f 80.000 up to 50 mvpp up to 100 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0e 66.667 up to 60 mvpp up to 120 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0d 53.333 up to 75 mvpp up to 0.15 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0c 40.000 up to 0.1 vpp up to 0.2 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0b 33.333 up to 0.12 vpp up to 0.24 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0a 28.571 up to 0.14 vpp up to 0.28 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x09 26.667 up to 0.15 vpp up to 0.3 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x08 20.000 up to 0.2 vpp up to 0.4 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x07 14.287 up to 0.28 vpp up to 0.56 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.4 v 0x06 10.000 up to 0.4 vpp up to 0.8 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.5 v 0x05 8.000 up to 0.5 vpp up to 1 vpp 0.8 v ... vdda - 1.4 v 1.0 v ... vdda - 1.6 v 0x04 6.667 up to 0.6 vpp up to 1.2 vpp 0.8 v ... vdda - 1.4 v 1.1 v ... vdda - 1.7 v 0x03 5.333 up to 0.75 vpp up to 1.5 vpp 0.9 v ... vdda - 1.5 v 1.3 v ... vdda - 1.9 v 0x02 4.000 up to 1 vpp up to 2 vpp 1.2 v ... vdda - 1.6 v 1.7 v ... vdda - 2.1 v 0x01 3.333 up to 1.2 vpp up to 2.4 vpp 1.2 v ... vdda - 1.7 v 1.8 v ... vdda - 2.3 v 0x00 2.667 up to 1.5 vpp up to 3 vpp 1.3 v ... vdda - 1.8 v 2.0 v ... vdda - 2.6 v table 6: gain select sinoffs adr 0x09, bit 7:0 cosoffs adr 0x0a, bit 7:0 code output offset input offset 0x00 0 v 0 v 0x01 -7.8125 mv -7.8125* mv / gain ... ... ... 0x7f -0.9922 v -0.9922 v / gain 0x80 0 v 0 v 0x81 +7,8125 mv +7.8125 mv / gain ... ... ... 0xff +0.9922 v +0.9922 v / gain notes *) with refoffs = 0x00 und vdda = 5 v. table 7: offset calibration sine/cosine refoffs adr 0x0b, bit 1 code reference voltage 0x00 depending on vdda (example of application: mr sensors) 0x01 not depending on vdda (example of application: sin/cos encoders) table 8: offset calibration reference ratio adr 0x0b, bit 0, adr 0x08, bit 3:0 code cos / sin code cos / sin 0x00 1.0000 0x10 1.0000 0x01 1.0067 0x11 0.9933 ... ... ... ... 0x0f 1.1 0x1f 0.9000 table 9: amplitude calibration phase adr 0x0b, bit 7:2 code phase shift code phase shift 0x00 90 0x20 90 0x01 90.703125 0x21 89.296875 ... ... ... ... 0x12 102.65625 0x32 77.34375 ... 102.65625 ... 77.34375 0x1f 102.65625 0x3f 77.34375 table 10: phase calibration p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 12/ 26 converter functions selres adr 0x00, bit 4:0 code binary resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4304) 0x00 - 0x01 - 0x02 - 0x03 8192 158 hz, 635 hz 0x04 4096 317 hz, 1.27 khz 0x05 2048 634 hz, 2.54 khz 0x06 1024 1.27 khz, 5.1 khz 0x07 512 2.54 khz, 10.2 khz 0x08 256 5.1 khz, 20.3 khz 0x09 128 10.2 khz, 40.6 khz 0x0a 64 20.3 khz, 81.3 khz 0x0b 32 40.6 khz, 162.5 khz 0x0c 16 81.3 khz (max. 250 khz @ 0x4202) 0x0d 8 162 khz (max. 250 khz @ 0x4102) 0x0e - 0x0f - table 11: binary resolutions selres adr 0x00, bit 4:0 code decimal resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4304) 0x10 2000 650 hz, 2.6 khz 0x11 1600 812 hz, 3.3 khz 0x12 1000 1.3 khz, 5.2 khz 0x13 800 1.6 khz, 6.5 khz 0x14 500 2.6 khz, 10.4 khz 0x15 400 3.2 khz, 13 khz 0x16 250 *1 5.2 khz, 20.8 khz 0x17 125 *1,2 5.2 khz, 20.8 khz 0x18 320 4.1 khz, 16.3 khz 0x19 160 *2 4.1 khz, 16.3 khz 0x1a 80 *4 4.1 khz, 16.3 khz 0x1b 40 *8 4.1 khz, 16.3 khz 0x1c 200 6.5 khz, 26 khz 0x1d 100 *2 6.5 khz, 26 khz 0x1e 50 *1,4 6.5 khz, 26 khz 0x1f 25 *1,8 6.5 khz, 26 khz notes *1 not useful with increment a quad b output. *2,4,8 the internal converter resolution is higher by factor 2, 4 or 8. table 12: decimal resolutions hys adr 0x01, bit 7:5 code hysteresis in degree hysteresis in lsb absolute error* 0x00 0 0x01 0.0879 1 lsb @ 12 bit 0.044 0x02 0.1758 1/2 lsb @ 10 bit 0.088 0x03 0.3516 1 lsb @ 10 bit 0.176 0x04 0.7031 1/2 lsb @ 8 bit 0.352 0x05 1.4063 1 lsb @ 8 bit 0.703 0x06 5.625 2.813 0x07 45 only recommended for calibration 22.5 notes *) the absolute error is equivalent to one half the angle hysteresis table 13: hysteresis p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 13/ 26 maximum converter frequency the converter frequency automatically adjusts to the value necessary for the input frequency and resolution. this value ranges from zero to a maximum dependent on the oscillator frequency which can be set using reg- ister fctr. serial data output for serial data output the possible maximum converter frequency can be adjusted to suit the maximum in- put frequency; an automatic converter resolution step- down feature can be enabled via the fctr register. should the input frequency exceed the frequency limit of the selected converter resolution, the lsb is kept stable and not resolved any further; the interpolation resolution halves. if the next frequency limit is overshot, the lsb and the lsb+1 are kept stable and so on. when the input fre- quency again sinks below this frequency limit, the ?ne resolution automatically returns. maximum converter frequency for serial data output resolution protocol max. input frequency restrictions examples* requirements at high input frequencies ?n max [khz] at resol. fctr min. res. bin dec biss ssi ?n max 8192 1024 200 0x0004 x x x x fosc()min / 40 / resolution C 0.16 1.27 6.5 0x4102 8 x x x x fosc()min / 24 / resolution rel. angle error 2x increased 0.26 2.1 10.8 0x4202 16 x x x x 2 x fosc()min / 24 / res. rel. angle error 4x increased 0.53 4.2 21.6 0x4303 32 x x x x 4 x fosc()min / 32 / res. rel. angle error 8x increased 0.78 6.2 32.0 0x4602 32 x - x x 4 x fosc()min / 24 / res. resolution lowered by factor of 2 1.1 8.5 - 0x4a02 64 x - x x 8 x fosc()min / 24 / res. res. lowered by factor of 2-4 2.1 16.9 - 0x4e02 128 x - x x 16 x fosc()min / 24 / res. res. lowered by factor of 2-8 4.2 33.8 - 0x5202 256 x - x x 32 x fosc()min / 24 / res. res. lowered by factor of 2-16 8.5 67.7 - 0x5602 512 x - x x 64 x fosc()min / 24 / res. res. lowered by factor of 2-32 16.9 135 - 0x5a02 1024 x - x x 128 x fosc()min / 24 / res. res. lowered by factor of 2-64 33.8 250 - 0x5e02 2048 x - x x 256 x fosc()min / 24 / res. res. lowered by factor of 2-128 67.7 - - 0x6202 4096 x - x x 512 x fosc()min / 24 / res. res. lowered by factor of 2-256 135 - - notes *) calculated with fosc()min taken from electrical characteristics item a01. table 14: possible maximum converter frequency for serial data output. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 14/ 26 incremental output to a, b and z there are two criteria which must be considered when setting the maximum possible converter frequency via the fctr register: 1. the maximum input frequency 2. system limitations, e.g. due to slow counters or cable transmission when facing system limitations it is useful to prese- lect a minimum transition distance for the output sig- nals. a digital zero-delay glitch ?lter then takes care of a temporal edge-to-edge separation, guaranteeing spike-free output signals after an esd impact to the sensor, for instance. a serial data output is simultaneously possible at any time. however, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal applied to pin clk. 1. maximum converter frequency de?ned by the maximum input frequency output frequency resolution maximum input frequency restrictions examples* fout @ ?n max requirem. at high input frequencies ?n max [khz] at resol. fctr a, b bin dec ?n max 8192 1024 200 0x0004 325 khz x x fosc()min / 40 / resolution none 0.16 1.27 6.5 0x4102 542 khz x x fosc()min / 24 / resolution relative angle error 2x increased 0.26 2.1 10.8 0x4202 1.08 mhz x x 2 x fosc()min / 24 / res. relative angle error 4x increased 0.53 4.2 21.6 0x4303 1.6 mhz x x 4 x fosc()min / 32 / res. relative angle error 8x increased 0.78 6.2 32.0 notes *) calculated with fosc()min taken from electrical characteristics item a01. table 15: possible maximum converter frequency for incremental a/b/z output, de?ned by the maximum input frequency 2. maximum converter frequency de?ned by the minimum transition distance output frequency resolution minimum transition distance restrictions example* fout @ t mtd requirem. at a, b at high input frequencies t mtd [sec] fctr a, b bin dec t mtd 0x00ff 10 khz x x 2048 / fosc()max none 22.8 0x00fe 10.05 khz x x 2040 / fosc()max none 22.7 0x00fd 10.09 khz x x 2032 / fosc()max none 22.6 ... ... ... ... ... ... ... 0x0006 366 khz x x 56 / fosc()max none 0.62 0x0005 427 khz x x 48 / fosc()max none 0.53 0x0004 512 khz x x 40 / fosc()max none 0.44 0x4102 854 khz x x 24 / fosc()max relative angle error 2x increased 0.27 0x4202 1.7 mhz x x 12 / fosc()max relative angle error 4x increased 0.13 0x4303 2.8 mhz x x 8 / fosc()max relative angle error 8x increased 0.09 notes *) calculated with fosc()max taken from el.char. item a01; the min. transition distance refers to output a vs. output b without reversing the sense of rotation. table 16: possible maximum converter frequency for incremental a/b/z output, de?ned by the minimum transition distance p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 15/ 26 incremental signals cfgabz adr 0x02, bit 3:2 code mode a b z 0x00 normal a b z 0x01 control signals for external period counters ca cb cz 0x02 calibration mode offset+phase the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 8: offset sin* figure 9: offs. cos* figure 10: phase* 0x03 calibration mode offset+amplitude the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 11: offset sin* figure 12: offs. cos* figure 13: amplit.* notes *) trimmed accurately when duty cycle is 50 %; recommended trimming order (after selecting gain): offset, phase, amplitude ratio, offset; table 17: outputs a, b, z rot adr 0x02, bit 5 code code direction 0x00 ascending order, b then a 0x01 descending order, a then b table 18: code direction cbz adr 0x02, bit 4 code clear by zero 0x00 disabled 0x01 enabled table 19: reset enable for period counter enresdel adr 0x02, bit 7 code output* function 0x00 immediately an external counter displays the absolute angle following power on. 0x01 after 5 ms an external counter only displays changes vs. the initial power-on condition (moving halted to reapply power is precondition.) notes *) output delay after device con?guration and internal reset. table 20: output turn-on delay a, b, z figure 14: clear by zero function of the period counter when enabled by cbz = 1. example for resolution 64 (sel- res = 0x0a), zero signal at 45 (zpos = 0x04, cfgab = 0x00) and the direction of rotation not inverted (rot = 0x00, cos leads sin). p r e l i m i n a r y p r e l i m i n a r y -180 -90 0 45 90 180 sin cos 000000 ab z p(23:0) ccw: 0->f ffffff cw: f->0
IC-NQI 13-bit sin/d converter with calibration rev a2, page 16/ 26 zpos adr 0x01, bit 4:0 code position 0x00 0 0x08 90 0x10 180 0x18 270 0x01 11.25 (1 x 11.25) ... ... 0x1f 348.75 (31 x 11.25) notes the zero signal is only output if released by the input pins (for instance with pzero = 5 v, nzero = vref). table 21: zero signal position cfgz adr 0x02, bit 1:0 code length 0x00 90 0x01 180 0x02.. 03 synchronization table 22: zero signal length cfgab adr 0x03, bit 5:4 code z = 1 for 0x00 b = 1, a = 1 0x01 b = 0, a = 1 0x02 b = 1, a = 0 0x03 b = 0, a = 0 table 23: zero signal logic figure 15: incremental output signals for various length of the zero signal. example for resolution 64 (selres = 0x0a), a zero signal position of 45 (zpos = 0x04, cf- gab = 0x00) and no reversal of the rotational sense (rot = 0x00, cos leads sin). p r e l i m i n a r y p r e l i m i n a r y -180 -90 0 45 90 180 winkel sin cos a b z (cfgz= 1) z (cfgz= 2) z (cfgz= 0)
IC-NQI 13-bit sin/d converter with calibration rev a2, page 17/ 26 signal monitoring and error messages selampl ampl adr 0x0c, bit 2 adr 0x0c, bit 1:0 max ( |sin| , |cos| ) for selampl = 0 code voltage threshold v th output amplitude* 0x00 0.60 x vdda 1.4 v pp 0x01 0.64 x vdda 2.0 v pp 0x02 0.68 x vdda 2.6 v pp 0x03 0.72 x vdda 3.1 v pp sin 2 + cos 2 for selampl = 1 code v thmin $ v thmax output amplitude* 0x04 0.48 $ 0.68 x vdda 2.4 v pp $ 3.4 v pp 0x05 0.56 $ 0.76 x vdda 2.8 v pp $ 3.8 v pp 0x06 0.64 $ 0.84 x vdda 3.2 v pp $ 4.2 v pp 0x07 0.72 $ 0.92 x vdda 3.6 v pp $ 4.6 v pp notes *) entries are calculated with vdda = 5 v. table 24: signal amplitude monitoring figure 16: signal monitoring of minimum amplitude. figure 17: sin 2 + cos 2 signal monitoring. aerr adr 0x03, bit 1 code amplitude error message 0x00 disabled 0x01 enabled table 25: amplitude error ferr adr 0x03, bit 0 code excessive frequency error message 0x00 disabled 0x01 enabled note input frequency monitoring is operational for resolutions 16 table 26: frequency error con?guration error - messaging always released table 27: con?guration error error keys failure mode pin nerr error bits e1, e0 with biss and ssi no error hi 11 amplitude error lo/hi = 75 % (aerr = 0: hi) 01 (11) frequency error lo/hi = 50 % (ferr = 0: hi) 10 (11) con?guration lo 00 undervoltage lo 00 system error nerr = low caused by an external error signal 00 table 28: error keys each phase in the con?guration process is signaled by nerr = low; the signal is only reset following a suc- cessful crc (cyclic redundancy check). if the data transfer from the eeprom is faulty and the crc unsuccessful, then the con?guration phase is au- tomatically repeated. the process aborts following a third unsuccessful attempt and the error message out- put remains set to low. to enable the successful diagnosis of faults other types of error are signaled at nerr using a pwm code as given in the key on the left. two error bits are provided for error messaging via the serial 2-wire interface; these bits can decode four dif- ferent types of error. if nerr is held at low by an ex- ternal source, such as an error message from the sys- tem, for example, this can also be veri?ed via the serial 2-wire interface. error events are stored for the serial data output and deleted afterwards. errors at nerr are displayed for a minimum of ca. 10 ms, as far as no serial data readout causes a deletion. if an error in amplitude occurs the conversion pro- cess is terminated and the incremental output signals halted. an error in amplitude rules out the possibility of an error in frequency. p r e l i m i n a r y p r e l i m i n a r y vss vth vthmin vthmax
IC-NQI 13-bit sin/d converter with calibration rev a2, page 18/ 26 test functions tmode adr 0x06, bit 3:1 code signal at z description 0x00 z no test mode 0x01 a xor b output a exor b 0x02 enclk ic-haus device test 0x03 nlock ic-haus device test 0x04 clk ic-haus device test 0x05 divc ic-haus device test 0x06 pzero - nzero ic-haus device test 0x07 tp ic-haus device test condition cfgabz = 0x00 table 29: test mode tma adr 0x06, bit 0 code pin a pin b pin sda pin scl 0x00 a b sda scl 0x01 cos+ cos- sin+ sin- notes to permit the veri?cation of gain and offset settings, the input ampli?er outputs are available at the pins. to operate the converter a signal of 4 vpp is the ideal here and should not be exceeded. pin loads above 1 m
are adviceable for accurate measurements. eeprom access is not possible during mode tma. table 30: analog test mode figure 18: calibrated signals during analog test mode. parameter gain ideally adjusts the signal levels to ca. 4 vpp and should not be touched afterwards. both scope display modes are feasible for offs (pos- itive values) or ratio adjustments; regarding the ad- justment of phase the x/y mode may be preferred. for offs adjustment towards negative values the test signals cos- (pin b) and sin- (pin scl) are relevant. p r e l i m i n a r y p r e l i m i n a r y sda: sin+ a: cos+ 5 v x/y 0 v 1 v/div vert. 1 v/div hor. y/t 1 v/div vert.
IC-NQI 13-bit sin/d converter with calibration rev a2, page 19/ 26 serial 2-wire interface depending on the programming enable at pin nprg the serial 2-wire interface supports either a fast cyclic data output of the angle position and period counter data (for nprg = 1), or bidirectional register communi- cation for device programming, with write and read ac- cess to ram and eeprom registers (for nprg = 0). two timeouts are used that prescribe a default mini- mum clock frequency of f(clk)min for the master: sen- sor mode timeout ttos and register mode timeout ttor. for data to be transferred to the interface conversion is halted for one clk pulse from latch . this time must be taken into consideration with low clock frequencies when calculating the maximum permissible input fre- quency. as long as the con?guration error is active, the longest respective timeouts are set regardless of cfgtos or cfgtor. cfgtos adr 0x06, bit 5:4 code timeout t tos data output ref. clock counts f(clk) min* 0x00 typ. 128 s 256-259 11 khz 0x01 typ. 16 s 32-35 88 khz 0x02 typ. 4 s 8-11 352 khz 0x03 typ. 1 s 2-5 1.41 mhz cfgtor adr 0x06, bit 7:6 code timeout t tor programming ref. clock counts f(clk) min* 0x00 typ. 1 ms 2049-2060 1.4 khz 0x01 typ. 256 s 513-514 5.5 khz 0x02 typ. 32 s 67-68 42 khz 0x03 not permitted C C notes a ref. clock count is equal to 32 fosc (see el. char. a01). the permissible max. clock frequency is speci?ed by item e06. table 31: 2-wire interface timeout serial data output the position data provided by IC-NQI can contain the following data values: period counter (p), angle data (s), two error bits (e1, e0), and 5 or 6 crc bits. signal names name description p(23:0) period counter (0, 8, 12 or 24 bit) s(12:0) angle data (3 to 13 bit) e1 error bit (amplitude error) e0 error bit (frequency error) (0) zero bit(s) crc(5:0) crc bits, inverted output, 5 or 6 bits polynomial x 5 + x 2 + x 0 (0x25, resp. 100101) polynomial x 6 + x 1 + x 0 (0x43, resp. 1000011) with period counter output of 12 or 24 bit table 32: signal names figure 19: output with ssi protocol (error bits optional) figure 20: output with biss b protocol figure 21: output with biss c unidirectional proto- col p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 20/ 26 four parameters are relevant when setting the output protocol and data content; selssi and bissmod se- lect the protocol version, and m2s and cfgssi de?ne the optional data content. selssi adr 0x02, bit 6 code description 0x00 data output biss compatible 0x01 data output with ssi protocol (in binary format, msb ?rst) table 33: protocol version bissmod adr 0x00, bit 7 code description 0x00 data output biss b or ssi 0x01 data output biss c unidirectional table 34: protocol version m2s adr 0x00, bit 6:5 code data length crc poly. zero bit 0x00 - 0x25 yes 0x01 p(7:0) 0x25 yes 0x02 p(11:0) 0x43 yes 0x03 p(23:0) 0x43 no table 35: period counter output cfgssi adr 0x03, bit 7:6 code additional bits ring register operation 0x00 e1, e0, zero bit no 0x01 none no 0x02 e1, e0, zero bit yes 0x03 none yes table 36: output options for ssi protocol figure 22: ring operation with ssi protocol. examples of data output with ssi protocol ssi output formats 13-bit ssi res mode error crc t1 t2 t3 t4... t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 10 bit ssi x - s9 s8 s7 s6 ... s0 e1 e0 0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 0 13 bit ssi *1 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 ssi-r *2 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 example 0 25-bit ssi 13 bit ssi x - s12 s11 s10 s9 ... s3 s2 s1 s0 e1 e0 0 stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 8 + 13 bit *3 ssi x - p7 p6 p5 p4 ... p0, s12, s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 e1 e0 0 stop example 0 0 con?guration nprg = 0, selssi = 1, m2s = 0x00, cfgssi = 0x00, unless otherwise noted. *1 cfgssi = 0x01; *2 cfgssi = 0x03; *3 m2s = 0x01 caption ssi = ssi protocol ssi-r = ssi ring operation table 37: ssi output formats p r e l i m i n a r y p r e l i m i n a r y p7 clk dat p0 s12 s0 stop p7 p0 s12 s0 stop msb lsb msb lsb msb lsb msb lsb cycle latch timeout
IC-NQI 13-bit sin/d converter with calibration rev a2, page 21/ 26 bidirektional register communication the bidirectional programming mode for write and read access to ram and eeprom registers is active for pin nprg = 0. data is transmitted coded as a pwm which makes a simple transfer of clock pulse and data to the master clock line possible. a duty cycle of 75 % repre- sents a logic one, a duty cycle of 25 % a logic zero. the addressing sequence consists of a start bit (1), the device address (slave id 000), the register ad- dress (7 bits), a write/read bit wnr (1 for write, 0 for read), a 4-bit crc, and a stop bit (0). the generator polynomial for the 4-bit crc is 0x13 (or 10011); the crc bits are transmitted in inversion. register communication: read the master carries out the addressing sequence with the wnr bit at 0 and subsequently supplies at least 14 clock pulses. IC-NQI responds with a start bit (1), the addressed register byte (data(7...0)), a 4-bit crc (ncrc(3...0)), and a stop bit (0). the generator poly- nomial for the 4-bit crc is also 0x13 (or 10011) and the crc bits are again transmitted in inversion. when reading out the internal registers IC-NQI does not require any processing time and responds immedi- ately with the addressed register data. when reading the external eeprom registers, output of the start bit is delayed until data is available from the eeprom. during this wait period the master must continue the clock output. figure 23: register communication: read register communication: write to write data to a register the master carries out the addressing sequence with the wnr bit set to 1. after the second start bit the master transmits the data to be written which IC-NQI returns bit by bit one clock pulse later for veri?cation. the 8 bits of write data are antici- pated by a 4-bit crc (as before) and also returned by IC-NQI, this time not coded as a pwm, however. if access to the addressed register is protected, neither the start bit nor data are returned (the master ends the clock output after ca. 20 ms). data is transferred to eeprom registers in the back- ground and can be veri?ed by a read access once transmission has ?nished. write access to address 0 triggers an internal reset. this enables the period counter to be set to zero and the con?guration error deleted; the eeprom is not read out again. figure 24: register communication: write as long as the con?guration error is active, IC-NQI uses the longest respective timeouts regardless of cfgtos or cfgtor and ignores possible protec- tive settings from rpl. when programming for the ?rst time, the following addressing sequence is thus rec- ommended: ?rst addresses 1 to 12 and then address 0. rpl adr 0x03, bit 3:2 rpl con?guration addr 0-31 user addr 32-119 biss identi?er addr 120-127 0x00 read / write read / write read / write 0x01 read read / write read 0x02 - read / write read 0x03 - read read table 38: register protection settings p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 22/ 26 eeprom interface serial eeprom components permitting operation from 3.3 v to 5 v can be connected (such as 24c02, for example). when the device is switched on the memory area of bytes 0 to 15 is mapped onto IC-NQIs regis- ters. for register communication with the eeprom an ad- dress offset of 16 bytes must be taken into account; addresses 16-127 are destined for the eeprom bytes of addresses 0-111. if no eeprom is connected, IC-NQI does not re- spond to addresses 16-119; reading addresses 120- 127 transmits the device id. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 23/ 26 application hints principle input circuits figure 25: input circuit for voltage signals of 1 vpp with no ground reference. when grounds are not separated the connection nsin to vref must be omitted. figure 26: input circuit for current signals of 11 a. figure 27: input circuit for single-side voltage or cur- rent source signals with ground refer- ence (adaptation via resistors r3, r4). figure 28: simpli?ed input wiring for single-side voltage signals with ground reference. figure 29: input circuit for differential current sink sensor outputs, eg. using opto encoder ic-wg. figure 30: combined input circuit for 11 a, 1 vpp (with 120
termination) or ttl encoder signals. rs3/4 and cs1 serve as protec- tion against esd and transients. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 24/ 26 basic circuits figure 31: circuit for evaluation of magneto-resistor bridge sensors with inremental output. figure 32: circuit for evaluation of magneto-resistor bridge sensors with serial data output. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 25/ 26 evaluation board the IC-NQI device is equipped with an evaluation board for test purposes; descriptions are available sep- arately. design review: notes on chip functions IC-NQI v3 no. function, parameter/code description and application hints 1 selres illegal setting: 0x0e for resolution 4 a minimal resolution of 8 is required for the frequency monitoring function and period counting as well. thus, a binary resolution of 4 is not permitted when using the period counter and the serial interface for data output with the biss or ssi protocol. a resolution of 4 may be used for solely incremental applications with a/b/z output, what then requires the deactivation of the frequency monitoring function (by ferr set to 0x00). table 39: notes on chip functions regarding IC-NQI chip release v3 ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. p r e l i m i n a r y p r e l i m i n a r y
IC-NQI 13-bit sin/d converter with calibration rev a2, page 26/ 26 ordering information type package order designation IC-NQI tssop20 4.4 mm IC-NQI tssop20 IC-NQI tssop20 et -40/125 evaluation board IC-NQI eval nq7d for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners p r e l i m i n a r y p r e l i m i n a r y

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