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w24l11 128k 8 cmos static ram publication release date: a ugust 7, 2001 - 1 - revision a4 general description the w24l11 is a normal - speed, very low - power cmos static ram organized as 131072 8 bits that operates on a wide voltage range from 3.3v to 5v power supply. this device is manufactured using winbond's high performance cmos technology. features low power consumption access time: 55/70 ns 3.3v/5v power supply fully static operation all inputs and outputs directly ttl compatible three - state outputs battery back - up operation capability data retention voltage: 2v (min.) packaged 450 mil sop, standard type one, tsop (8 mm 20 mm), small type one and tsop (8 mm 13.4 mm) pin configurations block diagram v a8 a9 #we 1 2 3 4 5 2 4 2 5 2 6 2 7 2 8 nc a7 a6 a5 a12 a4 a3 a2 a1 6 7 8 9 2 0 2 1 2 2 2 3 a11 #oe a 1 0 #cs1 i / o 8 i / o 7 i / o 6 i / o 5 1 0 1 1 1 2 1 3 1 6 1 7 1 8 1 9 a0 i / o 2 i / o 3 i / o 1 1 4 1 5 i / o 4 a13 v a14 a16 3 2 3 1 3 0 2 9 a15 cs2 dd ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 a10 i/o7 i/o6 i/o5 i/o4 32-pin tsop 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 i/o8 a15 a12 a7 a6 a5 a4 v cs2 a13 a8 dd a11 a9 nc a14 a16 v ss i/o3 i/o2 i/o1 32-pin sop #we #oe #cs1 core cell array 1024 rows 128 x 8 columns data cntrl. clk gen. r o w d e c o d e r a15 i/o ckt. column decoder #we #oe clk gen. precharge ckt. a13 a8 a1 a0 a11 a10 #cs1 cs2 a16 a14 a12 a4 a3 a2 a7 a6 a5 a9 i/o1 i/o8 : pin description symbol description a0 - a16 a ddress inputs i/o1 - i/o8 data inputs/outputs #cs1, cs2 chip select input #we write enable input #oe output enable input v dd power supply v ss ground nc no connection
w24l11 - 2 - truth table #cs1 cs2 #oe #we mode i/o1 - i/o8 v dd current h x x x not selected high z i sb , i sb1 x l x x not selected high z i sb , i sb1 l h h h output disable high z i dd l h l h read data out i dd l h x l write data in i dd dc characteristics absolute maximum ratings rating parameter 3.3v 5v unit supply voltage to v ss potential - 0.5 to +4.6 - 0.5 to +7.0 v input/output to v ss potential - 0.5 to v dd +0.5 v allowable power dissipation 1.0 w storage temperature - 65 to +150 c operating temperature l/ll 0 to 70 c le - 20 to 85 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. operating characteristics (v dd = 5v 10%; v dd = 3.3v 5%; v ss = 0v; t a ( c) = 0 to 70 for ll, - 20 to 85 for le) parameter sym. test conditions min. max. unit 3.3v - 0.5 +0.6 input low voltage v il - 5v - 0.5 +0.8 v input high voltage v ih - +2.0 v dd +0.5 v input leakage current i li v in = v ss to v dd - 1 +1 m a output leakage current i lo vi/o = v ss to v dd , #cs1 = v ih (min.) or cs2 = v il (max.) or #oe = v ih (min.) or #we = v il (max.) - 1 +1 m a output low voltage v ol i ol = +2.1 ma - 0.4 v
w24l11 publication release date: august 7, 2001 - 3 - revision a4 operating characteristics, continued 3.3v 5v parameter sym. test conditions min. max. min. max. unit output high voltage v oh i oh = - 1.0 ma 2.2 - 2.4 - v 55 - 50 - 80 operating power supply current i dd #cs1= vil (max.) and cs2 = vih (min.), i/o = 0 ma, cycle = min. duty =100% 70 - 40 - 70 ma standby power supply current i sb #cs1 = v ih (min.) or cs2 = v il (max.) cycle = min. duty = 100% - 1 - 3 ma i sb1 #cs1 3 vdd - 0.2v ll/le - 50 - 50/70 m a or cs2 0.2v l - 100 - 100 note: typical parameter is measured under ambient temperature t a = 25 c and v dd = 3.3v/5v capacitance (v dd = 5v 10%; v dd = 3.3v 5%, t a = 25 c, f = 1 mhz) parameter sym. conditions max. unit input capacitance c in v in = 0v 6 pf input/output capacitance c i/o v out = 0v 8 pf note: these parameters are sampled but not 100% tested. ac characteristics ac test condi tions parameter conditions input pulse levels 0v to 3.0v input rise and fall times 5 ns input and output timing reference level 1.5v output load see the drawing below ac test loads and waveform 90% 90% 5 ns 10% 5 ns 10% output output 3.0 v 0 v 100 pf including jig and scope 5 pf including jig and scope 1 ttl 1 ttl clz, olz, chz, ohz, whz, ow (for t t t t t t )
w24l11 - 4 - ac characteristics, continued (v dd = 5 v 10%; v dd = 3.3v 5%; v ss = 0v; t a ( c) = 0 to 70 for ll, - 20 to 85 for le) read cycle 3.3v/5v parameter sym. 55 70 unit min. max. min. max. read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select access time t acs - 55 - 70 ns output enable to output valid t aoe - 30 - 35 ns chip selection to output in low z t clz * 10 - 10 - ns output enable to output in low z t olz * 5 - 5 - ns chip deselection to output in high z t chz * - 25 - 30 ns output disable to output in high z t ohz * - 25 - 30 ns output hold from address change t oh 10 - 10 - ns * these parameters are sampled but not 100% tested write cycle 3.3/5v parameter sym. 55 70 unit min. max. min. max. write cycle ti me t wc 55 - 70 - ns chip selection to end of write t cw 40 - 50 - ns address valid to end of write t aw 40 - 50 - ns address setup time t as 0 - 0 - ns write pulse width t wp 45 - 50 - ns write recovery time #cs1, cs2 , #we t wr 0 0 - ns data valid to end of write t dw 40/25 - 45/30 - ns data hold from end of write t dh 0 - 0 - ns write to output in high z t whz * - 25 - 25 ns output disable to output in high z t ohz * - 25 - 25 ns output active from end of write t ow 5 - 5 - ns * these parameters are sample d but not 100% tested
w24l11 publication release date: august 7, 2001 - 5 - revision a4 timing waveforms read cycle 1 (address controlled) address t rc t aa t oh t oh d out read cycle 2 (chip select controlled) d out #cs1 t clz t acs chz t cs2 read cycle 3 (output enable controlled) address t rc #cs1 t aa #oe t aoe t olz t oh t acs d out clz t chz t t ohz cs2
w24l11 - 6 - timing waveforms, continued write cycle 1 address #oe t wc t wr #we d out d in t wp t as t ohz (1, 4) t dw t dh t aw #cs1 t cw cs2 write cycle 2 (#oe = v il fixed) #we d out d in t as t dh t wp t whz dw t (2) (3) t ow t oh aw t (1, 4) t cw t wr address t wc #cs1 cs2 notes: 1. during this period, i/o pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. the data output from d out are the same as the data wri tten to d in during the write cycle. 3. d out provides the read data for the next address. 4. transition is measured 500 mv from steady state with c l = 5 pf. this parameter is guaranteed but not 100% tested.
w24l11 publication release date: august 7, 2001 - 7 - revision a4 data retention chara cteristics (t a ( c) = 0 to 70 for ll, - 20 to 85 for le) parameter sym. test conditions min. typ. max. unit v dd for data retention v dr #cs1 3 v dd - 0.2v or cs2 0.2v 2.0 - - v data retention current i dddr #cs1 3 v dd - 0.2v or cs2 0.2v, v dd = 3v - - 50 m a chip deselect to data retenti on time t cdr see data retention waveform 0 - - ns operation recovery time t r t rc * - - ns * read cycle time data retention wavef orm t cdr - 0.2v dd v v dd #cs1 t r #cs1 v dr 2v = > = > 0.9 dd v 0.9 dd v cs2 0v cs2 0.2v < = < =
w24l11 - 8 - ordering information part no. access time ( n s) operating voltage (v) operating temperature ( c) standb y current max. ( m a) package w24l11s - 55le 55 3.3v/5v - 20 to 85 50 450 mil sop w24l11t - 55le 55 3.3v/5v - 20 to 85 50 standard type one tsop w24l11q - 55le 55 3.3v/5v - 20 to 85 50 small type one tsop w24l11s - 55ll 55 3.3v/5v 0 to 70 50 450 mil sop w24l11t - 55 ll 55 3.3v/5v 0 to 70 50 standard type one tsop w24l11q - 55ll 55 3.3v/5v 0 to 70 50 small type one tsop w24l11s - 55l 55 3.3v/5v 0 to 70 100 450 mil sop w24l11t - 55l 55 3.3v/5v 0 to 70 100 standard type one tsop w24l11q - 55l 55 3.3v/5v 0 to 70 100 small typ e one tsop w24l11s - 70le 70 3.3v/5v - 20 to 85 50 450 mil sop w24l11t - 70le 70 3.3v/5v - 20 to 85 50 standard type one tsop w24l11q - 70le 70 3.3v/5v - 20 to 85 50 small type one tsop w24l11s - 70ll 70 3.3v/5v 0 to 70 50 450 mil sop w24l11t - 70ll 70 3.3v/5v 0 t o 70 50 standard type one tsop w24l11q - 70ll 70 3.3v/5v 0 to 70 50 small type one tsop w24l11s - 70l 70 3.3v/5v 0 to 70 100 450 mil sop w24l11t - 70l 70 3.3v/5v 0 to 70 100 standard type one tsop w24l11q - 70l 70 3.3v/5v 0 to 70 100 small type one tsop notes : 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a co nsequence of product failure.
w24l11 publication release date: august 7, 2001 - 9 - revision a4 bonding pad diagram x y a16 a14 a12 a7 a6 a4 a11 a8 a13 web v dd v dd 7 a5 cs2 a9 oeb 24 3 4 5 6 6 2 30 31 1 32 28 29 27 26 25 a15 33 17 18 19 a1 a0 i/o0 i/o1 v ss v ss i/o4 i/o5 i/o6 20 a2 12 13 14 15 10 11 21 cs1b 16 i/o7 i/o3 22 a10 23 i/o2 9 a3 8 ac5405 pad no. x y 1 - 485.31 2376.64 2 - 1200.87 2376.64 3 - 1341.05 2376.64 4 - 1480.80 2376.64 5 - 1622.21 2376.64 6 - 1767.47 2376.64 7 - 1993.03 2228.49 8 - 1990.55 - 2275.79 9 - 1789.57 - 2 382.05 10 - 1556.20 - 2382.05 11 - 1405.83 - 2382.05 12 - 1169.73 - 2383.00 13 - 870.28 - 2383.00 14 - 567.65 - 2383.00 15 - 336.94 - 2385.00 16 - 112.55 - 2385.00 17 224.85 - 2383.00 18 497.55 - 2383.00 19 772.25 - 2383.00 20 1044.95 - 2383.00 21 1319.65 - 2383. 00 22 1537.77 - 2382.05 23 1773.94 - 2382.05 24 1985.78 - 2297.62 25 1987.47 2221.27 26 1669.63 2376.64 27 1451.03 2376.64 28 1196.59 2376.64 29 956.65 2376.64 30 219.67 2376.64 31 79.47 2376.64 32 - 145.06 2343.58 33 - 353.56 2343.58 note: for b are chip form (c.o.b.) applications, the substrate must be connected to v dd or left floating in the pcb layout.
w24l11 - 10 - package dimensions 32 - pin sop wide body 1 17 32 16 y e d s seating plane b a a e h l l e e 1 c e 1 1 e a 2 see detail f detail f 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension b does not include dambar protrusion/intrusion. 3. dimensions d & e include mold mismatch and determined at the mold parting line. . notes: 4. controlling dimension: inches 5. general appearance spec should be based on final visual inspection spec. 0.20 0.15 0.008 0.006 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a l e 1 2 e 0.012 0.31 0.118 3.00 0.004 0.101 0.014 0.106 0.016 0.111 0.020 2.57 0.36 0.10 2.69 0.41 2.82 0.51 0.047 0.004 0 10 0.805 0.055 0.817 0.063 1.19 20.45 1.40 20.75 1.60 0.556 0.556 0.546 14.38 14.12 13.87 10 0 0.10 11.43 11.30 11.18 0.450 0.445 0.440 0.58 0.79 0.99 0.023 0.031 0.039 1.12 1.27 1.42 0.044 0.050 0.056 s 0.91 0.036 q q 32 - pin standard type one tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) q min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm q __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 1
w24l11 publication release date: august 7, 2001 - 11 - revision a4 pac kage dimensions, continued 32 - pin small type one tsop a a a 2 1 l l 1 y c e h d d b e 1 controlling dimension: millimeters min. dimension in mm nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d 11.70 13.20 0.675 1.25 0.05 0.15 1.05 1.00 0.95 0.17 0.14 0.30 0.00 0.20 0.27 0.15 0.16 11.80 11.90 13.40 13.60 0.50 0.50 0.70 0.10 0.049 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.0056 0.0059 0.0062 0.461 0.465 0.469 7.90 8.00 8.10 0.311 0.315 0.319 0.520 0.528 0.536 0.020 0.012 0.020 0.028 0.027 0.000 0.004 0.002 0 3 5 0 3 5 q dimension in inches q
w24l11 - 12 - version history version date page description a1 oct. 1999 - initial issued a2 may 2000 1, 2, 8, 9 delete 32 - pin p - dip package; add le in operating characteristics, data retention characteristics & ordering info. 9 add in bonding pad diagram a3 dec. 2000 1, 2, 3, 4, 8 add in 5v specification 1 add access time of 55 ns 3 add operating power supply current of 55 ns 4 add read cycle & writ e cycle of 55 ns a4 august 7, 2001 9 add 55 ns for ordering information headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change without notice.

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