integrated circuit systems, inc. general description features ICS9159-12 frequency generator and buffers for mobile pentium ? systems 9159-12 rev b 071797 block diagram the ICS9159-12 generates all clocks required for mobile microprocessor systems based on pentium/mobile triton chip sets. three different reference frequency multiplying factors are externally selectable with smooth frequency transitions. these multiplying factors can be customized for specific plications. a test mode is provided to drive all clocks directly. high drive bclk outputs provide greater than 1v/ns slew rate into 30pf loads. pclk outputs provide better than 1v/ ns slew rate into 20pf loads while maintaining 5% duty cycle. ? generates 14 clocks including processor, disk and reference ? meets all pentium/mobile triton 82430mx requirments ? independent buffers provide 4 and 6 clock copies ? buffered clocks skew matched to 250ps ? buffer inputs are 5v tolerant ? test clock mode eases system design ? selectable multiplying and processor/bus ratios ? custom configurations available ? 3.0v- 5.5v supply range ? 28pin, .209" ssop package pentium is a trademark of intel corporation. fs1 f s0 *vco x1, ref (mhz) cpu (mhz) 0 0 118/17*x1 1 4.318 50 (49.69) 0 1 65/7*x1 14.318 66.6 (66.47) 1 0 92/11*x1 14.318 60 (59.87) 1 1 test mode tclk tclk/2 cpu 24m vco/2 24 mhz tclk/2 tclk/4 functionality *vco range is limited form 60 - 200 mhz. pin configuration 28-pin ssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9159-12 pin descriptions note: bclk buffers cannot be supplied with 5 volts (pins 14 and 20) if cpu and fixed frequencies (pins 1, 8 and 26) are being supplied with 3 volts. pin number pin name type description 8, 25 vdd pwr power for logic, cpu and fixed frequency output buffers. 1x1 in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 10 - 30 mhz xtal. 2 x2 out xtal output which includes xtal load capacitance. 3 oen in oen tristates all outputs when low. this input has an internal pull-up device. 4 bpin in input to bpin(0:5) buffers. 5 bhin in input to bhin(0:3) buffers. 11, 23 gnd pwr ground for logic, cpu and fixed frequency output buffers. 6, 7, 9, 10 bh(0:3) out buffered copies of the bhin input, typically used to drive the pci device clock inputs at one half the cpu frequency. 13, 12 fs(0:1) in frequency multiplier select pins. see table below. these inputs have internal pull-up devices. 14, 20 vdd pwr power for bclk output buffers. 15, 16, 18 19, 21, 22 bp(0:5) out buffered copies of the bpin input, typically used to drive the host device clock inputs at the cpu frequency. 17 vss pwr ground for bclk output buffers. 24 cpu out the cpu output, which is a multiple of the input reference frequency as shown in the table above. duty cycle is 50/505% with a maximum frequency of 100 mhz. 26 24m out the 24m clock is fixed at 24 mhz. 28, 27 ref(0:1) out ref is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 mhz.
3 ICS9159-12 absolute maximum ratings electrical characteristics at 3.3v supply v oltage .......................................................................................................... 7.0 v logic inputs ....................................................................... gnd ?0.5 v to v dd +0.5 v ambient operating t emperature ............................................................. 0c to +70c storage t emperature ........................................................................... ?65c to +150c v dd = 3.0 ? 3.7 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in =0v - 10.5 28.0 a input high current i ih v in =v dd -5.0 - 5.0 a output low current i ol v ol =0.8v; for pclks & bclks 30.0 47.0 - ma output high current i oh v ol =2.0v; for pclks & bclks - -66.0 -42.0 ma output low current i ol v ol =0.8v; for fixed clks 25.0 38.0 - ma output high current i oh v ol =2.0v; for fixed clks - -47.0 -30.0 ma output low voltage v ol i ol =15ma; for pclks & bclks - 0.3 0.4 v output high voltage v oh i oh =-30ma; for pclks & bclks 2.4 2.8 - v output low voltage v ol i ol =12.5ma; for fixed clks - 0.3 0.4 v output high voltage v oh i oh =-20ma; for fixed clks 2.4 2.8 - v supply current i cc @66.66 mhz; all outputs unloaded - 55 110 ma
4 ICS9159-12 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v ac characteristics parameter symbol test conditions min typ max units rise time 0.8 to 2.0v t r 20pf load - 1.5 3 ns fall time 2.0 to 0.8v t f 20pf load - 0.9 2 ns rise time 20% to 80% t r 20pf load - 2 4.5 ns fall time 80% to 20% t f 20pf load - 1.8 4.25 ns duty cycle [cpu] d t 20pf load 45 50 55 % duty cycle, [ref(0:1)] d t 20pf load 40 - 60 % jitter, one sigma t j1s cpu clock; load=20pf, fout>25 mhz - 50 150 ps jitter, absolute t jab cpu clock; load=20pf, fout>25 mhz -250 - 250 ps jitter, one sigma t j1s fixed clk; load=20pf; comp. to the period - 1 3 % jitter, absolute t jab fixed clk; load=20pf; comp. to the period - 2 5 % input frequency f i - 14.318 - mhz clock skew window t sk bh to bh; load=20pf; @1.4v - 50 250 ps clock skew window t sk bp to bp; load=20pf; @1.4v - 50 250 ps clock skew window t sk bh to bp; load=20pf; @1.4v - 100 500 ps
5 ICS9159-12 ssop package ics xxxx f-ppp example: package type f=ssop device t ype (consists of 3 or 4 digit numbers) ics=standard device prefix ordering information ics9159f-12 pattern number(2 or 3 digit number for parts with rom code patterns) symbol common dimensions variations d min. nom. max. min. nom. max. a 0.068 0.073 0.078 14 0.239 0.244 0.249 a1 0.002 0.005 0.008 16 0.239 0.244 0.249 a2 0.066 0.068 0.070 20 0.278 0.284 0.289 b 0.010 0.012 0.015 24 0.318 0.323 0.328 c 0.005 0.006 0.008 28 0.397 0.402 0.407 d see variations 30 0.397 0.402 0.407 e 0.205 0.209 0.212 34 0.701 0.706 0.711 e 0.0256 bsc 36 0.602 0.607 0.612 h 0.301 0.307 0.311 44 0.701 0.706 0.711 l 0.022 0.030 0.037 48 0.620 0.625 0.630 n see variations 56 0.720 0.725 0.730 0 4 8 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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