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scd5031 rev p features ? radiation performance - total dose 1 mrad (si), dose rate = 50 - 300 rads(si)/s - sel: immune to 100 mev-cm 2 /mg - seu: immune up to 20 mev-cm 2 /mg (upsets found were benign and non-stressful to the pwm or supporting electronic components) ? cmos low power design ? sleep & enable control lines ? optimized for applications: buck, boost, flyback, forward and center tapped push-pull converters ? supports current mode or voltage mode operations ? selectable 50% / 100% duty cycle ? under-voltage lockout with hysteresis ? dual 1amp peak totem pole outputs ? 1 mhz maximum ? user selectable ? low ro error amp ? auxiliary op amp with shut down pin ? power ok indicator ? pwm5034 - same as pmw5032 except straight leads ? designed for commercial, aerospace an d high reliability space applications ? ceramic 24-lead, hermetic package, .6l x .3w x .13h - pwm5032 gull wing leads - pwm5034 straight leads - weight: 1.2 g max ? evaluation board available for test and evaluation. see aeroflex application note an5031-1 ? available on dscc smd 5962-06251 note: aeroflex plainview does not currently have a dscc certified radiation hardened assurance program developed in partnership with jhu/apl and the technology application group for the mars technology program; part of nasa?s mars exploration program overview and general operation the chip is a fixed frequency pulse width modulator based on the industry standard uc1843x series with significant enhancements in performance and functionality. the chip opera tes in either the voltage or current mode and can support a wide variety of converter topologies. radiation hardened by design techniques ensure the chip?s outstanding radiation tolerance (>1mrads) while reducing operating current by more than an order of magnitude over comparable parts. the pwm5032 provides an under voltage lockout feature with hyst eresis that also provides an output to indicate power is ok. an input called sleep is used to power down the entire chip, the enable input is used to shut down the oscillator / output drives, and the soft input drives the output to zero. there is al so a signal input called enaux that is used to disable the output to the auxiliary op-amp. the dual output drivers are de signed using a totem pole output capable of sinking and sourcing 50ma constant current and peak currents up to 1 amp to support a large variety of power mosfets. additional features that boost the appeal and utility of the part are: dual break-before-make totem pole output stage is employed that virtually eliminates cross conduction and current shoot through logic level input that allows the user to select either 50% or 100% maxi mum duty cycle operation improved oscillator stage that vastly increases wa veform linearity and reduces output voltage error uncommitted on-board op-amp which can be used for signal co nditioning, pulse feedback, or any other user defined purpose pwm5032 radhard high speed pwm controller standard products www.aeroflex.com/pwm april 22, 2010 radiation tolerant
2 scd5031 rev p 4/22/10 aeroflex plainview figure 1 ? block diagram isense vfb comp soft rset cset error amp 1.4v vee aout 1v current sense comparators enaux internal enable / shutdown control lockout sleep en 50% pwrok drvp outa drvn uncommitted op-amp vcc undervoltage vref outb output reference logic & control functions duty cycle limiting (50% or 100%) drive internal bias oscillator pin nin 12 15 16 14 13 18,19 20 21 22,23 2 17 3 10 11 1,24 8 9 7 4 5 6 s r q q 2.5v 2r r
3 scd5031 rev p 4/22/10 aeroflex plainview pwm5032 pwm pin description pin # signal name function description 1 24 vcc logic power 2 50% input selects maximum duty cycle (50% or 100%). logic ''1'' sel ects 50% max duty cycle and output b is the complement of output a. logic ''0'' selects 100% and output a is in-phase with output b. 3 sleep this input shuts down all functions on chip when asserted (active hi) 4 comp output of the error amplifier. place compensation network fr om this pin to v fb to stabilize converter. 5 vfb negative input to the error amplifier 6 isense input current sense pin used for current mode control 7 soft this high impedance input is used to limit the error amplifier output voltage. applying an rc circuit to this pin provides the standard softstart function. pull the pin to ground to force zero duty cycle. this input is internally shorted to ground when enable (pin 17) is low or sleep (pin 3) is high or an under voltage is detected. 8 cset works with rset to establish oscillator fr ee running frequency. place cap from this input pin to ground. can synchronize oscillator by overdr iving this pin with an external frequency source. 9 rset works with cset to establish oscillator free running frequency. place resistor from this input pin to ground. 10 pwrok logical output of uv lockout circuit -- logic ''1'' indicates chip has valid vcc 11 vref buffered 3v output reference voltage 12 vee logic ground 13 nin auxiliary op-amp inverting input 14 pin auxiliary op-amp non-inverting input 15 aout auxiliary op-amp output (short circuit protected) 16 enaux input enable of auxiliary op-amp (active hi) 17 en logic input that enables the oscillator and output drivers. reference voltage remains valid (active hi). 18 19 drvn output stage negative rail 20 out b totem pole output b 21 outa totem pole output a 22 23 drvp output stage positive rail
4 scd5031 rev p 4/22/10 aeroflex plainview absolute maximum ratings 1 /, 4 / operating temperature range -55c to +125c maximum junction temperature +135c storage temperature range -65c to +150c v cc supply voltage 7.0v dc drvp supply voltage pwm5031 7.0v dc pwm5032 14.0v dc steady state output current 50ma peak output current (internally limited) 1.0a analog inputs (pins 5, 6, 13, 14) v ee -0.5v to v cc +0.5v power dissipation at t a = +25c 500mw esd rating 2 / 450v lead temperature (soldering, 10 seconds) 300c digital inputs -0.3v to v cc + 0.3v notice: stresses above those list ed under "absolute maximums ratin g" may cause permanent damage to the device. these are stress rating only; functional operation beyond the "operation conditions" is not recommended and exte nded exposure beyond the "operation condition s" may effect device reliability. operating conditions 1 /, 4 / parameter condition symbol min typ max unit dc operating voltage - v cc 4.5 5.0 5.5 v quiescent current pwm5031 sleep @ '0'; en & enaux @ '1': no loads on outputs pwrok, aout and vref i cc - - 5.8 ma pwm5032 - - 7.1 ma output drive voltage pwm5031 -drvp --5.0v pwm5032 - - 12.0 v output duty cycle ? maximum 50% pin = logic 0 50% pin = logic 1 100% duty cycle 50% duty cycle - - 97 * - - - - 50 % % thermal resistance t jc - - - - 6.0 c/w sleep mode - i ccs --20a * dependent on value of c set & operating frequency electrical charac teristics 1 /, 4 / 4.5 v < vcc < 5.5v, -55c < t a < +125c, unless othe rwise specified parameter test conditions min typ max units reference section reference voltage t a = 25c, i o = -1 ma 3.00 3.05 3.10 v line regulation - - .1 .12 % load regulation 0 < i o < 3 ma 3 / - .05 .075 % thermal regulation - - 1 1.6 % output short circuit 3 /---40ma oscillator section initial accuracy range pwm5032 - 201 209 217 khz frequency range 3 / 20 - 1,000 khz frequency stability (part to part) - 2.0 3.8 % temperature stability t min < t a < t max , 3 /-0.5 1% r set range 3 / 50 - - k ? c set range - - 600 pf
5 scd5031 rev p 4/22/10 aeroflex plainview error amp section input offset voltage 3 / - - 3.3 mv input common mode voltage range v ee +0.2 - v cc -0.2 v input bias current - - -1.0 a open loop voltage gain (avol) 100 - - db unity gain bandwidth 1.0 2.0 - mhz power supply rejection ratio (psrr) 60 - - db output sink current v fb = 3.0v, v soft = 1.1v, 3 / --+10ma output source current v fb = 2.0v, v soft = 5v, 3 / ---28ma v out high (limited by v soft ) v fb = 2.0v, r l = 15k to gnd v soft - 0.2 -- v v out low v fb = 3.0v, r l = 15k to +5v --v ee +0.2 v gain (v comp /vi sense ) 3 / 2.85 3 3.15 v/v current sense section input offset voltage 3 / - - 3.3 mv common mode input voltage v soft = 5v, 3 / 4 / 0.1 - 1.0 v input bias current 3 / --1.0a i sense to output delay - 80 100 ns output section output low level i sink = 1.0ma - - 0.1 v i sink = 50ma pwm5031 - - 0.25 v i sink = 50ma pwm5032 - - 0.6 v output high level-pwm5031 i source = 1.0ma, drvp = 5v 4.9 - - v i source = 50ma, drvp = 5v 4.6 - - v output high level-pwm5032 i source = 1.0ma, drvp = 12v 11.9 - - v i source = 50ma, drvp = 12v 11.4 - - v peak output current 3 / 1.0 1.35 - a steady state output current - --50ma rise time t a = 25c , c l = 20pf, drvp = 5v 3 / - 8 18 ns fall time - 6 28 ns enable output off delay 3 / - - 100 ns sleep output off delay - - 100 ns under voltage output off delay - - 100 ns electrical charac teristics 1 /, 4 / 4.5 v < vcc < 5.5v, -55c < t a < +125c, unless othe rwise specified parameter test conditions min typ max units
6 scd5031 rev p 4/22/10 aeroflex plainview auxiliary amp section input offset voltage - - - 3.5 mv input common mode voltage range off v ee or v cc rail, 3 /v ee +0.2 - v cc -0.2 v input bias current 3 /-- 1.0a avol f = 40khz, 2v < v o < 4v, 3 / 100 - - db unity gain bandwidth 3 /1.0--mhz psrr 4.5v < v cc < 5.5v, 3 / 60 70 - db output sink current v pin < v nin , enaux = hi, 3 / --+45ma output source current - - -28 ma v out high v pin > v nin , enaux = hi, io = 2ma v cc -0.3 - - v v out low --v ee +0.2 v under-voltage lockout section start threshold 3.9 4.1 4.25 v operating voltage after turn on 3.35 3.5 3.65 v digital inputs v il logic low, 3 /- -0.8v v ih logic high, 3 /2.0--v leakage current - i in 3 / - - 100 na digital ouput (pwrok) v ol logic low at 1.6ma - - v ee +0.3 v v oh logic high at -1.6ma v cc -0.6 - - v notes 1 / all voltages are with respect to pin 12. all currents are positive into the specified terminal. 2 / meets esd testing per mil-st d-883, method 3015, class 1a. 3 / parameters are guarantee d by design, not tested. 4 / all electrical characteri zations for the pwm5034 are the same as the pwm5032. electrical charac teristics 1 /, 4 / 4.5 v < vcc < 5.5v, -55c < t a < +125c, unless othe rwise specified parameter test conditions min typ max units
7 scd5031 rev p 4/22/10 aeroflex plainview detailed component opera tion and performance power supplies three i/o pins are used to supply power to the chip: 1) two drvp (referenced to drvn) for the output stage. 2) v cc (referenced to v ee ) for all other functions. for protection against inadvertent over/und ervoltages, the chip?s input pins are di ode clamped to the supply rails through current limiting resistors. undervoltage lockout the chip includes an internal undervoltage lockout ci rcuit with built in hysteresis and a logic level power good indicator. the positive and negativ e going thresholds are nominally 4.1v and 3.5v, respectively. if vcc is below this range, the oscillator, error amplifier, main comparat ors, and output drive circuits are all di sabled. the power ok indicator is active high (logic ''1'') when a valid supply voltage is applied. shutdown logic the chip has two logic level inputs fo r implementing shutdown func tions. asserting a logic ''1 '' on the sleep pin disables all chip functions and puts the chip into a very low power consumption mode. asserting a logic ''0'' on the en pin shuts down all functions except the reference, bias generators, and auxiliary amplifier. inputs outputs sleep en enaux outa&b aout comp pwrok vref 0 0 0 0 0 0 active 3 v dc 0 0 1 0 active 0 active 3 v dc 0 1 0 active 0 active active 3 v dc 0 1 1 active active active active 3 v dc 1xx00000 x = don?t care. truth table 3.5v von voff 4.1v vcc power ok on/off command to rest of ic 24 v on i cc 1.6ma v off v cc 1 figure 2 ?undervoltage lockout
8 scd5031 rev p 4/22/10 aeroflex plainview oscillator the chip uses two precision current mirrors that alternately charge and discharge an exte rnal capacitor to generate an extremely linear sawtooth oscillator wavefo rm. at the start of each cycle, the charging current, set by the choice of resistor at the rset pin, is 1:1 mirrored over to the cset pin where it charges an external capacitor. when the capacitor voltage reaches the comparator?s upper threshold (nominally v ref ), the comparator switches current mirrors and begins to discharge the external capacitor. the di scharge current is set at roughly five ti mes the charging current to result in fast discharge and minimal dead time. when the voltage reach es the comparator?s lower threshold (0.9v), the comparator switches back to the charging mirror, powers down th e discharge mirror, and the whole process repeats. the frequency is set by choosing rset and cset such that: suggested ranges for cset and rset are: 50k ohms < rset < 300k 10pf < cset < 600pf rt ct rset cset gnd 6 7 12 20khz f osc 1mhz ?? 1 f ocs = charge time + dead time 1 = ( .7 x r set x (c set + 16 pf ) ) + ( 5250 x (c set + 12 pf ) ) figure 3 ? timing re sistance vs frequency 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 10 100 1000 frequency khz rset ?? ?? 390pf 200pf 100pf 47pf 20pf 10pf
9 scd5031 rev p 4/22/10 aeroflex plainview dead time the amount of dead time determines the maximum duty cycle that can be achiev ed. the dead time and the frequency of operation will determine the duty cycle. selecting r set and c set to select values for r set and c set perform the following steps to insure the smallest dead time.. 1) determine what frequency is required for your design. 2) use figure 4 to select a capacitor value for cset that will provide the highest duty cycle (shortest dead time) at the frequency required. 3) calculate the value of rset using the formula: note small values of rset increase power consumption fo r the pwm5032 and small values of cset may make pcb and stray capacitance a source of error. dead time 5250 c set 12pf + ?? = duty cycle 1 dead time 1 f osc ? ---------------------------- - ?? ?? ? = 1 r set = .7 x f osc x (c set + 16 pf ) figure 4 ? duty cycle vs frequency 86.00% 88.00% 90.00% 92.00% 94.00% 96.00% 98.00% 100.00% 10.00 100.00 1000.00 frequency khz duty cycle 390pf 200pf 100pf 47pf 20pf 10pf
10 scd5031 rev p 4/22/10 aeroflex plainview if desired, the user can synchronize the oscillator to an external frequency sour ce by coupling a pulse train to the cset pin: figure 5 ? pwm can be synchronized to external source with just two additional components. operation is similar to the free running case. cset is altern ately charged and discharged by the same current mirrors and the same comparator and thresholds are used . the only difference is that when a sync pulse is received, the capacitor voltage is level shifted up and reaches the comparator ?s upper threshold voltage before it normally would in the free running case . if a series of pulses are received with shorter period than that of the free running oscillator, the comparator will trip in response to the sync puls e and the oscillator will be synchronized. (note: the user must ensure that the sync pulse does not induce a voltage on c set that exceeds the pwm5032 voltage rati ng. if this cannot be guaranteed, a simple diode clamp to the positive rail shou ld be used to prevent damage to the pwm) error amplifier the main error amplifier is a n-type input folded cascade co nfiguration with a few intere sting additions. the positive input is internally tied to 2.5v derived from the on chip reference. the negative input typically draws less than 1a and has a voltage offset of less than 2mv. at 20a bias current, the amplifier exceeds 2mhz bandwidth and 120db open loop gain (see figure 7). the amplifier is designed to limit at whatev er voltage is applied to the soft pin. as mentioned previously, this function will allow the user to implement a softstart circuit, a contro lled turn-on delay, or any number of other useful functions. sync pulse 2nf 24 ? cset to p w m
11 scd5031 rev p 4/22/10 aeroflex plainview figure 6 ? current sense circuit error 1.4v 1v current comparators 2r r amp 5 7 4 12 6 v soft 2.5v v fb current sense v ee r s r c i s sense s r q q peak current (is) is determined by the formula: a small rc filter may be required to suppress switch transients i s max 1.0v r s ----------- - = or if i s max v soft 1.4 ? 3 r s -------------------------------- = v r s 1volt ? then comp figure 7 ? error amplifier open-loop frequency response at +125c & -55c gain frequency hz (log scale) db 120 80 40 0 -40 10 100 1k 10k 100k 1m 10m 1 +125c -55c
12 scd5031 rev p 4/22/10 aeroflex plainview output drive dual push-pull outputs outa and outb are provided for driving off chip switches. the output stages are identical: totem pole configuration break-before-make switching to prev ent harmful cross-conduction spikes separate positive and negative supply connections to decouple power stage and sensitive logic near rail-to-rail voltage swing 1a maximum peak current capability (capacitive load) the outputs have two modes of control depending on whether the 50% toggle option is selected. in the case where the 50% pin is logic low, the outputs are in-phase with each other and the duty cycle is free to take on any value up to 100%. however, when the 50% pin is asserted high (logic ''1'') , the outputs become limited to a maximum 50% duty cycle by turning off each output on every other cl ock period of the oscillator. in additio n output a and output b will never turn on during the same clock cycle, see figure 7a below. this wo uld lend itself to a two phase switching system that would be 180 out of phase.. figure 7a ? output drive options osc out a out b out a out b max output @ 50% output @ 25% pin 2 set low, 100% mode pin 2 set hi, 50% mode out a out b max output @ 100%
13 scd5031 rev p 4/22/10 aeroflex plainview auxiliary amplifier the chip includes an uncommitted op-amp with independent shutdown feature for use in any user-defined application. some possibilities are: signal conditioning of an isolated configuration feedback voltage implementation of more sophisticated compensation networks for control loop optimization the auxiliary amplifier has a unity gain bandwidth greater th an 1mhz and an open loop gain greater than 100db. the enaux pin is active high such that a logic ''1'' enables the amplifier and logic ''0'' disabl es it. the amplifier has near rail-to-rail capability on both the input and output. a typical single output forward converter application is shown in figure 9 to aid in the following operational description. during normal operation, the oscillato r jumpstarts each switching cycle by resetting the rs latch, causing the output stage to go high and turn on m1. current begins to bu ild linearly through t1 and m1 and a proportional voltage is developed across the small sense resistor rs. switching sp ikes are filtered by c1 and r1, and the resulting sawtooth waveform is passed into the pwm to serve as the current co mparator input. meanwhile, a portion of the output voltage is sensed and compared to the pwm?s inte rnal precision 2.5v reference. the difference is then amplified and level shifted to serve as the comparator th reshold. when the voltage on the i sense pin exceeds this threshold, the comparator fires and resets the latch. the output then turns off until the beginning of th e next oscillator cy cle when the process repeats. figure 8 ? output sink and source saturation characteristics at +25c v sat 110 mv 500 400 300 200 0 600 100 current ma 100 5031 5032
14 scd5031 rev p 4/22/10 aeroflex plainview typical applications like all current mode pwms, the chip provides built in fault protection by limiting peak switch current on a cycle by cycle basis. when an overload conditio n occurs, the sensed current reaches the current tr ip threshold earlier in the switching cycle than it otherwise would an d thus forces the pwm latch off until the start of the next cycle. the process repeats until the overload condit ion is removed and the pwm can return to a normal duty cycle. the chip is capable of operating in this mode indefinite ly without sustaining damage. there are two ways to set the current limit trip point . one is to simply tailor the sense resistor rs: some users may find the power is dissipated in rs to be unacc eptably high. in this case, the user can fix rs at a small value and vary the current comparator th reshold instead. fortunately, the pwm chip provides a very convenient method for doing so. because the error amplifier output is internally clamped to the soft pin, the user need simply apply the desired voltage level to the soft pin to arbitrarily lower the current comparator threshold. recalling that the ea output is level sh ifted and divided before being applied to the comparator input, the peak current limit is chosen by applying a voltage v soft such that: clamping the ea output to the soft pi n also makes implementing a softstart ciruit easy. rsoft and csoft are connected as in figure 9 to provide the soft pin an asy mptotically rising voltage. because of the internal clamp on the ea output, the pwm duty cycle will increase only as fast as the chosen time constant will allo w. in this way, excessive duty cycle and surge currents into the output capacito rs are avoided. a transistor may be optionally connected across the softstart figure 9 ? typical forward converter application rset cset c soft 0.1f r soft m2 c1 r1 rs t1 isolation barrier 3.3v, 0.5a opto-isolator or pulse transformer optional circuit to force zero duty cycle m1 r set c set v ee drvn v fb comp 50% i sense out a out b v cc drvp en soft v ref +5v dc i pk 1.0vdc r s ------------------ - = i pk v soft 1.4 ? 3 r s ? --------------- ---------- = 1.4v v soft 4.4v ??
15 scd5031 rev p 4/22/10 aeroflex plainview capacitor to force zero duty cycle on command. this is a particularly convenient meth od for implementing an externally controlled turn-on delay. the discussion so far assumes the user op erates the chip in the cu rrent mode: switch current is sensed and compared to the error between the output voltage and a precision referenc e. alternatively, the user may wish to implement voltage mode control in which the cont rol loop is dependent only on the output vo ltage. the pwm chip readily supports this configuration with the following modification: figure 10 ? circuit for implementing voltage mode control. a portion of the oscillator?s sawtoot h waveform is coupled to the i sense pin and becomes the input to the comparator stage. the operation is now identical to the current mode application: when the sawtooth voltage exceeds the amplified difference between the output and a voltage reference, the comparator fires and latches off the output until the start of the next cycle. selected application examples the flexibility and performance of the ch ip makes it suitable for an enormous ra nge of power converter applications ? step-up, step-down, dc-dc, ac-dc, is olated/non-isolated, and many more. this section will cover two of the more popular power converter applications for which this chip is particularly well suited although many more can be envisioned. 5v input, 3.3v isolated output (single ended fo rward converter) the isolated step down dc/dc converter is a staple of many satellite and aerosp ace systems. a comm on bus distributes raw primary power to various system lo ads which must then convert the primar y to one or more low voltage secondary outputs. these outputs are filtered, re gulated, and ground isolated from the primary side to keep emi and undesired subsystem interaction at a minimum. figure 9 is one example of a circuit that very effici ently performs this conversion. the values here were chosen to work for a 5v input and 3.3v output but th e circuit topology is general enough to support an infinite variety of applications. for example, outp ut voltages can be adjusted by changing values of just a few components. a wider input voltage rang e can be supported by varying the transformer?s turns ratios and by proper selection of m1. thus, a very wide range of power converte r applications can be satisfie d by simple variations of the circuit. at the start of each switching cycle, the pwm output goes high and turns on m1. energy is coupled across t1?s turns ratios to the secondary si de where it is caught, rectified, and filtered to produce a clean dc voltage. a sampling network on the output side feeds back a portion of the output across the isolation barrier into th e error amplifier negative input. this feedback can be accomp lished in a number of different ways: puls e transformers, optocouplers, or capacitive coupling are a few methods. the compensation network ma y need modification depending on the feedback method chosen. the additional winding and rectif ier on t1 are used to re set the transformer core after the pwm latches off m1 to prevent staircase saturation of the core. note the chip is powered dire ctly from the main power bus (via a zener a nd current limit resistor) without the need for additional bootstrap transformer windings . this is one of the main advantag es this pwm chip provides over other products. this scheme could not be implemented with other chips which draw significantly more current. on the other hand, supplying bias to our pwm chip is about as simple as it gets. out isense vref 2n2222 cset cset m1 switch current
16 scd5031 rev p 4/22/10 aeroflex plainview 5v to 1.8v buck converter a second application is a secondary side, non -isolated buck converter. the circu it takes a high voltage (5v in this case) and steps down to a lower voltage (5v to 1.8v in this example, although as pointed out above, these values are completely adjustable with proper compon ent selection). if the output voltage is less than 2.5v the auxiliary amplifier can be used to provide the gain necessary to get v fb back up to 2.5v. figure 11 ? buck converter the circuit switches m1 twice per cycle, chopping the 5v dc input into a fixed frequency pulse train whose dc average is the desired output voltage. the lc f ilter then simply smoothes this pulse tr ain to produce a clean dc output. the control loop regulates against operating po int perturbations (temperature, line, lo ad) by adjusting m1's duty cycle. the circuit is operated in the volta ge mode since switch current is not referenced to circuit ground. alternatively, a current transformer may be used to properly reference the i sense signal to permit current mode cont rol. an inverter is needed in the output path to properly drive the p-channel mosfet. for low current applications (le ss than -50ma output current), it may be possible to use the pwm's output drive stage as th e switching elements and eliminate m1 and d1 altogether. r set c set i nput 5v rcomp 1v/1.8v/2.5v/3.3v m1 o utput r soft c soft ccomp 0.1f r set c set v ee drvn v fb comp 50% i sense out a v cc drvp soft v ref d1
17 scd5031 rev p 4/22/10 aeroflex plainview figure 12 ? package pin vs function 24 vcc 23 drvp 22 drvp 21 outa 20 out b 19 drvn 18 drvn 17 en 16 enaux 15 a out 14 pin 13 nin vcc 1 50% 2 sleep 3 comp 4 vfb 5 isense 6 soft 7 cset 8 rset 9 pwrok 10 vref 11 vee 12 note: the lid is connected to pin 12
18 scd5031 rev p 4/22/10 aeroflex plainview . 3 00 max .500 .500 pin 1 & e s d ident .614 max .110 max (1. 3 00) .022 1 3 0 ma x .0 0 8 . 0 0 1 2 . 6 1 4 ma x . 0 1 9 . 3 00 . 3 94 .419 max 1 1 x . 0 5 0 = . 0 1 5 . 3 3 5 mi n . 0 2 2 .00 5 . 0 1 2 . 0 2 2 ma x re f . 3 5 4 . 0 3 0 re f . 5 5 0 . 0 0 6 .0 0 8 . 0 0 1 2 .0 0 8 . 0 0 1 2 .0 0 8 . 0 0 1 2 . 6 1 4 ma x . 0 1 9 . 3 00 . 3 94 .419 max 1 1 x . 0 5 0 = p i n 24 . 0 1 5 . 0 1 9 . 0 1 5 . 0 1 9 . 0 1 5 . 3 3 5 mi n . 0 2 2 .00 5 . 0 1 2 . 0 2 2 ma x re f . 3 5 4 . . 0 3 0 re f . 5 5 0 . 0 0 6 p i n 2 4 1 1 x . 0 5 0 = . 5 5 0 . 0 0 6 1 1 x . 0 5 0 = . 5 5 0 . 0 0 6 pin 1 & e s d ident figure 13 ? pwm5031 /pwm5032 flat package (gull wing) configuration outline figure 14 ? pwm5034 flat package (strai ght leads) configuration outline
19 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. scd5031 rev p 4/22/10 export control: export warning: this product is controlled for expor t under the international traffic in arms regulations (itar). a license from the u.s. department of state is required prior to the export of this product from the united states. aeroflex?s military and space pr oducts are controlled for export under the international traffic in arms regulations (itar) and may not be sold or proposed or offered for sale to certain countries. (see itar 126.1 for complete information.) configurations and o rdering information model dscc smd # screening package pwm5031-7 - obsolete, replace by pwm5032-7 flat package, gull wing pwm5031-s obsolete, replace by pwm5032-s pwm5032-7 commercial flow, 0c to +70c flat package, gull wing pwm5032-s military temperature, -55c to +125c screened in accordance with mil-prf-38534, class k pwm5034-7 commercial flow, 0c to +70c flat package, straight lead pwm5034-s military temperature, -55c to +125c screened in accordance with mil-prf-38534, class k pwm5032-eval see application note an5031-1 1 / 8'' x 11'' x 3.25''ht pwm5031-001-1s pwm5031-001-2s 5962-0625101kxc 5962-0625101kxa obsolete, replace by pwm5032-001-1s obsolete, replace by PWM5032-001-2S flat package, gull wing pwm5032-001-1s PWM5032-001-2S 5962-0625102kxc 5962-0625102kxa in accordance with dscc smd pwm5034-001-1s 5962-0625102kyc flat package, straight lead 1 / application note an5031-1, title d ? high speed pulse width modulator controller evaluation board?. evaluation board pwm5032- eval is supplied with a pwm5032-7 component.

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