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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . h i g h i n p u t v o l t a g e 8 a p w m c o n v e r t e r w i t h a d j . s o f t s t a r t f e a t u r e s g e n e r a l d e s c r i p t i o n a d j u s t a b l e o u t p u t v o l t a g e f r o m + 0 . 8 v t o + 1 2 v - 0.8v reference voltage - + 1% accuracy over temperature o p e r a t e s f r o m a n i n p u t b a t t e r y v o l t a g e r a n g e o f + 2 . 7 v t o + 2 8 v power-on-reset monitoring on vcc pin e x c e l l e n t l i n e a n d l o a d t r a n s i e n t r e s p o n s e s p f m m o d e f o r i n c r e a s e d l i g h t l o a d e f f i c i e n c y programmable pwm frequency from 100khz to 1000khz i n t e g r a t e d 3 0 m w a t v c c = 5 v n - c h a n n e l m o s f e t f o r h i g h s i d e i n t e g r a t e d 9 m w a t v c c = 5 v n - c h a n n e l m o s f e t f o r l o w s i d e i n t e g r a t e d b o o t s t r a p f o r w a r d p - c h m o s f e t e x t e r n a l a d j u s t a b l e s o f t - s t a r t a n d s o f t - s t o p selectable forced pwm or automatic pfm/pwm mode p o w e r g o o d m o n i t o r i n g 70% under-voltage protection 125% over-voltage protection c u r r e n t - l i m i t p r o t e c t i o n - using sense low-side mosfet?s rds(on) over-temperature protection tqfn-23 4mmx4mm package lead free and green device available (rohs compliant) a p p l i c a t i o n s n o t e b o o k m o t h e r b o a r d t a b l e p c h a n d - h e l d p o r t a b l e a i o p c s e t - t o p b o x e s l c d t v t h e a p w 8 7 1 3 i s a 8 a , s y n c h r o n o u s , s t e p - d o w n c o n v e r t e r w i t h i n t e g r a t e d 3 0 m w n - c h a n n e l h i g h - s i d e m o s f e t a n d 9 m w l o w - s i d e m o s f e t . t h e a p w 8 7 1 3 s t e p s d o w n h i g h v o l t a g e t o g e n e r a t e l o w - v o l t a g e c h i p s e t o r r a m s u p p l i e s i n n o t e b o o k c o m p u t e r s . t h e a p w 8 7 1 3 p r o v i d e s e x c e l l e n t t r a n s i e n t r e s p o n s e a n d a c c u r a t e d c v o l t a g e o u t p u t i n e i t h e r p f m o r p w m m o d e . i n p u l s e f r e q u e n c y m o d e ( p f m ) , t h e a p w 8 7 1 3 p r o v i d e s v e r y h i g h e f f i c i e n c y o v e r l i g h t t o h e a v y l o a d s w i t h l o a d i n g - m o d u l a t e d s w i t c h i n g f r e q u e n c i e s . i n p w m m o d e , t h e c o n - v e r t e r w o r k s n e a r l y a t c o n s t a n t f r e q u e n c y f o r l o w - n o i s e r e q u i r e m e n t s . t h e a p w 8 7 1 3 i s e q u i p p e d w i t h a c c u r a t e c u r r e n t - l i m i t , o u t p u t u n d e r - v o l t a g e , a n d o u t p u t o v e r - v o l t a g e p r o t e c t i o n s , p e r f e c t f o r v a r i o u s a p p l i c a t i o n s . a p o w e r - o n - r e s e t f u n c - t i o n m o n i t o r s t h e v o l t a g e o n v c c t o p r e v e n t w r o n g o p e r a t i o n d u r i n g p o w e r - o n . t h e a p w 8 7 1 3 h a s e x t e r n a l a d j u s t a b l e s o f t - s t a r t a n d b u i l t - i n a n i n t e g r a t e d o u t p u t d i s - c h a r g e m e t h o d f o r s o f t s t o p . a s o f t - s t a r t r a m p s u p t h e o u t p u t v o l t a g e w i t h p r o g r a m m a b l e t i m i n g t o r e d u c e t h e s t a r t - u p c u r r e n t . a s o f t - s t o p f u n c t i o n a c t i v e l y d i s c h a r g e s t h e o u t p u t c a p a c i t o r s . t h e a p w 8 7 1 3 i s a v a i l a b l e i n t q f n 4 x 4 - 2 3 ( p o w e r p a k ) .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 s i m p l i f i e d a p p l i c a t i o n c i r c u i t o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n apw 8713 handling code temperature range package code package code q b : t qfn 4 x 4 - 23 operating ambient temperature range i : - 40 to 85 c handling code tr : tape & reel lead free code l : lead free device assembly material apw 8713 qb : apw 8713 xxxxx xxxxx - date code g : halogen and lead free device v out l out en apw 8713 v in c ss ss c out pfm pok vcc lx vin r pok h / l = exposed and thermal pad tqfn 4 x 4 - 23 ( top view ) lx fb 5 ton 6 pok 1 en 2 pfm 3 agnd 4 n c 7 v i n 8 v i n 9 l x 1 0 l x 1 1 17 lx 16 lx 15 pgnd 14 pgnd 13 pgnd 12 pgnd 2 3 s s 2 2 v i n 2 1 v c c 2 0 b o o t 1 9 p g n d 1 8 l x vin
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v vcc vcc supply voltage ( vcc to a gnd) - 0.3 ~ 7 v v in vin supply voltage (vin to agnd) - 0.3 ~ 30 v v ton ton supply voltage (ton to agnd) - 0.3 ~ 30 v v boot - gnd boot supply voltage (boot to a gnd) - 0.3 ~ 3 7 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v v gnd agnd to pgnd - 0.3 ~ +0.3 v all other pins (pok, en, fb, ss and pfm to agnd) - 0.3 ~ 7 v v lx lx voltage ( lx to gnd) < 2 0n s pulse width > 2 0n s pulse width - 5 ~ 3 2 - 0.3 ~ 30 v t j junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature ( 10 seconds ) 26 0 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) 50 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n . symbol parameter range unit v vcc vcc supply voltage 4.5 ~ 5.5 v v in converter input voltage 2.7 ~ 2 8 v v out converter out put voltage 0.8 ~ 13.2 v i out converter output current 0 ~ 8 a c in pwm1/2 converter input capacitor (mlcc) 10 ~ m f c vcc vcc ou tput capacitor (mlcc) 1.0 ~ m f t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v in =12v,v en =5v and t a = -40 to 85 o c. typical values are at t a =25 o c. apw8713 symbol parameter test condition min. typ. max. unit v out and v fb v oltage v out output v oltage adjustable output range 0.8 13.2 v v ref reference voltage 0.8 v regulation accuracy t a = - 40 o c ~ 85 o c - 1.0 - +1.0 % i fb fb input bias current fb=0.75v 0.02 - m a t stop output discharge time en go low to output remain below 0.1v - 5*tss - - supply current i vcc_nor mal vcc quiescent supply current en=5v, fb=0.835v, vcc=5v - 0.7 1 m a i vcc_shd n vcc shutdown current en = gnd, vcc=5 v - - 25 m a on - time t imer and i nternal s oft s tart t on nom inal on time v in =12v, v out =1v, r ton =100k w 200 250 300 ns f sw frequency adjustable range 100 1000 khz t off (min) minimum off time v fb =0.75v, v phase = - 0.1v - 250 - ns i ss internal soft start current vss=0v ?a css=0.001uf to 0.1uf 8 10 12 m a t ss internal s o ft s tart t ime en high to pok high - 330*css - ms gate driver high side mosfet on resistance vin=12v ?a vcc=5v - 30 45 m w low side mosfet on resistance vin=12v ?a vcc=5v - 9 13.5 m w bootstrap switch v f ron v pvcc ? v boot - gnd , i f = 10ma - 0.5 0.7 v i r rev erse leakage v boot - gnd = 30v, v phase = 25v, v pvcc = 5v - - 0.5 m a vcc por threshold v lcc_thf falling vcc por threshold voltage 4.25 4.35 4.45 v ldo por hysteresis - 100 - mv control inputs en high - level input voltage 2.5 - - v en low - level inp ut voltage - - 0.5 v en leakage en=0v - 0.1 - m a pfm high - level input voltage 2.5 - - v pfm low - level input voltage - - 0.5 v pfm leakage pfm =0v - 0.1 - m a
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v in =12v,v en =5v and t a = -40 to 85 o c. typical values are at t a =25 o c. apw8713 symbol parameter test condition min. typ. max. unit power - ok indicator pok in from lower (pok goes high) 87 90 93 % v pok pok threshold pok out from normal (pok goes low) 120 125 130 % i pok p ok leakage current v pok =5v - 0.1 - m a p ok si nk current v pok =0.5v ?a 1.25 7.5 - ma pok out debounce time2 when run away 90% - 20 - m s pok enable delay time from en high to pok high - tss - ms current sense i ocp ocp threshold valley current of il 11 - - a zero c rossing c omparator o ffset v gnd - lx voltage, pfm=0v - 5 0 5 mv protection v uv uvp threshold 65 70 75 % uvp debounce interval 16 m s uvp enable delay en high to uvp workable tss ms v ovr ovp rising threshold 1 ovp occur 120 125 130 % ovp propagation delay v fb rising, over voltage= 10mv - 3 - m s t otr otp rising threshold (note 5) - 145 - o c otp hyste r esis (note 5) - 45 - o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s - 50 - 25 0 25 50 75 100 r e f e r e n c e v o l t a g e ( v ) reference voltage vs . junction temperature 0 . 804 0 . 794 0 . 796 0 . 798 0 . 8 0 . 802 junction temperature ( o c ) output current ( a ) automatic pfm / pwm mode force pwm mode 0 . 001 0 . 01 0 . 1 1 10 0 . 1 1 10 100 1000 switching frequency vs . output current s w i t c h i n g f r e q u e n c y ( k h z ) 0 2 4 6 8 10 1 . 05 1 . 06 1 . 07 1 . 08 1 . 09 1 . 10 automatic pfm / pwm mode force pwm mode o u t p u t v o l t a g e ( v ) output current ( a ) output voltage vs output current input voltage ( v ) output voltage vs input voltage 1 . 050 1 . 055 1 . 060 1 . 065 1 . 070 1 . 075 1 . 080 1 . 085 1 . 090 0 5 10 15 20 25 30 pfm operation pwm operation o u t p u t v o l t a g e ( v ) input voltage ( v ) 0 5 10 15 20 25 30 280 290 300 310 320 330 340 switching frequency vs . input voltage s w i t c h i n g f r e q u e n c y ( k h z )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . enable w ithout l oading 1 3 2 4 v en v lx v out v pok ch 1 : v en , 5 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : v out , 50 0 m v / div , dc time : 1 ms / div ch 4 : v pok , 5 v / div , dc c ss = 1 0 nf enable w ith l oading 1 3 2 4 v en v lx v out v pok c ss = 1 0 nf time : 1 ms / div ch 1 : v en , 5 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : v out , 50 0 m v / div , dc ch 4 : v pok , 5 v / div , dc soft - stop function 1 3 2 v en v lx v out v pok 4 ch 1 : v en , 5 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : v out , 50 0 m v / div , dc time : 5 ms / div ch 4 : v pok , 5 v / div , dc c ss = 1 0 nf shutdown w ith l oading 1 3 2 v en v lx v out v pok 4 ch 1 : v en , 5 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : v out , 50 0 m v / div , dc time : 500 m s / div ch 4 : v pok , 5 v / div , dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . pfm s witching w aveform 1 3 v lx i l v out 2 ch 1 : v out , 50 m v / div , a c ch 2 : v lx , 5 v / div , dc ch 3 : i l , 2 a / div , dc time : 1 m s / div pwm s witching w aveform 1 3 2 v lx i l v out ch 1 : v out , 50 m v / div , a c ch 2 : v lx , 10 v / div , dc ch 3 : i l , 2 a / div , dc time : 2 m s / div load tr ansient 1 1 3 v lx i l v out 2 ch 1 : v out , 100 m v / div , a c ch 2 : v lx , 10 v / div , dc ch 3 : i l , 5 a / div , dc time : 20 m s / div load tr ansient 2 1 3 v lx i l v out 2 ch 1 : v out , 100 m v / div , a c ch 2 : v lx , 10 v / div , dc ch 3 : i l , 5 a / div , dc time : 20 m s / div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . current l imit and uvp function 1 3 v lx i l v out 2 ch 1 : v out , 1 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : i l , 10 a / div , dc time : 500 m s / div short c ircuit p rotection 1 3 v lx i l v out 2 ch 1 : v out , 1 v / div , dc ch 2 : v lx , 10 v / div , dc ch 3 : i l , 10 a / div , dc time : 20 m s / div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 0 p i n d e s c r i p t i o n pin no. name function 1 pok power - g ood o utput p in of pwm . p ok is an open - drain output used to i ndicate the status of the pwm output voltage. connect the pok in to +5v through a pull - high resistor. 2 en pwm enable . pwm is enabled when en=1. when en=0, p wm is in shutdown. 3 pfm pfm selection input. when the pfm is above high logic level, the device is in force pwm mode. when the pfm is below low logic level , the device is in automatic pfm/pwm mode. 4 agnd signal ground for the ic. 5 fb output v oltage f eedback p in. this pin is connected to the resistive divider that set the desired output voltage. the p ok , uvp, and ovp circuits detect this signal to report output voltage status. 6 ton this p in is a llowed to a djust t he s witching f requency. connect a res i stor r ton from ton pin to vin pin. 7 nc no connect. 8, 9, 22 vin battery v oltage i nput p in. vin powers linear regulators and is also used for the constant on - time pwm on - time one - shot circuits. connect vin to the battery input and bypass with a 1 m f capac itor for noise interference . 10, 11, 16~18 lx junction p oint of t he h igh - s ide mosfet source, o utput f ilter i nductor and t he l ow - s ide mosfet drain for pwm . connect this pin to the source of the high - side mosfet. lx serves as the lower supply rail for the u gate high - side gate driver. lx is the current - sense input for the pwm. 12~15, 19 pgnd power g round of t he lg ate l ow - s ide mosfet d river s . 20 boot supply input for t he ug ate gate driver and an internal level - shift circuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 21 vcc supply voltage input pin for control circuitry, connect +5v from the vcc pin to the gnd pin. decoupling at least 1 m f of a mlcc capacitor from the vcc pin to the agnd pin. 23 ss soft start output. connect a capacitor to gnd to set the soft start interval.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 1 b l o c k d i a g r a m fb error comparator ov uv 70 % v ref 125 % v ref v ref por vcc en p w m s i g n a l c o n t r o l l e r thermal shutdown gnd pok lx fault latch logic on - time generator 90 % v ref 125 % v ref z c lx delay lx pgnd ug gate driver gate driver vcc lg boot vcc v lx vin current limit reference pfm ldo soft - start ss mean value circuit ton pfm
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 2 t y p i c a l a p p l i c a t i o n c i r c u i t w h e n v i n = 1 9 v , d u a l p o w e r i n p u t : ton lx pgnd fb r top 20 k r gnd 62 k l out 1 . 0 uh apw 8713 c in 10 uf / 25 v x 4 ( mlcc ) 19 v v out 1 . 058 v , 8 a c out 2 22 ufx 4 ss agnd 5 v c vcc 1 uf pok vcc en vin 100 k boot c out 1 150 uf c boot 0 . 1 uf pfm mode selection r pok 100 k
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 3 t y p i c a l a p p l i c a t i o n c i r c u i t ton lx pgnd fb r top 20 k r gnd 62 k l out 1 . 0 uh apw 8713 c in 10 uf / 1 2 v x 4 ( mlcc ) 5 v v out 1 . 058 v , 8 a c out 2 22 ufx 4 ss agnd c vcc 1 uf pok r pok 100 k vcc en vin 100 k boot c out 1 150 uf c boot 0 . 1 uf pfm mode selection w h e n v i n = 5 v , s i n g l e p o w e r i n p u t :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n c o n s t a n t - o n - t i m e p w m c o n t r o l l e r w i t h i n p u t f e e d - f o r w a r d t h e c o n s t a n t o n - t i m e c o n t r o l a r c h i t e c t u r e i s a p s e u d o - f i x e d f r e q u e n c y w i t h i n p u t v o l t a g e f e e d - f o r w a r d . t h i s a r - c h i t e c t u r e r e l i e s o n t h e o u t p u t f i l t e r c a p a c i t o r ? s e f f e c t i v e s e r i e s r e s i s t a n c e ( e s r ) t o a c t a s a c u r r e n t - s e n s e r e s i s t o r , s o t h e o u t p u t r i p p l e v o l t a g e p r o v i d e s t h e p w m r a m p s i g n a l . i n p f m o p e r a t i o n , t h e h i g h - s i d e s w i t c h o n - t i m e c o n t r o l l e d b y t h e o n - t i m e g e n e r a t o r i s d e t e r m i n e d s o l e l y b y a o n e - s h o t w h o s e p u l s e w i d t h i s i n v e r s e l y p r o p o r t i o n a l t o i n p u t v o l t a g e a n d d i r e c t l y p r o p o r t i o n a l t o o u t p u t v o l t a g e . i n p w m o p e r a t i o n , t h e h i g h - s i d e s w i t c h o n - t i m e i s d e t e r m i n e d b y a s w i t c h i n g f r e q u e n c y c o n t r o l c i r c u i t i n t h e o n - t i m e g e n - e r a t o r b l o c k . t h e s w i t c h i n g f r e q u e n c y c o n t r o l c i r c u i t s e n s e s t h e s w i t c h - i n g f r e q u e n c y o f t h e h i g h - s i d e s w i t c h a n d k e e p s r e g u l a t - i n g i t a t a c o n s t a n t f r e q u e n c y i n p w m m o d e . t h e d e s i g n i m p r o v e s t h e f r e q u e n c y v a r i a t i o n a n d i s m o r e o u t s t a n d - i n g t h a n a c o n v e n t i o n a l c o n s t a n t o n - t i m e c o n t r o l l e r , w h i c h h a s l a r g e s w i t c h i n g f r e q u e n c y v a r i a t i o n o v e r i n p u t v o l t a g e , o u t p u t c u r r e n t a n d t e m p e r a t u r e . b o t h i n p f m a n d p w m , t h e o n - t i m e g e n e r a t o r , w h i c h s e n s e s i n p u t v o l t a g e o n v i n p i n , p r o v i d e s v e r y f a s t o n - t i m e r e s p o n s e t o i n p u t l i n e t r a n s i e n t s . a n o t h e r o n e - s h o t s e t s a m i n i m u m o f f - t i m e ( t y p i c a l : 2 5 0 n s ) . t h e o n - t i m e o n e - s h o t i s t r i g g e r e d i f t h e e r r o r c o m - p a r a t o r i s h i g h , t h e l o w - s i d e s w i t c h c u r r e n t i s b e l o w t h e c u r r e n t - l i m i t t h r e s h o l d , a n d t h e m i n i m u m o f f - t i m e o n e - s h o t h a s t i m e d o u t . o v e r - c u r r e n t p r o t e c t i o n o f t h e p w m c o n v e r t e r in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: w h e r e f s w i s t h e n o m i n a l s w i t c h i n g f r e q u e n c y o f t h e c o n v e r t e r i n p w m m o d e . t h e l o a d c u r r e n t a t h a n d o f f f r o m p f m t o p w m m o d e i s g i v e n b y : in out sw out in pfm - on out in pwm) to (pfm load v v f 1 2l v - v t l v - v 2 1 i = = in out sw pfm - on v v f 1 t = f o r c e d - p w m m o d e the forced-pwm mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current zero crossing. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while ug maintains a duty factor of v out /v in . the benefit of forced- pwm mode is to keep the switching frequency fairly constant. the forced-pwm mode is most useful for re- ducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- namic output voltage adjustment. when v pfm is above the pfm high threshold (2.5v, minimum), the converter is in forced-pwm mode. when v pfm is below the pfm low threshold (0.5v, maximum), the chip is in automatic pfm/pwm mode. p o w e r - o n - r e s e t a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. should this voltage drop lower than 4.25v (typical), the por disables the chip. e n p i n c o n t r o l when v en is above the en high threshold (2.5v, minimum), the converter is enabled. when v en is below the en low threshold (0.5v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) t h e a p w 8 7 1 3 i n t e g r a t e s s o f t - s t a r t c i r c u i t s t o r a m p u p t h e o u t p u t v o l t a g e o f t h e c o n v e r t e r t o t h e p r o g r a m m e d r e g u - l a t i o n s e t p o i n t a t a p r e d i c t a b l e s l e w r a t e . t h e s l e w r a t e o f o u t p u t v o l t a g e i s i n t e r n a l l y c o n t r o l l e d t o l i m i t t h e i n r u s h c u r r e n t t h r o u g h t h e o u t p u t c a p a c i t o r s d u r i n g s o f t - s t a r t p r o c e s s . w h e n t h e e n p i n i s p u l l e d a b o v e t h e r i s i n g e n t h r e s h o l d v o l t a g e , t h e d e v i c e i n i t i a t e s a s o f t - s t a r t p r o - c e s s t o r a m p u p t h e o u t p u t v o l t a g e . d u r i n g s o f t - s t a r t s t a g e b e f o r e t h e p g o o d p i n i s r e a d y , t h e u n d e r v o l t a g e p r o t e c t i o n i s p r o h i b i t e d . t h e o v e r v o l t - a g e a n d c u r r e n t l i m i t p r o t e c t i o n f u n c t i o n s a r e e n a b l e d . i f t h e o u t p u t c a p a c i t o r h a s r e s i d u e v o l t a g e b e f o r e s t a r t u p , b o t h l o w - s i d e a n d h i g h - s i d e m o s f e t s a r e i n o f f - s t a t e u n t i l t h e s o f t s t a r t v o l t a g e e q u a l t h e v f b v o l t a g e . t h i s w i l l e n s u r e t h e o u t p u t v o l t a g e s t a r t s f r o m i t s e x i s t i n g v o l t a g e l e v e l . i n t h e e v e n t o f u n d e r - v o l t a g e , o v e r - v o l t a g e , o v e r - t e m p e r a - t u r e o r s h u t d o w n , t h e c h i p e n a b l e s t h e s o f t - s t o p f u n c t i o n . t h e s o f t - s t o p f u n c t i o n d i s c h a r g e s t h e o u t p u t v o l t a g e s b y l o w s i d e t u r n s m o s f e t o n l i n e a r l y . p o w e r g o o d i n d i c a t o r pok is actively held low in shutdown and soft-start status. in the soft-start process, the pok is an open-drain. when the soft-start is finished, the pok is released. in normal operation, the pok window is from 90% to 125% of the converter reference voltage. when the output voltage has to stay within this window, pok signal will become high. when the output voltage outruns 90% or 125% of the target voltage, pok signal will be pulled low immediately. in order to prevent false pok drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. u n d e r - v o l t a g e p r o t e c t i o n ( u v p ) in the process of operation, if a short circuit occurs, the output voltage will drop quickly. when load current is big- ger than current limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the fb volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under voltage threshold, the under voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 16ms de-bounce time, the device turns off both high side and low-side mosefet with latched. toggling enable pin to low, or recycling vin, will clear the latch and bring the chip back to operation. s o f t - s t a r t t h e a p w 8 7 1 3 p r o v i d e s t h e p r o g r a m m e d s o f t - s t a r t f u n c - t i o n t o l i m i t t h e i n r u s h c u r r e n t . t h e s o f t - s t a r t t i m e c a n b e p r o g r a m m e d b y t h e e x t e r n a l c a p a c i t o r b e t w e e n s s a n d g n d . t y p i c a l c h a r g e c u r r e n t i s 1 0 u a , a n d t h e s o f t - s t a r t t i m e c a n b e c a l c u l a t e d b y t h e f o l l o w i n g f o r m u l a : o v e r - v o l t a g e p r o t e c t i o n ( o v p ) the over voltage function monitors the output voltage by fb pin. should the fb voltage increase over 125% of the reference voltage due to the high-side mosfet failure or for other reasons, the over voltage protection comparator designed with a 3 m s noise filter will force the low-side mosfet gate driver fully turn on and latch high. this ac- tion actively pulls down the output voltage. this ovp scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side mosfet driver. it?s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can only be reset by toggling en or vin power-on-reset signal. (nf) c 330 s) ( t ss ss = m c u r r e n t l i m i t the current limit circuit employs a "valley" current-sens- ing algorithm (see figure 1). the apw8713 uses the low-side mosfet?s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at lx pin is above the current-limit threshold 11a(minimum), the pwm is not allowed to ini- tiate a new cycle. the actual peak current is greater than the current-limit threshold by an amount equal to the in- ductor ripple current. therefore, the exact current-limit char- acteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 . c u r r e n t l i m i t a l g o r i t h m time i n d u c t o r c u r r e n t 0 i peak i out i limit g i c u r r e n t l i m i t ( c o n t . ) the pwm controller uses the low-side mosfets on-re- sistance r ds(on) to monitor the current for protection against shorted outputs. the mosfet?s r ds(on) is varied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture?s datasheet. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at lx. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when combined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance. o v e r - t e m p e r a t u r e p r o t e c t i o n ( o t p ) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over temperature protection state that suspends the pwm, which forces the ug and lg gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 45 o c. the otp designed with a 45 o c hysteresis lowers the average t j during con- tinuous thermal overload conditions, which increases life- time of the apw8713. p r o g r a m m i n g t h e o n - t i m e c o n t r o l a n d p w m s w i t c h - i n g f r e q u e n c y the apw8713 does not use a clock signal to produce pwm. the device uses the constant on-time control ar- chitecture to produce pseudo-fixed frequency with input voltage feed-forward. the on-time pulse width is propor- tional to output voltage v out and inverse proportional to input voltage v in . in pwm, the on-time calculation is writ- ten as below equation. (v) v ) ( r 10 2 t in ton -12 on w = 3 . 6 where: r ton is the resistor connected from ton pin to vin pin. furthermore, the approximate pwm switching frequency is written as: on in out sw sw on t v v f f d t = = ?a where: f sw is the pwm switching frequency.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n o u t p u t i n d u c t o r s e l e c t i o n the output voltage is adjustable from 0.8v to 12v with a resistor-divider connected with fb, gnd, and converter?|s output. using 1% or better resistors for the resistor-di- vider is recommended. the output voltage is determined by: w h e r e 0 . 8 i s t h e r e f e r e n c e v o l t a g e , r t o p i s t h e r e s i s t o r c o n n e c t e d f r o m c o n v e r t e r ? | s o u t p u t t o f b , a n d r g n d i s t h e r e s i s t o r c o n n e c t e d f r o m f b t o g n d . s u g g e s t e d r g n d i s i n t h e r a n g e f r o m 1 k t o 2 0 k w . t o p r e v e n t s t r a y p i c k u p , l o c a t e r e s i s t o r s r t o p a n d r g n d c l o s e t o a p w 8 7 1 3 . ) r r (1 0.8 v gnd top out + = o u t p u t i n d u c t o r s e l e c t i o n the duty cycle (d) of a buck converter is the function of the input voltage and output voltage. once an output voltage is fixed, it can be written as: o u t p u t c a p a c i t o r s e l e c t i o n o u t p u t v o l t a g e r i p p l e a n d t h e t r a n s i e n t v o l t a g e d e v i a t i o n a r e f a c t o r s t h a t h a v e t o b e t a k e n i n t o c o n s i d e r a t i o n w h e n s e l e c t i n g a n o u t p u t c a p a c i t o r . h i g h e r c a p a c i t o r v a l u e a n d l o w e r e s r r e d u c e t h e o u t p u t r i p p l e a n d t h e l o a d t r a n s i e n t d r o p . t h e r e f o r e , s e l e c t i n g h i g h p e r f o r m a n c e l o w e s r c a p a c i t o r s i s r e c o m m e n d e d f o r s w i t c h i n g r e g u l a t o r a p p l i c a t i o n s . i n a d d i t i o n t o h i g h f r e q u e n c y n o i s e r e l a t e d t o m o s f e t t u r n - o n a n d t u r n o f f , t h e o u t p u t v o l t a g e r i p p l e i n c l u d e s t h e c a p a c i t a n c e v o l t a g e d r o p d v c o u t a n d e s r v o l t a g e d r o p d v e s r c a u s e d b y t h e a c p e a k - t o - p e a k i n d u c t o r ? s c u r r e n t . t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y : in out v v d = the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient response. higher inductor value reduces the inductor?|s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: in out sw out in ripple v v l f v - v i = where f sw is the switching frequency of the regulator. although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor?s ripple current and the regu- lator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an in- ductor that is capable of carrying the required peak cur- rent without going into saturation.in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this re- sults in a larger output ripple voltage. besides, the induc- tor needs to have low dcr to reduce the loss of efficiency. sw out ripple out f c 8 i c = d esr ripple esr r i v = d t h e s e t w o c o m p o n e n t s c o n s t i t u t e a l a r g e p o r t i o n o f t h e t o t a l o u t p u t v o l t a g e r i p p l e . i n s o m e a p p l i c a t i o n s , m u l t i p l e c a p a c i t o r s h a v e t o b e p a r a l l e l e d t o a c h i e v e t h e d e s i r e d e s r v a l u e . i f t h e o u t p u t o f t h e c o n v e r t e r h a s t o s u p p o r t a n o t h e r l o a d w i t h h i g h p u l s a t i n g c u r r e n t , m o r e c a p a c i t o r s a r e n e e d e d i n o r d e r t o r e d u c e t h e e q u i v a l e n t e s r a n d s u p p r e s s t h e v o l t a g e r i p p l e t o a t o l e r a b l e l e v e l . a s m a l l d e c o u p l i n g c a p a c i t o r ( 1 m f ) i n p a r a l l e l f o r b y p a s s i n g t h e n o i s e i s a l s o r e c o m m e n d e d , a n d t h e v o l t a g e r a t i n g o f t h e o u t p u t c a p a c i t o r s a r e a l s o m u s t b e c o n s i d e r e d . t o s u p p o r t a l o a d t r a n s i e n t t h a t i s f a s t e r t h a n t h e s w i t c h - i n g f r e q u e n c y , m o r e c a p a c i t o r s a r e n e e d e d f o r r e d u c i n g t h e v o l t a g e e x c u r s i o n d u r i n g l o a d s t e p c h a n g e . a n o t h e r a s p e c t o f t h e c a p a c i t o r s e l e c t i o n i s t h a t t h e t o t a l a c c u r - r e n t g o i n g t h r o u g h t h e c a p a c i t o r s h a s t o b e l e s s t h a n t h e r a t e d r m s c u r r e n t s p e c i f i e d o n t h e c a p a c i t o r s i n o r d e r t o p r e v e n t t h e c a p a c i t o r f r o m o v e r - h e a t i n g .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i c a t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e d a n c e p c b l a y o u t . i n p u t c a p a c i t o r s e l e c t i o n sw sw in out ds(on) 2 out upper )f )(t )(v 0.5(i )d tc)(r (1 i p + + = b e c a u s e t h e a p w 8 8 0 2 b u i l d - i n h i g h - s i d e a n d l o w - s i d e m o s f e t , t h e h e a t d i s s i p a t e d m a y e x c e e d t h e m a x i m u m j u n c t i o n t e m p e r a t u r e o f t h e p a r t i n a p p l i c a t i o n s . i f t h e j u n c - t i o n t e m p e r a t u r e r e a c h e s a p p r o x i m a t e l y 1 5 0 o c , b o t h p o w e r s w i t c h e s w i l l b e t u r n e d o f f a n d t h e l x n o d e w i l l b e c o m e h i g h i m p e d a n c e . t o a v o i d t h e a p w 8 7 1 3 f r o m e x c e e d i n g t h e m a x i m u m j u n c t i o n t e m p e r a t u r e , t h e u s e r w i l l n e e d t o d o s o m e t h e r m a l a n a l y s i s . t h e g o a l o f t h e t h e r m a l a n a l y s i s i s t o d e t e r m i n e w h e t h e r t h e p o w e r d i s - s i p a t e d e x c e e d s t h e m a x i m u m j u n c t i o n t e m p e r a t u r e o f t h e p a r t . t h e m a i n p o w e r d i s s i p a t e d b y t h e p a r t i s a p p r o x i m a t e d : t h e r m a l c o n s i d e r a t i o n d) - )(1 tc)(r (1 i p ds(on) 2 out lower + = i o u t i s t h e l o a d c u r r e n t t c i s t h e t e m p e r a t u r e d e p e n d e n c y o f r d s ( o n ) f s w i s t h e s w i t c h i n g f r e q u e n c y t s w i s t h e s w i t c h i n g i n t e r v a l d i s t h e d u t y c y c l e n o t e t h a t b o t h i n t e r n a l m o s f e t s h a v e c o n d u c t i o n l o s s e s w h i l e t h e u p p e r m o s f e t i n c l u d e a n a d d i t i o n a l t r a n s i t i o n l o s s . t h e s w i t c h i n g i n t e r n a l , t s w , i s t h e f u n c t i o n o f t h e r e v e r s e t r a n s f e r c a p a c i t a n c e c r s s . t h e ( 1 + t c ) t e r m f a c - t o r s i n t h e t e m p e r a t u r e d e p e n d e n c y o f t h e r d s ( o n ) a n d c a n b e e x t r a c t e d f r o m t h e " r d s ( o n ) v s . t e m p e r a t u r e " c u r v e o f t h e p o w e r m o s f e t . i n a p w 8 7 1 3 c a s e , t h e r d s ( o n ) i s a b o u t 3 0 m w f r o m s p e c i f i c a t i o n t a b l e . layout consideration in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at higher frequency, the resulting current transient will cause volt- age spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off condition, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is freewheeling by the low side mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting impedances and the magni- tude of voltage spike. besides, signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: - keep the switching nodes (boot and lx) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. - the large layout plane between the drain of the mosfets (vin and lx nodes) can get better heat sinking. - the current sense resistor should be close to ocset pin to avoid parasitic capacitor effect and noise coupling. - decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. - the output bulk capacitors should be close to the loads. the input capacitor?s ground should be close to the grounds of the output capacitors. - locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (boot and lx).
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 1 9 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) recommended minimum footprint 0 . 51 mm 0 . 3 mm 0 . 45 mm 4 mm * just recommend tqfn 4 x 4 - 23 0 . 45 mm * 4 mm thermalvia diameter 0 . 3 mm x 12 2 . 6 8 m m 1 . 35 mm 0 . 94 mm 0 . 5 mm 0 . 14 mm 0 . 37 mm 0 . 2 mm
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 0 p a c k a g e i n f o r m a t i o n t q f n 4 x 4 - 2 3 e d pin 1 b a a 1 a 3 nx aaa c e 1 pin 1 corner d 1 d 2 e 2 k l e 0 . 124 d 2 2 . 95 3 . 15 0 . 116 0 . 057 e 1 1 . 24 1 . 44 0 . 049 0 . 70 0 . 041 0 . 028 0 . 002 0 . 50 bsc 0 . 020 bsc k 0 . 20 0 . 008 3 . 90 4 . 10 0 . 154 0 . 161 3 . 90 4 . 10 0 . 154 0 . 161 0 . 08 aaa 0 . 003 s y m b o l min . max . 0 . 80 0 . 00 0 . 20 0 . 30 2 . 58 2 . 78 0 . 05 0 . 85 a a 1 b d d 1 e e 2 e l millimeters a 3 0 . 20 ref tqfn 4 x 4 - 23 0 . 35 0 . 45 1 . 05 0 . 008 ref min . max . inches 0 . 032 0 . 000 0 . 008 0 . 012 0 . 102 0 . 109 0 . 033 0 . 014 0 . 018
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 1 d e v i c e s p e r u n i t c a r r i e r t a p e & r e e l d i m e n s i o n s package type unit quantity tqfn4x4 tape & reel 3000 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.50 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfn4x4 4.00 ? 0.10 8.00 ? 0.10 2.00 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 4.30 ? 0.20 4.30 ? 0.20 1.00 ? 0.20 (mm) h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 2 c l a s s i f i c a t i o n p r o f i l e t a p i n g d i r e c t i o n i n f o r m a t i o n t q f n 4 x 4 user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 3 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - s e p . , 2 0 1 3 a p w 8 7 1 3 w w w . a n p e c . c o m . t w 2 4 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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