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rev.4.2 _00 2-wire cmos serial e 2 prom s-24cs64a seiko instruments inc. 1 the s-24cs64a is a 2-wired, low power and wide range operation 64 k-bit e 2 prom organized as 8192 words 8 bits. page write and sequential read are available. ? features ? low power consumption standby : 5.0 a max. (v cc = 5.5 v) read : 0.8 ma max. (v cc = 5.5 v) ? operating voltage range read : 1.8 to 5.5 v write : 2.7 to 5.5 v ? page write : 32 bytes / page ? sequential read ? operating frequency : 400 khz (v cc = 2.7 to 5.5 v) ? write disable function when power supply voltage is low ? endurance: 10 6 cycles / word *1 (at + 25 c) write capable, 10 5 cycles / word *1 (at + 85 c) *1. for each address (word: 8 bits) ? data retention: 10 years (after rewriting 10 5 cycles / word at + 85 c) ? write protection : 100 % ? lead-free products ? packages drawing code package name package tape reel 8-pin sop (jedec) fj008-a fj008-d fj008-d 8-pin tssop ft008-a ft008-e ft008-e wlp please contact our sales office regarding the product with wlp package. caution this product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devi ces. before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to sii is indispensable.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 2 ? pin configurations 8-pin sop (jedec) top view table 1 pin no. symbol description 1 a0 slave address input 2 a1 slave address input 3 a2 slave address input 4 gnd ground 5 sda serial data input / output 6 scl serial clock input 7 wp write protection input connected to v cc : protection valid connected to gnd: protection invalid 8 vcc power supply remark see dimensions for details of the package drawings. 1 2 3 4 8 7 6 5 vcc wp scl sd a a0 a1 gnd a2 figure 1 s-24cs64a0i-j8t1g 8-pin tssop top view table 2 pin no. symbol description 1 a0 slave address input 2 a1 slave address input 3 a2 slave address input 4 gnd ground 5 sda serial data input / output 6 scl serial clock input 7 wp write protection input connected to v cc : protection valid connected to gnd: protection invalid 8 vcc power supply remark see dimensions for details of the package drawings. 1 2 3 4 8 7 6 5 vcc wp scl sd a a0 a1 gnd a2 figure 2 s-24cs64a0i-t8t1g
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 3 wlp bottom view table 3 pin no. symbol description 1 a0 slave address input 2 vcc power supply 3 wp write protection input connected to v cc : protection valid connected to gnd: protection invalid 4 scl serial clock input 5 sda serial data input / output 6 gnd ground 7 a2 slave address input 8 a1 slave address input vcc wp scl sda gnd 1 5 2 3 4 6 a0 a1 a2 7 8 figure 3 S-24CS64A0I-H8TX remark please contact our sales office r egarding the product with wlp package.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 4 ? block diagram vcc gnd serial clock controller device address comparator address counter y decoder data output ack output controller start / stop detector data register e 2 prom x decoder selector high-voltage generator scl sda a 2 d in d out r / w load inc comp load wp a 1 a 0 voltage detecto r figure 4
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 5 ? absolute maximum ratings table 4 item symbol ratings unit power supply voltage v cc ? 0.3 to + 7.0 v input voltage v in ? 0.3 to + 7.0 v output voltage v out ? 0.3 to + 7.0 v operating ambient temperature t opr ? 40 to + 85 c storage temperature t stg ? 65 to + 150 c caution the absolute maximum ratings are rated values exceeding which the product could suffer physical damage. these values must therefore not be exceeded under any conditions. ? recommended operating conditions table 5 item symbol conditions min. typ. max. unit read operation 1.8 ? 5.5 v power supply voltage v cc write operation 2.7 ? 5.5 v v cc = 2.5 to 5.5 v 0.7 v cc ? v cc v high level input voltage v ih v cc = 1.8 to 2.5 v 0.8 v cc ? v cc v v cc = 2.5 to 5.5 v 0.0 ? 0.3 v cc v low level input voltage v il v cc = 1.8 to 2.5 v 0.0 ? 0.2 v cc v ? pin capacitance table 6 (ta = 25c, f = 1.0 mhz, v cc = 5 v) item symbol conditions min. typ. max. unit input capacitance c in v in = 0 v (scl, a0, a1, a2, wp) ? ? 10 pf input / output capacitance c i / o v i / o = 0 v (sda) ? ? 10 pf ? endurance table 7 item symbol operation temperature min. typ. max. unit endurance n w ? 40 to + 85 c 10 5 ? ? cycles / word *1 *1. for each address (word: 8 bits)
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 6 ? dc electrical characteristics table 8 v cc = 4.5 to 5.5 v f = 400 khz v cc = 2.7 to 4.5 v f = 100 khz v cc = 1.8 to 2.7 v f = 100 khz item symbol conditions min. typ. max. min. typ. max. min. typ. max. unit current consumption (read) i cc1 ? ? ? 0.8 ? ? 0.5 ? ? 0.3 ma current consumption (write) i cc2 ? ? ? 4.0 ? ? 3.0 ? ? ? ma table 9 v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 1.8 to 2.7 v item symbol conditions min. typ. max. min. typ. max. min. typ. max. unit standby current consumption i sb v in = v cc or gnd ? ? 5.0 ? ? 3.0 ? ? 3.0 a input leakage current i li v in = gnd to v cc ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 a output leakage current i lo v out = gnd to v cc ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 a i ol = 3.2 ma ? ? 0.4 ? ? ? ? ? ? v low level output voltage v ol i ol = 1.5 ma ? ? 0.3 ? ? 0.3 ? ? 0.3 v current address hold voltage v ah ? 1.5 ? 5.5 1.5 ? 4.5 1.5 ? 2.7 v
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 7 ? ac electrical characteristics table 10 measurement conditions input pulse voltage 0.1 v cc to 0.9 v cc input pulse rising / falling time 20 ns output judgement voltage 0.5 v cc output load 100 pf + pull-up resistor 1.0 k ? v cc r=1.0 k ? sda c=100 pf figure 5 output load circuit table 11 v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 1.8 to 2.7 v item symbol min. typ. max. min. typ. max. min. typ. max. unit scl clock frequency f scl 0 ? 400 0 ? 400 0 ? 100 khz scl clock time ?l? t low 1.0 ? ? 1.0 ? ? 4.7 ? ? s scl clock time ?h? t high 0.9 ? ? 0.9 ? ? 4.0 ? ? s sda output delay time t aa 0.1 ? 0.9 0.1 ? 0.9 0.1 ? 3.5 s sda output hold time t dh 50 ? ? 50 ? ? 100 ? ? ns start condition setup time t su.sta 0.6 ? ? 0.6 ? ? 4.7 ? ? s start condition hold time t hd.sta 0.6 ? ? 0.6 ? ? 4.0 ? ? s data input setup time t su.dat 100 ? ? 100 ? ? 200 ? ? ns data input hold time t hd.dat 0 ? ? 0 ? ? 0 ? ? ns stop condition setup time t su.sto 0.6 ? ? 0.6 ? ? 4.0 ? ? s scl, sda rising time t r ? ? 0.3 ? ? 0.3 ? ? 1.0 s scl, sda falling time t f ? ? 0.3 ? ? 0.3 ? ? 0.3 s bus release time t buf 1.3 ? ? 1.3 ? ? 4.7 ? ? s noise suppression time t i ? ? 50 ? ? 100 ? ? 100 ns scl sda in sda out t buf t r t su.sto t su.dat t hd.dat t dh t aa t high t low t hd.sta t su.sta t f figure 6 bus timing
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 8 table 12 v cc = 2.7 to 5.5 v item symbol min. typ. max. unit write time t wr ? 6.0 10.0 ms scl sda d0 write data a cknowledge stop condition start condition t wr figure 7 write cycle timing
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 9 ? pin functions 1. a0, a1 and a2 (slave address input) pins the slave address is assigned by connecting pins a0, a1 and a2 to the gnd or to the v cc respectively. one of the eight different slave address can be a ssigned by the combination of pins a0, a1 and a2. the given slave address, which is compared with the slave address transmitted from the master device, is used to select the one among the multiple devices connected to the bus. the address input pin should be connected to the gnd or to the v cc . 2. sda (serial data input / output) pin the sda pin is used for bi-directional transmission of se rial data. it consists of a signal input pin and an nch open-drain output pin. the sda line is usually pulled up to the v cc , and or-wired with other open-drain or open-collector output devices. 3. scl (serial clock input) pin the scl pin is used for serial clock input. since si gnals are processed at the rising or falling edge of the scl clock input signal, attention should be paid to t he rising time and falling time to conform to the specifications. 4. wp (write protection input) pin the write protection is enabled by connecting the wp pin to the v cc . when there is no need for write protection, connect the pin to the gnd.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 10 ? operation 1. start condition start is identified by a high to low transition of the sda line while the scl line is stable at high. every operation begins from a start condition. 2. stop condition stop is identified by a low to high transition of the sda line while the scl line is stable at high. when a device receives a stop condition during a r ead sequence, the read operation is interrupted, and the device enters standby mode. when a device receives a stop condition during a write s equence, the reception of t he write data is halted, and the e 2 prom initiates a write cycle. t su.sta t hd.sta t su.sto start condition stop condition scl sda figure 8 start / stop conditions
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 11 3. data transmission changing the sda line while the scl line is low, data is transmitted. changing the sda line while the scl line is high, a start or stop condition is recognized. t su.dat t hd.dat scl sda figure 9 data transmission timing 4. acknowledge the unit of data transmission is 8 bits. during the 9th clock cycle period the receiver on the bus pulls down the sda line to acknowledge the receipt of the 8-bit data. when a internal write cycle is in progre ss, the device does not generate an acknowledge. 1 8 9 acknowledge output t aa t dh start condition scl (e 2 prom input) sda (master output) sda (e 2 prom output) figure 10 acknowledge output timing
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 12 5. device addressing to start communication, the master device on the system generates a start condition to the bus line. next, the master device sends 7-bit device address and a 1-bi t read / write instruction code on to the sda bus. the 4 most significant bits of the device address are called the ?device code?, and are fixed to ?1010?. successive 3 bits are called the ?slave address?. t hese 3 bits are used to identify a device on the system bus and are compared with the predetermined value whic h is defined by the addre ss input pins (a0, a1 and a2). when the comparison result matches, the sl ave device responds with an acknowledge during the 9th clock cycle. slave address 1 0 1 0 a2 a1 a0 r / w device code lsb msb figure 11 device address 6. write 6.1 byte write when the master sends a 7-bit device address and a 1-bit read / write instruction code set to ?0?, following a start condition, the e 2 prom acknowledges it. the e 2 prom then receives the upper 8 bits of the word address and responds with an acknowledge. and the e 2 prom receives the lower 8 bits of the word address and responds with an acknowledge. after the e 2 prom receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the writ e cycle at the addressed memory. during the write cycle all operations ar e forbidden and no acknowledge is generated. a2 a1 a0 s t a r t 1 0 1 0 w r i t e device address upper word address r / w m s b sda line adr inc ( address increment ) a c k l s b lower word address a c k a c k 0 s t o p data x x x w7 w6 w5 w4 w3 w2 w1 w0 d7 d6 d5 d4 d3 d2 d1 d0 a c k a c k w12 w11 w10 w9 w8 figure 12 byte write
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 13 6.2 page write the page write mode allows up to 32 bytes to be writt en in a single wire operation in the s-24cs64a. basic data transmission procedure is the same as t hat in the ?byte write?. however, when the e 2 prom receives 8-bit write data which corresponds to the page size, the page can be written. when the e 2 prom receives a 7-bit device address and a 1-bi t read / write instruction code set to ?0?, following a start condition, it gener ates an acknowledge. then the e 2 prom receives the upper 8 bits of the word address and responds with an acknowledge. and the e 2 prom receives the lower 8 bits of the word address and responds with an acknowledge. after the e 2 prom receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. the e 2 prom repeats reception of 8- bit write data and generation of acknowledge in succession. the e 2 prom can receive as many write data as the maximum page size. receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data. s t a r t 1 0 1 0 w r i t e s t o p device address lower word address (n) upper word address (n) r / w m s b sda line a2 a1 a0 a c k l s b a c k a c k 0 x x x w12 d7 d0 adr inc a c k adr inc a c k data (n) data (n+x) w11 w10 w9 w7 w5 w4 w3 w2 w1 w0 w6 w8 d7 d0 figure 13 page write the lower 5 bits of the word address are aut omatically incremented every time when the e 2 prom receives 8-bit write data. if the si ze of the write data exceeds 32 byte s, the upper 8 bits of the word address remain unchanged, and the lower 5 bits are rolled over and previously received data will be overwritten.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 14 6.3 write protection write protection is available in the s-24cs 64a. when the wp pin is connected to the v cc , write operation to memory area is forbidden at all. when the wp pin is connected to the gnd, the writ e protection is invalid, and write operation in all memory area is available. fix the level of the wp pin from the rising edge of sc l for loading the last writ e data (d0) until the end of the write time (10 ms max.). if the wp pin changes during this time, the address data being written at this time is not guaranteed. there is no need for using write protection, the wp pin should be connected to the gnd. the write protection is valid in the operating voltage range. sda wp scl acknowledge wp pin fixed period stop condition start condition write data t wr d0 figure 14 wp pin fixed period 6.4 acknowledge polling acknowledge polling is used to know the co mpletion of the write cycle in the e 2 prom. after the e 2 prom receives a stop condition and once starts the write cycle, all operations are forbidden and no response is made to the signal tr ansmitted by the master device. accordingly the master device can recognize the completion of the write cycle in the e 2 prom by detecting a response from the slave device after tr ansmitting the start condition, the device address and the read / write instruction code to the e 2 prom, namely to the slave devices. that is, if the e 2 prom does not generate an acknowledge, the write cycle is in progress and if the e 2 prom generates an acknowledge, the wr ite cycle has been completed. keep the level of the wp pin fix ed until acknowledge is confirmed. it is recommended to use the read instruction ?1? as the read / write instructi on code transmitted by the master device.
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 15 7. read 7.1 current address read either in writing or in reading the e 2 prom holds the last accessed memory address, internally incremented by one. the memory address is maintai ned as long as the power voltage is higher than the current address hold voltage v ah . the master device can read the data at the memory address of the current address pointer without assigning the word address as a result, when it rec ognizes the position of t he address pointer in the e 2 prom. this is called ?current address read?. in the following the address counter in the e 2 prom is assumed to be ?n?. when the e 2 prom receives a 7-bit device address and a 1-bi t read / write instruction code set to ?1? following a start condition, it responds with an acknowledge. next an 8-bit data at the address ?n? is sent from the e 2 prom synchronous to the scl clock. the address counter is incremented at the falling edge of the scl clock for the 8th bit data, and the content of the address counter becomes n + 1. the master device outputs stop condition not an acknowledge, the reading of e 2 prom is ended. s t a r t 1 0 1 0 r e a d s t o p device address r / w m s b sda line a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a c k l s b adr inc 1 data no ack from master device figure 15 current address read attention should be paid to the following point on the recognition of the address pointer in the e 2 prom. in the read operation the memory address counter in the e 2 prom is automatically incremented at every falling edge of the scl clock for the 8th bit of the out put data. in the write operation, on the other hand, the upper 8 bits of the memory address are left unchanged and are not incremented at the falling edge of the scl clock for the 8th bit of the received data.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 16 7.2 random read random read is used to read the data at an arbitrary memory address. a dummy write is performed to load the me mory address into the address counter. when the e 2 prom receives a 7-bit device address and a 1-bi t read / write instruction code set to ?0? following a start condition, it responds with an acknowledge. the e 2 prom then receives an 8-bit upper word address and responds with an acknowledge. next the e 2 prom then receives an 8-bit lower word address and responds with an acknowledge. the memory address is loaded to the address counter in the e 2 prom by these operations. recepti on of write data does not follow in a dummy write whereas reception of write data follows in a byte write and in a page write. since the memory address is loaded into the memory address counter by dummy wr ite, the master device can read the data starting from the arbitrary memo ry address by transmitting a new start condition and performing the same operation in the current address read. that is, when the e 2 prom receives a 7-bit device address and a 1- bit read / write instruction code set to ?1?, following a start condition signal, it responds wi th an acknowledge. next, 8-bit data is transmitted from the e 2 prom in synchronous to the scl clock. t he master device outputs stop condition not an acknowledge, the reading of e 2 prom is ended. sda line s t a r t 1 0 1 0 w r i t e device address lower word address r / w m s b a2 a1 a0 a c k l s b w7 w6 w5 w4 w3 w2 w1 a c k 0 dummy write s t o p s t a r t 1 0 1 0 r e a d device address r / w m s b a2 a1 a0 a c k l s b 1 <
$?x no ack from master device adr inc data upper word address x w9 w8 x x x d7 d6 d5 d4 d3 d2 d1 d0 a c k w12 w11 w10 w0 figure 16 random read
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 17 7.3 sequential read when the e 2 prom receives a 7-bit device address and a 1-bit read / write instruction code set to ?1? following a start condition both in current and random read operations, it responds with an acknowledge. an 8-bit data is then sent from the e 2 prom synchronous to the scl clock and the address counter is automatically incremented at the falling edge of the scl clock for the 8th bit data. when the master device responds with an acknowl edge, the data at the next memory address is transmitted. response with an acknowledge by the mast er device has the memory address counter in the e 2 prom incremented and makes it possible to read data in succession. this is called ?sequential read?. the master device outputs stop condition not an acknowledge, the reading of e 2 prom is ended. data can be read in succession in the sequential r ead mode. when the memory address counter reaches the last word address, it rolls over to the first memory address. r e a d s t o p device address r / w adr inc a c k a c k a c k 1 adr inc a c k adr inc sda line data(n) d7 d0 d7 d0 d7 d0 d7 d0 data (n+1) data (n+2) data (n+x) no ack from master device adr inc figure 17 sequential read
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 18 8. address increment timing the timing for the automatic address increment is the falling edge of the scl clock for the 8th bit of the read data in read operation and the the falling edge of the scl clock for the 8th bit of the received data in write operation. scl sda r / w=1 a ddress increment 891 89 d7 output d0 output a ck output figure 18 address increment timing in reading scl sda r / w=0 891 89 d7 input d0 input a ck output a ck output a ddress increment figure 19 address increment timing in writing ? write inhibition function at low power voltage the s-24cs64a have a detection circuit for low power voltage. the detection circuit cancels a write instruction when the power voltage is low or the pow er switch is on. the detection voltage is 1.85 v typically and the release voltage is 1.95 v typically, the hysteresis of approximate 0.1 v thus exists. (see figure 20 .) when a low power voltage is detected, a write instruction is canceled at the reception of a stop condition. when the power voltage lowers during a data transmission or a write operation, the date at the address of the operation is not assured. power supply voltage write instruction cancel release voltage (+v det ) 1.95 v typ. detection voltage (-v det ) 1.85 v typ. hysteresis width 0.1 v approximately figure 20 operation at low power voltage
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 19 ? using s-24cs64a 1. adding a pull-up resistor to sda i/o pin and scl input pin add a 1 to 5 k ? pull-up resistor to the scl input pin *1 and the sda i/o pin in order to enable the functions of the i 2 c-bus protocol. normal communication c annot be provided without a pull-up resistor. *1. when the scl input pin of the e 2 prom is connected to a tri-state output pin of the microprocessor, connect the same pull-up resistor to prevent a high impedance status from being input to the scl input pin. this protects the e 2 prom from malfunction due to an undefined output (high impedance) from the tri- state pin when the microprocessor is reset when the voltage drops. 2. i/o pin equivalent circuit the i/o pins of this ic do not include pull-up and pull-down resistors. the sda pin is an open-drain output. the following shows the equivalent circuits. scl figure 21 scl pin sda figure 22 sda pin
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 20 wp figure 23 wp pin a0, a1, a2 figure 24 a0, a1, a2 pin
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 21 3. matching phases while e 2 prom is accessed the s-24cs64a does not have a pin for resetting (the internal circuit), therefore, the e 2 prom cannot be forcibly reset externally. if a communication interruption occurs in the e 2 prom, it must be reset by software. for example, even if a reset signal is input to t he microprocessor, the internal circuit of the e 2 prom is not reset as long as the stop condition is not input to the e 2 prom. in other words, the e 2 prom retains the same status and cannot shift to the next operation. this symptom applies to the case when only the microprocessor is reset when the power supply voltage dr ops. with this status, if the power supply voltage is restored, reset the e 2 prom (after matching the phase with the microprocessor) and input an instruction. the following shows this reset method. [how to reset e 2 prom] the e 2 prom can be reset by the start and stop instructions. when the e 2 prom is reading data ?0? or is outputting the acknowledge signal, 0 is output to t he sda line. in this status, the microprocessor cannot output an instruction to the sda line. in this case, terminate the acknowledge output operation or read operation, and then input a start instruction. figure 25 shows this procedure. first, input the condition. then transmit 9 clocks ( dummy clocks) of scl. during this time, the microprocessor sets the sda line to high level. by this operation, the e 2 prom interrupts the acknowledge output operation or data output, so input the start condition *1 . when a start condition is input, the e 2 prom is reset. to make doubly sure, input the stop condition to the e 2 prom. normal operation is then possible. 9 8 2 1 scl sda start condition stop condition start condition dummy clock figure 25 resetting e 2 prom *1. after 9 clocks (dummy clocks), if the scl clo ck continues to be output without a start condition being input, a write operation may be started upon receip t of a stop condition. to prevent this, input a start condition after 9 clocks (dummy clocks). remark it is recommended to perform the above rese t using dummy clocks when the system is initialized after the power supply voltage has been raised.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 22 4. acknowledge check the i 2 c-bus protocol includes an acknowledge check function as a handshake function to prevent a communication error. this function allows detecti on of a communication failure during data communication between the microprocessor and e 2 prom. this function is effective to prevent malfunction, so it is recommended to perform an acknowledge check on the microprocessor side. 5. built-in power-on-clear circuit e 2 proms have a built-in power-on-clear circuit that initializes the e 2 prom. unsuccessful initialization may cause a malfunction. for the power-on-clear circ uit to operate normally, the following conditions must be satisfied for raising the power supply voltage. 5.1 raising power supply voltage raise the power supply voltage, starting at 0.2 v maxi mum, so that the voltage reaches the power supply voltage to be used within the time defined by t rise as shown in figure 26 . for example, when the power supply voltage to be used is 5.0 v, t rise is 200 ms as shown in figure 27 . the power supply voltage must be raised within 200 ms. 0.2 v v init (max.) t init *2 (max.) t rise (max.) power supply voltage (v cc ) 0 v *1 *1. 0 v means there is no difference in potential between the vcc pin and the gnd pin of the e 2 prom. *2. t init is the time required to initialize the e 2 prom. no instructions are accepted during this time. figure 26 raising power supply voltage
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 23 rise time (t rise ) max. [ms] power supply voltage (v cc ) [v] 50 5.0 4.0 3.0 2.0 100 150 200 for example: if your e 2 prom supply voltage = 5.0 v, raise the power supply voltage to 5.0 v within 200 ms. figure 27 raising time of power supply voltage when initialization is successfully comple ted via the power-on-clear circuit, the e 2 prom enters the standby status. if the power-on-clear circuit does not operat e, the following are the possible causes. (1) because the e 2 prom has not been initialized, an instruction fo rmerly input is valid or an instruction may be inappropriately recognized. in this case, writing may be performed. (2) the voltage may have dropped due to power off while the e 2 prom is being accessed. even if the microprocessor is reset due to the low power voltage, the e 2 prom may malfunction unless the power-on-clear operation conditions of e 2 prom are satisfied. for the power-on-clear operation conditions of e 2 prom, refer to 5.1 raising power supply voltage . if the power-on-clear circuit does not operate, ma tch the phase (reset) so that the internal e 2 prom circuit is normally reset. the statuses of the e 2 prom immediately after the power-on-clear circuit operates and when phase is matched (reset) are the same.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 24 5.2 wait for the initialization sequence to end the e 2 prom executes initialization during the time t hat the supply voltage is increasing to its normal value. all instructions must wait until after initializ ation. the relationship between the initialization time (t init ) and rise time (t rise ) is shown in figure 28 . rise time (t rise ) [s] e 2 prom initialization time (t init ) max. [s] 100 m 10 m 1.0 m 100 10 1.0 1.0 10 100 1.0 m 10 m 100 m figure 28 initialization time of e 2 prom
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 25 6. data hold time (t hd. dat = 0 ns) if scl and sda of the e 2 prom are changed at the same time, it is necessary to prevent the start / stop condition from being mistakenly recognized due to the effect of noise. if a start / stop condition is mistakenly recognized during communication, the e 2 prom enters the standby status. it is recommended that sda is delayed from the falling edge of scl by 0.3 s minimum in the s-24cs64a. this is to prevent time lag caused by the load of t he bus line from generating the stop (or start) condition. scl sda t hd. dat = 0.3 s min. figure 29 e 2 prom data hold time 7. sda pin and scl pin noise suppression time the s-24cs64a includes a built-in low-pass filter to suppress noise at the sda and scl pins. this means that if the power supply voltage is 5.0 v, noise with a pulse width of 160 ns or less can be suppressed. the guaranteed for details, refer to noise suppression time (t i ) in table 11 . noise suppression time (t i ) max. [ns] 200 100 300 2 3 4 5 power supply voltage (v cc ) [v] figure 30 noise suppression time for sda and scl pins
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 26 8. trap: e 2 prom operation in case that the stop condition is received during write operation before receiving the defined data value (l ess than 8-bit) to scl pin when the e 2 prom receives the stop condition signal compulso rily, during receiving 1 byte of write data, ?write? operation is aborted. when the e 2 prom receives the stop condition signal after receiving 1 byte or more of data for ?page write?, 8-bit of data received normally before re ceiving the stop condition signal can be written. 9. trap: e 2 prom operation and write data in case that write data is input more than defined page size at ?page write? when write data is input more than defined page size at page write operation, fo r example, s-24cs64a (which can be executed 32-byte page write) is received data more than 33 byte, 8-bit data of the 33rd byte is over written to the first byte in the same page. data over the capacity of page address cannot be written. 10. trap: severe environments absolute maximum ratings: do not operate these ics in excess of the absolute max ratings, as listed on the data sheet. exceeding the suppl y voltage rating can cause latch-up. operations with moisture on the e 2 prom pins may occur malfunction by short-circuit between pins. especially, in occasions like picking the e 2 prom up from low temperature tank during the evaluation. be sure that not remain frost on e 2 prom pin to prevent malf unction by short-circuit. also attention should be paid in using on environmen t, which is easy to dew for the same reason.
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 27 ? precautions do not apply an electrostatic discharge to this ic that exceeds the performance ratings of the built-in electrostatic protection circuit. sii claims no responsibility for any and all disputes aris ing out of or in connection with any infringement of the products including this ic upon patents owned by a third party. ? precautions for wlp package the side of device silicon substrate is exposed to t he marking side of device package. since this portion has lower strength against the mechanical stress t han the standard plastic package, chip, crack, etc should be careful of the handing of a package enough. moreover, the exposed side of silicon has electrical potential of device substr ate, and needs to be kept out of cont act with the external potential. in this package, the overcoat of the resin of trans lucence is carried out on the side of device area. keep it mind that it may affect the characteristic of a dev ice when exposed a device in the bottom of a high light source.
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 28 ? characteristics (typical data) 1. dc characteristics 1.1 current consumption (read) i cc1 1.2 current consumption (read) i cc1 ? ambient temperature ta ? ambient temperature ta v cc = 5.5 v f scl = 100 khz dat a = 0101 ?40 0 85 300 100 200 0 i cc1 ( a) ta ( c) ta ( c) v cc = 3.3 v f scl = 100 khz data = 0101 ?40 0 85 300 100 200 0 i cc1 ( a) 1.3 current consumption (read) i cc1 1.4 current consumption (read) i cc1 ? ambient temperature ta ? power supply voltage v cc v cc = 1.8 v f scl = 100 khz data = 0101 300 100 200 0 i cc1 ( a) ta ( c ) ?40 0 85 ta = 25 c f scl = 100 khz data = 0101 2 3 4 5 6 7 v cc (v) 300 100 200 0 i cc1 ( a) 1.5 current consumption (read) i cc1 1.6 current consumption (read) i cc1 ? power supply voltage v cc ? clock frequency f scl ta = 25 c f scl = 400 khz data = 0101 2 3 4 5 6 7 v cc (v) 500 200 400 0 i cc1 ( a) 300 100 v cc = 5.0 v ta = 25 c 100k f scl (hz) 400k 1m i cc1 ( a) 500 200 400 300 100
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 29 1.7 current consumption (program) i cc2 1.8 current consumption (program) i cc2 ? ambient temperature ta ? ambient temperature ta v cc = 5.5 v ta ( c) ?40 0 85 1.0 0.5 0 i cc2 (ma) 1.5 v cc = 3.3 v ta ( c) ?40 0 85 i cc2 (ma) 1.0 0.5 0 1.5 1.9 current consumption (program) i cc2 1.10 current consumption (program) i cc2 ? ambient temperature ta ? power supply voltage v cc v cc = 2.7 v i cc2 (ma) ta ( c) ?40 0 85 1.0 0.5 0 1.5 ta = 25 c v cc (v) i cc2 (ma) 2 1 3 4 5 6 1.0 0.5 0 1.5 1.11 standby current consumption i sb 1.12 input leakage current i li ? ambient temperature ta ? ambient temperature ta 2.0 1.0 v cc = 5.5 v 0 i sb ( a) ta ( c) ?40 0 85 1.0 0.5 0 i li ( a) ta ( c ) ?40 0 85 v cc = 5.5 v sda, scl, wp = 0 v
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 30 1.13 input leakage current i li 1.14 output leakage current i lo ? ambient temperature ta ? ambient temperature ta 1.0 0.5 v cc = 5.5 v 0 i li ( a) ta ( c ) ?40 0 85 sda, scl, wp = 5.5 v 1.0 0.5 v cc = 5.5 v sda = 0 v 0 i lo ( a) ta ( c) ?40 0 85 1.15 output leakage current i lo 1.16 low level output voltage v ol ? ambient temperature ta ? low level output current i ol 1.0 0.5 v cc = 5.5 v sd a = 5.5 v 0 i lo ( a) ta ( c) ?40 0 85 0.3 0.2 v ol (v) 0.1 0 2 1 3 4 5 6 ta =? 40 c i ol (ma) v cc = 1.8 v v cc = 5.0 v 1.17 low level output voltage v ol 1.18 low level output voltage v ol ? low level output current i ol ? low level output current i ol 0.3 0.2 v ol (v) 0.1 0 2 1 3 4 5 6 ta = 25 c i ol (ma) v cc = 1.8 v v cc = 5.0 v 0.3 0.2 v ol (v) 0.1 0 2 1 3 4 5 6 ta = 85 c i ol (ma) v cc = 1.8 v v cc = 5.0 v
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 31 1.19 high input inversion voltage v ih 1.20 high input inversion voltage v ih ? power supply voltage v cc ? ambient temperature ta ta = 25 c sda, scl 1.0 0 2.0 3.0 v ih (v) v cc (v) 7 6 2 3 4 5 1 v cc = 5.0 v sda, scl 1.0 0 2.0 3.0 v ih (v) ta ( c ) ?40 0 85 1.21 low input inversion voltage v il 1.22 low input inversion voltage v il ? power supply voltage v cc ? ambient temperature ta 1.0 0 2.0 3.0 v il (v) v cc (v) 7 6 2 3 4 5 1 ta = 25 c sda, scl 1.0 0 2.0 3.0 v il (v) ta (c) ?40 0 85 v cc = 5.0 v sda, scl 1.23 low power supply detection voltage ? v det 1.24 low power supply release voltage + v det ? ambient temperature ta ? ambient temperature ta 1.0 0 2.0 ? v det (v) ta (c) ?40 0 85 1.0 0 2.0 +v det (v) ta (c) ?40 0 85
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 32 2. ac characteristics 2.1 maximum operating frequency f max. 2.2 write time t wr ? power supply voltage v cc ? power supply voltage v cc 10k 2 3 4 5 ta = 25 c v cc (v) f max. (hz) 1 100k 1m v cc (v) 8 4 ta = 25 c t wr (ms) 2 6 0 6 2 3 4 5 1 2.3 write time t wr ? ambient temperature ta 2.4 write time t wr ? ambient temperature ta v cc = 4.5 v t wr (ms) 9 6 3 0 ta ( c) ?40 0 85 v cc = 2.7 v t wr (ms) 9 6 3 0 ta ( c) ?40 0 85 2.5 sda output delay time t aa 2.6 sda output delay time t aa ? ambient temperature ta ? ambient temperature ta ta ( c) ?40 0 85 v cc = 4.5 v 1.0 0.5 t aa ( s) 0 ta ( c) ?40 0 85 v cc = 2.7 v 1.0 0.5 t aa ( s) 0
2-wire cmos serial e 2 prom rev.4.2 _00 s-24cs64a seiko instruments inc. 33 2.7 sda output delay time t aa ? ambient temperature ta ta( c) ?40 0 85 v cc = 1.8 v 1.0 0.5 t aa ( s) 0
2-wire cmos serial e 2 prom s-24cs64a rev.4.2 _00 seiko instruments inc. 34 ? product name structure 1. 8-pin sop(jedec), 8-pin tssop packages s-24cs64a 0i - xxxx g package name (abbreviation) and ic packing specifications j8t1: 8-pin sop (jedec), tape t8t1: 8-pin tssop, tape fixed product name s-24cs64a: 64 kbit 2. wlp package s-24cs64a 0i - h8tx package name (abbreviation) and ic packing specifications h8tx: wlp, tape fixed product name s-24cs64a: 64 kbit remark please contact our sales office r egarding the product with wlp package.

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the information described herein is subject to change without notice. seiko instruments inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. when the products described herein are regulated products subject to the wassenaar arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. use of the information described herein for other purposes and/or reproduction or copying without the express permission of seiko instruments inc. is strictly prohibited. the products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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