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1 features two drivers and two receivers with individual enables >400.0 mbps (200 mhz) switching rates + 340mv differential signaling 3.3 v power supply ttl compatible inputs 10ma lvds output drivers ttl compatible outputs cold spare all pins ultra low power cmos technology operational environment; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) - latchup immune (let > 100 mev-cm 2 /mg) packaging options: - 18-lead flatpack (dual in-line) standard microcircuit drawing 5962-06202 - qml q and v compliant part introduction the ut54lvdm055lv dual driv er/dual receiver is designed for applications requiring ultra low power dissipation and high data rates. the device is designe d to support data rates in excess of 400.0 mbps (200 mhz) utilizing low voltage differential signaling (lvds) technology. the ut54lvdm055lv driver accepts low voltage ttl input levels and translates them to low voltage (350mv) differential output signals. in addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to a low idle power state. the ut54lvdm055lv receiver accepts low voltage (350mv) differential input signals and translates them to 3v cmos output levels. the receiver suppor ts a three-state function that may be used to multiplex output s. the receiver also supports open, shorted and terminated (35 ) input fail-safe. receiver output will be high for all fail-safe conditions. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvdm055lv dual driver and receiver data sheet december 2008 www.aeroflex.com/lvds figure 1. ut54lvdm055lv dual dr iver and receiver block diagram + r1 - r in1+ r in1- r in2+ r in2- den2 r out1 r out2 d in1 d in2 + r2 - d2 d1 den1 d out2- d out2+ d out1+ d out1- ren1 ren2
2 truth table pin description enables input output d en d in d out+ d out- l x z z h l l h h h l enables input output r en r in+ - r in -r out lxz hv id > 0.1v h v id < -0.1v l full fail-safe open/short or terminated h figure 2. ut54lvdm055lv pinout ut54lvdm055lv driver/receiver 18 17 16 15 14 13 12 r en1 r out1 r out2 gnd v dd d en2 d in2 1 r in1- 2 r in1+ 3 r in2+ 4 r in2- 5 r en2 6 d out2- 7 d out2+ 8 9 d out1+ d out1- 11 d in1 10 d en1 pin no. name description 11, 12 d in driver input pin, ttl/cmos compatible 7, 8 d out+ non-inverting driver output pin, lvds levels 6, 9 d out - inverting driver output pin, lvds levels 10, 13 d en driver active high enable pin 2, 5 r in+ non-inverting receiver input pin 1, 4 r in- inverting receiver input pin 16, 17 r out receiver output pin 5, 18 r en receiver active high enable pin 14 v dd power supply pin, +3.3 + 0.3v 15 v ss ground pin
3 applications information the ut54lvdm055lv provides two drivers and two receiv- ers in the same package. each driver and each receiver has a dedicated output enable pin. th is allows maximum flexibility for the device. the intended application of th ese devices and signaling tech- nique is for both point-to-point (single termination) and multi- point (double termination) data transmissions over controlled impedance media. the transmission media may be printed-cir- cuit board traces, backplanes, or cables. (note: the ultimate rate and distance of data transf er is dependent upon the attenu- ation characteristics of the me dia, the noise coupling to the environment, and other appli cation specific characteristics.) the ut54lvms055lv differential line driver is a balanced current source design. a current mode driver, has a high out- put impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a con- stant voltage for a range of loads). current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic stat e. the current mode requires that a resistive termination be employed to ter- minate the signal and to complete the loop as shown in figure 3. ac or unterminated configur ations are not allowed. the 10ma loop current will develop a differential voltage of 350mv across the 35 termination resistor which the receiver detects with a 250mv minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350mv - 100mv = 250mv)). the signal is centered around +1.2v (driver offset, vos) with respect to ground as shown in figure 4. note: the steady-state voltage (vss) peak-to-peak swing is twice th e differential voltage (vod) and is typically 700mv. the ut54lvdm055lv receiver?s are capable of detecting signals as low as 100mv, over a +/- 1v common- mode range centered around +1.2v. both receiver input pins should honor their specified operating input voltage range of 0v to +2.4v (measured from each pin to ground). the receiver is connected to th e driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply pcb traces . the termination resistor con- verts the current sourced by the driver into voltages that are detected by the receiver. othe r configurations are possible such as a multi-receiver configurat ion, but the effects of a mid- stream connector(s), cable stub (s), and other impedance dis- continuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. receiver fail-safe the ut54lvdm055lv receiver is a high gain, high speed device that amplifies a small diff erential signal (20mv) to ttl logic levels. due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. the receiver?s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating, terminated or shor ted receiver inputs. open input pins . the ut54lvdm055lv is a dual receiver device, and if an application re quires only 1 receiver, the unused channel inputs should be left open. do not tie unused receiver inputs to ground or any other voltages. the input is biased by internal high value pull up and pull down resistors to set the output to a high state. this in ternal circuitry will guarantee a high, stable output st ate for open inputs. terminated input . if the driver is disconnected (cable unplugged), or if the driver is in a three-state or power-off condition, the receiver output w ill again be in a high state, even with the end of cable 35 termination resistor across the input pins. the unplugged cable can become a floating antenna which can pick up noise. if the cable picks up more than 10mv of differential noise, the receiver may see the noise as a valid signal and switch. to insure that any noise is seen as common- mode and not differential, a ba lanced interconnect should be used. twisted pair cable offers better balance than flat ribbon cable. shorted inputs . if a fault condition occurs that shorts the receiver inputs together, thus resu lting in a 0v differential input voltage, the receiver output rema ins in a high state. shorted input fail-safe is not supported across the common-mode range of the device (v ss to 2.4v). it is only supported with inputs shorted and no external co mmon-mode voltage applied. enable data input lvds driver lvds receiver + - data output figure 3. point-to-point application rt 35
4 operational environment absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute ma ximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operationa l sections of this specifi cation is not recommended. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability and performance. 2. maximum junction temperatur e may be increased to +175 c during burn-in and life test. 3. test per mil-std-883, method 1012. recommended operating conditions parameter limit units total ionizing dose (tid) 1.0e6 rad(si) single event latchup (sel) >100 mev-cm 2 /mg symbol parameter limits v dd dc supply voltage -0.3 to 4.0v v i/o voltage on any pin during operation -0.3 to (v dd + 0.3v) voltage on any pin during cold spare -.3 to 4.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.25 w t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -55 to +125 c v in dc input voltage, receiver inputs dc input voltage, logic inputs 2.4v 0 to v dd
5 dc electrical characteristics driver * 1, 2,4 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referen ced to ground except differential voltages. 2. output short circuit current (i os ) is specified as magnitude only, mi nus sign indicates direction only. 3. guaranteed by characterization 4. receivers are included for parameters i ccl and i ccz . symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v v il low-level input voltage (ttl) 0.8 v v ol low-level output voltage r l = 35 0.855 v v oh high-level output voltage r l = 35 1.750 v i in input leakage current v in = v dd or gnd, v dd = 3.6v -5 +5 a i cs cold spare leakage current v in =3.6v, v dd =v ss -10 +10 ? v od 1 differential output voltage r l = 35 (figure 5) 250 400 mv v od 1 change in magnitude of v od for complementary output states r l = 35 (figure 5) 35 mv v os offset voltage r l = 35 , v os = 1.055 1.550 v v os change in magnitude of v os for complementary output states r l = 35 (figure 5) 35 mv v cl input clamp voltage i cl = +18ma -1.5 v i os 2, 3 output short circuit current v in = v dd , v out+ = 0v or v in = gnd, v out- = 0v, d en = v dd 40 ma i oz output three-state current d en = 0.8v v out = 0v or v dd, v dd = 3.6v -5 +5 ? i ccl 4 loaded supply current, drivers and receivers enabled r l = 35 all channels r en = d en = v dd v in = v dd or v ss (all inputs) 40.0 ma i ccz 4 loaded supply current, drivers and receivers disabled d in = v dd or v ss r en = d en = v ss 15.0 ma voh vol + 2 -------------------------------- - ?? ??
6 ac switching characteristics driver* 1, 2, 3 (v dd = +3.3v + 0.3v, t c = -55 c to +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irr adiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the ma ximum tid level procured. 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50, t r < 1ns, and t f < 1ns. 3. c l includes probe and jig capacitance. 4. guaranteed by characterization 5. chip to chip skew is defi ned as the difference between the minimum and maximum specified differ ential propagation delays. 6. may be tested at higher load capacita nce and the limit interp olated from character ization data to guar antee this parameter. symbol parameter min max unit t phld 6 differential propagation delay high to low (figures 5 and 6) 0.5 1.8 ns t plhd 6 differential propagation delay low to high (figures 5 and 6) 0.5 1.8 ns t skd differential skew (t phld - t plhd ) (figures 5 and 6) 0 0.4 ns t sk1 1 channel-to-channel skew (figures 5 and 6) 0 0.5 ns t sk2 5 chip-to-chip skew (figure 5 and 6) 1.3 ns t tlh 4 rise time (figures 5 and 6) 1.5 ns t thl 4 fall time (figures 5 and 6) 1.5 ns t phz disable time high to z (figures 7 and 8) 5 ns t plz disable time low to z (figures 7 and 8) 5 ns t pzh enable time z to high (figures 7 and 8) 7.0 ns t pzl enable time z to low (figures 7 and 8) 7.0 ns
7 dc electrical characteristics receiver* 1,2,4 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referen ced to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not exce ed 1 second. 3. guaranteed by characterization. 4. refer to driver dc characteristics for i ccl and i ccz . symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v v il low-level input voltage (ttl) 0.8 v v ol low-level output voltage i ol = 2ma, v dd = 3.0v 0.25 v v oh high-level output voltage i oh = -0.4ma, v dd = 3.0v 2.7 v i in logic input leakage current enables = r en = 0 and 3.6v, v dd = 3.6 -5 +5 a i i lvds receiver input current v in = 2.4v, v dd = 3.6 -15 +15 ? i cs cold spare leakage current v in =3.6v, v dd =v ss -10 +10 ? v th 3 differential input high threshold v cm = +1.2v +100 mv v tl 3 differential input low threshold v cm = +1.2v -100 mv i oz 3 output three-state current disabled, v out = 0 v or v dd r en = 0.8v -5 +5 ? v cl input clamp voltage i cl = -18ma -1.5 v i os 2, 3 output short circuit current enabled, v out = 0 v 2 r en = v dd -75 ma
8 ac switching characteristics receiver* 1, 2, 3 (v dd = +3.3v + 0.3v, t a = -55 c to +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irr adiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the ma ximum tid level procured. 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. generator waveform for all tests unless otherwise specified: f = 1 mhz, z 0 = 50 , t r and t f (0% - 100%) < 1ns for r in and t r and t f < 1ns for en or en . 3. c l includes probe and jig capacitance. 4. guaranteed by characterization. 5. chip to chip skew is defi ned as the difference between the minimum and maximum specified differ ential propagation delays. 6. may be tested at higher load capacita nce and the limit interp olated from character ization data to guar antee this parameter. 7. during t pzl the output may transitio n high before going low. symbol parameter min max unit t phld 6 differential propagation delay high to low (figures 9 and 10) 1.0 2.0 ns t plhd 6 differential propagation delay low to high (figures 9 and 10) 1.0 2.0 ns t skd differential skew (t phld - t plhd ) (figures 9 and 10) 0 0.35 ns t sk1 1 channel-to-channel skew (figures 9 and 10) 0 0.5 ns t sk2 5 chip-to-chip skew (figures 9 and 10) 1.0 ns t tlh 4 rise time (figures 9 and 10) 1.2 ns t thl 4 fall time (figures 9 and 10) 1.2 ns t phz disable time high to z (figures 11 and 12) 4.0 ns t plz disable time low to z (figures 11 and 12) 4.0 ns t pzh enable time z to high (figures 11 and 12) 3.0 ns t pzl 7 enable time z to low (figures 11 and 12) 3.0 ns
9 figure 4. driver v od and v os test circuit or equivalent circuit d d in d out- d out+ 40pf driver enabled generator 50 r l = 35 v od 40pf d d in d out- d out+ driver enabled generator 50 r l = 35 figure 5. driver propagation delay and transition time test circuit or equivalent circuit 40pf 40pf
10 d in d out- d out+ v diff t phld v dd 0v v oh v ol 0v v diff = d out+ - d out- 0v (differential) v dd /2 t thl 20% 80% 0v 20% 80% t tlh t plhd v dd /2 figure 6. driver propagation delay and transi tion time waveforms or equivalent circuit d v dd v ss d in en generator 50 en 17.5 d out+ d out- figure 7. driver three-state delay test circuit or equivalent circuit or equivalent circuit 40pf 40pf 17.5
11 en when en = v dd en when en = v ss or d out+ when d in =v dd d out- when d in = v ss d out+ when d in = v ss d out- when d in = v dd t plz t pzl 50% 50% v ol v os v os v oh 0v v dd 0v v dd v dd /2 v dd /2 v dd /2 v dd /2 50% t pzh t phz figure 8. driver three-state delay waveform or eq uivlent circuit 50%
12 r r in+ r out receiver enabled generator 50 figure 9. receiver propagation delay and transiti on time test circuit or equivalent circuit r in- 50 40pf r in- r in+ r out t phld v ol v oh +1.1v 50% +1.2v t thl 20% 80% 50% 20% 80% t tlh 0v differential figure 10. receiver propagation delay and transi tion time waveforms or equivalent circuits t plhd v id = 200mv +1.3v
13 figure 11. receiver three-st ate delay test circuit or equivalent circuit r in+ r in- en v dd 100 100 40pf en when en = v dd en when en = v ss output when v id = -100mv output when v id = +100mv t phz t pzh 50% 50% v oh v dd/2 v dd/2 0v v dd 0v v dd v dd /2 v dd /2 v dd /2 v dd /2 50% t pzl t plz figure 12. receiver three-state del ay waveform or equivalent circuit 50% v ol
14 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. lead position and copl anarity are not measured. 5. id mark symbol is vendor option and may be different than shown. 6. with solder, increase maximum by 0.003. 7. package weight 0.8 grams. figure 13. 18-pin ceramic flatpack
15 ordering information ut54lvdm055lv dual driver/receiver: ut 54lvdm055lv- * * * * * device type: ut54lvdm055lv lvds receiver access time: not applicable package type: (u) = 18-lead flatpack (dual-in-line) screening: (c) = hirel temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, th en the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aerofl ex colorado springs manufacturing flow s document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
16 ut54lvdm055lv dual driver/receiver: smd 5962 - ** * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) drawing number: 5962-06202 device type 01 - dual driver receiver 100krad(si) 300krad(si) class designator: (q) = qml class q (v) = qml class v case outline: (x) = 18 lead fl atpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) ** 06202 notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
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