View UPD720100AGM-8EY_7332177.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd720100a usb2.0 host controller document no. s15535ej2v0ds00 (2nd edition) date published october 2002 ns cp (k) printed in japan data sheet the mark shows major revised points. ? 2001 the pd720100a complies with the universal serial bus specification revision 2.0 and open host controller interface specification for full-/low-speed signaling and intel's enhanced host controller interface specification for high-speed signaling and works up to 480 mbps. the pd720100a is integrated three host controller cores with pci interface and usb2.0 transceivers into a single chip. detailed function descriptions are provided in the following user?s manual. be sure to read the manual before designing. pd720100a user?s manual: s15534e features ? compliant with universal serial bus specification revision 2.0 (data rate 1.5/12/480 mbps) compliant with open host controller interface specification for usb rev 1.0a compliant with enhanced host controller interface specification for usb rev 0.95 pci multi-function device consists of two ohci host controller cores for full-/low-speed signaling and one ehci host controller core for high-speed signaling. root hub with five (max.) downstream facing ports which are shared by ohci and ehci host controller core all downstream facing ports can handle high-speed (480 mbps), full-speed (12 mbps), and low-speed (1.5 mbps) transaction. configurable number of downstream facing ports (2 to 5) 32-bit 33 mhz host interface compliant to pci specification release 2.2. supports pci mobile design guide revision 1.1. supports pci-bus power management interface specification release 1.1. pci bus bus-master access system clock is generated by 30 mhz x?tal or 48 mhz clock input. operational registers direct-mapped to pci memory space legacy support for all downstream facing ports. legacy support features allow easy migration for motherboard implementation. 3.3 v power supply, pci signal pins have 5 v tolerant circuit. ordering information part number package pd720100agm-8ed 160-pin plastic lqfp (fine pitch) (24 24) pd720100agm-8ey 160-pin plastic lqfp (fine pitch) (24 24) pd720100as1-2c 176-pin plastic fbga (15 15)
data sheet s15535ej2v0ds 2 pd720100a block diagram intb0 pci bus pci bus interface arbiter ohci host controller #1 ohci host controller #2 ehci host controller root hub phy usb bus port 1 port 2 port 3 port 4 port 5 pme0 wakeup_event wakeup_event wakeup_event inta0 intc0 smi0
data sheet s15535ej2v0ds 3 pd720100a pci bus interface :handles 32-bits 33 mhz pci bus master and target function which comply with pci specification release 2.2. the number of enabled ports are set by bit in configuration space. arbiter :arbitrates among two ohci host controller cores and one ehci host controller core. ohci host controller #1 :handles full- (12 mbps)/low-speed (1.5 mbps) signaling at port 1, 3, and 5. ohci host controller #2 :handles full- (12 mbps)/low-speed (1.5 mbps) signaling at port 2 and 4. ehci host controller :handles high- (480 mbps) signaling at port 1, 2, 3, 4, and 5. root hub :handles usb hub function in host controller and controls connection (routing) between host controller core and port. phy :consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, etc inta0 :is the pci interrupt signal for ohci host controller #1. intb0 :is the pci interrupt signal for ohci host controller #2. intc0 :is the pci interrupt signal for ehci host controller. smi0 :is the interrupt signal which is specified by open host controller interface specification for usb rev 1.0a. the smi signal of each ohci host controller appears at this signal. pme0 :is the interrupt signal which is specified by pci-bus power management interface specification release 1.1. wakeup signal of each host controller core appears at this signal.
data sheet s15535ej2v0ds 4 pd720100a pin configuration ? 160-pin plastic lqfp (fine pitch) (24 24) pd720100agm-8ed pd720100agm-8ey top view v dd ntest1 ntest2 test xt1/sclk xt2 legc v dd v ss vccrst0 smi0 iri1 iri2 iro1 iro2 a20s pme0 pclk vbbrst0 v dd v ss v dd_pci inta0 intb0 intc0 pin_en gnt0 req0 ad31 ad30 v ss ad29 ad28 ad27 ad26 ad25 ad24 cbe30 idsel v dd v ss v ss rsdm1 dm1 v dd dp1 rsdp1 v ss rsdm2 dm2 v dd dp2 rsdp2 v ss v dd av ss av dd pc2 av ss pc1 n.c. av dd av ss (r) rref av ss v dd v ss rsdm3 dm3 v dd dp3 rsdp3 v ss rsdm4 dm4 v dd dp4 rsdp4 v ss v ss v ss v ss ad6 ad7 cbe00 ad8 ad9 ad10 ad11 ad12 v dd ad13 ad14 ad15 v ss cbe10 par serr0 perr0 stop0 v dd_pci devsel0 trdy0 irdy0 frame0 cbe20 ad16 ad17 ad18 v dd ad19 ad20 ad21 ad22 sot/tout sin/tin smc ad23 v ss v ss v dd selclk n.c. seldat v ss rsdp5 dp5 v dd dm5 rsdm5 v ss clksel v ss ppon5 teb ppon4 sck/tclk ppon3 ppon2 v ss v dd oci3 amc oci4 oci2 oci5 ppon1 oci1 srmod srclk srdta v dd_pci crun0 ad0 ad1 ad2 ad3 ad4 ad5 v dd 1 5 10 15 20 25 35 30 41 50 55 45 60 65 70 81 80 75 85 90 95 100 105 110 115 120 125 130 145 150 160 40 121 135 140 155
data sheet s15535ej2v0ds 5 pd720100a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v dd 41 v ss 81 v dd 121 v ss 2 ntest1 42 v ss 82 ad5 122 v ss 3 ntest2 43 ad23 83 ad4 123 rsdm1 4 test 44 smc 84 ad3 124 dm1 5 xt1/sclk 45 sin/tin 85 ad2 125 v dd 6 xt2 46 sot/tout 86 ad1 126 dp1 7 legc 47 ad22 87 ad0 127 rsdp1 8v dd 48 ad21 88 crun0 128 v ss 9v ss 49 ad20 89 v dd_pci 129 rsdm2 10 vccrst0 50 ad19 90 srdta 130 dm2 11 smi0 51 v dd 91 srclk 131 v dd 12 iri1 52 ad18 92 srmod 132 dp2 13 iri2 53 ad17 93 oci1 133 rsdp2 14 iro1 54 ad16 94 ppon1 134 v ss 15 iro2 55 cbe20 95 oci5 135 v dd 16 a20s 56 frame0 96 oci2 136 av ss 17 pme0 57 irdy0 97 oci4 137 av dd 18 pclk 58 trdy0 98 amc 138 pc2 19 vbbrst0 59 devsel0 99 oci3 139 av ss 20 v dd 60 v dd_pci 100 v dd 140 pc1 21 v ss 61 stop0 101 v ss 141 n.c. 22 v dd_pci 62 perr0 102 ppon2 142 av dd 23 inta0 63 serr0 103 ppon3 143 av ss (r) 24 intb0 64 par 104 sck/tclk 144 rref 25 intc0 65 cbe10 105 ppon4 145 av ss 26 pin_en 66 v ss 106 teb 146 v dd 27 gnt0 67 ad15 107 ppon5 147 v ss 28 req0 68 ad14 108 v ss 148 rsdm3 29 ad31 69 ad13 109 clksel 149 dm3 30 ad30 70 v dd 110 v ss 150 v dd 31 v ss 71 ad12 111 rsdm5 151 dp3 32 ad29 72 ad11 112 dm5 152 rsdp3 33 ad28 73 ad10 113 v dd 153 v ss 34 ad27 74 ad9 114 dp5 154 rsdm4 35 ad26 75 ad8 115 rsdp5 155 dm4 36 ad25 76 cbe00 116 v ss 156 v dd 37 ad24 77 ad7 117 seldat 157 dp4 38 cbe30 78 ad6 118 n.c. 158 rsdp4 39 idsel 79 v ss 119 selclk 159 v ss 40 v dd 80 v ss 120 v dd 160 v ss remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? .
data sheet s15535ej2v0ds 6 pd720100a ? 176-pin plastic fbga (15 15) pd720100as1-2c bottom view 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 17 30 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 46 16 29 88 141 142 143 144 145 146 147 148 149 150 151 152 153 104 47 15 28 87 140 171 172 173 154 105 48 14 27 86 139 155 106 49 13 26 85 138 156 107 50 12 25 84 137 157 108 51 11 24 83 136 170 174 158 109 52 10 23 82 135 169 175 159 110 53 9 22 81 134 168 176 160 111 54 8 21 80 133 161 112 55 7 20 79 132 162 113 56 6 19 78 131 163 114 57 5 18 77 130 167 166 165 164 115 58 4 17 76 129 128 127 126 125 124 123 122 121 120 119 118 117 116 59 3 16 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 2 151413121110987654321 1 utrpnmlkjhgfedcba
data sheet s15535ej2v0ds 7 pd720100a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 45 v dd 89 selclk 133 ppon1 2v ss 46 ntest1 90 v ss 134 oci4 3 smc 47 nandtest 91 rsdm1 135 v ss 4 ad20 48 test 92 rsdp1 136 sck/tclk 5ad18 49v ss 93 dm2 137 ppon5 6 cbe20 50 iri1 94 rsdp2 138 v ss 7 devsel0 51 iro2 95 av ss 139 v dd 8v dd_pci 52 vbbrst0 96 pc2 140 rsdp5 9 serr0 53 v dd 97 av ss 141 v dd 10 v ss 54 inta0 98 dm3 142 dp1 11 ad14 55 pin_en 99 dp3 143 v ss 12 ad11 56 req0 100 rsdm4 144 v dd 13 cbe00 57 ad29 101 dp4 145 v ss 14 ad6 58 ad25 102 v ss 146 av dd 15 v ss 59 cbe30 103 v ss 147 n.c. 16 ad5 60 n.c. 104 v dd 148 rref 17 n.c. 61 idsel 105 ntest2 149 v ss 18 ad3 62 v ss 106 legc 150 v dd 19 v dd_pci 63 ad23 107 vccrst0 151 v ss 20 srmod 64 ad22 108 iri2 152 dm4 21 oci5 65 ad19 109 a20s 153 xt1/sclk 22 oci3 66 ad17 110 pclk 154 xt2 23 v dd 67 frame0 111 intc0 155 v dd 24 ppon3 68 trdy0 112 ad31 156 smi0 25 teb 69 cbe10 113 v ss 157 iro1 26 v ss 70 ad13 114 ad27 158 pme0 27 dm5 71 ad12 115 ad24 159 v ss 28 v ss 72 ad9 116 v dd 160 intb0 29 n.c. 73 ad7 117 sin/tin 161 gnt0 30 n.c. 74 v ss 118 sot/tout 162 ad30 31 v ss 75 v ss 119 ad21 163 ad28 32 n.c. 76 v dd 120 v dd 164 ad26 33 dm1 77 ad4 121 ad16 165 v ss 34 rsdm2 78 ad0 122 irdy0 166 v dd 35 dp2 79 srdta 123 stop0 167 perr0 36 v dd 80 oci1 124 par 168 v ss 37 av ss 81 oci2 125 ad15 169 v ss 38 pc1 82 amc 126 v dd 170 ppon2 39 av ss (r) 83 ppon4 127 ad10 171 v ss 40 v dd 84 clksel 128 ad8 172 v ss 41 rsdm3 85 rsdm5 129 ad2 173 av dd 42 rsdp3 86 dp5 130 ad1 174 v ss 43 n.c.(v dd ) 87 seldat 131 crun0 175 v dd 44 rsdp4 88 v dd 132 srclk 176 v dd_pci remarks 1. pin 43 can be opened. but this signal is connected to pin 45 in the package. should not be connected to gnd. 2. av ss (r) should be used to connect rref through 1 % precision reference resistor of 9.1 k ? .
data sheet s15535ej2v0ds 8 pd720100a 1. pin information (1/2) pin name i/o buffer type active level function ad (31 : 0) i/o 5 v pci i/o pci ? ad [31 : 0] ? signal cbe (3 : 0)0 i/o 5 v pci i/o pci ? c/be [3 : 0] ? signal par i/o 5 v pci i/o pci ? par ? signal frame0 i/o 5 v pci i/o pci ? frame# ? signal irdy0 i/o 5 v pci i/o pci ? irdy# ? signal trdy0 i/o 5 v pci i/o pci ? trdy# ? signal stop0 i/o 5 v pci i/o pci ? stop# ? signal idsel i 5 v pci input pci ? idsel ? signal devsel0 i/o 5 v pci i/o pci ? devsel# ? signal req0 o 5 v pci output pci ? req# ? signal gnt0 i 5 v pci input pci ? gnt# ? signal perr0 i/o 5 v pci i/o pci ? perr# ? signal serr0 o 5 v pci n-ch open drain pci ? serr# ? signal inta0 o 5 v pci n-ch open drain low pci ? inta# ? signal intb0 o 5 v pci n-ch open drain low pci ? intb# ? signal intc0 o 5 v pci n-ch open drain low pci ? intc# ? signal pclk i 5 v pci input pci ? clk ? signal vbbrst0 i 5 v pci input low hardware reset for chip crun0 i/o 5 v pci i/o pci ? clkrun# ? signal pme0 o 5 v pci n-ch open drain low pci ? pme# ? signal vccrst0 i 5 v tolerant input low reset for power management smi0 o 5 v tolerant n-ch open drain low system management interrupt output pin_en i 5 v tolerant input high pci interface enable xt1/sclk i input system clock input or oscillator in xt2 o output oscillator out dp (5 : 1) i/o usb high speed d+i/o usb ? s high speed d+ signal dm (5 : 1) i/o usb high speed d ? i/o usb ? s high speed d ? signal rsdp (5 : 1) o usb full speed d+ o usb ? s full speed d+ signal rsdm (5 : 1) o usb full speed d ? ousb ? s full speed d ? signal oci (5 : 1) i (i/o) 5 v tolerant input low usb root hub port ? s overcurrent status input ppon (5 : 1) o (i/o) 5 v tolerant output high usb root hub port ? s power supply control output legc i (i/o) input high legacy support switch iri1 i (i/o) 5 v tolerant input high int input from keyboard iri2 i (i/o) 5 v tolerant input high int input from mouse iro1 o 5 v tolerant output high int output from keyboard iro2 o 5 v tolerant output high int output from mouse a20s o 5 v tolerant 3-state output gatea20 state output
data sheet s15535ej2v0ds 9 pd720100a (2/2) pin name i/o buffer type active level function rref a analog reference resistor pc1 a analog capacitor for pll pc2 a analog capacitor for pll ntest(2:1) i input with 12 k ? pull down r high test pin smc i input with 50 k ? pull down r high scan mode control sin/tin i input with 50 k ? pull down r scan input or ram bist input sot/tout o output scan output or ram bist output teb i input with 50 k ? pull down r high bist enable amc i input with 50 k ? pull down r high atg mode control sck/tclk i input with 50 k ? pull down r scan clock or ram bist clock clksel i input with 50 k ? pull down r clock select signal test i input with 50 k ? pull down r high test control nandtest i input with 50 k ? pull down r high nand tree test enable seldat o output test signal selclk o output test signal srclk o output serial rom clock out srdta i/o i/o serial rom data srmod i input with 50 k ? pull down r high serial rom input enable av dd v dd for analog circuit v dd v dd v dd_pci 5 v (5 v pci) or 3.3 v (3.3 v pci) av ss v ss for analog circuit v ss v ss n.c. not connect remarks 1. ? 5 v tolerant ? means that the buffer is 3 v buffer with 5 v tolerant circuit. 2. ? 5 v pci ? indicates a pci buffer, which complies with the 3 v pci standard, has a 5 v tolerant circuit. it does not indicate a buffer that fully complies with 5 v pci standard. however, this function can be used for evaluating the operation of a device on a 5v add-in card. 3. the signal marked as ? (i/o) ? in the above table operates as i/o signals during testing. however, they do not need to be considered in normal use.
data sheet s15535ej2v0ds 10 pd720100a 2. electrical specifications 2.1 buffer list ? 3 v input buffer with pull down resister ntest1, ntest2, test, smc, sin/tin, srmod, amc, sck/tclk, clksel, teb ? 3 v output buffer sot/tout (i ol = 9 ma), srclk (i ol = 3 ma) ? 3 v bi-directional buffer legc (i ol = 9 ma), srdta (i ol = 3 ma) ? 3 v oscillator interface xt1/sclk, xt2 ? 5 v input buffer vccrst0, pin_en ? 5 v i ol = 12 ma n-ch open drain buffer smi0, pme0, inta0, intb0, intc0, serr0 ? 5 v i ol = 6 ma 3-state output buffer a20s ? 5 v i ol = 12 ma 3-state output buffer iro1, iro2 ? 5 v pci input buffer with enable (or type) pclk, vbbrst0, gnt0, idsel ? 5 v pci i ol = 12 ma 3-state output buffer req0 ? 5 v pci i ol = 12 ma bi-directional buffer with input enable (or-type) ad(31:0), cbe(3:0)0, par, frame0, irdy0, trdy0, stop0, devsel0, perr0, crun0, iri(1:2), ppon(1:5), oci(1:5) ? usb interface dp(1:5), dm(1:5), rsdp(1:5), rsdm(1:5), pc1, pc2, rref, seldat, selclk above, ? 5 v ? refers to a 3-v buffer with 5-v tolerant circuit. therefore, it is possible to have a 5-v connection for an external bus, but the output level will be only up to 3 v, which is the v dd voltage. similarly, ? 5 v pci ? above refers to a pci buffer that has a 5-v tolerant circuit, which meets the 3-v pci standard; it does not refer to a pci buffer that meets the 5-v pci standard.
data sheet s15535ej2v0ds 11 pd720100a 2.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. operating temperature t a indicates the ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. terms used in recommended operating range parameter symbol meaning power supply voltage v dd indicates the voltage range for normal logic operations occur when v ss = 0v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ? min. ? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ? max. ? value is applied, the input voltage is guaranteed as low level voltage. terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. output short circuit current i os indicates the current that flows when the output pin is shorted (to gnd pins) when output is at high-level. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high- level output voltage is being applied.
data sheet s15535ej2v0ds 12 pd720100a 2.3 electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ? 0.5 to + 4.6 v input voltage, 5 v buffer v i 3.0 v v dd 3.6 v v i < v dd + 3.0 v ? 0.5 to + 6.6 v input voltage, 3.3 v buffer v i 3.0 v v dd 3.6 v v i < v dd + 0.5 v ? 0.5 to + 4.6 v output voltage, 5 v buffer v o 3.0 v v dd 3.6 v v o < v dd + 3.0 v ? 0.5 to + 6.6 v output voltage, 3.3 v buffer v o 3.0 v v dd 3.6 v v o < v dd + 0.5 v ? 0.5 to + 4.6 v operating temperature t a 0 to + 70 c storage temperature t stg ? 65 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd 3.0 3.3 3.6 v high-level input voltage v ih 3.3 v high-level input voltage 2.0 v dd v 5.0 v high-level input voltage 2.0 5.5 v low-level input voltage v il 3.3 v low-level input voltage 0 0.8 v 5.0 v low-level input voltage 0 0.8 v
data sheet s15535ej2v0ds 13 pd720100a dc characteristics (v dd = 3.0 to 3.6 v, t a = 0 to + + + + 70 c) control pin block parameter symbol condition min. max. unit off-state output current i oz v o = v dd or v ss 10 a output short circuit current i os note ? 250 ma low-level output current 3.3 v low-level output current 3.3 v low-level output current 5.0 v low-level output current 5.0 v low-level output current i ol v ol = 0.4 v v ol = 0.4 v v ol = 0.4 v v ol = 0.4 v 9.0 3.0 12.0 6.0 ma ma ma ma high-level output current 3.3 v high-level output current 3.3 v high-level output current 5.0 v high-level output current 5.0 v high-level output current i oh v oh = 2.4 v v oh = 2.4 v v oh = 2.4 v v oh = 2.4 v ? 9.0 ? 3.0 ? 2.0 ? 2.0 ma ma ma ma input leakage current 3.3 v buffer 3.3 v buffer with 50 k ? pd 5.0 v buffer i i v i = v dd or v ss v i = v dd v i = v dd or v ss 10 191 10 a a a note the output short circuit time is one second or less and is only for one pin on the lsi. pci interface block parameter symbol condition min. max. unit high-level input voltage v ih 2.0 5.25 v low-level input voltage v il 00.8v low-level output current i ol v ol = 0.4 v 12.0 ma high-level output current i oh v oh = 2.4 v ? 2.0 ma input high leakage current i ih v in = 2.7 70 a input low leakage current i il v in = 0.5 ? 70 a pme0 leakage current i off v o < 3.6 v v cc off or floating 1 a
data sheet s15535ej2v0ds 14 pd720100a usb interface block parameter symbol conditions min max unit serial resistor between dp (dm) and rsdp (rsdm). r s 35.64 36.36 ? output pin impedance z hsdrv includes r s resistor 40.5 49.5 ? input levels for low-/full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 low-level input voltage v il 0.8 v differential input sensitivity v di ? (d+) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for low-/full-speed: high-level output voltage v oh r l of 14.25 k ? to gnd 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch detection threshold (differential signal) v hssq 100 150 mv high-speed disconnect detection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling level see figure 2-4. output levels for high-speed: high-speed idle state v hsoi ? 10.0 + 10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10.0 + 10 mv chirp j level (different signal) v chirpj 700 1100 mv chirp k level (different signal) v chirpk ? 900 ? 500 mv
data sheet s15535ej2v0ds 15 pd720100a figure 2-1. differential input sensitivity range for low-/full-speed 4.6 -1.0 input voltage range (volts) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 2-2. full-speed buffer v oh /i oh characteristics for high-speed capable transceiver max. min. -80 -60 -40 -20 0 v dd -0.3 vout (v) iout (ma) v dd -2.3 v dd -3.3 v dd -0.8 v dd v dd -1.3 v dd -1.8 v dd -2.8 figure 2-3. full-speed buffer v ol /i ol characteristics for high-speed capable transceiver max. min. 80 60 40 20 0 00.511.5 2 2.5 3 vout (v) iout (ma)
data sheet s15535ej2v0ds 16 pd720100a figure 2-4. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 0% 100% figure 2-5. receiver measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ? pin capacitance parameter symbol condition min. max. unit input capacitance c i 68pf output capacitance c o 10 12 pf i/o capacitance c io 10 12 pf pci input pin capacitance c in 8pf pci clock input pin capacitance c clk 68pf pci idsel input pin capacitance c idsel v dd = 0 v, t a = 25 c f c = 1 mhz unmeasured pins returned to 0 v 8pf
data sheet s15535ej2v0ds 17 pd720100a power consumption parameter symbol condition typ. unit p wd0-0 the power consumption under the state without suspend. device state = d0, all the ports does not connect to any function. note 1 168.0 ma the power consumption under the state without suspend. device state = d0, the number of active ports is 2. note 2 p wd0-2 ehci host controller is inactive. ehci host controller is active. 186.2 301.6 ma ma the power consumption under the state without suspend. device state = d0, the number of active ports is 3. note 2 p wd0-3 ehci host controller is inactive. ehci host controller is active. 195.3 368.4 ma ma the power consumption under the state without suspend. device state = d0, the number of active ports is 4. note 2 p wd0-4 ehci host controller is inactive. ehci host controller is active. 204.4 435.2 ma ma the power consumption under the state without suspend. device state = d0, the number of active ports is 5. note 2 p wd0-5 ehci host controller is inactive. ehci host controller is active. 213.5 502.0 ma ma p wd0_s the power consumption under suspend state. device state = d0, the internal clock is stopped. note 3 136.2 ma p wd0_c the power consumption under suspend state during pci clock is stopped by crun0. device state = d0, the internal clock is stopped. note 3 113.0 ma p wd1 device state = d1, analog pll output is stopped. note 3, 4 24.7 ma p wd2 device state = d2, analog pll output is stopped. note 3, 4 10.9 ma p wd3h device state = d3 hot , pin_en = high analog pll output is stopped. note 3, 4 10.9 ma power consumption p wd3c device state = d3 cold , pin_en = low oscillator output is stopped. note 3, 4, 5 650 a notes 1. when any device is not connected to all the ports of hc, the power consumption for hc does not depend on the number of active ports. 2. the number of active ports is set by the value of port no field in pci configuration space ext register. 3. for the condition of clock stop, see pd720100a user ? s manual 7.3 control for system clock operation . 4. when the device state = d1, pci clock is defined as it is running. when the device state = d2 or d3, pci clock is defined as it is stopped. 5. if 48 mhz oscillator clock-in is used, power consumption for oscillator block + hc chip will be more than 15 ma.
data sheet s15535ej2v0ds 18 pd720100a system clock ratings parameter symbol condition min. typ. max. unit x ? tal ? 500 ppm 30 + 500 ppm mhz clock frequency f clk oscillator block ? 500 ppm 48 + 500 ppm mhz clock duty cycle t duty 40 50 60 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of x ? tal or oscillator block is including initial frequency accuracy, the spread of x ? tal capacitor loading, supply voltage, temperature, and aging, etc.
data sheet s15535ej2v0ds 19 pd720100a ac characteristics (v dd = 3.0 to 3.6 v, t a = 0 to + + + + 70 c) pci interface block parameter symbol conditions min. max. unit pci clock cycle time t cyc 30 ns pci clock pulse, high-level width t high 11 ns pci clock pulse, low-level width t low 11 ns pci clock, rise slew rate s cr 0.2 v dd to 0.6 v dd 14 v/ns pci clock, fall slew rate s cf 0.2 v dd to 0.6 v dd 14 v/ns pci reset active time (vs. power supply stability) t rst 1ms pci reset active time (vs. clk start) t rst-clk 100 s output float delay time (vs. rst0 )t rst-off 40 ns pci reset rise slew rate s rr 50 mv/ns pci bus signal output time (vs. pclk )t val 211 ns pci point-to-point signal output time (vs. pclk ) t val (ptp) req0 2 12 ns output delay time (vs. pclk )t on 2ns output float delay time (vs. pclk )t off 28 ns input setup time (vs. pclk )t su 7ns point-to-point input setup time (vs. pclk )t su (ptp) gnt0 10 ns input hold time t h 0ns
data sheet s15535ej2v0ds 20 pd720100a usb interface block (1/2) parameter symbol conditions min. max. unit low source electrical characteristics rise time (10% - 90%) t lr c l = 50 pf ? 150 pf, r s = 36 ? 75 300 ns fall time (90% - 10%) t lf c l = 50 pf ? 150 pf, r s = 36 ? 75 300 ns differential rise and fall time matching t lrfm (t lr /t lf )80125% low-speed data rate t ldraths average bit rate 1.49925 1.50075 mbps source jitter total (including frequency tolerance): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 + 25 + 14 ns ns source jitter for differential transition to se0 transition t ldeop -40 + 100 ns receiver jitter: to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 + 152 + 200 ns ns source se0 interval of eop t leopt 1.25 1.50 s receiver se0 interval of eop t leopr 670 ns width of se0 interval during differential transition t fst 210 ns full-speed source electrical characteristics rise time (10% - 90%) t fr c l = 50 pf, r s = 36 ? 420ns fall time (90% - 10%) t ff c l = 50 pf, r s = 36 ? 420ns differential rise and fall time matching t frfm (t fr /t ff )90111.11% full-speed data rate t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 + 5ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns
data sheet s15535ej2v0ds 21 pd720100a (2/2) parameter symbol conditions min. max. unit high-speed source electrical characteristics rise time (10% - 90%) t hsr 500 ps fall time (90% - 10%) t hsf 500 ps driver waveform see figure 2-6. high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high- speed bit times data source jitter see figure 2-6. receiver jitter tolerance see figure 2-4. hub event timings time to detect a downstream facing port connect event t dcnn 2.5 2000 s time to detect a disconnect event at a downstream facing port: t ddis 2.0 2.5 s duration of driving resume to a downstream port t drsmdn nominal 20 ms time from detecting downstream resume to rebroadcast. t ursm 1.0 ms inter-packet delay for packets traveling in same direction for high-speed t hsipdsd 88 bit times inter-packet delay for packets traveling in opposite direction for high-speed t hsipdod 8bit times inter-packet delay for root hub response for high-speed t hsrspipd1 192 bit times time for which a chirp j or chirp k must be continuously detected during reset handshake t filt 2.5 s time after end of device chirp k by which hub must start driving first chirp k t wtdch 100 s time for which each individual chirp j or chirp k in the chirp sequence is driven downstream during reset t dchbit 40 60 s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 s
data sheet s15535ej2v0ds 22 pd720100a figure 2-6. transmit waveform for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 point 1 point 2 point 3 point 4 point 5 point 6 0% 100% figure 2-7. transmitter measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s15535ej2v0ds 23 pd720100a timing diagram pci clock 0.4v dd 0.6v dd 0.2v dd 0.5v dd 0.3v dd 0.4v dd (ptp:min) t cyc t high t low pci reset pclk pwr_good vbbrst0 100 ms (typ.) t rst t rst-off pci signals valid t rst-clk pci output timing measurement condition pclk 0.4v dd 0.6v dd 0.2v dd output delay output 0.615v dd (for falling edge) 0.285v dd (for falling edge) t val , t val (ptp) t on t off
data sheet s15535ej2v0ds 24 pd720100a pci input timing measurement condition pclk 0.4v dd 0.6v dd 0.2v dd input t su , t su (ptp) 0.6v dd 0.2v dd 0.4v dd t h usb differential data jitter for low-/full-speed t period differential data lines crossover points consecutive transitions n t period + t dj1 , t ddj1 paired transitions n t period + t dj2 , t ddj2 usb differential-to-eop transition skew and eop width for low-/full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt t leopt receiver eop width: t feopr t leopr diff. data-to- se0 skew n t period + t fdeop , t ldeop
data sheet s15535ej2v0ds 25 pd720100a usb receiver jitter tolerance for low-/full-speed differential data lines t period t jr , t ujr t jr1 , t ujr1 t jr2 , t ujr2 consecutive transitions n t period + t jr1 , t ujr1 paired transitions n t period + t jr2 , t ujr2 low-/full-speed disconnect detection d-/d+ d+/d- v izh (min) v il v ss device disconnected disconnect detected t ddis full-/high-speed device connect detection v ih v ss device connected connect detected d- d+ t dcnn
data sheet s15535ej2v0ds 26 pd720100a low-speed device connect detection v ih v ss device connected connect detected d+ d- t dcnn
data sheet s15535ej2v0ds 27 pd720100a 3. package drawing s s n j detail of lead end r k m l p i s q g f m h 160-pin plastic lqfp (fine pitch) (24x24) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 26.0 0.2 24.0 0.2 0.5 (t.p.) 2.25 j 26.0 0.2 k c 24.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 2.25 n p q 0.10 1.4 0.1 0.125 0.075 s160gm-50-8ed-3 s 1.7 max. h 0.22 + 0.05 ? 0.04 m 0.145 + 0.055 ? 0.045 r3 + 7 ? 3 120 121 160 140 41 80 81 a b cd
data sheet s15535ej2v0ds 28 pd720100a 160-pin plastic lqfp (fine pitch) (24x24) 160 1 41 40 80 81 121 120 item millimeters note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. h 0.22 a 26.0 0.2 b 24.0 0.2 c 24.0 0.2 d 26.0 0.2 f 2.25 g 2.25 i 0.08 j 0.5 (t.p.) k 1.0 0.2 + 0.05 ? 0.04 p160gm-50-8ey c d a h i b q t k j m s l u r p g f detail of lead end m 0.17 l 0.5 n 0.08 p 1.4 0.05 q 0.10 0.05 + 0.03 ? 0.07 r3 s 1.6 max. t 0.25 (t.p.) u 0.16 0.15 + 4 ? 3 m s n s
data sheet s15535ej2v0ds 29 pd720100a 176-pin plastic fbga (15x15) item millimeters b c e 14.40 1.10 14.40 p r0.3 c1.0 q 25 r w 0.20 0.08 m j 1.51 0.15 f 0.8 (t.p.) g 0.35 0.1 h 0.36 i 1.16 k 0.10 l 0.50 + 0.05 ? 0.10 a 15.00 0.10 d 15.00 0.10 s176s1-80-2c-1 y1 0.20 a b c d e f g h j k l m n p r t u 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s q p index mark w w b s a s a b a b cd r h j i g e s sab s m kf m l y1
data sheet s15535ej2v0ds 30 pd720100a 4. recommended soldering conditions the pd720100a should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. pd720100agm-8ed: 160-pin plastic lqfp (fine pitch) (24 24) pd720100agm-8ey: 160-pin plastic lqfp (fine pitch) (24 24) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-3 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. pd720100as1-2c: 176-pin plastic fbga (15 15) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-3 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet s15535ej2v0ds 31 pd720100a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec l 2 c components conveys a license under the philips l 2 c patent rights to use these components in an l 2 c system, provided that the system conforms to the l 2 c standard specification as defined by philips.
pd720100a usb logo is a trademark of usb implementers forum, inc. m8e 00. 4 the information in this document is current as of october, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD720100AGM-8EY

	To Download UPD720100AGM-8EY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .