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c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 1 of 13 http://www.imicorp.com/ product features supports intel 440bx, and via promedia chipsets supports mobile pentium ? ii and pentium ? iii 2 ref clocks 2 low skew (<175ps) cpu clocks 6 pci clocks (1 free running, 5 manageable) 1 48mhz fixed clock 1 selectable 48 or 24 mhz fixed clock separate supply pins for mixed 3.3/2.5v application. high speed host bus operation, up to 150mhz imi spread spectrum technology for reducing emi rich power management functions. 28-pin ssop & tssop packages for minimum board space. block diagram fig.1 frequency table(mhz) hfs# sel 100/66# cpu(1:2) pci(_f,1:5) 1 0 66.6 33.3 1 1 100 33.3 0 0 150 37.5 0 1 133.3 33.3 table 1 pin configuration vss xin xout pci_f pci1 pci2 vss vddp pci3 pci4 pci5 vddf 48m 48_24/hfs# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vddr ref1/sel48# ref2/ss# vddc cpu1 cpu2 vss vss ps# vdd cs# pd# sel100/66# vss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vddp vddc vddr vddr vddf vddf pll1 rin hfs# s100/66# pd# cs# ps# cpu pci ss# 300k 36pf 36pf xb uf 6 2 1 1 1 pll2 rin 48 pd# 24 0 1 1 xin xout pci(_f,1:5) cpu(0:1) ref2/ss# ref1/sel48# pd# cs# ps# sel100/66# 48mhz 48_24/hfs#
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 2 of 13 http://www.imicorp.com/ pin description pin no. pin name pwr i/o description 2 xin vdd i on-chip reference oscillator input pin. requires either an external parallel resonant crystal (nominally 14.318 mhz) or externally generated reference signal 3 xout vdd o o-chip reference oscillator output pin. drives an external parallel resonant crystal (14.318 mhz) when an externally generated reference signal is used. 19 vdd - p 3.3 volt power supply for core logic. 23, 24 cpu(2,1) vddc o cpu clock outputs. see frequency table page 1. 17 pd# - i powers down device when low (1) 18 cs# - i when signal is low, stops cpu clocks in low state. (1) 16 sel100/66# - i frequency select input pins. see frequency select table 1 on page 1. no internal pullup resistor at this input. 25 vddc - p 2.5v power for cpu and host clock outputs. 4 pci_f vddp o free running pci clock 3.3v. does not stop when ps# is at a logic low level 5,6,9, 10,11 pci(1:5) vddp o pci output clocks. see frequency table of page 1. 20 ps# - i when signal is low, stops all pci clocks in low state. (1) 8 vddp - p 3.3 volt power supply pins for free running pci clock output buffer. 13 48m vddf o fixed 48 mhz clock. 14 48-24mhz / hfs# vddf i/o this is a power up bi-directional pin. during power up, this pin is an hfs# input. hfs# is a high frequency select line for programming the cpu/pci output clock frequency, see table 1 page 1. for strapping resistor, see application note page 5. when the power reaches the rail, this pin becomes an sio or usb clock output depending on the state of pin 27, sel48#. if sel48# is strapped high, then the frequency is 24mhz, sio. if sel48# is strapped low, then the frequency is 48mhz, usb. (1) 26 ref1 / ss# vddr i/o at power up this pin determines if the devices spread spectrum modulation feature is enabled or disabled. after power up this pin becomes a reference clock output. a 0 (logic low) enables sscg and a 1 (logic high) disables sscg. (1) 27 ref2 / sel48# vddr i/o at power up this pin determine the frequency of the clock at pin 14. if it is low, the clock will be 48 mhz, if high the clock will be 24 mhz. after power up this pin will become a reference clock output. (default high) 12 vddf - p power for fixed clock output buffer. 1,7,15, 21,22 vss - p ground pins for device. 28 vddr - p power for reference oscillator output buffer. note: 1. pins have internal pullup resistors that will guarantee to a logic 1 (high) level if no connection is made to the devices p in. other pins do not contain this function and must be electrically connected to vdd or vss by external circuitry to ensure a valid logic 1 or 0 is sensed.
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 3 of 13 http://www.imicorp.com/ power management functions ps# cs# pd# cpu (1:2) 48m, 48_24m pci (1:5) pci_f ref (1:2) vcos x x 0 low low low low low off 1 0 1 low on on on on on 0 1 1 on on low on on on 0 0 1 low on low on on on 111on on onononon cs# is the cpu stop control pin. it is used to turn off the cpu clocks for low power operation. cs# is asserted asynchronously by the external clock control logic with the rising edge of free running pci clock (and hence cpu clock) and must be internally synchronized to the external pci_f output. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. cpu clock on latency need to be 2 or 3 cpu clocks periods in time and cpu clock off latency needs to be 2 or 3 cpu clocks periods in time. cpu cs# cpu stop timing cpu pci ref 48m pd# power down timing pci ps# pci stop timing
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 4 of 13 http://www.imicorp.com/ power management functions (cont.) the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. pd# is an asynchronous function for powering up the system. internal clocks are not running after the device is put in power down. when pd# is active low, all clocks need to be driven to a low value and held prior to turning off the vcos and the crystal. the power-up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. as# and cs# are considered to be dont cares during the power down operations. power management timing latency signal signal state no. of rising edges of free running pci clock (pcif) cs# 0 (disabled) 1 1 (enabled) 1 pd# 1 (cold start/normal operation) 3 ms 0 (power down) 1 notes: clock on/off latency is defined in the number of rising edges of free running pci clock between the clock disable goes low/high to the first valid clock comes out of the device. power on bi-directional pins power up condition: pins 14, 26, and 27 are power up bi-directional pins and are used for different features in this device (see pin description, page 2). during power-up, these pins are in input mode (see fig 2, below), therefore, they are considered input select pins internal to the ic. after a settling time, the selection data is latch into internal control registers and these pins become toggling clock outputs. - hi-z inputs toggle outputs power supply ramp select data is latched into register then pin becomes clock output signal. vdd rail 48_24mhz/hfs# ref1/ss# ref2/sel48# fi g . 2
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 5 of 13 http://www.imicorp.com/ strapping resistor options for pins with internal pull-ups: the power up bidirectional pins have a large value pull- up each (250k w) , therefore, a selection 1 is the default. if the system uses a slow power supply (over 3ms settling time), then it is recommended to use an external pullup (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig. 3a and fig. 3b. fig. 3a represents an additional pull up resistor 50k w connected from the pin to the power line, which allows a faster pull to a high level. if a selection 0 is desired, then a jumper is placed on jp1 to a 5k w resistor as implemented as shown in fig.3a. please note the selection resistors (rup, and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 3b represent a single resistor 10k w connected to a 3 way jumper, jp2. when a 1 selection is desired, a jumper is placed between leads1 and 3. when a 0 selection is desired, a jumper is placed between leads 1 and 2. load load fig.3a fig.3b vdd vdd rup 50k rd imi c9914 bidirectional jp1 jumper jp2 3 way jumper rsel 10k rd imi c9914 bidirectional rdn 5k spectrum spread clocking spectrum analysis spread non -spread reduction
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 6 of 13 http://www.imicorp.com/ spectrum spreading selection table min (mhz) center (mhz) max (mhz) cpu frequency % of frequency spreading mode 99.3 99.65 100 100 .7% (-.7% + 0%) down spread 66.13 66.37 66.6 66 .7% (-.7% + 0%) down spread 132.4 132.87 133.33 133.3 .7% (-.7% + 0%) down spread 148.95 149.48 150 150 .7% (-.7% + 0%) down spread test and measurement condition output buffer test point specifie d test load condition cl clock output wave form 3.3 v clocking interface 2.5 v clocking interface pci (_f,1:5) , 48-24m, 48 m, ref(1,2) cpu (1,2) thkp thkp duty cycle duty cycle 3.3 v 2.5 v 2.4 v 2.0 v 1.5 v 1.25 v 0.4 v 0.4 v 0.0 v 0.0 v tr tf tr tf
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 7 of 13 http://www.imicorp.com/ absolute maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65oc to + 150oc operating temperature: 0oc to +85oc maximum esd protection 2kv maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 8 of 13 http://www.imicorp.com/ ac switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % cpu= measured at 1.25v all others measured at 1.50v cpu to pci offset (cpu leads) toff 1.5 - 4 ns cpu=20 pf load measured at 1.25v pci=30 pf load measure at 1.50v d period adjacent cycles d p -- 500 ps pci only vdd = vddf = vddp =vddr =3.3v 5 %, vddc = 2.5v 5 %, ta = 0oc to +70oc ac skew requirements characteristic bank skew cycle to cycle jitters vdd skew, jitters measure point cpu (20pf) 175ps 250ps 2.5v 1.25v 48 mhz n/a 500ps 3.3v 1.5v pci, pci_f (30pf) 500ps 500ps 3.3v 1.5v ref n/a 500ps 3.3v 1.5v buffer characteristics buffer characteristics for cpu outputs characteristic symbol min typ max units conditions pull-up current min ioh min -27 - ma vout = 1.0 v pull-up current max ioh max -27 ma vout = 2.375 v pull-down current min iol min 27 - - ma vout = 1.2 v pull-down current max iol max - - 30 ma vout = 0.3 v rise time between 0.4 v and 2.0 v tr 0.4 - 1.6 ns 20 pf load fall time between 0.4 v and 2.0 v tf 0.5 - 1.6 ns 20 pf load vdd = vddf = vddp = vddr =3.3v 5 %, vddc = 2.5v 5 %, ta = 0oc to +70oc
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 9 of 13 http://www.imicorp.com/ buffer characteristics for 48m, 48-24m and ref outputs characteristic symbol min typ max units conditions pull-up current min ioh min -29 - - ma vout = 1.0 v pull-up current max ioh max - - -63 ma vout = 3.135 v pull-down current min iol min 20 - - ma vout = 1.95 v pull-down current max iol max - - 27 ma vout = 0.4 v rise time between 0.4 v and 2.4 v tr 0.5 - 2.0 ns 20 pf load fall time between 0.4 v and 2.4 v tf 0.5 - 2.0 ns 20 pf load dc buffer characteristics for pci_f, pci (1:5) characteristic symbol min typ max units conditions pull-up current min ioh min -33 - - ma vout = 1.0 v pull-up current max ioh max - - -100 ma vout = 3.135 v pull-down current min iol min 20 - - ma vout = 1.95 v pull-down current max iol max - - 38 ma vout = 0.4 v rise time between 0.4 v and 2.4 v tr 0.5 - 2.0 ns 30 pf load fall time between 0.4 v and 2.4 v tf 0.5 - 2.0 ns 30 pf load vddp= vddr =3.3v 5 %, vddc = 2.5v 5 %, ta = 0oc to +70oc
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 10 of 13 http://www.imicorp.com/ suggested oscillator crystal parameters characteristic symbol min typ max units conditions frequency f o 14.17 14.31818 14.46 mhz tolerance t c - - +/-100 ppm note 1 frequency stability t s - - +/- 100 ppm stability (t a -10 to +60c) note 1 operating mode - - - - parallel resonant, note 1 load capacitance c xtal - 20 - pf the crystals rated load. note 1 effective series resistance (esr) r esr - 40 - ohms note 2 note1: for best performance and accurate frequencies from this device, it is recommended but not mandator y that the chosen crystal meets or exceeds these specifications note 2: larger values may cause this device to exibit oscillator startup problems to obtain the maximum accuracy, the total circuit loading capacitance should be equal to c xtal . this loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (c ftg ), any circuit trace capacitance (c pcb ), and any onboard discrete load capacitance (c disc ). the following formula and schematic illustrates the application of the loading specification of a crystal (c xtal )for a design. c l = (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb + c xoutftg + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb + c xoutftg + c outdisc ) where: c xtal = the load rating of the crystal c xoutftg = the clock generators xin pin effective device internal capacitance to ground c xoutftg = the clock generators xout pin effective device internal capacitance to ground c xinpcb = the effective capacitance to ground of the crystal to device pcb trace c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace c xindisc = any discrete capacitance that is placed between the xin pin and ground c xoutdisc = any discrete capacitance that is placed between the xout pin and ground c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator as an example, and using this formula for this datasheets device, a design that has no discrete loading capacitors (c disc ) and each of the crystal to device pcb traces has a capacitance (c pcb ) to ground of 4pf (typical value) would calculate as: c l = (4pf + 36pf + 0pf) x (4pf + 36pf + 0pf) = 40 x 40 = 1600 = 20pf (4pf + 36pf + 0pf) + (4pf + 36pf + 0pf) 40 + 40 80 therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design examp le, you should specify a parallel cut crystal that is designed to work into a load of 20pf
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 11 of 13 http://www.imicorp.com/ package drawings and dimensions 28 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.397 0.402 0.407 10.07 10.20 10.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.025 bsc 0.635 bsc h 0.301` 0.307 0.311 7.65 7.80 7.90 a 0 4 8 0 4 8 l 0.022 0.030 0.037 0.55 0.75 0.95 a b e a a 1 a 2 d e h l c
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 12 of 13 http://www.imicorp.com/ package drawings and dimensions bo surfaces roughness: 6+ 27n(rz) d -b- 385 e1 l20 r0.1 b e -c- c 0.07 rd 4 [10 typ r1.30 1.0 0.10~0.15 0.00 ~ 0.05 section v-v 0.05 max. 0.05 max. 1.0 1.0 e r0.15 a a1 0.25 a2 r l1 l a 8 b c c1 b1 detail b .08 cb a detail a 14 typ 28 pin tssop dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.037 0.039 0.041 0.95 1.00 1.05 l 0.019 0.023 0.029 0.50 0.60 0.75 l1 0.035 0.039 0.043 0.90 1.00 1.10 b 0.007 - 0.011 0.19 - 0.30 b1 0.007 0.008 0.010 0.19 0.22 0.25 c 0.004 - 0.007 0.105 - 0.175 c1 0.004 0.005 0.006 0.105 0.125 0.145 q 0 - 8 0 - 8 e 0.026 bsc 0.65 bsc d 0.378 0.382 0.386 9.6 9.7 9.8 e 0.244 0.252 0.260 6.2 6.4 6.6 e1 0.169 0.173 0.177 4.3 4.4 4.5 r 0.035 - - 0.9 - -
c9914 clock generator for 100mhz and 133.3mhz mobile applications preliminary international microcircuits, inc., 525 los coches st., rev. 1.0 2/4/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax: 408-263-6571 page 13 of 13 http://www.imicorp.com/ ordering information part number package type production flow IMIC9914BY 28 pin ssop commercial, 0 c to + 85 c imic9914bt 28 pin tssop commercial, 0 c to + 85 c note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi c9914 date code, lot # IMIC9914BY package y = ssop t = tssop revision imi device number

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