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freescale semiconductor technical data document number: mc56f8006 rev. 4, 06/2011 ? freescale semiconductor, inc., 2009?2011. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. mc56f8006/mc56f8002 48-pin lqfp case: 932-03 7 x 7 mm 2 28-pin soic case: 751f-05 7.5 x 18 mm 2 32-pin lqfp case: 873a-03 7 x 7 mm 2 32-pin psdip case: 1376-02 9 x 28.5 mm 2 this document applies to parts marked with 2m53m. the 56f8006/56f8002 is a member of the 56800e core-based family of digital signal contro llers (dscs). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create a cost-eff ective solution. because of its low cost, configuration flex ibility, and compact program code, the 56f8006/56f8002 is well-suited for many applications. it includes many peripherals that are especially useful for cost-sensitive applications, including: ? industrial control ? home appliances ? smart sensors ? fire and security systems ? switched-mode power supply and power management ?power metering ? motor control (acim, bldc, pmsm, sr, and stepper) ? handheld power tools ? arc detection ? medical device/equipment ? instrumentation ? lighting ballast the 56800e core is based on a dual harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per in struction cycle. the mcu-style programming model and optimized instruction set allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f8006/56f8002 supports program execution from internal memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 56f8006/56f8002 also offers up to 40 general-purpos e input/output (gpio) lines, depending on peripheral configuration. the 56f8006/56f8002 digital signal controller includes up to 16 kb of program flash and 2 kb of unified data/program ram. program flash memory can be independently bulk erased or erased in small pa ges of 512 bytes (256 words). on-chip features include: ? up to 32 mips at 32 mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? on-chip memory ? 56f8006: 16 kb (8k x 16) flash memory ? 56f8002: 12 kb (6k x 16) flash memory ? 2 kb (1k x 16) unified data/program ram ? one 6-channel pwm module ? two 28-channel, 12-bit analog-to-digital converters (adcs) ? two programmable gain amplifiers (pga) with gain up to 32x ? three analog comparators ? one programmable interval timer (pit) ? one high-speed serial comm unication interface (sci) with lin slave functionality ? one serial peripheral interface (spi) ? one 16-bit dual timer (2 x 16 bit timers) ? one programmable delay block (pdb) ? one smbus compatible inter-integrated circuit (i 2 c) port ? one real time counter (rtc) ? computer operating properly (cop)/watchdog ? two on-chip relaxation oscillators ? 1 khz and 8 mhz (400 khz at standby mode) ? crystal oscillator ? integrated power-on reset (por) and low-voltage interrupt (lvi) module ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 40 gpio lines ? 28-pin soic, 32-pin lqfp, 32-pin psdip, and 48-pin lqfp packages mc56f8006/mc56f8002 digital signal controller
mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 2 table of contents 1 mc56f8006/mc56f8002 family configuration . . . . . . . . . . . .3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 56f8006/56f8002 features . . . . . . . . . . . . . . . . . . . . . .4 3.2 award-winning development environment. . . . . . . . . . .8 3.3 architecture block diagram. . . . . . . . . . . . . . . . . . . . . . .9 3.4 product documentation . . . . . . . . . . . . . . . . . . . . . . . .11 4 signal/connection descriptions . . . . . . . . . . . . . . . . . . . . . . .11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 56f8006/56f8002 signal pins . . . . . . . . . . . . . . . . . . .17 5 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.2 program map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.3 data map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.4 interrupt vector table and reset vector . . . . . . . . . . . .31 5.5 peripheral memory-mapped registers . . . . . . . . . . . . .32 5.6 eonce memory map . . . . . . . . . . . . . . . . . . . . . . . . . .33 6 general system control information . . . . . . . . . . . . . . . . . . .34 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.2 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.3 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.4 on-chip clock synthesis . . . . . . . . . . . . . . . . . . . . . . . .34 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.6 system integration module (sim) . . . . . . . . . . . . . . . . .37 6.7 pwm, pdb, pga, and adc connections. . . . . . . . . . .38 6.8 joint test action group (jtag)/enhanced on-chip emulator (eonce) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.1 operation with security enabled. . . . . . . . . . . . . . . . . .40 7.2 flash access lock and unlock mechanisms . . . . . . . .40 7.3 product analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . 42 8.3 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 recommended operating conditions . . . . . . . . . . . . . 45 8.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . 46 8.6 supply current characteristics . . . . . . . . . . . . . . . . . . 51 8.7 flash memory characteristics . . . . . . . . . . . . . . . . . . . 53 8.8 external clock operation timing. . . . . . . . . . . . . . . . . 53 8.9 phase locked loop timing . . . . . . . . . . . . . . . . . . . . . 54 8.10 relaxation oscillator timing . . . . . . . . . . . . . . . . . . . . 54 8.11 reset, stop, wait, mode select, and interrupt timing. 56 8.12 external oscillator (xosc) characteristics . . . . . . . . . 56 8.13 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . 57 8.14 cop specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.15 pga specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.16 adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.17 hscmp specifications . . . . . . . . . . . . . . . . . . . . . . . . 68 8.18 optimize power consumption . . . . . . . . . . . . . . . . . . . 68 9 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.1 thermal design considerations . . . . . . . . . . . . . . . . . 70 9.2 electrical design considerations. . . . . . . . . . . . . . . . . 71 9.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 package mechanical outline drawings . . . . . . . . . . . . . . . . . 73 10.1 28-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.2 32-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.3 48-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.4 32-pin psdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 appendix a interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 appendix b peripheral register memory map and reset value . . . . . . . 86 mc56f8006/mc56f8002 family configuration mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 3 1 mc56f8006/mc56f8002 family configuration mc56f8006/mc56f8002 device comparison in table 1 . table 1. mc56f8006 series device comparison feature mc56f8006 mc56f8002 28-pin 32-pin 48-pin 28-pin flash memory size (kbytes) 16 12 ram size (kbytes) 2 analog comparators (acmp) 3 analog-to-digital converters (adc) 2 unshielded adc inputs 6776 shielded adc inputs 9 11 17 9 total number of adc input pins 1 1 some adc inputs share the same pin. see ta b l e 4 . 15 18 24 15 programmable gain amplifiers (pga) 2 pulse-width modulator (pwm) outputs 6 pwm fault inputs 3443 inter-integrated circuit (iic) 1 serial peripheral interface (spi) 1 high speed serial communications interface (sci) 1 programmable interrupt timer (pit) 1 programmable delay block (pdb) 1 16-bit multi-purpose timers (tmr) 2 real-time counter (rtc) 1 computer operating properly (cop) timer yes phase-locked loop (pll) yes 1 khz on-chip oscillator yes 8 mhz (400 khz at standby mode) on-chip rosc yes crystal oscillator yes power management controller (pmc) yes ieee 1149.1 joint test action group (jtag) interface yes enhanced on-chip emulator (eonce) ieee 1149.1 joint test action group (jtag) interface ye s mc56f8006/mc56f8002 digital si gnal controller, rev. 4 block diagram freescale semiconductor 4 2 block diagram figure 1 shows a top-level block diagram of the mc56f8006/mc56f8002 digital signal controller. package options for this family are described later in this document. italics indicate a 56f8002 device parameter. figure 1. mc56f8006/mc56f8002 block diagram 3 overview 3.1 56f8006/56f8002 features 3.1.1 core ? efficient 16-bit 56800e family digital signal controller (dsc) engine with dual harvard architecture ? as many as 32 million instructions per second (mips) at 32 mhz core frequency ? 155 basic instructions in conjunction with up to 20 address modes ? single-cycle 16 ? 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller 4 unified data / program ram 2kb pdb cdbr spi ipbus bridge r/w control memory pa b cdbw jtag/eonce port or gpiod digital reg analog reg low-voltage supervisor v dd v ss v dda v ssa 4 reset 6 dual gp timer adca 4 24 total clock generator* system integration module rosc pwm outputs pwm cop/ watchdog adcb flash memory 16 kbytes flash 12 kbytes flash pga/adc sci 2 3 cmp0 2 cmp2 2 cmp or gpiod cmp1 2 crystal oscillator power management controller programmable i 2 c 2 pit delay block 3 40 gpio are muxed with all other func pins. pmc 3 fault inputs pdb xab1 xab2 system bus control pa b cdbr cdbw xdb2 osc rtc note: all pins are muxed with other peripheral pins. 2 overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 5 ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, processor speed?independent, real-time debugging 3.1.2 operation range ? 1.8 v to 3.6 v operation (power supplies and i/o) ? from power-on-reset: approximately 1.9 v to 3.6 v ? ambient temperature operating range: ? ?40 c to 125 c 3.1.3 memory ? dual harvard architecture permits as many as thr ee simultaneous accesses to program and data memory ? flash security and protection that prevent unauthorized users from ga ining access to the internal flash ? on-chip memory ? 16 kb of program flash for 56f8006 and 12 kb of program flash for 56f8002 ? 2 kb of unified data/program ram ? eeprom emulation capability using flash 3.1.4 interrupt controller ? five interrupt priority levels ? three user programmable priority levels for each interrupt source: level 0, 1, 2 ? unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, swi3 instruction. maskable level 3 interrupts include: eo nce step counter, eonce breakpoint unit, eonce trace buffer ? lowest-priority software interrupt: level lp ? allow nested interrupt that higher priority level interrup t request can interrupt lower priority interrupt subroutine ? the masking of interrupt priority level is managed by the 56800e core ? one programmable fast interrupt that can be assigned to any interrupt source ? notification to system integration module (sim) to restart clock out of wait and stop states ? ability to relocate interrupt vector table 3.1.5 peripheral highlights ? one multi-function, six-output pulse width modulator (pwm) module ? up to 96 mhz pwm operating clock ? 15 bits of resolution ? center-aligned and edge-aligned pwm signal mode ? phase shifting pwm pulse generation mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 6 ? four programmable fault inputs with programmable digital filter ? double-buffered pwm registers ? separate deadtime insertions for rising and falling edges ? separate top and bottom pulse-width correction by means of software ? asymmetric pwm output within both center aligned and edge aligned operation ? separate top and botto m polarity control ? each complementary pwm signal pair allows selection of a pwm supply source from: ? pwm generator ? internal timers ? analog comparator outputs ? two independent 12-bit analog-to-digital converters (adcs) ? 2 x 14 channel external inputs plus seven internal inputs ? support simultaneous and software triggering conversions ? adc conversions can be synchronized by pwm and pdb modules ? sampling rate up to 400 ksps for 10- or 12-bit conversion result; 470 ksps for 8-bit conversion result ? two 16-word result registers ? two programmable gain amplifier (pgas) ? each pga is designed to am plify and convert diff erential signals to a single-ende d value fed to one of the adc inputs ? 1x, 2x, 4x, 8x, 16x, or 32x gain ? software and hardware triggers are available ? integrated sample/hold circuit ? includes additional calibration features: ? offset calibration eliminates any errors in the internal reference used to generate the vdda/2 output center point ? gain calibration can be used to veri fy the gain of the overall datapath ? both features require software correction of the adc result ? three analog comparators (cmps) ? selectable input source includes external pins, internal dacs ? programmable output polarity ? output can drive timer input, pwm fault input, pwm source, external pin output, and trigger adcs ? output falling and rising edge detection able to generate interrupts ? one dual channel 16-bit multi-purpose timer module (tmr) ? two independent 16-bit counter/timers with cascading capability ? up to 96 mhz operating clock ? each timer has capture and compare and quadrature decoder capability ? up to 12 operating modes ? four external inputs an d two external outputs ? one serial communicatio n interface (sci) with lin slave functionality ? up to 96 mhz operating clock ? full-duplex or single-wire operation ? programmable 8- or 9- bit data format ? two receiver wakeup methods: ? idle line ? address mark overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 7 ? 1/16 bit-time noise detection ? one serial peripheral interface (spi) ? full-duplex operation ? master and slave modes ? programmable length transactions (2 to 16 bits) ? programmable transmit and recei ve shift order (msb as fi rst or last bit transmitted) ? maximum slave module frequency = module clock frequency/2 ? one inter-integrated circuit (i 2 c) port ? operates up to 400 kbps ? supports master and slave operation ? supports 10-bit address mode and broadcasting mode ? supports smbus, version 2 ? one 16-bit programmable interval timer (pit) ? 16 bit counter with programmable counter modulo ? interrupt capability ? one 16-bit programmable delay block (pdb) ? 16 bit counter with programmable counter modulo and delay time ? counter is initiated by positive transition of internal or external trigger pulse ? supports two independently controlled delay pulses used to synchronize pga and adc conversions with input trigger event ? two pdb outputs can be ored together to schedule two conversions from one input trigger event ? pdb outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the cmp windowing comparison ? supports continuous or single shot mode ? bypass mode supported ? computer operating properly (cop)/watchdog time r capable of selecting different clock sources ? programmable prescaler and timeout period ? programmable wait, stop, and partial powerdown mode operation ? causes loss of reference reset 128 cycles after loss of reference clock to the pll is detected ? choice of clock sources from four sources in support of en60730 and iec61508: ? on-chip relaxation oscillator ? external crystal oscillat or/external clock source ? system clock (ipbus up to 32 mhz) ? on-chip low power 1 khz oscillator ? real-timer counter (rtc) ? 8-bit up-counter ? three software selectable clock sources ? external crystal oscillat or/external clock source ? on-chip low-power 1 khz oscillator ? system bus (ipbus up to 32 mhz) ? can signal the device to exit power down mode ? phase lock loop (pll) provides a high- speed clock to the co re and peripherals ? provides 3x system clock to pwm and dual timer and sci ? loss of lock interrupt ? loss of reference clock interrupt mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 8 ? clock sources ? on-chip relaxation oscillator with two user selectab le frequencies: 400 khz for low speed mode, 8 mhz for normal operation ? on-chip low-power 1 khz oscillator can be se lected as clock source to the rtc and/or cop ? external clock: crystal oscillator, ceram ic resonator, and external clock source ? power management controller (pmc) ? on-chip regulator for digital and analog circuitry to lower cost and reduce noise ? integrated power-on reset (por) ? low-voltage interrupt with a user select able trip voltage of 1.81 v or 2.31 v ? user selectable brown-out reset ? run, wait, and stop modes ? low-power run, wait, and stop modes ? partial power down mode ? up to 40 general-purpose i/o (gpio) pins ? individual control for each pin to be in peripheral or gpio mode ? individual input/output direction control for each pin in gpio mode ? hysteresis and configurable pullup device on all input pins ? configurable slew rate and drive strength and optional input low pass filters on all output pins ? 20 ma sink/source current ? jtag/eonce debug programming interface for real-time debugging ? ieee 1149.1 joint test action group (jtag) interface ? eonce interface for real-time debugging 3.1.6 power saving features ? three low power modes ? low-speed run, wait, and stop modes: 200 khz ip bus clock provided by rosc ? low-power run, wait, and stop modes: cl ock provided by external 32?38.4 khz crystal ? partial power down mode ? low power external oscillator can be used in any low-power mode to provi de accurate clock to active peripherals ? low power real time counter for use in run, wait, and stop modes with internal and external clock sources ? 32 ? s typical wakeup time from partial power down modes ? each peripheral can be indivi dually disabled to save power 3.2 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) t ool that combines easy-to-use component-based software application creation with an expert knowledge system. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms), demonstration bo ard kit, and development system cards support concurrent engineering. together, pe, codewarrior, and evms create a complete, scalable tool s solution for easy, fast, and efficient development. a full set of programmable peripherals ? pwm, pgas, adcs, sci, spi, i 2 c, pit, timers, and analog comparators ? supports various applications. each peripheral can be independently shut do wn to save power. any pin in these peripherals can also be used as general-purpose input/outputs (gpios). overview mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 9 3.3 architecture block diagram the 56f8006/56f8002?s architecture is shown in figure 2 and figure 3 . figure 2 illustrates how the 56800e system buses communicate with internal memories and the ipbus interface a nd the internal connections among each unit of the 56800e core. figure 3 shows the peripherals and control blocks connected to the ipbus bridge. please see the system integration module (sim) section in the mc56f8006 reference manual for information about which signals are multiplexed with those of other peripherals. figure 2. 56800e core block diagram data dsp56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data/ ipbus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 n y multi-bit shifter once? program ram mc56f8006/mc56f8002 digital si gnal controller, rev. 4 overview freescale semiconductor 10 figure 3. peripheral subsystem second clcok source reste gpioa7 gpioa6 gpioa5 gpioa4 gpioa3 gpioa2 gpioa1 gpioa0 port a gpiob7 gpiob6 gpiob5 gpiob4 gpiob3 gpiob2 gpiob1 gpiob0 port b gpioc7 gpioc6 gpioc5 gpioc4 gpioc3 gpioc2 gpioc1 gpioc0 port c gpiod3 gpiod2 gpiod1 gpiod0 port d pdb i2c pwm cmp2 adca pga0 ana15 adcb pga1 anb15 cmp1 cmp0 pwm input mux dual timer (tmr) sci spi sim rtc pmc intc cop occs cosc rosc crystal 1khz system clock ipbus bridge gpio mux gpiof3 gpiof2 gpiof1 gpiof0 port f gpioe7 gpioe6 gpioe5 gpioe4 gpioe3 gpioe2 gpioe1 gpioe0 port e pwm synch trigger a trigger b pretrigger a pretrigger b signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 11 3.4 product documentation the documents listed in table 2 are required for a complete description and proper design with the 56f8006/56f8002. documentation is available from local freescale distributo rs, freescale semiconductor sales offices, freescale literature distribution centers, or online at http://www.freescale.com . 4 signal/connection descriptions 4.1 introduction the input and output signals of the 56f8006/56f8002 are organized into functional groups, as detailed in table 3 . table 4 summarizes all device pins. in table 4 , each table row describes the signal or sign als present on a pin, sorted by pin number. table 2. 56f8006/56f8002 device documentation topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm 56f800x peripheral reference manual detailed description of peripherals of the 56f8006 and 56f8002 devices mc56f8006rm 56f80x serial bootloader user guide detailed description of the serial bootloader in the 56f800x family of devices tbd 56f8006/56f8002 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8006 56f8006/56f8002 errata details any chip issues that might be present mc56f8006e table 3. functional group pin allocations functional group number of pins in 28 soic number of pins in 32 lqfp number of pins in 32 psdip number of pins in 48 lqfp power inputs (v dd , v dda ) 2224 ground (v ss , v ssa ) 3334 reset 1 1 pins may be shared with other peripherals. see ta b l e 4 . 1111 pulse width modulator (pwm) ports 1 10 12 12 12 serial peripheral interface (spi) ports 1 5777 serial communications interface 0 (sci) ports 1 4555 inter-integrated circuit interface (i 2 c) ports 1 6777 analog-to-digital converter (adc) inputs 1 16 18 18 24 high speed analog comparator inputs 1 13 15 15 25 programmable gain amplifiers (pga) 1 4444 dual timer module (tmr) ports 1 8 101010 programmable delay block (pdb) 1 ??? 1 clock 1 5555 jtag/enhanced on-chip emulation (eonce 1 )4444 mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 12 in table 4 , peripheral pins in bold identify reset state. table 4. 56f8006/56f8002 pins pin number pin name peripherals 28 soic 32 lqfp 32 psdip 48 lqfp gpio i 2 c sci spi adc pga comp dual timer pwm power and ground jtag misc. 261291gpiob6 /rxd/sda/ana13 and cmp0_p2/clkin b6 sda rxd ana13 1 cmp0_p2 clkin 272302gpiob1 /ss /sda/ana12 andcmp2_p3 b1 sda ss ana12 1 cmp2_p3 3313gpiob7 /txd/scl/ana11 and cmp2_m3 b7 scl txd ana11 1 cmp2_m3 4324gpiob5 /t1/fault3/sclk b5 sclk t1 fault3 5gpioe0e0 6gpioe1 /anb9 and cmp0_p1 e1 anb9 1 cmp0_p1 28 5 1 7 anb8 and pga1+ and cmp0_m2/ gpioc4 c4 anb8 1 pga1+ cmp0_m2 8gpioe2 /anb7 and cmp0_m1 e2 anb7 1 cmp0_m1 1 6 2 9 anb6 and pga1? and cmp0_p4/ gpioc5 c5 anb6 1 pga1? cmp0_p4 10 gpioc7 /anb5 and cmp1_m2 c7 anb5 1 cmp1_m2 2 7 3 11 anb4 and cmp1_p1 /gpioc6/pwm2 c6 anb4 1 cmp1_p1 pwm2 38 412 v dda v dda 49 513 v ssa v ssa 14 gpioe3 /ana10 and cmp2_m1 e3 ana10 1 cmp2_m1 5 10 6 15 ana9 and pga0? and cmp2_p4/ gpioc2 c2 ana9 1 pga0? cmp2_p4 16 gpioe5/ ana8 and cmp2_p1 e5 ana8 1 cmp2_p1 6 11 7 17 ana7 and pga0+ and cmp2_m2/ gpioc1 c1 ana7 1 pga0+ cmp2_m2 18 gpioe4/ana6 and cmp2_p2 e4 ana6 1 cmp2_p2 7 12 8 19 ana5 and cmp1_m1/ gpioc0/fault0 c0 ana5 1 cmp1_m1 fault0 813 9 20 v ss v ss 21 v dd v dd 9141022 tck/ gpiod2/ana4 and cmp1_p2/cmp2_out d2 ana4 1 cmp1_p2, cmp2_out tck 10 15 11 23 reset / gpioa7 a7 reset 11 16 12 24 gpiob3/ mosi/tin3/ana3 and anb3/pwm5/cmp1_out b3 mosi ana3 1 and anb3 1 cmp1_out tin3 pwm5 17 13 25 gpiob2 /miso/tin2/ana2 and anb2/cmp0_out b2 miso ana2 and anb2 cmp0_out tin2 12 18 14 26 gpioa6/ fault0/ana1 and anb1/scl/txd/clko_1 a6 scl txd ana1 and anb1 fault0 clko_1 13 19 15 27 gpiob4/ t0/clko_0/miso/ sda/rxd/ana0 and anb0 b4 sda rxd miso ana0 and anb0 t0 clko_0 signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 13 4.2 pin assignment mc56f8006 and mc56f8002 28-pin small outlin e ic (28soic) assignment is shown in figure 4 ; mc56f8006 32-pin low-profile quad flat pack (32lqfp) is shown in figure 5 ; mc56f8006 32-pin plastic shrink dual in-line package (psdip) is shown in figure 6 ; mc56f8006 48-pin low-profile quad flat pack (48lqfp) is shown in figure 7 . 28 gpioe6 e6 14 20 16 29 gpioa5/ pwm5/fault2 or ext_sync/tin3 a5 tin3 pwm5, fault2 or ext_ sync 30 v ss v ss 31 v dd v dd 15 21 17 32 gpiob0/ sclk/scl/anb13/ pwm3/t1 b0 scl sclk anb13 t1 pwm3 16 22 18 33 gpioa4/ pwm4/sda/fault1 /tin2 a4 sda tin2 pwm4, fault1 34 gpioe7/ cmp1_m3 e7 cmp1_m3 23 19 35 gpioa2 /pwm2 a2 pwm2 17 24 20 36 gpioa3/ pwm3/txd/extal a3 txd pwm3 extal 18 25 21 37 gpiof0 /xtal f0 xtal 19 26 22 38 v dd v dd 20 27 23 39 v ss v ss 40 gpiof1 /cmp1_p3 f1 cmp1_p3 41 gpiof2 /cmp0_m3 f2 cmp0_m3 42 gpiof3 /cmp0_p3 f3 cmp0_p3 21 28 24 43 gpioa1 /pwm1 a1 pwm1 22 29 25 44 gpioa0 /pwm0 a0 pwm0 23 30 26 45 tdi /gpiod0/anb12/ss / tin2/cmp0_out d0 ss anb12 cmp0_out tin2 tdi 46 gpioc3/ ext_trigger c3 ext_ trgger 24 31 27 47 tms/ gpiod3/anb11/t1/ cmp1_out d3 anb11 cmp1_out t1 tms 25 32 28 48 tdo / gpiod1/anb10/t0/ cmp2_out d1 anb10 cmp2_out t0 tdo 1 shielded adc input. table 4. 56f8006/56f8002 pins (continued) pin number pin name peripherals 28 soic 32 lqfp 32 psdip 48 lqfp gpio i 2 c sci spi adc pga comp dual timer pwm power and ground jtag misc. mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 14 figure 4. top view, mc56f8006/mc56f8002 28-pin soic package anb6 & pga1? & cmp0_p4/gpioc5 anb4 & cmp1_p1/gpioc6/pwm2 v dda v ssa ana9 & pga0? & cmp2_p4/gpioc2 ana7 & pga0+ & cmp2_m2/gpioc1 ana5 and cmp1_m1/gpioc0/fault0 v ss tck/gpiod2/ana4 & cmp1_p2/cmp2_out reset /gpioa7 gpiob3/mosi/tin3/ana3 & anb3/pwm5/cmp1_out gpioa6/fault0/ana1 & anb1/scl/txd/clko_1 gpiob4/t0/clko_0/miso/sda/rxd/ana0 & anb0 gpioa5/pwm5/fault2 or ext_sync/tin3 anb8 & pga1+ & cmp0_m2/gpioc4 gpiob1/ss /sda/ana12 & cmp2_p3 gpiob6/rxd/sda/ana13 & cmp0_p2/clkin tdo/gpiod1/anb10/t0/cmp2_out tms/gpiod3/anb11/t1/cmp1_out tdi/gpiod0/anb12/ss /tin2/cmp0_out gpioa0/pwm0 gpioa1/pwm1 v ss v dd gpiof0/xtal gpioa3/pwm3/txd/extal gpioa4/pwm4/sda/fault1/tin2 gpiob0/sclk/scl/anb13/pwm3/t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 signal/connection descriptions mc56f8006/mc56f8002 digital si gnal controller, rev. 4 freescale semiconductor 15 figure 5. top view, mc56f8006 32-pin lqfp package orientation mark gpiob6/rxd/sda/ana13 & cmp0_p2/clkin gpiob1/ss /sda/ana12 & cmp2_p3 gpiob7/txd/scl/ana11 & cmp2_m3 gpiob5/t1/fault3/sclk anb8 and pga1+ & cmp0_m2/gpioc4 anb6 and pga1? & cmp0_p4/gpioc5 anb4 & cmp1_p1/gpioc6/pwm2 v dda v ssa ana9 and pga0? & cmp2_p4/gpioc2 ana7 and pga0+ & cmp2_m2/gpioc1 ana5 and cmp1_m1/gpioc0/fault0 v ss tck/gpiod2/ana4 & cmp1_p2/cmp2_out reset /gpioa7 gpiob3/mosi/tin3/ana3 & anb3/pwm5/cmp1_out gpioa3/pwm3/txd/extal gpioa2/pwm2 gpiob0/sclk/scl/anb13/pwm3/t1 gpioa5/pwm5/fault2 or ext_sync/tin3 gpiob4/t0/clko_0/miso/sda/rxd/ana0 & anb0 gpioa6/fault0/ana1 & anb1/scl/txd/clko_1 gpiob2/miso/tin2/ana2 & anb2/cmp0_out tdo/gpiod1/anb10/t0/cmp2_out tms/gpiod3/anb11/t1/cmp1_out tdi/gpiod0/anb12/ss /tin2/cmp0_out gpioa0/pwm0 gpioa1/pwm1 v ss v dd gpiof0/xtal gpioa4/pwm4/sda/fault1/tin2 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 mc56f8006/mc56f8002 digital si gnal controller, rev. 4 signal/connect ion descriptions freescale semiconductor 16 figure 6. top view, mc56f8006 32-pin psdip package ! . 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