philips semiconductors product specification 74f385 quad serial adder/subtractor 1 1989 sep 20 8530868 97678 features ? four independent adders/subtractors ? two' s complement arithmetic ? synchronous operation ? common clear and clock ? 74f385 is designed for use with serial multipliers in implementing digital filters and butterfly networks in fast fourier transforms description the 74f385 contains four independent adder/subtractor elements with common clock and master reset. each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. flip-flop state changes occur on the rising edge of the clock pulse (cp) input signal. the select (s) input should be low for the add (a plus b) mode and high for the subtract (a minus b) mode. a low signal on the asynchronous master reset (mr ) input clears the sum flip-flop and resets the carry flip-flop to zero in the add mode or presets it to one in the subtract mode. pin configura tion 20 19 18 17 16 15 14 7 6 5 4 3 2 1 13 8 v cc cp f0 s0 b0 a0 a1 b1 s1 f1 gnd f3 s3 b3 a3 a2 b2 s2 f2 mr sf00928 12 9 11 10 type typical f max typical suppl y current (total) 74f385 140 mhz 55ma ordering information description commercial range v cc = 5v 10%, t amb = 0 c to +70 c 20-pin plastic dip n74f385n 20-pin plastic so n74f385d input and output loading and f an out table pins description 74f (u.l.) high/low load value high/low a0 a3 a operand inputs 1.0/1.0 20 m a/0.6ma b0 b3 b operand inputs 1.0/1.0 20 m a/0.6ma s0 s3 function select inputs 1.0/1.0 20 m a/0.6ma cp clock pulse input (active rising edge) 1.0/1.0 20 m a/0.6ma mr asynchronous master reset input (active low) 1.0/1.0 20 m a/0.6ma f0f3 sum or dif ference outputs 50/33 1.0ma/20ma note: one (1.0) f ast unit load is defined as: 20 m a in the high state and 0.6ma in the low state.
philips semiconductors product specification 74f385 quad serial adder/subtractor 1989 sep 20 2 logic symbol f0 f1 f2 f3 v cc = pin 20 gnd = pin 10 a0 b0 a1 b1 a2 b2 a3 b3 5 4 6 7 15 14 16 17 cp mr s0 s1 s2 s3 1 11 3 8 13 18 2 9 12 19 sf00929 iec/ieee symbol 9 11 19 5 p sf00930 8 6 7 13 15 14 18 16 q 11 1 2 17 m3 4(3c i/ 3bi) 3c o/ 3bo /pq z4 2d r 2d 3r 3s 3 4 z1 c2 function table inputs carry flip-flop st ate outputs operating mode mr s a b before after f mode l l x x l l l clear l h x x h h l clear h l l l l l l add h l l l h l h add h l l h l l h add h l l h h h l add h l h l l l h add h l h l h h l h l h h l h l h l h h h h h h h l l l l h subtract h h l l h h l subtract h h l h l l l subtract h h l h h l h subtract h h h l l h l subtract h h h l h h h h h h h l l h h h h h h h l h = high voltage level l = low voltage level x = don't care = low-to-high clock transition
philips semiconductors product specification 74f385 quad serial adder/subtractor 1989 sep 20 3 logic diagram v cc = pin 20 gnd = pin 10 11 sf00931 5 4 3 1 mr a0 b0 s0 cp r d cp q sum d cp s r q f0 2 6 7 8 a1 b1 s1 r d cp q sum d cp s r q f1 9 15 14 13 a2 b2 s2 r d cp q sum d cp s r q f2 12 16 17 18 a3 b3 s3 r d cp q sum d cp s r q f3 19 carry carry carry carry
philips semiconductors product specification 74f385 quad serial adder/subtractor 1989 sep 20 4 absolute maximum ra tings (operation beyond the limit set forth in this table may impair the useful life of the device. unless otherwise noted these limits are over the operating free-air temperature range.) symbol parameter rating unit v cc supply voltage 0.5 to +7.0 v v in input voltage 0.5 to +7.0 v i in input current 30 to +5 ma v out v oltage applied to output in high output state 0.5 to v cc v i out current applied to output in low output state 40 ma t amb operating free-air temperature range 0 to +70 c t stg storage temperature 65 to +150 c recommended opera ting conditions symbol parmeter limits unit symbol parmeter min nom max unit v cc supply voltage 4.5 5.0 5.5 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ik input clamp current 18 ma i oh high-level output current 1 ma i ol low-level output current 20 ma t amb operating free-air temperature range 0 70 c dc electrical characteristics (over recommended operating free-air temperature range unless otherwise noted.) symbol parameter test limits unit symbol parameter conditions 1 min typ 2 max v oh high-level output voltage v cc = min, v il = max, 10%v cc 2.5 v v oh high-level output voltage v ih = min, i oh = max 5%v cc 2.7 3.4 v v ol low-level output voltage v cc = min, v il = max, 10%v cc 0.35 0.50 v v ol low-level output voltage v ih = min, i ol = max 5%v cc 0.35 0.50 v v ik input clamp voltage v cc = min, i i = i ik 0.73 1.2 v i i input current at maximum input voltage v cc = max, v i = 7.0v 100 m a i ih high-level input current v cc = max, v i = 2.7v 20 m a i il low-level input current v cc = max, v i = 0.5v 20 m a i os short-circuit output current 3 v cc = max 60 150 ma i cc supply current (total) v cc = max 55 80 ma notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applicable type. 2. all typical values are at v cc = 5v, t amb = 25 c. 3. not more than one output should be shorted at a time. for testing i os , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. in any sequence of parameter tests, i os tests should be performed last.
philips semiconductors product specification 74f385 quad serial adder/subtractor 1989 sep 20 5 ac electrical characteristics limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf , r l = 500 w c l = 50pf, r l = 500 w min typ max min max f max maximum clock frequency w aveform 1 105 140 90 mhz t plh t phl propagation delay , cn to fn w aveform 1 3.0 3.5 5.0 5.5 8.0 9.0 2.5 3.5 9.0 10.0 ns t plh propagation delay , mr to fn w aveform 2 4.0 6.5 9.5 4.0 10.5 ns ac setup requirements limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf , r l = 500 w c l = 50pf, r l = 500 w min typ max min max t s (h) t s (l) setup time, high or low an, bn or sn to cp w aveform 3 12.0 12.0 12.0 12.0 ns t h (h) t h (l) hold time, high or low an, bn or sn to cp w aveform 3 0 0 0 0 ns t s (h) t s (l) cp pulse width high or low w aveform 2 6.0 6.0 6.0 6.0 ns t w (l) mr pulse width low w aveform 2 6.0 6.0 ns t rec (l) recovery time mr to cp w aveform 2 8.5 9.5 ns ac waveforms for all waveforms, v m = 1.5v. the shaded areas indicate when the input is permitted to change for predictable output performances. cp v m v m v m t w (h) 1/f max v m v m t plh t w (l) t phl fn sf00932 w aveform 1. propagation delay , clock input to output, clock pulse w idth, and maximum clock frequency v m v m v m v m fn mr t phl t rec sf00933 cp t w (l) waveform 2. master reset pulse w idth, master reset to output delay and master reset to clock recovery t ime v m v m v m v m v m v m t s (l) t h (l) t s (h) t h (h) an, bn, sn cp sf00934 waveform 3. data and select setup and hold t imes
philips semiconductors product specification 74f385 quad serial adder/subtractor 1989 sep 20 6 test circuit and w aveform t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0v 0v t thl ( t f ) input pulse requirements rep. rate t w t tlh t thl 1mhz 500ns 2.5ns 2.5ns input pulse definition v cc family 74f d.u.t. pulse generator r l c l r t v in v out t est circuit for t otem-pole outputs definitions: r l = load resistor; see ac electrical characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac electrical characteristics for value. r t = t ermination resistance should be equal to z out of pulse generators. t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.0v 1.5v v m sf00006
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