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| asahikasei [ak8813/14] rev.00 - 1 - 2004/oct ak8813/14 ntsc/pal digital video encoder general description the ak8813/14 is low voltage, low power and sm all packaged digital video encoder. it is suitable for a stb or digital tv. it converts itu-r. bt601/656 standard 8- bit parallel data into analog composite video signal, s-video in ntsc and pal formats. ak8813/14 supports copy protecti on, closed captioning and video bl anking id(cgms-a) and wss. these functions are c ontrolled by high-speed i 2 c bus interface. features ? ntsc-m, pal-b,d,g,h,i,m,n encoding. ? simultaneous composite video signal and s-video signal outputs ? itu-r bt.656 4:2:2 8-bit parallel input - eav decoding ? master/slave operation - digital field sync i/o - digital vertical/horizontal sync i/o ? y filtering 2 x over-sampling ? c filtering 4 x over-sampling ? single 27mhz clock (the polarity could be inverted by sysinv pin) ? triple 10-bit dacs ? i 2 c bus interface (400khz) ? closed caption encoding (ntsc: li ne 21,284-smpte pal: line 22,335-ccir) ? macrovision copy protecti on rev. 7.1 * (only ak8814 ) ? vbid, cgms-a(eiaj cpr-1024) ? wss ? on-chip color bar generator ? low power consumption ? 2.8v to 3.3v operation cmos monolithic ? 48pin lqfp package / 57pin fbga package (*note) this device is protected by u.s. pat ent numbers 4,631,603, 4,577, 216, and 4,819,098, and other intellectual rights. the use of ma crovision?s copy protection technol ogy in the device must be authorized by macrovision and is intended for home and other lim ited pay-per -view use only, unless otherwise authorized in written by macrovision. reve rse engineering or disassembly is prohibited.
asahikasei [ak8813/14] rev.00 - 3 - 2004/oct block diagram 4:2:2 to 4:4:4 (x 2 interpolator) 10-bit dac cgm s - a wss timing generator syn c -for m generator u -p i/f (i 2 c) & register v ref generator avdd avss dvdd dvss data[7:0] sda scl sela vrefin vrefout iref clk y composite c /pd hsync input formatter eav decode y delay c delay vsync macrovisi on clknv sub-carrier generator luma filter (x 2 interpolator) chrom a lpf filter (x 2 interpolator) /reset 10-bit dac 10-bit dac asahikasei [ak8813/14] rev.00 - 4 - 2004/oct ordering guide ak8813vq: lqfp48 non-macrovision (pb free) ak8813vg: fbga57 non-macrovision AK8813VGP: fbga57 non-macrovision (pb free) ak8814vq: lqfp48 macrovision (pb free) ak8814vg: fbga57 macrovision (pb free) asahikasei [ak8813/14] rev.00 - 5 - 2004/oct pin layout 48pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ud9 d7 d6 d5 d4 dvdd dvss d3 d2 d1 d0 test test sela scl sda pd /reset a vss y a vdd c a vss cvbs avss avdd vrefout vrefin iref dvss dvdd ud0 ud1 ud2 ud3 ud4 sysinv dvss hsync fid/vsync dvdd ud8 dvdd syscl k dvss ud7 ud6 ud5 57pin fbga a b c d e f g h j 9 8 7 65432 1 bottom view asahikasei [ak8813/14] rev.00 - 6 - 2004/oct pin/function 48pin lqfp no. pin name i/o description 1 ud9 i/o test pin. open for normal operation 2-5, 8-11 d7 - d0 i 27mhz 8-bit 4:2:2 multiple xed y,cb,cr data input. for rec.656 format, ak8813/14 decodes eav. for non-rec.656 format (without eav), ak8813/14 operates in master or slave mode. 12-13 test i test pin. ground for normal operation 14 sela i the slave address is set with this pin. ?l?:40h ?h?:42h 15 scl i serial interface clock 16 sda i/o serial interface data 17 pd i power down pin. after returning from pd mode to normal operation, reset sequence should be done to ak8813/14. 18 /reset i after this pin becomes ?l?, ak8813/14 starts the internal initializing sequence. after initializing sequence, ak8813/ 14 is set ntsc mode, rec.656 decoding mode. all dacs off condition. after power up, ak8813/14 must be initialized with this pin. (27mhz clock is necessary for reset sequence.) 20 y o output of luminance signal. 22 c o output of the chrominance signal 24 composite o output of composite video signal 27 vrefout o output of the internal vref. terminat e with 0.1uf or more capacitor. 28 vrefin i input of the reference voltage 29 iref o the currents flow this pin adjusts the full-scale output current of the dac. connect this pin to analog ground via a 6.8kohm resistor ( better than +/- 1% accuracy ). 32-39 ud0-ud7 i/o test pin. open for normal operation 41 sysclk i 27mhz clock input. the polarity could be inverted by sysinv. 43 ud8 i/o test pin. open for normal operation 45 fid /vsync i/o either of fid or vsync se lected by the register. rec.656 decode mode :output master mode : output slave mode : input fid shows that ?l? is odd field and ?h? is even field. 46 hsync i/o rec.656 decode mode : output master mode : output slave mode : input 48 sysinv i ?l ? : data is latched with rising edge. ?h? : data is latched with falling edge. 21,26 avdd p analog power supply 6,31, 42,44 dvdd p digital power supply 19,23,25 avss g analog ground 7,30, 40,47 dvss g digital ground asahikasei [ak8813/14] rev.00 - 7 - 2004/oct 57pin fbga no. pin name i/o description a1 nc - open for normal operation b1 avss g analog ground c1 avdd p analog power supply c2 vrefout o output of the internal vref. terminat e with 0.1uf or more capacitor. d1 vrefin i input of the reference voltage d2 iref o the currents flow this pin adjusts the full-scale output current of the dac. connect this pin to analog ground via a 6.8kohm resistor ( better than +/- 1% accuracy ). e1 dvss g digital ground e2 dvdd p digital power supply f2 ud0 i/o test pin. open for normal operation f1 ud1 i/o test pin. open for normal operation g2 ud2 i/o test pin. open for normal operation g1 ud3 i/o test pin. open for normal operation h1 ud4 i/o test pin. open for normal operation j1 nc - open for normal operation j2 ud5 i/o test pin. open for normal operation h2 ud6 i/o test pin. open for normal operation h3 ud7 i/o test pin. open for normal operation j3 dvss g digital ground h4 sysclk i 27mhz clock input. the polarity could be inverted by sysinv. j4 dvdd p digital power supply h5 ud8 i/o test pin. open for normal operation j5 dvdd p digital power supply j6 fid/vsync i/o either of fid or vsync se lected by the register. rec.656 decode mode :output master mode : output slave mode : input fid shows that ?l? is odd field and ?h? is even field. h6 hsync i/o rec.656 decode mode : output master mode : output slave mode : input h7 dvss g digital ground j7 sysinv i ?l ? : data is latched with rising edge. ?h? : data is latched with falling edge. h8 ud9 i/o test pin. open for normal operation j9 nc - open for normal operation j8 d7 i video data input (msb) g8 d6 i video data input asahikasei [ak8813/14] rev.00 - 8 - 2004/oct h9 d5 i video data input g9 d4 i video data input f8 dvdd p digital power supply f9 dvss g digital ground e8 nc - open for normal operation e9 d3 i video data input d8 d2 i video data input d9 d1 i video data input c8 d0 i video data input c9 test i open for normal operation b9 test i open for normal operation a9 nc - open for normal operation a8 sela i the slave address is set with this pin. ?l?:40h ?h?:42h b8 scl i serial interface clock b7 sda i/o serial interface data a7 pd i power down pin. after returning from pd mode to normal operation, reset sequence should be done to ak8813/14. a6 /reset i after this pin becomes ?l?, ak8813/14 starts the internal initializing sequence. after initializing sequence, ak8813/ 14 is set ntsc mode, rec.656 decoding mode. all dacs off condition. after power up, ak8813/14 must be initialized with this pin. (27mhz clock is necessary for reset sequence.) b6 avss g analog ground a5 nc - open for normal operation b5 y o output of luminance signal. b4 avdd p analog power supply a4 c o output of the chrominance signal b3 avss g analog ground a3 cvbs o output of composite video signal b2 nc - open for normal operation a2 nc - open for normal operation c3 nc - open for normal operation (note1) at itu-r.bt656 i/f mode operation, fid/vsy nc, hsync pins should be pulled up to vdd with 100k-ohm resistor (note2) this device requires reset operation. before resetti ng the state of the pin of i/o are unknown state. after reset sequence, i/opins (fid/vsync, hsync) turns hi-z states. asahikasei [ak8813/14] rev.00 - 9 - 2004/oct electrical characteristics absolute maximum ratings parameter min max units supply voltage (vdd) dvdd, avdd -0.3 4.6v v input pin voltage (vin) -0.3 vdd+0.3 v input pin current (iin) - 10 ma analog reference current (iref) - 0.37 ma analog output current - 11.6 ma storage temperature -40 125 c (note) when all ground pins(d vss, avss) are set to 0v. recommended operating conditions parameter min typ. max units supply voltage (vdd) 2.8 3.3 3.6 v operating temperature -20 85 c asahikasei [ak8813/14] rev.00 - 10 - 2004/oct dc characteristics [power supply:2.8 ~ 3.6v temperature:-20 ~ 85 c] parameter symbol min max units conditions digital input high voltage vih1 0.7vdd v note1) digital input low voltage vil1 0.3vdd v note1) digital input leak current il 10 ua note1) digital output high voltage voh 2.4/2.2 note 3) v ioh =-1ma note 2) digital output low volt age vol1 0.4 v iol = 2ma note 2) i 2 c input high voltage i 2 c(sda,scl) vih2 0.7vdd v i 2 c input low voltage i 2 c(sda,scl) vil2 0.3vdd v i 2 c(sda) output voltage vol2 0.4 v iol = 3ma note 1) d[9:0],fid/vsync, hsync, sysclk, /reset pin note 2) fid/vsync, hsync pin note 3) dvdd=2.8v~3.0v voh 2.2v note ) connected test pin to ground, sela and sysinv pin are desired polarity. analog characteristics [avdd:3.3v temperature:25 c load resistance 220ohm iref resistance 6.8kohm] parameter min typ max units conditions dac resolution 10 bit dac integral linearity error 0.6 2 lsb dac differential linearity error 0.4 1 lsb dac output full scale voltage 1.21 1.28 1.35 v note1) dac output offset voltage 5.0 mv note2) unbalances between dacs 1 5 % note3) isolation between dacs 50 db 1mhz full scale dac load capacitance 30 pf note4) internal reference voltage 1.17 1.235 1.30 v internal reference drift -50 ppm/ c note 1) under the condition of output load 220 ? , iref pin with 6.8k ? , using internal reference. the output full-scale current iout is calculated as full scale output voltage (typ. 1.28v) /220 ? =typ. 5.82ma. note 2) dac output when feeding code of 0 (decimal). note 3) deviation between the dac output w hen feeding 1v generating code of 800(decimal). note 4) the value is a design target. this value is not tested. dissipation current [avdd=dvdd=:3.3v temperature:-25~85 c ] parameter min typ max units conditions dac current (active mode) 24 ma note1) dac current (sleep mode) 10 ua note2) power down current 10 100 ua note3) total current 50 65 ma note4) note 1) all dacs are operating. note 2) all dacs are turned off with no system clock. note 3) in case the value after power down sequence. note 4) ntsc internal color bar with 3ch dacs operation and slave mode operation. dac output pins is connected with only 220 ? load. asahikasei [ak8813/14] rev.00 - 11 - 2004/oct ac characteristics (2.8v - 3.6v temperature ?20 ~ 85 c cl=30pf) (1). sysclk clk fclk tclkh tclkl vil vih 50%level between vih and vil parameter symbol min. typ. max unit sysclk fsysclk 27 mhz sysclk pulse width h tclkh 15 nsec sysclk pulse width l tclkl 15 nsec (2). pixel data input timing (2-1) sysinv = low tds tdh d7:d0 clk vih vil (2-2) sysinv = high tds tdh d7:d0 clk vih vil parameter symbol min typ max units data setup time tds 5 nsec data hold time tdh 8 nsec asahikasei [ak8813/14] rev.00 - 12 - 2004/oct (3). synchronizing signal ( fid/vsync, hsync ) (3-1) sysinv=low (3-1-1) input timing tds tdh fid/vsync, hsync sysclk vih vil parameter symbol min typ. max units data setup time tds 5 nsec data hold time tdh 8 nsec (3-1-2) output timing sysclk fid/vsync, hsync tdel vih parameter symbol min typ. max units delay from sysclk tdel 27 nsec asahikasei [ak8813/14] rev.00 - 13 - 2004/oct (3-2) sysinv = high (3-2-1) input timing tds tdh fid/vsync, hsync sysclk vih vil parameter symbol min typ. max units data setup time tds 5 nsec data hold time tdh 8 nsec (3-2-2) output timing sysclk fid/vsync, hsync tdel parameter symbol min typ. max units delay from sysclk tdel 27 nsec asahikasei [ak8813/14] rev.00 - 14 - 2004/oct (4). reset (initialize) reset timing /reset pres sysclk 1 2 9 10 hsync,vsync,sda hi-z indefinite state parameter symbol min typ. max units /reset pulse width pres 10 sysclk after power up, i/o pins of ak 8813/14 are in the indefin ite state. it should be initialize with reset sequence. while reset sequence system clock s hould be input to ak8813/14 and scl, sda should be high state. (5) power down sequence /reset ppd sysclk 1 2 99 100 pd vss vdd 101 parameter symbol min typ. max units /reset pulse width pstop 100 sysclk during ?power down? state, control si gnal should be set to vdd state or vss state. asahikasei [ak8813/14] rev.00 - 15 - 2004/oct ( 5). i 2 c bus (scl 400khz cycle mode ) (5-1) i/o timing 1 tr tlow sda tbuf thd:sta tf tr tf tsu:sto tsu:sta scl parameter symbol min max units bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec bus signal rise time tr 300 nsec bus signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec all the figures shown above list are not rest ricted by ak8813/14 but are restricted by i 2 c bus standard. please see the i 2 c bus standard for further details. (5-2) i/o timing 2 sda thd:dat thigh tsu:dat scl parameter symbol min. max. unit. data setup time tsu:dat 100 (1) nsec data hold time thd:dat 0.0 0.9 (2) usec clock pulse high time thigh 0.6 usec (note1) in case of normal i 2 c bus mode tsu:dat 250nsec (note2) using under minimum tlow, this value must be satisfied. (note3) i2c i/f reset is done by reset sequence of ak8813/14 , system clock (27mhz) is necessary to do reset sequence. however, sda pin is always hi-z state when pd pin is set to high. asahikasei [ak8813/14] rev.00 - 16 - 2004/oct functional description ? reset when the reset pin [ /reset ] set to ?l?, ak8813/14 is in reset state. ak8813/14 starts in the internal initializing sequence at the tr ailing edge of the first sysclk after the rese t pin is ?l?. all internal registers are set to be default value by this initializing sequence. ak8813/14 needs at least 10 clock counts of sysclk for this reset operation. after the reset oper ation, the video output pi ns are in high-impedance. ak8813/14 requires sysclk for the reset operation. ? master clock ak8813/14 requires 27mhz clock at sysclk pin fo r operation. video input dat a (itu-r bt.656) is sampled at the trailing edge of this 27m hz. sysinv decides the edge direction. sysinv = l data is sampled at rising edge of sysclk. sysinv = h data is sampled at falling edge of sysclk. ? video signal interface ak8813/14 can interface with t he video input data by the following 3 modes. the mode is set by the register [ interface mode register(00h) ]. 1. itu-r bt.656 format ak8813/14 decodes eav in stream data and m anages an internal synchronization. in this case, ak8813/14 outputs fid ( odd : ?l? even : ?h?)/ vsync and hsync. ccir-bit of [ interface mode regi ster (00h) ] should be set ?1? . 2. itu-r bt.656 like format (4:2:2 y/cb/cr) there are master and slave modes, for itu-r bt.656 like format which does not include eav. in this mode, ccir-bit of [ interface mode register(00h) ] should be set ?0? . asahikasei [ak8813/14] rev.00 - 17 - 2004/oct ? video signal conversion video reconstruction module conv erts the multiplexed data (itu-r . bt601 y/cb/cr) to the interlace format of ntsc-m, pal-m, pal-b,d,g,h,i,n and ot her formats (ex. ntsc-4.43 and pal60). the video reconstruction format, the line number, the color encode way(ntsc or pal) and the frequency of color sub-carrier is specified by [video process 1 register(01h)]. (cf. burs t signal table) the frequency and the phase of color sub-carrier are al so adjustable by [sub c. freq. register(06h)] and [sub c. phase register(07h)]. the sub-carrier has a free-runni ng mode and a reset-mode. in the reset-mode, the sub-carrier is reset automatically to the initial phas e for every 4 fields (ntsc) or 8 fields (pal). asahikasei [ak8813/14] rev.00 - 18 - 2004/oct ? luminance filter luminance signal passes through the 2x low pass filt er with sin(x)/x com pensation. fig.1 is the characteristic of luminance filter. luma filter -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency [mhz] gain [db] fig. 1 luminance filter asahikasei [ak8813/14] rev.00 - 19 - 2004/oct ? chrominance filter chrominance signals (cb,cr) before sub-carrier m odulation pass through the 1.3 mhz low pass filter shown in fig.2. chrominance signal modulated by sub-carrier passes thr ough the filter shown in fig.3. fig. 2 chroma-1 lpf fig. 3 chroma-2 lpf -70 -60 -50 -40 -30 -20 -10 0 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 frequency [mhz] gain [db] -70 -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency [mhz] gain [db] asahikasei [ak8813/14] rev.00 - 20 - 2004/oct ? color burst signal color burst signal is generated by 32bits-length digital frequency synt hesizer. the default frequency of the color burst is selected by [video process 1 register(0x01)]. standard sub-carrier freq. [mhz] video process 1 [vm1,vm0] ntsc-m 3.57954545 [0,0] pal-m 3.57561188 [0,1] pal-b,d,g,h,i 4.43361875 [1,1] pal-n(arg.) 3.5820558 [1,0] pal-n(non-arg.) 4.43361875 [1,1] pal60 4.43361875 [1,1] ntsc-4.43 4.43361875 [1,1] burst signal table sub-carrier frequency 3.57561188mhz is allo wed when pal-m mode is selected. the burst frequency and initial phas e resolution are as follows. frequency resolution 0.8046hz sch phase resolution 360 /256 ? video dac ak8813/14 has the three current driven 10bits-dacs at 27mhz operation. the full scale voltage of dac is determined by the current output from iref pin. typical output vo ltage is 1.28vo-p under the condition of vrefin 1.235v, 6.8k ? between iref pin and ground(avss) and dac load resistance of 220 ? . this full-scale voltage should be set in the range of 1.17v to 1.33v by adjusting the re sistor which terminates iref pin. each dac output can be set to ?active state? or to ?inactive state? individually by [dac mode register(05h)]. when dac is in ?inactive state?, t he output is hi-impedance. w hen all dacs are set to ?inactive state?, the analog part of ak8813/14 goes into sleep mode. in this case ak8813/14 stops outputting the reference voltage(vref) output. when any da c is switched over in ?active state? from sleep mode, ak8813/14 starts outputting re ference voltage. in this case ak8813/14 needs several milliseconds for vref wake-up time. using internal vref as the re ference voltage, connect [vref out] pin with [vref in] pin and [vref out] pin is terminated with more than 0.1uf capacitor. ? use external reference voltage in order to improve the accuracy of dac output, external reference voltage may be used. in this case, vrefout pin still needs to be terminated with more than 0.1uf capacitor. asahikasei [ak8813/14] rev.00 - 21 - 2004/oct ? copy protection ak8814 has the function of macrov ision copy protection. inform ation about the ma crovision encoding functions of the ak8814 is avail able to macrovision licensees. ak8813 doesn?t have this function. macrovision corporation 2830 de la cruz boulevard santa clara, california 95050 u.s.a. main telephone (switchboard): +1 408 743-8600 main fax: +1 408 743-8610 technical support group fax: +1 408 743-8617 asahikasei [ak8813/14] rev.00 - 22 - 2004/oct ? closed caption and extended data ak8813/14 supports both closed captioning and extended data. they are controlled ?on? or ?off? respectively by [ video process 2 register(02h ) ]. each data consists of 2 continuous bytes register( closed caption r (16h, 17h) ), and it is rec ognized as the data is renewed when the second byte(17h register) is written in the register . after the data is renew ed, ak8813/14 enc odes closed captioning and extended data at the designated line. if the data isn?t renewed, ak8813/14 outputs ?ascii-null? code. the data is s upposed as odd parity and 7 bit us- ascii code. host should provide a parity bit. *in pal encoding mode, ak8813/14 out puts them at the same timing and same pattern as ntsc. *the line where closed captioning dat a is encoded is as follows. 525/60 system (smpte) 625/50 system (ccir) closed caption 21 line def ault 22 line default extended data 284 line default 335 line default 40ir e 50 +/- 2 ir e start parity parity d0-d6 d0-d6 240+/- 48nsec 240+/- 48nsec two 7-bit + parity ascii characters data 10.003 +/- 0.25usec 27.382 usec 33.764 usec 61 usec 10.5 +/- 0.25usec 12.91 usec fig. 4 closed captioning wave form asahikasei [ak8813/14] rev.00 - 23 - 2004/oct ? video id ak8813/14 supports video id (eiaj standard, cpr-1204) encoding for the distinction of an aspect ratio or cgms-a etc. setting or resetting the vbid-bit of [ video process 2 register(02h) ], this function is switched on/off. the data is set by usi ng [ video id data register(1ah, 1bh) ]. vbid data renewal timing. vsync new data data old data new data i 2 c sda set control register fig. 5 vbid data renewal timing vbid data layout vbid is consists of 20 bits and its format is shown as follows. ak8813/14 generates crc code automatically and appends it to t he data. initial value of the polynomial is 1. data bit1 bit20 word0 2bit word1 4bit word2 8bit crc 6bit fig. 6 vbid code assignment asahikasei [ak8813/14] rev.00 - 24 - 2004/oct vbid waveform ref. bit1 bit2 bit3 bit20 ??? 2.235usec +/- 50nsec 11.2usec +/- 0.3usec 11.2usec +/- 0.3usec 1h 70ire +/- 10ire 0ire + 10 ire ? 5 ire fig. 7 vbid wave form 5 2 5/60 sys t e m 6 2 5/50 sys t e m am p litude 70 ire 490 mv encode line 20/283 20/333 vbid parameter table asahikasei [ak8813/14] rev.00 - 25 - 2004/oct ? wss ak8813/14 supports wss(itu-r.bt.1119) encoding for the distinction of an aspect ratio etc. setting or resetting the wss-bit of [ video process 2 register(02h ) ], this function is swit ched on/off. the data is set by using [ wss data register(08h, 09h) ]. wss data renewal timing vsync new data data old data new data i 2 c sda set control register fig. 8 wss data renewal timing 10.5usec 27.4usec 38.4usec 500mv +/- 50% 11.0 +/- 0.25usec 44.5usec 1.5usec 0 h fig. 9 wss wave form encode line: line 23 coding: bi-phase modulation coding clock: 5mhz (ts = 200ns) run-in start code group 1 aspect ratio group 2 enhanced services group 3 subtitles group4 reserved 29 elements 24 elements 24 elements 24 elements 18 elements 18 elements bit numbering 0 1 2 3 lsb msb 0 : 000111 1 : 111000 bit numbering 4 5 6 7 lsb msb 0 : 000111 1 : 111000 bit numbering 8 9 10 lsb msb 0 : 000111 1 : 111000 bit numbering 11 12 13 lsb msb 0 : 000111 1 : 111000 0x1f1c71c7 0x1e3c1f asahikasei [ak8813/14] rev.00 - 26 - 2004/oct ? ak8813/14 interface timing (part 1) m aster mode & itu-r bt. 656 mode on itu-r bt.656 decoding mode or master m ode operation, ak8813/14 out puts hsync and fid or vsync (selected by register). when ak8813/14 receives itu-r bt. 656 signal , ak8813/14 decodes [eav] code in the data for synchronization then outputs the h sync. ak8813 outputs hsync at t he rising edge of sysclk in the timing of the 32nd/24th(ntsc/pal) dat a slot, which is counted from t he [eav] starting point as below. (see also ac characteristics 2-2[input synchronizing signal]) on master mode operation, the fr ont device connected with ak8813/14 (ex. mpeg decoder) starts to set cb on the 276th/288th(ntsc/pal) slot, afte r starting to count hsync falling edge as 32nd/24th(ntsc/pal) slot. fid/vsync is output synchronously with hsync at the timing of solid line as in fig. 10 video field. eav sav y/ cb/ cr cb y cr y cb y cr y cb y cr y cb y cr y cb y cr y cb dat a# 525 system 360 720 360 721 361 722 361 723 368 736 368 855 428 856 428 857 0 0 0 1 1 dat a# 625 system 360 720 360 721 361 722 361 723 366 732 366 861 431 862 431 863 0 0 0 1 1 33 / 25t (525 / 625) 243 / 263t (525 / 625) tbd t sysclk hsync anal og out 276/ 288t (525 / 625) fig. 10 interface timing (itu -r bt.656 or master mode) asahikasei [ak8813/14] rev.00 - 27 - 2004/oct ? ak8813/14 interface timing (part 2) slave mode on slave mode operation, hsync and fid or vsync (s elected by register) are input to ak8813/14. ak8813/14 monitors the trans ition of hsync at the timing of t he rising edge of sysclk. (refer to ac characteristic 2-1. [input synchronizing signal]) after ak8813/14 recognizes hsync is low-logic, ak8813/14 sets the slot number to the 32nd/24th(ntsc/pal), internally , then ak8813/14 starts to sample the data as cb on 276th/ 288th(ntsc/pal) slot. video field is recognized the tr ansition timing between fi d/vsync and hsync. (fig. 10. video field) as in the figure, there is a tolerance of 1/4h. hsync cb 0 y 0 cr 0 y 1 data cb 1 y 2 cr 1 244t / 264t (525/625) 27mhz tbd-clk fig. 11 interfacing timing (slave mode) hsync vsync/field 1/4 h start of 1st field 1/2 h 1/2 h vsync/field start of 2nd field 1/4 h 1/4 h 1/4 h fig. 12 video field asahikasei [ak8813/14] rev.00 - 28 - 2004/oct ? hsync fid/vsync timing 525 system hsync vsync di gi tal line-no. 4 5 6 7 8 9 10 11 3 2 1 525 fid hsync vsync 267 268 269 270 271 272 273 274 266 di gi tal line-no. 265 264 263 262 fid 625 system hsync vsync digital line-no. fid 1 2 3 4 5 6 7 8 625 624 623 622 hsync vsync digital line-no. 314 315 316 317 318 319 320 313 312 311 310 fid fig. 13 hsync fid/vsync timing asahikasei [ak8813/14] rev.00 - 29 - 2004/oct ? internal color bars generator ak8813/14 generates the common color bar signal fo r ntsc and pal internally. the generated color bar is ?100% amplitude, 100% saturation?. when ak 8813/14 is set to black bu rst output mode, ak8813/14 does not output color bar even colo r bar output register is set. blanking level 100%white synctip level white yellow cyan green magenta red blue black luminance chrominance fig. 14 luminance and chrominance waveform the following values are code for itu-r. bt601 white yellow cyan green magenta red blue black cb 128 16 166 54 202 90 240 128 y 235 210 170 145 106 81 41 16 cr 128 146 16 34 222 240 110 128 ? internal black burst generator ak8813/14 generates black burst signal for ntsc and pal internally. when ak8813/14 is set to black burst output mode, ak8813/14 works same operation as that t he input y/cb/cr data is 16/128/128. in this mode, ak8813/14 does not output color bar even color bar output register is set. asahikasei [ak8813/14] rev.00 - 30 - 2004/oct ? synchronizing signal and burst waveform (1-1) ntsc / ntsc-4.43 / pal-m( video process 1 r egister [vm3:vm2]-bit = 00 / 01 ) (smpte-170m) 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end sync horizontal reference point h blanking start to h -reference 50% sync level 90% 10% h . ref. to b urst start burst envelope rise tim e 50% burst height burst fig. 15 synchronizing signal and burst waveform measurement point value recommended tolerance units total line period(derived) 63.556 usec sync level 40 +/- 1 ire horizontal blanking rise time 10% - 90% 140 +/- 20 nsec sync rise time 10% - 90% 140 +/- 20 nsec burst envelope rise time 10% - 90% 300 +200 -100 nsec h-blanking start to h-reference 50% 1.5 +/- 0.1 usec horizontal sync 50% 4.7 +/- 0.1 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles h reference to h-blanking end 50% 9.2 + 0.2 ?0.1 usec burst 50% 9 +/- 1 cycles burst height * 40 +/- 1 ire * burst height of pal-m is 306mv 9 cycles 19 cycles +/-10 50% fig. 16 synchoronizing signal and burst waveform (ntsc) asahikasei [ak8813/14] rev.00 - 31 - 2004/oct (1-2-1) hsync timing (ntsc/ntsc4.43) 3h 3h 1 2 3 4 5 6 7 89 0.5h 3h 19 +1/- 2line (set control register) 3h 3h 263 264 0.5h 3h 265 266 267 268 269 270 271 272 273 19 283 a b c d e f fig. 17 hsync timing symbol duration measurement point reference a 429t b 858t c 31t d 429t e 858t f 63t 50% 13.5mhz clock fig. 18 equalizing pulse and serration pulse equalizing pulse serration pulse g h 286mv i i i i symbol measurement point value recommended tolerance units field period (derived) 16.6833 msec frame period (derived) 33.3667 msec vertical blanking start before first equalizing pulse 50% 1.5 +/- 0.1 usec vertical blanking (63.556usec x 20lines + 1.5usec) 19* lines + 1.5 usec 0 +/- 0.1 lines usec pre-equalizing duration 3 lines g pre-equalizing pulse width 50% 2.3 +/- 0.1 usec vertical sync duration 3 lines h vertical serration pulse width 50% 4.7 +/- 0.1 usec post-equalizing duration 3 lines g post-equalizing pulse width 50% 2.3 +/- 0.1 usec i sync rise time 140 +/- 20 nsec * this value can be set by the register. asahikasei [ak8813/14] rev.00 - 32 - 2004/oct (1-2-2) fid/vsync timing and phase of burst (pal-m) a b 523 524 525 123 4 56 8 7 910 522 521 520 519 a b 263 264 265 266 267 268 270 269 271 272 261 262 260 259 258 257 a b 523 524 525 123 4 56 8 7 910 522 521 520 519 263 264 265 266 267 268 270 269 271 272 261 262 260 259 258 257 a b fig. 19 fid/vsync timing and phase of burst a : phase of burst : nominal value + 135 b : phase of burst : nominal value - 135 asahikasei [ak8813/14] rev.00 - 33 - 2004/oct (2-1) pal-b,d,g,h,i,n / pal-60 ( video pr ocess 1 register [vm3:vm2]-bit = 11) 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end horizontal sync horizontal reference point h blanking start to h -reference 50% sync level 90% 10% h . ref. to b urst start burst envelope rise tim e 50% burst height burst fig. 20 pal waveform measurement point value recommended tolerance units total line period(derived) 64.0 usec sync level 300 mv horizontal blanking rise time 10% - 90% 0.3 +/- 0.1 usec sync rise time 10% - 90% 0.2 +/- 0.1 usec burst envelope rise time 10% - 90% nsec h-blanking start to h-reference 50% 1.5 +/- 0.3 usec horizontal sync 50% 4.7 +/- 0.2 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles h reference to h-blanking end 50% 10.5 usec burst * 50% 10 +/- 1 cycles burst height ** 300 mv asahikasei [ak8813/14] rev.00 - 34 - 2004/oct (2-2) fid/vsync timing and phase of burst pal-b,d,g,h,i,n / pal-60 ( video process 1 register [vm3:vm2]-bit = 11) 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b a b 623 624 625 123 4 56 8 7 622 621 620 a b 623 624 625 123 4 56 8 7 622 621 620 fig. 21 fid/vsync timing and phase of burst a : phase of burst : nominal value + 135 b : phase of burst : nominal value - 135 asahikasei [ak8813/14] rev.00 - 35 - 2004/oct ? i 2 c control sequence ak8813/14 is controlled by i 2 c bus. the slave address can be selected as 40h or 42h by selecting sela pin. sela slave address pull down [low] 0x40 pull up [high] 0x42 operation : write sequence: (a)1byte write sequence s slave address w a sub address a data a stp 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit (b) sequential write operation s slave address w a sub address(n) a data(n) a data(n+1) a data(n+m) a stp 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit ??? 8-bits 1- bit read sequence: s slave address w a sub address (n) a rs slave address r a data1 a data2 a data3 a ??? data n stp 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 s, rs : start condition a : acknowledge (sda low ) : not acknowledge (sda high) stp : stop condition r/w 1 : read 0 : write : master device (host) : slave device (ak8813/14) asahikasei [ak8813/14] rev.00 - 36 - 2004/oct ? register map sub address register default r/w function 0x00 interface mode register 0x00 r/w setting interface mode 0x01 video process 1 register 0x00 r/w setting standard (ntsc, pal etc.) 0x02 video process 2 register 0x00 r/w setting closed caption/extended data/vbid 0x03 video process 3 register 0x00 r/w setting composite signal or component signal adjusting chrominance/luminance delay 0x04 reserved register 0xaa r/w 0x05 dac mode register 0x00 r/w each dac on/off switch 0x06 sub carrier frequency register 0x00 r/w adjusting sub-carrier frequency 0x07 sub carrier phase register 0x00 r/w adjusting sub-carrier phase 0x08 wws data 1 register 0x00 r/w wss data register 0x09 wws data 2 register 0x00 r/w wss data register 0x16 closed caption 1 register 0x00 r/w closed caption lower byte data 0x17 closed caption 2 register 0x00 r/w closed caption upper byte data 0x18 closed caption extended 1 register 0x00 r/w extended lower byte data 0x19 closed caption extended 2 register 0x00 r/w extended upper byte data 0x1a video id 1 register 0x00 r/w video id lower byte data 0x1b video id 2 register 0x00 r/w video id upper byte data 0x24 status register 0x00 r status 0x25 device id register 0x00 r device id 0x26 device revision register 0x00 r revision asahikasei [ak8813/14] rev.00 - 37 - 2004/oct interface mode register (r/w) [address 0x00] sub address 0x00 default value 0xa4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bln4 bln3 bln2 bln1 bln0 fid mas rec656 default value 1 0 1 0 0 1 0 0 interface mode register definition bit register name r/w definition bit 0 rec656 rec656 i/f mode bit r/w 0 : rec656 non-decode 1 : rec656 decode (at rec.656 mode operation, mas-bit should be 0.) bit 1 mas master mode set bit r/w 0 : slave mode 1 : master mode when rec=0,it?s valid bit 2 fid field id set bit r/w 0 : select vsync 1 : select fid bit 3 ~ bit 7 bln0 ~ bln4 blanking line no bit r/w line blanking no. asahikasei [ak8813/14] rev.00 - 38 - 2004/oct video process 1 register (r/w) [address 0x01] sub address 0x01 default value 0x30 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bbg cbg setup scr vm3 vm2 vm1 vm0 default value 0 0 1 1 0 0 0 0 video process 1 register definition bit register name r/w definition bit 0 ~ bit 3 vm0 ~ vm3 video mode 0 register ~ video mode 3 register r/w [vm1:vm0]-bit 00 : 3.57954545 mhz 01 : 3.57561188 mhz 10 : 3.5820558 mhz 11 : 4.43361875 mhz [vm3:vm2]-bit 00 : 525/60 01 : 525/60 pal (pal-m etc.) 10 : reserved 11 : 625/50 pal (pal-b,d,g,h,i,n) bit 4 scr sub carrier reset bit r/w 0 : sub c. phase reset off 1 : standard field reset bit 5 setup setup bit r/w 0 : no set-up 1 : 7.5 ire set-up bit 6 cbg color bar generator bit r/w 0 : video encode 1 : generates color bar bit 7 bbg black burst generator r/w 0 : video encode 1 : generates black burst register setting of each standar d is shown as following ; vm3-vm0 ntsc-m 0000 pal-b,d,g,h,i 1111 pal-m 0101 pal-60 0111 ntsc4.43 0011 ? when scr is ?on?, the subcarrier phase is reset every 4 fields for ntsc, every 8 fields for pal. ? even when setup is ?on?, there is no se t-up (pedestal) during the blanking lines. asahikasei [ak8813/14] rev.00 - 39 - 2004/oct video process 2 register (r/w) [address 0x02] sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved wss cc284 cc21 vbid default value 0 0 0 0 0 0 0 0 video process 2 register definition bit register name r/w definition bit 0 vbid video id bit r/w 0 : video id off 1 : video id on bit 1 cc21 closed caption bit r/w 0 : closed caption off 1 : closed caption on bit 2 cc284 closed caption extended data bit r/w 0 : extended data off 1 : extended data on bit 3 wss wss set bit r/w 0 : wss off 1 : wss on bit 4 ~ bit 7 reserved reserved bit r/w reserved video process 3 register (r/w) [address 0x03] sub address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved syd2 syd1 syd0 cyd2 cyd1 cyd0 default value 0 0 0 0 0 0 0 0 video process 3 register definition bit register name r/w definition bit 0 ~ bit 2 cyd0 ~ cyd2 composite y delay bit r/w s-video y component delay no. from chroma: 2's comp. bit 3 ~ bit 5 syd0 ~ syd2 s-video y delay bit r/w composite y component delay no. from chroma: 2's comp. bit 6 ~ bit 7 reserved reserved bit r/w reserved ? s-video and y component of the composite signal can be shifted for the chroma signal independently at 3-system clock (27mhz). asahikasei [ak8813/14] rev.00 - 40 - 2004/oct reserved register (r/w) [address 0x04] sub address 0x04 default value 0xaa bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved reserved default value 1 0 1 0 1 0 1 0 reserved bit register name r/w definition bit 0 ~ bit 7 reserved reserved bit. r/w reserved dac mode register (r/w) [address 0x05] sub address 0x05 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved outcp outc outy default value 0 0 0 0 0 0 0 0 dac mode register definition bit register name r/w definition bit 0 outy ydac out bit r/w 0: y signal output : off 1: y signal output : on bit 1 outc cdac out bit r/w 0: chrominance signal output : off 1: chrominance signal output : on bit 2 outcp cpdac out bit r/w 0: composite video signal or u signal output : off 1: composite video signal or u signal output : on bit 3 ~ bit 7 reserved reserved bit. r/w reserved ? video output of ak8813/14 (dac) can be forced ?off? independently. the output of dac that is forced ?off? is hi-impedance. when thr ee dacs are forced ?off?, then the internal vref is also forced ?o ff?. in this case, it takes several milliseconds before the internal vref reaches the proper voltage after any dac becomes ?on?. asahikasei [ak8813/14] rev.00 - 41 - 2004/oct sub carrier frequency control register (r/w) [address 0x06] sub address 0x06 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 subf7 subf6 subf5 subf4 subf3 subf2 subf1 subf0 default value 0 0 0 0 0 0 0 0 sub carrier frequency control register definition bit register name r/w definition bit 0 ~ bit 7 subf0 ~ subf7 sub carrier frequency control bit r/w adjustment of frequency between +127 and ?128 step of 0.8hz sub carrier phase control register (r/w) [address 0x07] sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 subp7 subp6 subp5 subp4 subp3 subp2 subp1 subp0 default value 0 0 0 0 0 0 0 0 sub carrier phase control register definition bit register name r/w definition bit 0 ~ bit 7 subp0 ~ subp7 sub carrier phase control bit r/w adjustment of frequency between +127 and ?128 step of 0.8hz ? sub- carrier phase is adjustable by (360 /256) step. wss data 1 register (r/w) [address 0x08] wss data 2 register (r/w) [address 0x09] sub address 0x08 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 default value 0 0 0 0 0 0 0 0 sub address 0x09 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g4-12 g4-11 g3-10 g3-9 g3-8 default value 0 0 0 0 0 0 0 0 ? ak8813/14 generates the necessary sub-carrier frequency from a system clock by dfs (digital frequency synthesizer) ? frequency of default is adjustabl e by specifying this bit. th is bit adjusts the default frequency. asahikasei [ak8813/14] rev.00 - 42 - 2004/oct closed caption data 1 register (r/w) [address 0x16] closed caption data 2 register (r/w) [address 0x17] sub address 0x16 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc 6 cc5 cc4 cc3 cc2 cc1 cc0 default value 0 0 0 0 0 0 0 0 sub address 0x17 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 default value 0 0 0 0 0 0 0 0 closed caption extended data 1 register (r/w) [address 0x18] closed caption extended data 2 register (r/w) [address 0x19] sub address 0x18 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 default value 0 0 0 0 0 0 0 0 sub address 0x19 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 default value 0 0 0 0 0 0 0 0 ? when the 2nd byte of closed caption data and extended data is written in, ak8813/14 recognizes the renewed data and enc odes it in the video line. when the data is not renewed ak8813/14 outputs null code. asahikasei [ak8813/14] rev.00 - 43 - 2004/oct video id 1 register (r/w) [address 0x1a] video id 2 register (r/w) [address 0x1b] sub address 0x1a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 default value 0 0 0 0 0 0 0 0 sub address 0x1b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14 default value 0 0 0 0 0 0 0 0 ? please write value 0 at reserved bit. ? bit numbers correspond to fig. 5 vbid code assignment. ? ak8813/14 generates crc 6 bit data automatically. status register (r/w) [address 0x24] sub address 0x24 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved en284 en21 sync sts2 sts1 sts0 status register definition bit register name r/w definition bit 0 ~ bit 2 sts0 ~ sts2 status bit r shows the processing field no. bit 3 sync bit s-video y delay bit r 0 : missing synchronization in slave mode. 1 : synchronization was achieved. bit 4 en21 encode21 bit r 0 : wait for the appointed video line to encode. 1 : ready for the c.c. dat a input to the register. bit 5 en284 encode 284 bit r 0 : wait for the appointed video line to encode. 1 : ready for the c.c. dat a input to the register. bit 6 ~ bit 7 reserved reserved bit. r reserved ? status register becomes effectiv e when sync bit turns to ?1?. when in master mode operation, this bit is ?1?. ? sts2-sts2 holds the field number of processi ng. some time lag is inevitable for thei 2 c acquisition. ? closed caption data should be renewed after firm that the en* flag is ?1?. en* flag bit is cleared after the second byte( sub address 17h,19h) was accessed. ? reserved-bit is always value 0. asahikasei [ak8813/14] rev.00 - 44 - 2004/oct device id register (r/w) [address 0x25] sub address 0x25 default value 0x14 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dev7 dev6 dev5 dev4 dev3 dev2 dev1 dev0 default value 0 0 0 1 0 1 0 0 device id register definition bit register name r/w definition bit 0 ~ bit 7 dev0 ~ dev7 device id bit r shows the device id. ?0x13? is assigned for ak8813 . ?0x14? is assigned for ak8814. revision id register (r/w) [address 0x26] sub address 0x26 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 default value 0 0 0 0 0 0 0 0 revision id register definition bit register name r/w definition bit 0 ~ bit 7 rev0 ~ rev7 revision id bit r this value will be modified when the control software has to be modified. shows the revision id. asahikasei [ak8813/14] rev.00 - 45 - 2004/oct system connection example digital 3.3v analog gnd digital gnd a nalog 3.3v amp + lpf 220 ? 75 ? composite - y - c - vrefin iref vrefout d0 - d7 sysclk fid/ vsync hsync sda scl 0.1uf 10uf a vss 6.8k ? mpeg decoder i 2 c bus dvss a vdd dvdd a k8813/14 0.1uf 10uf 0.1uf 10uf asahikasei [ak8813/14] rev.00 - 46 - 2004/oct package 48pin lqfp package & lead frame material package molding compound : epoxy lead frame material : cu lead frame surface treatment : solder plate 1.70 max 1.4 typ 0.13 0.13 0.17 0.08 units = mm 9.0 0.2 9.0 0.2 0.22 0.08 0.5 0.10 m 7.0 1 48 0.5 0.2 0 ? 10 0.10 asahikasei [ak8813/14] rev.00 - 47 - 2004/oct 57pin fbga 5.0 0.1 5.0 0.1 0.5 4.0 = 0.5 8 a b c d e f g 57 ? 0.3 0.05 0.25 0.05 1.00 max h j 9 0.08 s seating plane s 0.05 m a b s 0.20 s b a 0.5 4.0 8 7 6 5 4 3 2 1 package & lead frame material package molding compound: epoxy interposer material: bt resin asahikasei [ak8813/14] rev.00 - 48 - 2004/oct a k8813vq 48pin lqfp (pb free package) 1) asahi kasei logo 2) marketing code : ak8813 3) date code : xxxxxxx (7 digits) 4) pin #1 indication asahikasei [ak8813/14] rev.00 - 49 - 2004/oct 8813 ywwl 8813p ywwl 57pin fbga 1) pin #1 indication 2) marketing code : 8813 3) date code : ywwl (4 digits) y: year ww: week l: lot 57pin fbga (pb free package) 1) pin #1 indication 2) marketing code : 8813p 3) date code : ywwl (4 digits) y: year ww: week l: lot asahikasei [ak8813/14] rev.00 - 50 - 2004/oct a k8814vq 48pin lqfp (pb free package) 1) asahi kasei logo 2) marketing code : ak8814 3) date code : xxxxxxx (7 digits) 4) pin #1 indication asahikasei [ak8813/14] rev.00 - 51 - 2004/oct 8814 ywwl 57pin fbga (pb free package) 1) pin #1 indication 2) marketing code : 8814 3) date code : ywwl (4 digits) y: year ww: week l: lot asahikasei [ak8813/14] rev.00 - 52 - 2004/oct ? these products and their spec ifications are subject to change without notice. befo re considering any use o r application, consult the asahi kasei microsystems co ., ltd. (akm) sales office or authorized distributo r concerning their current status. ? akm assumes no liability for infringement of any patent, in tellectual property, or other right in the application o r use of any information contained herein. ? any export of these products, or dev ices or systems containing them, may require an export license or othe r official approval under the law and regul ations of the country of export pertaining to customs and tariffs, currenc y exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical co mponents in any safety, life support, o r other hazard related device or system, and akm assumes no responsibility re lating to any such use, except with the express written consent of the representative direc tor of akm. as used here: (a) a hazard related device or system is one des igned or intended for life support or maintenance o f safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to resu lt in loss of life or in significant injury o r damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectivene ss of the device or system containing it, and which must t herefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who di stributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akm harmless from an y and all claims arising from the use of said product in the absence of such notification. important notice |
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