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rev. 1.10 S1R72U06 data sheet
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit a nd, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. all brands or product names mentioned herein are tradem arks and/or registered trad emarks of their respective companies. ?seiko epson corporation 2009, all rights reserved.
table of contents 1. overview ....................................................................................................................... 1 2. features ........................................................................................................................ 2 3. block diagram .............................................................................................................. 3 4. functions ...................................................................................................................... 4 4.1 serial i/f (uart/spi) ................................................................................................................. 4 4.2 usb host sie ............................................................................................................................ 4 4.3 usb device sie ......................................................................................................................... 4 4.4 transceiver macro .................................................................................................................... 4 4.5 fifo ........................................................................................................................................... 4 4.6 bridge sequencer ..................................................................................................................... 5 4.7 sio ............................................................................................................................................. 5 4.8 debug i/f ................................................................................................................................... 5 4.9 1.8-v regulator ......................................................................................................................... 5 4.10 3.3-v regulator ......................................................................................................................... 5 4.11 vbus sw ................................................................................................................................... 5 4.12 test circuit ............................................................................................................................... .5 5. pin layout diagram ...................................................................................................... 6 6. pin functions ................................................................................................................ 7 7. commands ...................................................................................................................11 8. electrical characteristics .......................................................................................... 12 8.1 absolute maximum ratings ................................................................................................... 12 8.2 recommended operating conditions ................................................................................... 12 8.3 dc characteristics .................................................................................................................. 13 8.3.1 current consumption ......................................................................................................... 13 8.3.2 input characteristics ........................................................................................................... 14 8.3.3 output characteristics ........................................................................................................ 15 8.3.4 pin capacitance ................................................................................................................. 17 8.3.5 vbus supply function characteristics ................................................................................ 18 8.3.6 fail-safe cell ...................................................................................................................... 19 8.4 ac characteristics .................................................................................................................. 20 8.4.1 power supply input/cutoff timing ........................................................................................ 20 8.4.2 reset timing ....................................................................................................................... 21 8.4.3 clock timing ....................................................................................................................... 21 8.4.4 usb i/f timing ................................................................................................................... 21 8.4.5 serial i/f (main cpu) timing .............................................................................................. 22 8.4.6 serial i/f (history display) timing ........................................................................................ 22 9. connection examples ................................................................................................ 23 10. external dimensions diagrams ............................................................................... 24 10.1 qfp12-48 ............................................................................................................................... .. 24 10.2 qfn7-48 ............................................................................................................................... .... 25 S1R72U06 data sheet seiko epson corporation i (rev. 1.10)
11. product codes .......................................................................................................... 26 revision history ............................................................................................................. 27 ii seiko epson corporation S1R72U06 data sheet (rev. 1.10)
1. overview S1R72U06 data sheet seiko epson corporation 1 (rev. 1.10) 1. overview the S1R72U06 is a serial (uart/spi) - usb 2.0 host/device bridge lsi supporting usb 2.0 fs/ls. the main cpu controls the lsi ? s usb functions using simplified commands. no usb driver is required. the usb classes supported are mass storage class (for usb host ope ration) and human interface device class (for usb host/device operation).
2. features 2. features ? ease of use and easy connections (serial connections) uses simplified commands to control usb functions the main cpu controls this lsi?s usb functions us ing simplified commands. no usb driver needs to be installed. the uart (2-wire asynchronous) or spi (clock sy nchronous) serial interface permits the easy connection of various cpu types. ? built-in regulator usb regulator core voltage regulator the S1R72U06 has two regulators: one (input range: 3.3 to 5.0 v) to generate 3.3 v for the usb and another (input voltage: 3.3 to 5.0 v) to generate the internal core voltage of 1.8 v. this allows the S1R72U06 to operate from a single power source as long as the supplied voltage is at least 3.3 v. ? built-in vbus supply function no external vbus power sw required the S1R72U06 features a built-in vbus supply func tion for usb host operations, eliminating the need for the external vbus power sw previously required by the usb host controller. the S1R72U06 features an interface that controls the external vb us power sw if the built-in vbus supply function cannot supply adequate current. if necessary, connect an external vbus power sw to ensure sufficient current capacity for bus-powered devices. ? product (system) develo pment support function history display the S1R72U06 uses a serial interface (asynchronous type) to display the history of internal lsi processing, etc. this function provides useful information during product (system) development. 2 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
3. block diagram 3. block diagram fifo xreset transceiver macro usb host sie dp dm vbus vbusen osc pll clk test circuit* atpgen vbusflg bridge sequencer serial i/f spixuart sio debug i/f* dbgdclk, dbgdt, dbgst sin0 sout0 xo xi clkin usb device sie clkout tpl sck ss mosi miso sio_ready xirq_event xirq_status vbus sw 3.3v reg. 1.8v reg. vrin vrout_enb vbus_5v_in vbus_out tsten clksel clk_source hostxdevice wakeup init_baud manydev manyhub vbus_cur figure 3.1 block diagram S1R72U06 data sheet seiko epson corporation 3 (rev. 1.10)
4. functions 4. functions 4.1 serial i/f (uart/spi) the S1R72U06 is connected to the main cpu via uart (2-wire asynchronous) or spi (clock synchronous). when using with uart, set the spixuart mode setting pin to low. when using with spi, set the spixuart mode setting pin to high. the interface voltage (cvdd) can be used across a broad range, from 1.8 to 5.0 v. ? uart connection (asynchronous serial i/f) initial baud rate: 300/9600 bps (set by mode setting pin init_baud) baud rate: settable (max. 3 mbps) lsb first 8-bit data 1/2 stop bit odd/even/no parity ? spi connection (clock synchronous serial i/f) spi slave mode 0 (positive pulse latch first) baud rate: max. 6 mbps (sck pin input) msb first 8-bit data 4.2 usb host sie the usb host function complies with the usb 2.0 (universal serial bus specification revision 2.0) standard. it supports fs (12 mbps) and ls (1.5 mbps) speed modes. the usb functions are controlled by the bridge sequencer block inside the lsi. the usb classes suppor ted are the mass storage class and the human interface device class. 4.3 usb device sie the usb device function complies with the usb 2.0 (unive rsal serial bus specification revision 2.0) standard. it supports fs (12 mbps) and ls (1.5 mbps) speed m odes. the usb function is controlled by the bridge sequencer block inside the lsi. the usb class supported is the human interface device class. 4.4 transceiver macro this is a usb analog macro block shared by host and device. 4.5 fifo this fifo block serves as a buffer for data between the serial interface and the usb. 4 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
4. functions 4.6 bridge sequencer this controls the usb functions based on commands from the serial interface. 4.7 sio this block is used to display the history of the product (system) development support functions and for analog tests. 4.8 debug i/f this is a debugging pin for the built-in bridge sequencer. it is not intended for use by the user and should be disregarded. 4.9 1.8-v regulator this regulator generates 1.8-v internal core voltage. the range of input voltages is from 3.3 to 5.0 v. 4.10 3.3-v regulator this regulator generates 3.3 v for the usb. the range of input voltages is from 3.3 to 5.0 v. 4.11 vbus sw this is a vbus output block built into the lsi. 4.12 test circuit this is a circuit for ic tests. it is not intended for use by the user and should be disregarded. S1R72U06 data sheet seiko epson corporation 5 (rev. 1.10)
5. pin layout diagram 5. pin layout diagram 36 35 34 33 32 31 30 29 28 27 26 25 wakeup hostxdev spixuart sck cvdd vss vss lvdd vrin vss vbus_out vbus_5v_in vss vrin uvdd3 vss ss miso xreset mosi xirq_status xirq_event sio_ready 37 atpgen tpl 24 38 init_baud manydev 23 39 clksel manyhub 22 40 clkin vbus_cur 21 41 clk_source 20 42 clkout (nc) 19 43 dbgdt 18 44 tsten dbgst 17 45 vrout_enb dbgdclk 16 46 sin0 15 47 sout0 14 48 vbusen 13 dm dp vbus xi xo vbusflg 123456789101112 figure 5.1 package pin layout diagram (common to qfp and qfn) 6 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
6. pin functions 6. pin functions general (cvdd system) bga qfp name i/o reset pin description - 29 xreset in - reset signal - 39 clksel in - clock frequency selection set the frequency input from the clock source (clkin or xi pin). 1: 24 mhz 0: 12 mhz - 41 clk_source in - clock source selection set whether the clock source is input from the clkin or xi pin. 1: clkin 0: xi - 40 clkin in - clock input 12 mhz / 24mhz if the clock input is from the xi pin, set this pin to low. - 42 clkout out low clock output refer to the S1R72U06 technical manual for information on how to change the clock output. 48 mhz / 24 mhz / 12 mhz / 6 mhz / 3 mhz / stop osc (lvdd system) bga qfp name i/o reset pin description - 10 xi in - internal oscillator circuit input if the clock input is from the clkin pin, set this pin to low. 12 mhz / 24 mhz - 11 xo out - internal oscillator circuit output if the clock input is from the clkin pin, leave this pin open. test (lvdd, cvdd systems) bga qfp name i/o reset pin description - 44 tsten in(pd) - test pin ( * 1); not intended for use by user - 37 atpgen in(pd) - test pin ( * 1); not intended for use by user pd: pull-down i/os are used. * 1 this is pulled down inside the lsi. however, we recommend fixing it at low on the circuit board. usb (uvdd3 system) bga qfp name i/o reset pin description - 9 vbus in - vbus input pin vbus input pin when S1R72U06 is used as usb device. leave this pin open when using S1R72U06 as a usb host. - 8 dp bi hi-z usb data line data+ - 7 dm bi hi-z usb data line data- S1R72U06 data sheet seiko epson corporation 7 (rev. 1.10)
6. pin functions vbus (uvdd3 system) bga qfp name i/o reset pin description - 12 vbusflg in(pu) - usb power switch fault detection signal 1: normal, 0: error cmos schmitt input use when external usb power switch is added. leave open when not used. - 13 vbusen out low usb power switch control signal use when external usb power switch is added. leave open when not used. pu: pull-up i/os are used. serial i/f (cvdd system): main cpu bga qfp name i/o reset pin description - 30 miso tri high serial data output (hi-z is output when the ss pin is set to high even when using in uart mode.) - 28 mosi in - serial data input - 31 ss in - slave selection in spi mode (can be used to control output from the miso pin even when using in uart mode. if hi-z output is not required, fix this pin at low.) - 33 sck in - serial clock in spi mode (fix at low when using in uart mode.) - 25 sio_ready out low communication ready notification pin refer to the S1R72U06 technical manual for detailed instructions on using this pin. leave open when not used. - 27 xirq_status out high status notification refer to the S1R72U06 technical manual for detailed instructions on using this pin. leave open when not used. - 26 xirq_event out high event read request refer to the S1R72U06 technical manual for detailed instructions on using this pin. leave open when not used. serial i/f (uvdd3 system): history display bga qfp name i/o reset pin description - 15 sin0 in - asynchronous serial data in serial data in pin for history display. refer to the S1R72U06 development support manual for specifics of history display. fix at high when not used. - 14 sout0 out high asynchronous serial data out serial data out pin for history display. refer to the S1R72U06 development support manual for specifics of history display. leave open when not used. 8 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
6. pin functions debug i/f (uvdd3 system) bga qfp name i/o reset pin description - 16 dbgdclk out high not used ( * 1) - 18 dbgdt bi(pu) - not used ( * 2) - 17 dbgst out low not used ( * 1) pu: pull-up i/os are used. * 1 leave open. * 2 this is pulled up in the lsi. however, an external pull-up of about 10 k is recommended. gpi (cvdd system) bga qfp name i/o reset pin description - 34 spixuart in - setting pin 0: uart mode 1: spi mode - 35 hostxdevice in - setting pin 1: host mode, 0: device mode switching modes resets the lsi. - 36 wakeup in - wake-up pin used to resume from sleep state. rising edge activates the wake-up trigger. - 38 init_baud in - initial baud rate setting pin 1: 9600bps 0: 300bps uart baud rate can be set to between 300 bps and 3 mbps using the serial po rt setting. refer to the S1R72U06 technical manual for detailed instructions on making serial port settings. gpo (cvdd system) bga qfp name i/o reset pin description - 24 tpl out low unsupported device 1: error, 0: - used for usb compliance testing. leave open when not used. - 23 manydev out low too many devices 1: error, 0: - used for usb compliance testing. leave open when not used. - 22 manyhub out low too many hubs 1: error, 0: - used for usb compliance testing. leave open when not used. - 21 vbus_cur out low vbus over current 1: error, 0: - used for usb compliance testing. leave open when not used. S1R72U06 data sheet seiko epson corporation 9 (rev. 1.10)
6. pin functions regulator (vrin system) bga qfp name i/o reset pin description - 4, 47 vrin power - regulator input connect cin = 1.0 f to each pin. make sure to keep this open when not using the regulator. - 45 vrout_enb in - enables the regulator set this to the same leve l as vrin when using the regulator. make sure to se t this to low when not using the regulator. vbus sw (vbus_5v_in system) bga qfp name i/o reset pin description - 2 vbus_5v_in power - vbus generation input voltage input pin for built-in vbus supply function. the power supply (vswin in 8.3.5) should be provided even when this function is not used. - 1 vbus_out power - vbus output vbus output pin for built-in vbus supply function. leave open when this function will not be used. power bga qfp name voltage pin description - 5 uvdd3 3.3v power supply for usb when using regulator: connect cout = 1.0 f. when not using regulator: apply the voltage indicated to the left. - 46 lvdd 1.8v internal power supply, test power supply, osc power supply when using regulator: connect cout = 1.0 f. when not using regulator: apply the voltage indicated to the left. - 32 cvdd 1.8 to 5.0v power supply for main cpu i/f - 3, 6, 20, 43, 48 vss 0v gnd 10 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
7. commands 7. commands communication with the main cpu is implemented via commands. for detailed information on commands, refer to the S1R72U06 uart interface manual and the S1R72U06 spi interface manual . S1R72U06 data sheet seiko epson corporation 11 (rev. 1.10)
8. electrical characteristics 8. electrical characteristics 8.1 absolute maximum ratings item code rating unit cvdd vrin ( * 1) -0.3 to 7.0 v uvdd3 -0.3 to 4.0 v power supply voltage lvdd ( * 2) -0.3 to 2.5 v vi ( * 3) -0.3 to cvdd+0.5 -0.3 to uvdd3+0.5 -0.3 to lvdd+0.5 v input voltage vbus_5v_in -0.3 to 7.0 v vo ( * 3) -0.3 to cvdd+0.5 -0.3 to uvdd3+0.5 -0.3 to lvdd+0.5 v output voltage vbus_out vbus_5v_in+0.3 v output current/pin iout 10 ma storage temperature tstg -65 to 150 c * 1 vrin uvdd3, vrin lvdd * 2 cvdd, uvdd3 lvdd * 3 power supply voltages 8.2 recommended operating conditions item code min. typ. max. uni cvdd 1.65 1.80 to 5.00 5.50 v vrin 3.00 3.30 to 5.00 5.50 v uvdd3 3.00 3.30 3.60 v power supply voltage lvdd 1.65 1.80 1.95 v input voltage vi ( * ) -0.3 - cvdd+0.3 uvdd3+0.3 lvdd+0.3 v ambient temperature t a -40 25 85 c * power supply voltages for each pin [precautions for power on sequence] be careful of the power supply timing when providing an external power supply without using a built-in regulator. refer to ?8.4.1 power su pply input/cutoff timing? for more information. 12 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
8. electrical characteristics 8.3 dc characteristics 8.3.1 current consumption item code condition min. typ. max. unit power supply current ( * 1) power supply current iddh0 cvdd = 5.5v - 5 - ma iddh1 uvdd3 = 3.6v - 5 * 2 - ma iddl lvdd = 1.95v - 25 * 2 - ma iddr vrin = 5.5v - 30 * 3 - ma power supply current (static current) ( * 4) power supply current idds max. condition of each power supply fixed to power supply or gnd - 50 - a input leak input leakage current il max. condition of each power supply -5 - 5 a * 1 at recommended operating conditions (t a = 25c). operating current for seiko ep son evaluation board configuration. * 2 operating current for seiko epson evaluat ion board configuration with external power supply and no built-in regulator. * 3 operating current for seiko epson evaluation board configuration with built-in regulator. * 4 static current when ta = 25 c and when using regulator. S1R72U06 data sheet seiko epson corporation 13 (rev. 1.10)
8. electrical characteristics 8.3.2 input characteristics item code condition min. typ. max. unit input characteristics pin: lvdd-system pin ?h? level input voltage vih1 lvdd = 1.95v 1.27 - - v ?l? level input voltage vil1 lvdd = 1.65v - - 0.57 v input characteristics (schmitt) pin: cvdd- and uvdd3-system pin ?h? level trigger voltage vt1+ cvdd = 5.5v cvdd = 3.6v cvdd = 1.95v uvdd3 = 3.6v - - 4.00 2.52 1.36 2.52 v ?l? level trigger voltage vt1- cvdd = 4.5v cvdd = 3.0v cvdd = 1.65v uvdd3 = 3.0v 0.80 0.75 0.42 0.75 - - v hysteresis voltage v1 cvdd = 4.5v cvdd = 3.0v cvdd = 1.65v uvdd3 = 3.0v 0.30 0.30 0.17 0.30 - - v schmitt input characteristics (usb: fs) pin: dp, dm ?h? level trigger voltage vtu+ uvdd3 = 3.6v - - 2.0 v ?l? level trigger voltage vtu- uvdd3 = 3.0v 0.8 - - v input characteristics (usb: fs differential input) pin: dp, dm pair differential input sensitivity vdsu uvdd3 = 3.0v differential input voltage: 0.8 to 2.5 v 0.2 - - v input characteristics pin: vbusflg, dbgdt pull-up resistance rplu vi = 0v ( vdd3 = 3.0v) 52 160 384 k input characteristics pin: atpgen pull-down resistance rpld vi = cvdd cvdd = 4.5v vi = cvdd cvdd = 3.0v vi = cvdd cvdd = 1.65v 32 52 200 100 160 600 240 384 1440 k input characteristics pin: tsten pull-down resistance rpldl vi = lvdd (lvdd = 1.65v) 40 120 288 k input characteristics pin name: vbus pull-down resistance rpldb vi = 5.0v 100 125 165 k 14 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
8. electrical characteristics 8.3.3 output characteristics (v ss =0v) item code condition min. typ. max. unit output characteristics pin: sio_ready, xirq _event, xirq_status, tpl, manydev, manyhub, vbus_cur, vbusen ?h? level output voltage voh1 cvdd = 4.5v (ioh = -2.0ma) cvdd = 3.0v (ioh = -1.4ma) cvdd = 1.65v (ioh = -0.6ma) uvdd3 = 3.0v (ioh = -1.4ma) cvdd ? 0.4 cvdd ? 0.4 cvdd ? 0.4 uvdd3 ? 0.4 - - v ?l? level output voltage vol1 cvdd = 4.5v (ioh = 2.0ma) cvdd = 3.0v (ioh = 1.4ma) cvdd = 1.65v (ioh = 0.6ma) uvdd3 = 3.0v (ioh = 1.4ma) - - 0.4 0.4 0.4 0.4 v output characteristics pi n: miso, sout0, clkout ?h? level output voltage voh2 cvdd = 4.5v (ioh = -4.0ma) cvdd = 3.0v (ioh = -2.8ma) cvdd = 1.65v (ioh = -1.2ma) uvdd3 = 3.0v (ioh = -2.8ma) cvdd ? 0.4 cvdd ? 0.4 cvdd ? 0.4 uvdd3 ? 0.4 - - v ?l? level output voltage vol2 cvdd = 4.5v (ioh = 4.0ma) cvdd = 3.0v (ioh = 2.8ma) cvdd = 1.65v (ioh = 1.2ma) uvdd3 = 3.0v (ioh = 2.8ma) - - 0.4 0.4 0.4 0.4 v output characteristics (usb: fs) pin: dp, dm ?h? level output voltage vohuf uvdd3 = 3.0v 2.8 - - v ?l? level output voltage voluf uvdd3 = 3.6v - - 0.3 v output characteristics pin: cvdd-system pin off-state leakage current ioz cvdd = 5.5v voh = cvdd vol = vss -5 - 5 a S1R72U06 data sheet seiko epson corporation 15 (rev. 1.10)
8. electrical characteristics { fmax-cl type1a: sio_ready, xirq_event, xirq_status, tpl, manydev, manyhub, vbus_cur, vbusen type2a: miso, sout0, clkout ? using 5.0 v io voltage (rev. 1.10) ? using 3.3 v io voltage ? using 1.8 v io voltage i/o ? (cvdd=1.65v , 125 , model slow ) 1 10 100 1000 0 50 100 150 200 250 fmax (mhz) ? (pf) type1a type2a i/o ? (cvdd=1.8v , 25 , model typ) 1 10 100 0 50 100 150 200 250 fmax (mhz) ? (pf) type1a type2a load capacity (pf) maximum i/o output frequency load capacity (pf) maximum i/o output frequency i/o ? (cvdd/uvdd3=3.0v , 125 , model slow) 1 10 100 1000 0 50 100 150 200 250 fmax (mhz) ? (pf) type1a type2a i/o ? (cvdd/ uvdd3= 3. 3v , 25 , model typ) 1 10 100 1000 0 50 100 150 200 250 ? (pf) fmax (mhz) type1a type2a load capacity (pf) maximum i/o output frequency load capacity (pf) maximum i/o output frequency i/o ? (cvdd=4.5v , 125 , model slow ) 1 10 100 1000 0 50 100 150 200 250 fmax (mhz) ? (pf) type1a type2a i/o ? (cvdd=5.0v , 25 , model typ) 1 10 100 1000 0 50 100 150 200 250 fmax (mhz) ? (pf) type1a type2a load capacity (pf) maximum i/o output frequency maximum i/o output frequency load capacity (pf) 16 seiko epson corporation S1R72U06 data sheet
8. electrical characteristics 8.3.4 pin capacitance item code condition min. typ. max. unit pin capacitance pin name: all input pins input pin capacitance ci f = 1mhz - - 8 pf pin capacitance pin name: all output pins output pin capacitance co f = 1mhz - - 8 pf pin capacitance pin name: all output pins except dp and dm input/output pin capacitance cb f = 1mhz - - 8 pf pin capacitance pin name: dp, dm input/output pin capacitance (usb) cbu f = 1mhz - - 15 pf S1R72U06 data sheet seiko epson corporation 17 (rev. 1.10)
8. electrical characteristics 8.3.5 vbus supply func tion characteristics item code condition min. typ. max. unit input voltage vswin 3.0 5.0 5.5 v on resistance rswon vbus_5v_in = 5.0v vbus_5v_in = 3.0v - 2.4 3.5 4.0 - off leakage current iswoff vbus_5v_in = 5.0v vbus_5v_in = 3.0v - 10 10 100 100 na overcurrent detection iswlmt vbus_5v_in = 5.0v vbus_5v_in = 3.0v 21 - 26 17 35 - ma overcurrent response time tswoff overcurrent vbus off 300 s 18 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
8. electrical characteristics 8.3.6 fail-safe cell the S1R72U06 uses fail-safe cells for certain pins . fail-safe cells have the following advantages: ? they prevent input leakage currents when a power supply is applied to input pins or input/output pins in the input state, even if the signal input exceeds the power supply voltage. (note that a leakage current of approximately 30 a will occur for pins with pull-up resistance.) ? no input leakage current occurs when the power supply is cu t off, even when an external input signal is applied. note that while signals with a voltage level exceeding th e operating voltage can be received, the signal voltage that can be applied to the fail-safe cell cannot exceed the absolute maximum rating. miso, mosi, sck, ss, sio_ready, xirq_eve nt, xirq_status, spixuart, hostxdevice, wakeup, init_baud, tpl, manydev, manyhub, vbus_cur, sin0, sout0, vbusflg, vbusen, clkout, clkin, clk_source, clksel, db gdclk, dbgdt, dbgst, xreset, atpgen S1R72U06 data sheet seiko epson corporation 19 (rev. 1.10)
8. electrical characteristics 8.4 ac characteristics 8.4.1 power supply input/cutoff timing a. power supply input/ cutoff timing (for lvdd hvdd / hvdd lvdd: recommended conditions) timing parameters voltage parameters item code min. typ. max. unit hvdd power supply input timing tlhh 0 - 10 sec hvdd cutoff timing thll 0 - 10 sec item code input cutoff unit lvdd initial voltage v_lvdd lvdd_min lvdd_min v hvdd initial voltage v_hvdd hvdd_min hvdd_min v voltage conditions b. power supply input/cutoff timing (for hvdd lvdd / lvdd hvdd) timing parameters voltage parameters item code min. typ. max. unit lvdd power supply input timing tlhh 0 - 1 sec lvdd cutoff timing thll 0 - 1 sec item code input cutoff unit lvdd initial voltage v_lvdd lvdd_min lvdd_min v hvdd initial voltage v_hvdd 0.1 0.1 v voltage conditions * hvdd refers to usb uvdd3 or interface cvdd. * for lvdd hvdd timing, refer to a for input and b for cutoff. for hvdd lvdd timing, refer to b for input and a for cutoff. ? ? ? ? ? timing diagram lvdd hvdd( * ) v_lvdd v_hvdd tlhh thll timing diagram hvdd( * ) lvdd v_hvdd v_lvdd tlhh thll 20 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
8. electrical characteristics 8.4.2 reset timing code description min typ max unit treset reset pulse width 40 - - ns xreset treset 8.4.3 clock timing code description min. typ. max. unit tcyc clock cycle (clksel = "l") - 12.000 - mhz tcyc clock cycle (clksel = "h") - 24.000 - mhz tcycl tcych clock duty 45 50 55 % xi, clkin tcycl tcych tcyc * the clock source selected must satisfy the accuracy requirements under usb standards. fs: 2,500 ppm, ls: 15,000 ppm 8.4.4 usb i/f timing complies with usb 2.0 (universal serial bus specification revision 2.0) standard. S1R72U06 data sheet seiko epson corporation 21 (rev. 1.10)
8. electrical characteristics 8.4.5 serial i/f (main cpu) timing code description min. typ. max. unit tbrm baud rate 300 - 3m bps mosi/miso tbrm b0 b1 b2 b3 b4 b5 b6 b7 in uart operation code description min. typ. max. unit tchw in spi operation sck ss miso mosi b7 tclw tccy b7 b6 b6 b0 b0 b1 b1 tccy clock cycle - - 6m hz trdd t r d h trbh twdh twds tchw clock high width 50 - - ns tclw clock low width 50 - - ns trdd data output start delay 2 - 20 ns trdh data output switchover delay - - 35 ns trbh data output hold - - 20 ns twds received data setup 10 - - ns twdh received data hold 5 - - ns 8.4.6 serial i/f (history display) timing code description min. typ. max. unit tbrh baud rate - 38400 - bps sin0/sout0 tbrh b0 b1 b2 b3 b4 b5 b6 b7 22 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
9. connection examples 9. connection examples refer to the S1R72U06 evaluation board manual . S1R72U06 data sheet seiko epson corporation 23 (rev. 1.10)
10. external dimensions diagrams 10. external dimensions diagrams 10.1 qfp12-48 24 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
10. external dimensions diagrams 10.2 qfn7-48 S1R72U06 data sheet seiko epson corporation 25 (rev. 1.10)
11. product codes 11. product codes product code description S1R72U06f12e100 qfp12-48 package S1R72U06f07e100 qfn7-48 package 26 seiko epson corporation S1R72U06 data sheet (rev. 1.10)
revision history revision history attachment-1 rev. no. date page category contents rev.1.00 06/05/2009 all pages new newly established p8 amend amend i/o and processing method when function is not used before : in(pu) leave open after : in fix at high rev.1.10 09/07/2009 p14 remove remove sin0 pin from the object of rplu S1R72U06 data sheet seiko epson corporation 27 (rev. 1.10)
international sales operations america epson electronics america, inc. 2580 orchard parkway, san jose, ca 95131, usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15, 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg., no.89 jinbao st., dongcheng district, beijing 100005, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, block b, hi-tech bldg., 900 yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 shenzhen branch 12f, dawning mansion, keji south 12th road, hi-tech park, shenzhen 518057, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson hong kong ltd. 20/f, harbour centre, 25 harbour road, wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110, taiwan phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corp. korea office 50f, kli 63 bldg., 60 yoido-dong, youngdeungpo-ku, seoul 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 seiko epson corp. semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 411682202 first issue june 2009 revised september 2009 in japan d

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