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4 GL800HT25 usb 2.0 utmi compliant transceiver ip core datasheet revision 1.30 nov. 28, 2002 genesys logic, inc.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 2 copyright: copyright ? 2003 genesys logic incorporated. all rights reserved. no part of the materials may be reproduced in any form or by any means without prior written consent of genesys logic inc.. disclaimer: all materials are provided "as is" without express or implied warranty of any kind. no license or right is granted under any patent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all warranties, implied or express, of merchantability, fitness for any particular purpose, and non-infringement of intellectual property. in no event shall genesys logic be liable for any damages including, without limitation, damages resulting from loss of information or profits. please be advised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products described therein at any time without notice. trademarks: is a registrated trademark of genesys logic inc.. all trademarks are the proper ties of their respective owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http://www.genesyslogic.com
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 3 revision history revision date description 1.0 02/22/2002 first draft release 1.1 06/21/2002 1. remove optional output signals in sec.vii. 2. add testing circuit in sec.ix. 3. add ix.6 application circuit for tester. 1.2 07/10/2002 modify vii.2 interf ace port description. (1) pad descriptions are se parated from interface signals. (2) use the same pad names and pad order as layout. (3) add description for bonding options. 1.21 07/16/2002 1. insert table for operation mode in sec ix.2 2. add some description on analogue test. 1.22 07/29/2002 1. insert table for pin description while in testing. 2. add some description on analogue test. 3. more description on layout guide. 1.23 08/02/2002 1. revert figure 7.3 horizontally. 2. clkout -> clk30. 1.24 08/12/2002 re-organize layout recommendation 1.30 11/28/2002 modify pin description of dvdd1 of test sample.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 4 table of contents chapter 1 general description........................................................................ 6 chapter 2 features ................................................................................................... 7 chapter 3 block diagram..................................................................................... 8 3.1 s ystem c onfiguration .............................................................................................. 8 3.2 b lock d iagram ........................................................................................................... 9 chapter 4 pin assignment.................................................................................... 11 4.1 p inouts ....................................................................................................................... 11 4.2 p in l ist ........................................................................................................................ 12 4.3 p in d escriptions ....................................................................................................... 12 chapter 5 functional description............................................................... 15 5.1 t ransmit o peration ................................................................................................ 15 5.1.1 transmit state diagram..................................................................................... 15 5.1.2 transmit timing for data packet ..................................................................... 16 5.2 r eceive o peration .................................................................................................. 16 5.2.1 receive state diagram ....................................................................................... 16 5.2.2 receive timing for data packet (with crc-16).............................................. 17 5.3 t iming c hart ............................................................................................................ 18 5.3.1 clk30 rising and falling edge vs. input/output signals ........................... 18 5.3.2 relationship between mode chan ge and other input signals ...................... 19 chapter 6 package dimension.......................................................................... 20
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 5 list of figures f igure 3.1 - s ystem d iagram ......................................................................................... 8 f igure 3.2 - b lock d iagram ........................................................................................... 9 f igure 4.1 - p inout d iagram ........................................................................................ 11 f igure 5.1 - t ransmit s tate d iagram ........................................................................ 15 f igure 5.2 - t iming d iagram of t ransmit for d ata p acket ................................ 16 f igure 5.3 - r eceive s tate d iagram .......................................................................... 16 f igure 5.4 - t iming d iagram of r eceive for d ata p acket ( with crc-16) ....... 17 f igure 5.5 - clk30 r ising and f alling e dge vs. i nput /o utput s ignals ........... 18 f igure 5.6 - r elationship b etween m ode c hange and o ther i nput s ignals .. 19 f igure 6.1 - GL800HT25 48 p in lqfp p ackage ........................................................ 20 list of tables t able 4.1 - p in l ist ......................................................................................................... 12 t able 4.2 - p in d escriptions ......................................................................................... 12
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 6 chapter 1 general description GL800HT25 is a high performance usb 2.0 transceiver compliant with the utmi (usb 2.0 transceiver macrocell interface) specifica tion proposed by intel. the utmi specifi cation defines a standard interface to usb 2.0 high-speed transceivers that enables common design across prototype and production implementations. the GL800HT25 integrates high-speed , mixed-signal circuitry to serve as the interface between the high performance usb serial bus and the 16-bit sie bus. the transceiver is controlled by input signals from the sie bus, which is synchronized with the 30mhz clock output. the utmi transceiver handles the low level usb protocol and signaling. this includes features such as: data serialization and deserialization, bit stuffing and clock recovery and synchronization. the primary focus of the utmi transceiver is to shift the clock domain of the data from the usb 2.0 rate to one that is compatible with the general logic. to eliminate the difficult high-speed, mixed-signal usb 2.0 logic design for system and peripheral developers, the GL800HT25 with standard utmi and 40x improvement in data rate can be easily adapted for implementation of usb 2.0 high speed compliant design of widely applications, including scanners, printers, portable storage, external cd-rom / cd-rw / dvd-rom , flash card readers, and pc cameras. the ip block now is certified and available on the 0.35m umc stan dard cmos process; and it is also scheduled for 0.25m tsmc standard cmos process in 3q?02.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 7 chapter 2 features complies with universal serial bus specification rev. 2.0. complies with usb 2.0 transceiver m acrocell interface (utmi) specification. supports 480 mbit/s "high speed" (hs) / 12 mbit/s ?ful l speed? (fs), fs only se rial data transmission rates. 16 bit bi-directional serial interface engine (sie) bus. sync/eop generation and checking. supports ?chirp? for high speed recognition. data and clock recovery from serial stream on the usb. bit-stuffing / unstuffing; bit stuff error detection. holding registers to stage transmit and receive data. supports reset and suspend. single parallel data clock output with on-chip pll to generate higher speed serial data clocks. available in 48 pin lqfp package or ip macrocell on the 0.35m umc / 0.25m tsmc standard cmos processes.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 8 chapter 3 block diagram 3.1 system configuration utmi sie (serial interface engine) device specific logic gl800 usb 2.0 transceiver macrocell interface usb 2.0 figure 3.1 - system diagram 1. GL800HT25 the usb 2.0 utmi transceiver, which handles the low level usb protocol and signaling, and shifts the clock domain of the data from the usb 2.0 rate to one that is compatible with the general logic. 2. serial interface engine the serial interface engine can be fu rther sub-divided into 2 types of su b-blocks; the sie control logic and the endpoint logic. the sie control logic contains the usb pid and address recognition logic, and other sequencing and state machine logic to handle usb p ackets and transactions. the endpoint logic contains the endpoint specific logic: e ndpoint number recognition, fifo s and fifo control, etc. sie logic module can be developed by peripheral vendors or purchased from ip vendors. the standardization of the utmi allows multiple sour ces of sie logic to connect with GL800HT25 to implement the usb 2.0 high-speed design. 3. device specific logic this block is the glue that ties the usb inte rface to the specific application of the device.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 9 3.2 block diagram hs dll elasticity buffer m u x nrzi decoder bit unstuffer rcv status/ control xmit hs xcvr rx register parallel rx data receive state machine transmit state machine tx register parallel tx data bit stuffer nrzi encoder clock multiplier control logic control clk external crystal fs dll & data recovery rcv status/ control xmit fs xcvr data+ data- analog front end figure 3.2 - block diagram 1. hs xcvr hs xcvr contains the low-level analog circuitry requi red to physically interface usb 2.0 signaling to the usb dp/dm signal lines. 2. fs xcvr fs xcvr includes the logic necessary to send and receive the fs data on usb. 3. clock multiplier clock multiplier generates the internal clocks for the GL800HT25 usb 2.0 tr ansceiver and the clk30 signal. all data transfer signals are synchronized with the clk30 signal. in hs mode there is one clock cycle per byte time. the frequency of clock does not change when the utmi is switched between hs to fs modes. in fs mode th ere are 5 clock cycles per fs bit time, typically 40 clock cycles per fs byte time. if a received byte co ntains a stuffed bit then the byte boundary can be stretched to 45 clock cycles, and two stuffed bits would result in a 50 clock delay between bytes. 4. hs dll (high speed delay line pll) dll extracts clock and data from the data received ove r the usb 2.0 interface for reception by the receive deserializer. the data output from the dll is synchronous with the local clock.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 10 5. elasticity buffer elasticity buffer is used to compensate for differe nce between transmitting a nd receiving clocks. the usb specification defines a maximum clock error of +/- 500 ppm. when the error is cal culated over the maximum packet size up to +/- 12 bits of drift can occur. the elas ticity buffer is filled to a threshold prior to enabling the remainder of the down st ream receive logic. overview and underflow conditions detected in the elasticity buffer can be reported with the rxerr signal. 6. mux the mux block allows the data from the hs or fs receive rs to be routed to the shared receive logic. the state of the mux is determined by the fspeed input. 7. nrzi decoder the nrzi decoder is compliant to standard usb 1.x specification, and it can operate at fs and hs data rates. 8. bit unstuffer the bit unstuffer is compliant to standard usb 1.x specification, and it can operate at fs and hs data rates. the bit unstuffer is a state machine, which strips a st uffed 0 bit from the data stream and detects bit stuff errors. in fs mode bit stuff errors asserts the rxerr signal. in hs mode bit stuff errors are used to generate the eop signal so the rxerr signal is not asserted. 9. rx register rx register is in charge of converting seri al data received from the usb to parallel data. 10. receive state machine the behavior of the receive state machine is described at chapter 6, function description. 11. nrzi encoder the nrzi encoder is compliant to standard usb 1.x specification, and it can operate at fs and hs data rates. 12. bit stuffer bit stuffer is used by insert a zero af ter every six consecutive ones in the data stream before the data is nrzi encoded in order to ensure adequate signal transitions. bit stuffing is enabled beginning with the sync pattern and through the entire transmission. the data ?one? that ends the sync pattern is counted as the first one in a sequence. in fs mode bit stuffing by the transmitter is always enfo rced, without exception. if required by the bit stuffing rules, a zero bit is inserted even after the last bit before the txvld signal is negated. after 8 bits are stuffed into the usb data stream txrd y is negated for one byte time to hold up the data stream on the data bus. 13. tx register tx register is in charge of reading parallel data from the parallel applicati on bus interface upon command and serializing for transmission over usb. 14. transmit state machine the behavior of the transmit state machine is described at chapter 6, function description.
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 11 chapter 4 pin assignment 4.1 pinouts GL800HT25 lqfp - 48 fspeed 1 hrst#/advdd 2 hsterm# 3 suspnd# 4 rpu 5 avdd0 6 dpf 7 dph 8 dmf 9 dmh 10 agnd0 11 rref 12 d7 d6 d5 d4 dgnd0 dvdd0 d3 d2 d1 d0 txrdy validh 36 35 34 33 32 31 30 29 28 27 26 25 d8 37 d9 38 d10 39 d11 40 dvdd1 41 dgnd1 42 d12 43 d13 44 d14 45 d15 46 linest1 47 linest0 48 txvld clkout rxvld rxerr rxactv opmod0 opmod1 test0 agnd1 xi xo avdd1 24 23 22 21 20 19 18 17 16 15 14 13 figure 4.1 - pinout diagram
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 12 4.2 pin list table 4.1 - pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 fspeed i 13 avdd1 p 25 validh b 37 d8 b 2 hrst# i 148 xo b 26 txrdy o 38 d9 b 3 hsterm# i 15 xi i 27 d0 b 39 d10 b 4 suspnd# i 16 agnd1 p 28 d1 b 40 d11 b 5 rpu - 17 test0 i 29 d2 b 41 dvdd1 p 6 avdd0 p 18 opmod1 i 30 d3 b 42 dgnd1 p 7 dpf b 19 opmod0 i 31 dvdd0 p 43 d12 b 8 dph b 20 rxactv o 32 dgnd0 p 44 d13 b 9 dmf b 21 rxerr o 33 d4 b 45 d14 b 10 dmh b 22 rxvld o 34 d5 b 46 d15 b 11 agnd0 p 23 clkout o 35 d6 b 47 linest1 o 12 rref - 24 txvld i 36 d7 b 48 linest2 o 4.3 pin descriptions table 4.2 - pin descriptions pin name pin# type description fspeed 1 i (pu) transceiver select. this signal selects between the fs and hs transceivers: 0: high speed transceiver enabled 1: full speed transceiver enabled hrst# / advdd 2 i (pu) umc 0.35um sample: reset. chip reset input, active low. this signal is used to reset all state machines in the GL800HT25. tsmc 0.25um sample: this pin should be digital 2.5v power for transceiver. hsterm# 3 i (pu) termination select. hs termination enable, active low suspnd# 4 i (pd) suspend mode enable, active low. this signal places the GL800HT25 in a mode that draws minimal power from supplies. shuts down all blocks not necessary for suspend/resume operation. while suspended, hsterm# must always be disabled (fs mode) to ensure that the 1.5k pull-up on dp remains powered. rpu 5 - 3.3v pull up control for dpf avdd0~1 6,13 p positive analog supply (3.3v) dpf 7 b positive usb differential data (full speed) dph 8 b positive usb differential data (high speed) dmf 9 b negative usb differential data (full speed)
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 13 dmh 10 b negative usb differential data (high speed) agnd0~1 11,16 p analog ground (0v) rref 12 - 510 ? reference resistor input xo 14 b crystal output xi 15 i 12mhz crystal/oscillator input test0 17 i (pd) test mode enable opmod1 18 i (pu) opmod0 19 i (pd) operational mode. these signals select between various operational modes: [1] [0] description 0 0 0: normal operation 0 1 1: non-driving 1 0 2: disable bit stuffing and nrzi encoding 1 1 3: reserved rxactv 20 o receive active, active high. indi cates that the receive state machine has detected sync and is active. rxactv is negated after a bit stuff error or an eop is detected. in hs mode, rxactv must be negated no less than 3 and no more than 8 clks after an idle state is detected on the usb. and rxactv must be negated for at least 1 clk between consecutive received packets. in fs/fs only modes, rxactv must be negated no more than 2 clks after a fs idle state is de tected on the usb. and rxactv must be negated for at least 4 clks between consecutive received packets. rxerr 21 o receive error, active high. 0: indicates no error. 1: indicates that a receive error has been detected. this output is clocked with the same timing as the data lines and can occur at anytime during a transfer. if asserted, it will force the negation of rxvld on the next rising edge of clk30. rxvld 22 o receive data valid, active high. i ndicates that the data bus has valid data. the rx register is full and ready to be unloaded. the sie is expected to latch the data bus on the clock edge. clkout 23 o clock. this 30mhz clock output is used for clocking receive and transmit hs/fs 16-bit parallel data. txvld 24 i transmit valid, active high. indicates that the data bus is valid. the assertion of transmit valid initiates sync on the usb. the negation of transmit valid initiates eop on the usb. in hs mode, the sync pattern must be asserted on the usb between 8 and 16 bit times after the assertion of txvld is detected by the transmit state machine. in fs/ fs only modes, the sync pattern must be asserted on the usb no less than 1 clk and no more than 5 clks after the assertion of txvld is detected by the transmit state machine. validh 25 b transmit/receive valid high, active high. txrdy 26 o transmit data ready, active high. if txvld is asserted, the sie must always have data available for clocking in to the tx register on the rising edge of clk30. if txvld is true and txrdy is asserted at the rising edge of clk30, the GL800HT25 will load the data on the data bus into the tx register on the next rising ed g e of clk30, at that time, sie should immediatel y p resen t the
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 14 data for next transfer on the data bus. if txvld is asserted and txrdy is negated, the sie must hold the previously asserted data on the data bus. from the time txvld is negated, txrdy is a don?t care for the sie. d0~d15 27~30, 33~40, 43~46 b data bus 0~15 dvdd0 31 p positive digital supply (3.3v) dvdd1 41 p positive digital supply umc 0.35um sample : 3.3v tsmc 0.25um sample : 2.5v dgnd0~1 32,42 p digital ground (0v) linest1 47 o linest0 48 o line state. these signals reflect the current state of the single ended receivers. they are combin atorial until a ?usable? clk30 is available then they are synchroni zed to clk30. they directly reflect the current state of th e dp (linestate[0]) and dm (linestate[1]) signals: dm dp description 0 1 0: se0 0 1 1: ?j? state 1 0 2: ?k? state 1 1 3: se1 notation: type o output i input b bi-directional b/i bi-directional, default input b/o bi-directional, default output p power / ground a analog so automatic output low when suspend pu internal pull up pd internal pull down odpu open drain with internal pull up
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 15 chapter 5 functional description 5.1 transmit operation 5.1.1 transmit state diagram figure 5.1 - transmit state diagram transmit must be asserted to enable any transmissions. the sie asserts txvld to begin a transmission. the sie negates txvld to end a transmission. after the sie asserts txvld it can assume that the transmission has started when it detects txrdy asserted. the sie assumes that the utm has consumed a data byte if txrdy and txvld are asserted. the sie must have valid packet information (pid) asse rted on the data bus coincident with the assertion of txvld. depending on the utm implementation, txrdy may be asserted by the transmit state machine as soon as one clk after the assertion of txvld. txvld and txrdy are sampled on the rising edge of clk30. the transmit state machine does not automatically generate packet id?s (pids) or crc. when transmitting, the sie is always expected to present a pid as the first byte of the data stream and if appropriate, crc as the last bytes of the data stream. the sie must use linest0/1 to verify a bus idle condition before asserting txvld in the tx wait state. reset !txrdy tx wait send sync tx data load txrdy tx data wait !txrdy send eop !txrdy hrst# !hrst# txvld !txvld tx hold reg empty tx hold reg full tx hold reg empty tx hold reg full eop not done !txvld
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 16 5.1.2 transmit timing for data packet figure 5.2 - timing diagram of transmit for data packet the sie negates txvld to complete a packet. once nega ted, the transmit state machine will never reassert txrdy until after the eop has been loaded into the tr ansmit shift register. note that the utm transmit state machine can be ready to start another package immediately, however the sie must confirm to the minimum inter-packet delays identified in the usb 2.0 specification. 5.2 receive operation 5.2.1 receive state diagram figure 5.3 - receive state diagram data data data data crc crc pid sync pid data data data data crc c crc c eop p clk30 txvld data txrdy dp/dm reset !rxactv !rxvld rx wait trip sync rxactv rx data rxvld rx data wait !rxvld strip eop !rxactv !rxvld hrst# !hrst# sync detected data !data !sync sync data data abort 1 !rxactv !rxvld !rxerr terminate !rxactv abort 2 !rxvld !rxerr error rxerr eop detected !data receive error !idle state idle state
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 17 rxactv and rxvld are sampled on the rising edge of clk30. in the rx wait state the receive r is always looking for sync. the macrocell asserts rxactv when sync is detected (strip sync state). the macrocell negates rxactv when an eop is detected (strip eop state). when rxactv is asserted, rxvld will be asserted if the rx holding register is full. rxvld will be negated if the rx holding register was not loaded during the previous byte time. this will occur if 8 stuffed bits have been accumulated. the sie must be ready to consume a data byte if rxactv and rxvld are a sserted (rx data state). in fs mode, if a bit stuff error is detected then the receive state machine will negate rxactv and rxvld, and return to the rxwait state. 5.2.2 receive timing for data packet (with crc-16) figure 5.4 - timing diagram of receive for data packet (with crc-16) note that the usb 2.0 transceiver does not decode pa cket id?s (pids). they are passed to the sie for decoding. this timing example is in hs mode. when a hs/fs ut m is in fs mode there are approximately 40 clock cycles every byte time. the receive st ate machine assumes that the sie capt ures the data on the data bus if rxactv and rxvld are asserted. in fs mode, rxvld will only be asserted for one clock per byte time. note that the receive and transmit sections of the tr ansceiver operate independently. the receiver will receive any packets on the usb. the transceiver does not identif y whether the packet that it is receiving from the upstream or the downstream port. the sie must ignore receive data while it is transmitting. data data data data crc crc pid sync pid data data data data crc crc eop clk30 rxactv data rxvld rxerr dp/dm
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 18 5.3 timing chart 5.3.1 clk30 rising and falling edge vs. input/output signals * output signals includes txrdy, rxactv, rxerr, rxvld, linest[1:0], d[15:0] ** input signals includes txvld, validh figure 5.5 - clk30 rising and falling edge vs. input/output signals max. min. unit t1 8 - ns t2 3 - ns t3 - 8 ns t1 t2 t3 clk30 output (*) input (**)
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 19 5.3.2 relationship between mode change and other input signals figure 5.6 - relationship between mode change and other input signals max. min. t4 - 4t t5 - 4t t4 t5 t hsterm/ opmod[1:0] fspeed txvld/ validh clk30
GL800HT25 usb 2.0 utmi compliant transceiver ip core ?2000-2003 genesys logic inc.?all rights reserved. page 20 chapter 6 package dimension control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 9.00 basic 9.00 basic 7.00 basic 7.00 basic 0.354 basic 0.354 basic 0.276 basic 0.276 basic 0.05 1.35 1.40 1.60 0.15 1.45 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 5.50 basic 5.50 basic 0.020 basic 0.217 basic 0.217 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 1 24 25 36 37 48 12 13 seating plane e b 4x 4x e e 1 e 2 a abd c aaa b ad h bbb ddd m c b a ss d b d1 d2 d d a a2 a1 0 . 0 5 s l 1 c 0 1 - 0 - c c ccc gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h figure 6.1 - GL800HT25 48 pin lqfp package

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