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12 - bi t high bandwidth multiplyi ng dac with serial interface data sheet ad5452w rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features 12 mhz multiplying bandwidth 8 - lead msop package 2.5 v to 5.5 v supply operation pin - compatible 12 - bit current output dac 10 v reference input 50 mhz serial interface 2.7 msps update rate extended temperature range: C 40 c to +125 c 4 - quadrant multiplication power - on reset with brownout detect <0.4 a typical current consumption guaranteed monotonic qualified for automotive applications applications portable battery - powered appl ications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming functional block dia gram figure 1. general description the ad5452w is a cmos 1 2 - bit current output digital - to - analog converter. th is device operate s from a 2.5 v to 5.5 v power supply, making it suited to several applications, including battery - powered applications. as a result of manufacture on a cmos submicron process, this dac offer s excellent four - quadrant multiplication characteri s- tics of up to 12 mhz. this dac utilize s a double - buffered, 3 - wire serial interf ace that is compatible with spi , qspi?, microwire?, and most dsp interface standards. upon power - up, the internal shift register and latches are filled with 0s, and the dac ou tput is at zero scale. the applied external reference input voltage (v ref ) determines the full - scale output current. this part can handle 10 v inputs on the reference, despite operating from a single - supply power supply of 2.5 v to 5.5 v. an integrated f eedback resistor (r fb ) provides temperature tracking and full - scale voltage output when combined with an external current - to - voltage precision amplifier. the ad5452w dac is available in an 8 - lead msop package . 12-bit ref r-2r dac dac register input latch power-on reset control logic and input shift register r i out 1 r fb v dd v ref gnd sdin sclk sync ad5452w 10657-001
ad5452w data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 13 theory of operation ...................................................................... 14 dac section ................................................................................ 14 circuit operation ....................................................................... 14 single - sup ply applications ....................................................... 16 adding gain ................................................................................ 16 divider or programmable gain element ................................ 16 reference selection .................................................................... 17 amplifier selection .................................................................... 17 serial i nterface ............................................................................ 19 microprocessor interfacing ....................................................... 19 pcb layout and power supply decoupling ........................... 21 outline dimensions ....................................................................... 23 ordering g uide .......................................................................... 23 automotive products ................................................................. 23 revision history 4/12 revision 0: initial version
data sheet ad5452w rev. 0 | page 3 of 24 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v. t a = full operating temperature range . all specifications t min to t max , unless otherwise noted. dc performance measured with op177 and ac performance measured with ad8038 , unless otherwise noted. table 1 . paramete r min typ max unit test conditions /comments static performance resolution 12 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic total unadjusted error 1 lsb gain error 0.5 lsb gain error temperature coefficient 1 2 ppm fsr/c output leakage current 1 na data = 0x0000, t a = 25c, i out 1 10 na data = 0x0000, t a = ?40c to +125c, i out 1 reference inpu t 1 reference input range 10 v v ref input resistance 7 9 11 k input resistance, tc = ? 50 ppm/c r fb feedback resistance 7 9 11 k input resistance, tc = ? 50 ppm/c input capacitance zero - scale code 18 22 pf full - scale code 18 22 pf digital inputs/outputs 1 input high voltage, v ih 2.0 v v dd = 3.6 v to 5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 na t a = 25c 10 na t a = ?40c to +125c input capacitance 10 pf dynamic performance 1 reference multiplying bw 12 mhz v ref = 3.5 v, dac loaded with all 1s multiplying feedthrough error v ref = 3.5 v, dac loaded with all 0s 72 db 100 khz 64 db 1 mhz 44 db 10 mhz output voltage settling time v ref = 10 v, r load = 100 ; dac latch alternately loaded with 0s and 1s measured to 1 mv of fs 100 110 ns measured to 4 mv of fs 24 40 ns measured to 16 mv of fs 16 33 ns digital delay 20 40 ns interface delay time 10% to 90% settling time 10 30 ns rise and fall times, v ref = 10 v, r load = 100 digital -to - analog glitch impulse 2 nv -s ec 1 lsb change around major carry, v ref = 0 v output capacitance i out 1 13 pf dac latches loaded with all 0s 28 pf dac latches loaded with all 1s
ad5452w data sheet rev. 0 | page 4 of 24 paramete r min typ max unit test conditions /comments digital feedthrough 0.5 nv -s ec feedthrough to dac output with cs high and alternate loading of all 0s and all 1s analog thd 83 db v ref = 3.5 v p - p, all 1s loaded, f = 1 khz digital thd clock = 1 mhz, v ref = 3.5 v 50 khz f out 71 db 20 khz f out 77 db output noise spectral density 25 nv/hz @ 1 khz sfdr performance (wide b and) clock = 1 mhz, v ref = 3.5 v 50 khz f out 78 db 20 khz f out 74 db sfdr performance (narrow - band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 87 db 20 khz f out 85 db intermodulation distortion 79 db f 1 = 20 khz, f 2 = 25 khz, clock = 1 mhz, v ref = 3.5 v power requirements power supply range 2.5 5.5 v i dd 0.4 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd 0.6 a t a = 25c, logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization ; not subject to production test.
data sheet ad5452w rev. 0 | page 5 of 24 timing characteristi cs all input signals are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, t a = full operating temperature range . all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 v dd = 2.5 v to 5.5 v unit conditions/comments f sclk 50 mhz max maximum clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 8 ns min sync falling edge to sclk active edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 5 ns min sync rising edge to sclk active edge t 8 30 ns min minimum sync high time update rate 2.7 msps consists of cycle time, sync high time, data setup, and output voltage settling time 1 guaranteed by design and characterization, not subject to production test. figure 2 . timing diagram sclk sync sdin db15 db0 t 7 t 3 t 2 t 6 t 5 t 4 t 8 t 1 10657-002
ad5452w data sheet rev. 0 | page 6 of 24 absolute maximum rat ings transient currents of up to 100 ma do not cause scr latch - up. t a = 25c, unless otherwise noted. table 3 . parameter rating v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i out 1 to gnd ?0.3 v to +7 v input current to any pin except supplies 10 ma logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 8 - lead msop 206c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at sclk, sync , and s din are clamped by internal diodes. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5452w rev. 0 | page 7 of 24 pin configuration and function descrip tions figure 3. pin configuration table 4 . pin function descriptions pin no mnemonic description 1 i out 1 dac current output. 2 gnd ground pin. 3 sclk serial clock input. by default, data is clocked into the input shift register upon the falling edge of the serial clock input. alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register upon the rising edge of sclk. 4 sdin serial data input. data is clocked into the 16 - bit input register upon the active edge of the serial clock input. by default, in power - up mode data is clocked into the shift register upon the falling edge of sclk. the control bits allow the user to change the active edge to a rising edge. 5 sync active low control input. this is the frame synchronization signal for the input data. data is loaded to the shift register upon the active edge of the following clocks. 6 v dd positive power supply input. these parts can operate from a supply of 2.5 v to 5.5 v. 7 v ref dac reference voltage input. 8 r fb dac feedback resistor. establish voltage output for the dac by connecting to external amplifier output. i out 1 gnd sclk sdin r fb v ref v dd sync ad5452w t op view (not to scale) 1 2 3 4 8 7 6 5 10657-004
ad5452w data sheet rev. 0 | page 8 of 24 typical performance characte ristics figure 4. inl vs. code figure 5. dnl vs. code figure 6 . inl vs. reference voltage figure 7 . dnl vs. reference voltage figure 8 . tue v s. code figure 9. tue vs. reference voltage 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 512 1024 1536 2048 2560 3072 2584 4096 code inl (lsb) t a = 25c v ref = 10v v dd = 5v 10657-022 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 2584 4096 code dnl (lsb) t a = 25c v ref = 10v v dd = 5v 10657-026 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 2 3 4 5 6 7 8 9 10 reference voltage (v) inl (lsb) t a = 25c v dd = 5v ad5452 max inl min inl 10657-070 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2 3 4 5 6 7 8 9 10 reference voltage (v) dnl (lsb) t a = 25c v dd = 5v ad5452 max dnl min dnl 10657-071 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 2584 4096 code tue (lsb) t a = 25c v ref = 10v v dd = 5v 10657-032 ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2 3 4 5 8 9 10 reference voltage (v) tue (lsb) 7 6 max tue ?0.5 0.5 t a = 25c v dd = 5v ad5452 min tue 10657-072
data sheet ad5452w rev. 0 | page 9 of 24 figure 10. gain error (lsb) vs. temperature figure 11. gain error (lsb) vs. reference voltage figure 12. i out 1 leakage current vs. temperature figure 13. supply current vs. logic input voltage figure 14. supply current vs. temperature figure 15. supply current vs. update rate ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?60 ?40 ?20 0 60 80 100 120 140 temperature (c) gain error (lsb) 4020 v dd = 5v v dd = 3v 10657-073 ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2345 8910 reference voltage (v) gain error (lsb) 76 ?0.5 0.5 t a = 25c v dd = 5v ad5452 10657-074 2.0 1.6 1.2 0.8 0.4 0 ?40 ?20 0 20 40 60 80 100 120 temperature (c) leakage (na) v dd = 5v v dd = 3v 10657-039 2.5 2.0 1.5 1.0 0.5 0 10657-038 input voltage (v) current (m a ) t a = 25c v dd = 5v v dd = 3v 0123 5 4 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40?200 20406080100120 temperature (c) current (a) v dd = 5v v dd = 3v all 1s all 0s 10657-037 1 10 100 1k 10k 100k 1m 10m frequency (hz) 6 0 1 2 3 4 5 current (ma) t a = 25c ad5452 loading 010101010101 v dd = 5v v dd = 3v 10657-075
ad5452w data sheet rev. 0 | page 10 of 24 figure 16 . threshold voltage vs. supply voltage figure 17 . reference multiplying bandwidth vs. frequency and code figure 18 . reference multiplying bandwidth all 1s loaded figure 19 . reference multiplying bandwidth vs. frequency and compensation capacitor figure 20 . midscale transition, v ref = 0 v figure 21 . midscale transition, v ref = 3.5 v 2.5 5.5 voltage (v) 1.8 1.2 1.0 0.4 0.2 0 v ih 1.6 1.4 0.8 0.6 3.0 3.5 4.5 4.0 5.0 v il threshold voltage (v) t a = 25c 10657-076 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m 100m gain (db) frequency (hz) all on db11 db10 db9 db8 db6 db5 db4 db3 db7 db2 db12 db13 v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier t a = 25c loading zs to fs 10657-108 0.6 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 10k 100k 1m 10m 100m gain (db) frequency (hz) t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier 10657-109 10k 100k 1m 10m 100m frequency (hz) 3 ?9 0 gain (db) t a = 25c v dd = 5v ?6 ?3 v ref = 2v, ad8038 c comp = 1pf v ref = 2v, ad8038 c comp = 1.5pf v ref = 15v, ad8038 c comp = 1pf v ref = 15v, ad8038 c comp = 1.5pf v ref = 15v, ad8038 c comp = 1.8pf 10657-079 50 200 225 250 time (ns) 0.08 ?0.06 output voltage (v) ?0.02 175 100 125 150 75 0.06 0.04 0.02 0 ?0.04 t a = 25c v dd = 0v ad8038 amplifier c comp = 1.8pf v dd = 5v 0x7ff to 0x800 nrg = 2.154nv-sec v dd = 3v 0x7ff to 0x800 nrg = 1.794nv-sec v dd = 5v 0x800 to 0x7ff nrg = 0.694nv-sec v dd = 5v 0x800 to 0x7ff nrg = 0.694nv-sec 10657-080 50 200 225 250 time (ns) ?1.66 ?1.80 output voltage (v) ?1.76 175 100 125 150 75 ?1.68 ?1.70 ?1.72 ?1.74 ?1.78 v dd = 5v 0x7ff to 0x800 nrg = 2.154nv-sec v dd = 3v 0x7ff to 0x800 nrg = 1.794nv-sec v dd = 5v 0x800 to 0x7ff nrg = 0.694nv-sec v dd = 5v 0x800 to 0x7ff nrg = 0.694nv-sec 10657-081 t a = 25c v dd = 3.5v ad8038 amplifier c comp = 1.8pf
data sheet ad5452w rev. 0 | page 11 of 24 figure 22 . power supply rejection ratio vs. frequency figure 23 . thd + noise vs. frequency figure 24 . wideband sfdr vs. f out frequency figure 25 . wideband sfdr, f out = 20 khz, clock = 1 mhz figure 26 . wideband sfdr, f out = 50 khz, clock = 1 mhz figure 27 . narrow - band sfdr, f out = 20 khz, clock = 1 mhz 1 10 100 1k 10k 100k 1m 10m frequency (hz) 10 ?100 ?90 ?70 ?50 ?30 ?10 psrr (db) t a = 25c v dd = 3v ad8038 amplifier ?80 ?60 ?40 ?20 0 full scale zero scale 10657-082 thd + n (db) t a = 25c v dd = 5v v ref = 3.5v 100 1k 10k 100k frequency (hz) ?60 ?90 ?85 ?75 ?65 ?80 ?70 10657-083 0 50 f out (khz) 100 0 sfdr (db) 40 20 30 40 10 80 60 20 t a = 25 c v ref = 3.5v ad8038 amplifier mclk = 500khz mclk = 1mhz mclk = 200khz 10657-084 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier frequency (hz) 400k 300k 200k 100k sfdr (db) 10657-085 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k frequency (hz) 400k 300k 200k 100k sfdr (db) t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier 10657-086 ?120 ?100 ?80 ?60 ?40 ?20 0 10k 30k frequency (hz) 25k 20k 15k sfdr (db) t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier 10657-087
ad5452w data sheet rev. 0 | page 12 of 24 figure 28 . narrow - band sfdr , f out = 50 khz, clock = 1 mhz figure 29 . narrow - band imd, f out = 20 khz, 25 khz, clock = 1 mhz figure 30 . wideband imd, f out = 20 khz, 25 khz, clock = 1 mhz figure 31 . output noise spectral density ?120 ?100 ?80 ?60 ?40 ?20 0 30k 70k t a = 25c v dd = 5v v ref = 3.5v ad8038 amplifier frequency (hz) 60k 50k 40k sfdr (db) 10657-088 ?100 ?90 ?80 ?60 ?40 ?20 0 10k 35k frequency (hz) 30k 25k 20k 15k imd (db) ?70 ?50 ?30 ?10 t a = 25c v ref = 3.5v ad8038 amplifier 10657-089 ?100 ?90 ?80 ?60 ?40 ?20 0 0 500k t a = 25c v ref = 3.5v ad8038 amplifier frequency (hz) 400k 300k 200k 100k imd (db) ?70 ?50 ?30 ?10 10657-090 100 1k 10k 100k 1m frequency (hz) 80 0 70 50 60 40 20 30 10 full scale loaded to dac midscale loaded to dac zero scale loaded to dac output noise (nv/ hz) t a = 25c ad8038 amplifier 10657-091
data sheet ad5452w rev. 0 | page 13 of 24 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is mea - sured after adjusting for zero and full scale a nd is normally expressed in lsbs or as a percentage of the full - scale reading. differential nonlinearity the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of ?1 lsb m aximum over the operating temperature range ensures monotonicity. gain error (full - scale error) a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref ? 1 lsb. gain error of the dacs is adjustable to zero with external resistance. output leakage current the current that flows into the dac ladder switches when it is turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. output capacitance capacitance from i out 1 to agnd. output current settling time the amount of time it takes for the output to settle to a specified level for a full - scale input change. for these devices, it is specified with a 100 ? resistor to ground. the settling time specification includes the digital delay from the sync rising edge to the full - scale output change. digital -to - analog glitch impulse the amount of charge injected from the digital inputs to the analo g output when the inputs change state. this is normally specified as the area of the glitch in either pa - sec or nv - sec , depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequ ency logic activity on the devices digital inputs may be capacitively coupled through the device and produce noise on the i out pins. this noise is coupled from the outputs of the device onto follow - on circuitry. this noise is digital feedthrough. multiply ing feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower - order harmonics, such as second to fifth, are included. 1 5 4 3 2 v v v v v thd 2 2 2 2 log 20 + + + = digital intermodulation distortion (imd) second - order intermodulation measure ments are the relative magnitudes of the fa and fb tones generated digitally by the dac and the second - order products at 2fa ? fb and 2fb ? fa. compliance voltage range the maximum range of (output) terminal voltage for which the device provides the speci fied characteristics. spurious - free dynamic range (sfdr) the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. sfdr is the measure of difference in amplitude between the fundamental and the largest harmonica lly or nonharmonically related spur from dc to full nyquist bandwidth (half the dac sampling rate or f s /2). narrow - band sfdr is a measure of sfdr over an arbitrary window size, in this case 50% of the fundamental. digital sfdr is a measure of the usable dy namic range of the dac when the signal is a digitally generated sine wave.
ad5452w data sheet rev. 0 | page 14 of 24 theory of operation dac section the ad 5452w is 12 - bit current output dac, consisting of a segmented (4 - bit) inverting r - 2r ladder configuration. a simplified diagram for the dac is shown in figure 32. figure 32 . ad5452w simplified ladder the feedback resistor, r fb , has a value of r. the value of r is typically 9 k? (with a minimum value of 7 k? and a maximum value of 11 k?). if i out 1 is kept at the same potential as gnd, a constant current flows in each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref is always const ant and nominally of value r. the dac output (i out 1) is code - dependent, producing various resistances and capacitances. when choosing the external amplifier, take into account the variation in impedance generated by the dac on the amplifiers inverting inp ut node. access is provided to the v ref , r fb , and i out 1 terminals of the dac, making the device extremely versatile and allowing it to be configured in several operating modes; for example, it can provide a unipolar output or can provide 4 - quadrant multipl ication in bipolar mode. note that a matching switch is used in series with the internal r fb feedback resistor. if users attempt to measure r fb , power must be applied to v dd to achieve continuity. circuit operation unipolar mode using a single op amp, this device can eas ily be configured to provide a two - quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 33 . when an output amplifier is connected in unipolar mode, the output voltage is given by ref n out v d v ? = 2 where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 4095 (12 - bit ad5452w ). n is the number of bits. note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. figur e 33 . unipolar mode operation th is dac is designed to operate with either negative or positive reference voltages. the v dd power pin is only used by the internal digital logic to drive the on and off states of the dac switches. this dac is designed to accommodate ac reference input signals in the range of ?10 v to +10 v. with a fixed 10 v reference, the circuit shown in figure 33 gives a uni polar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2 - quadrant multiplication. table 5 shows the relationship betwe en the digital code and the expected output voltage for a unipolar operation using the 12- bit ad5452w . table 5 . unipolar code table for the ad5452w digital input analog output (v) 1111 1111 1111 ?v ref (4095/4096) 1000 0000 0000 ?v ref (2048/4096) = ?v ref /2 0000 0000 0001 ?v ref (1/4096) 0000 0000 0000 ?v ref (0/4096) = 0 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers r r fb i out 1 v ref r r r agnd 10657-060 r fb i out 1 gnd sclk sdin v ref v ref r1 sync ad5452w v dd v dd agnd c1 a1 r2 v out = 0 to ?v ref controller notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. 10657-009
data sheet ad5452w rev. 0 | page 15 of 24 bipolar mode in some applications, it may be necessary to generate a full four - quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier and some external resistors, as shown in figure 34 . in this circuit, the second amplifier, a2, provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in full 4 - quadrant multiplying operation. th e transfer function of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code 0 (v out = ? v ref ) to midscale (v out = 0 v ) to full scale (v out = +v ref ). ref n ref out v d v v ? ? ? ? ? ? ? = ? 1 2 where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 4095 (12 - bit ad5452w ). n is the resolution of the dac. when v in is an ac signal, the circuit performs 4 - quadrant multiplication. table 6 shows the relationship between the digital code and the expected output voltage for a bipolar operation using the 12 - bit ad5452w . table 6 . bipolar code table for the ad5452w digital input analog output (v) 1111 1111 1111 +v ref (2047/2048) 1000 0000 0000 0 0000 0000 0001 ? v ref (2047/2048) 0000 0000 0000 ? v ref (2048/2048) stability in the i - to - v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible, and proper pcb layout techniques must be employed. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open - loop response, which can cause ringing or instability in the closed - loop applications circuit. an optional compensation capacitor, c1, can be added in parallel with r fb for stability, as shown in figure 33 and figure 34. to o small a value of c1 can produce ringing at the o utput, and too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for the compensation. figure 34 . bipolar mode operation (4- quadrant multiplication) notes 1. r1 and r2 used only if gain adjustment is required. adjust r1 for v out = 0v with code 10000000 loaded to dac. 2. matching and tracking is essential for resistor pairs r3 and r4. 3. c1 phase compensation (1pf to 2pf) may be required if a1/a2 is a high speed amplifier. r fb i out 1 gnd sclk sdin v ref 10v v ref r1 sync v dd v dd agnd c1 a1 a2 r2 v out = ?v ref to +v ref controller r3 20k? r4 10k? r5 20k? 10657-010 ad5452w
ad5452w data sheet rev. 0 | page 16 of 24 single - supply applications voltage - switching mode figure 35 shows these dacs operating in the voltage - switching mode. the reference voltage, v in , is applied to the i out 1 pin, and the output voltage is available at the v ref terminal. in this configurat ion, a positive reference voltage results in a positive output voltage, making single - supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance); therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees constant input impedance, but one that varies with code; therefore, the voltage input should be driven from a low impedance source. figure 35 . single - supply voltage - switching mode it is important to note that , with this configuration , v in is limited to low voltages because the switches in the dac ladder do not have the same source - drain drive voltage. as a result, their on resistance differs, which degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3v, or an internal diode turns on, causing the device to exceed the maximum ratings. in this type of application, the full range of multiplying capability of the dac is lost. positive output voltage the ou tput voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of t he resistors tolerance errors. to generate a negative reference, the reference can be level - shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ? 2.5 v, respectively, as shown in figure 36. figure 36 . positive output voltage with minimum components adding gain in applications in which the output voltage is required to be greater than v in , gain c an be added with an additional external amplifier, or it can be achieved in a single stage. it is important to consider the effect of the temperature coefficients of the dacs thin film resistors. simply placing a resistor in series with the r fb resistor causes mismatches in the temperature coefficients and results in larger gain temperature coefficient errors. instead, increase the gain of the circuit by using the recommended configuration shown in figure 37 . r1, r2, and r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains greater than 1 are required. f igure 37 . increasing gain of current - output dac divider or programma ble gain element current - steering dacs are very flexible and lend themselves to many different applications. if this type of dac is connected as the feedback eleme nt of an op amp and r fb is used as the input resistor as shown in figure 38 , the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ? n , the output voltage is ( ) ? ? ? = ? = 2 1 as d is reduced, the output voltage increases. for small values of the digital fraction, d, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. fi gure 38 . current - steering dac used as a divider or programmable gain element notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb v in i out 1 v ref gnd v dd v dd v out r1 r2 10657-0 1 1 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb i out 1 gnd ?5v +5v adr03 gnd v out v in v ref ?2.5v v dd v dd = +5v c1 v out = 0v to +2.5v 10657-012 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. r fb i out 1 gnd r1 v ref v in v dd v dd c1 v out r3 r2 gain = r2 + r3 r2 r1 = r2r3 r2 + r3 10657-013 note additional pins omitted for clarity r fb i out 1 v ref gnd v dd v dd v out v in 10657-014
data sheet ad5452w rev. 0 | page 17 of 24 dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. because only a fraction, d, of the current in the v ref terminal is routed to the i out 1 terminal, the output voltage changes as follows: output error voltage due to leakage = ( leakage r )/ d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k?, and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv. reference selection when selecting a reference for use with this current - output dac, pay att ention to the references output voltage tempera - ture coefficient specification. this parameter not only affects the full - scale error, but also may affect the linearity (inl and dnl) performance. the reference temperature coefficient should be consistent w ith the system accuracy specifications. a 12 - bit system within 2 lsb accuracy requires a maximum drift of 10 ppm/c. choosing a precision reference with a low output temperature coefficient minimizes this error source. table 7 lists some dc references available from analog devices , inc., that are suitable for use with this current - output dac. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. the input offset voltage of an op amp is multiplied by the variable gain of the circuit due to the code - dependent output resistance of the dac. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the offset voltage of the amplifiers input. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which , if large enough, may cause the dac to be nonmonotonic. the input bias current of an op amp generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12 - bit applications. common - mode rejection of the op amp is important in voltage - switching circuits because it produces a code - dependent error at the voltage output of the circuit. most op amps have adequate common - mode rejection for use at 12 - bit resolutions. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, it is important to minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by usin g low input - capacitance buffer amplifiers and careful board design. most single - supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail - to - rail signals. there is a large range of single - s upply amplifiers available from analog devices.
ad5452w data sheet rev. 0 | page 18 of 24 table 7 . suitable analog devices precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p - p) package adr01 10 0.05 3 1 20 soic -8 adr01 10 0.05 9 1 20 tsot - 23, sc70 adr02 5 0.06 3 1 10 soic -8 adr02 5 0.06 9 1 10 tsot - 23, sc70 adr03 2.5 0.10 3 1 6 soic -8 adr03 2.5 0.10 9 1 6 tsot - 23, sc70 adr06 3 0.10 3 1 10 soic -8 adr06 3 0.10 9 1 10 tsot - 23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic -8 adr435 5 0.04 3 0.8 8 soic - 8 adr391 2.5 0.16 9 0.12 5 tsot -23 adr395 5 0.10 9 0.12 8 tsot -23 table 8 . suitable analog devices precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise (v p - p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic -8 op1177 2.5 to 15 60 2 0.4 500 msop, soic -8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic -8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic -8 table 9 . suitable analog devices high speed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1500 0.006 soic - 8, sot - 23, msop ad8021 2.5 to 12 490 120 1000 10500 soic - 8, msop ad8038 3 to 12 350 425 3000 750 soic - 8, sc70-5 ad9631 3 to 6 320 1300 10000 7000 soic -8
data sheet ad5452w rev. 0 | page 19 of 24 serial interface the ad5452w ha s an easy - to - use 3 - wire interface that is compatible with spi, qspi, microwire, and most dsp interface standards. data is written to the device in 16 - bit words. this 16 - bit word consists of two control bits and 12 data bits, as shown in figure 39 . the ad5452w uses 12 bits and ignores the two lsbs. dac control bits c1, c0 control bits c1 and c0 allow the user to load and update the new dac code and to change the active clock edge. by default, the shift register clocks data upon the falling edge; this can be changed via the control bits. if changed, the dac core is inoperative until the next data frame , and a power recycle is required to return it to active on the falling edge . a power cycle resets the core to default condition. on - ch ip power - on reset circuitry ensures that the device powers on with zero scale loaded to the dac register and i out 1 line. table 10 . dac control bits c1 c0 function implemented 0 0 load and update (power - on default) 0 1 reserved 1 0 reserved 1 1 clock data to shift register upon rising edge sync function sync is an edge - triggered input that acts as a frame - synchronization signal and chip enable. data can only be transferred to the device while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync falling to sclk falling edge setup time, t 4 . to minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, upon the falling edge of sync . the sclk and sdin input buffers are powered down upon the rising edge of sync . after the falling edge of the 16 th sclk pulse, bring sync high to transfer data from the input shift register to the dac register. figure 39 . ad5452w 12 - bit input shift register contents microprocessor inter facing microprocessor interfacing to a n ad5452w dac is through a serial bus that uses standard protocol and is compatible with microcontrollers and dsp processors. the communication channel is a 3 - wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5452w require s a 16- bit word, with the default being data valid upon the falling edge of sclk, but this is changeable using the control bits in the data - word. adsp - 21xx - to - ad5452w interface the adsp - 21xx family of dsps is easily interfaced to an ad545 2w dac without the need for extra glue logic. figure 40 is an example of an spi interface between the dac and the adsp - 2191m . sck of the dsp drives the serial data line, sdin. sync is driven from one of the port lines, in this case spixsel . figure 40 . adsp - 2191 spi - to - ad5452w interface a serial interface between the dac and dsp sport is shown in figure 41 . in this example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out upon eac h rising edge of the dsps serial clock and clocked into the dac input shift register upon the falling edge of its sclk. the update of the dac output takes place upon the rising edge of the sync signal. figure 41 . adsp - 2101 / adsp - 2191 port - to - ad5452w inter face communicat ion between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup - and - hold, data delay and data setup - and - hold, an d sclk width. the dac interface expects a t 4 ( sync falling edge to sclk falling edge setup time) of 8 ns minimum. see the adsp - 21xx user manual for infor - mation on clock and frame sync frequencies for the sport register. table 11 shows the setup for the sport control register. table 11 . sport control register setup name set ting description tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16 - bit data - word db0 (lsb) db15 (msb) db7 db6 db5 db4 db3 db2 db0 db1 c1 c0 db11 db10 db8 db9 x x control bits data bits 10657-007 sclk sck sync spixsel sdin mosi adsp-2191* *additional pins omitted for clarity ad5452w* 10657-100 sclk sclk sync tfs sdin dt adsp-2101/ adsp-2191* *additional pins omitted for clarity ad5452w* 10657-051
ad5452w data sheet rev. 0 | page 20 of 24 adsp - bf5xx - to - ad5452w interface the adsp - bf5xx family of processors has an spi - compatible port that enables the processor to communicate with spi - compatible devices. a serial interfa ce between the blackf in ? processor and the ad5452w dac is shown in figure 42. in this configuration, data is transferred through the mosi ( master output, slave input) pin. sync is driven by the spixsel pin, which is a reconfigured programmable flag pin. figure 42 . adsp - bf5xx - to - ad5452w interface the adsp - bf5xx processor incorporates channel synchronous serial ports (sport). a serial interface between the dac and the dsp sport is shown in figure 43 . when the s port is enabled, initiate transmission by writing a word to the tx register. the data is clocked out upon each rising edge of the dsps serial clock and clocked into the dacs input shift register upon the falling edge of sclk. the dac output is updated by using the transmit frame synchronization (tfs) line to provide a sync signal. figure 43 . adsp - bf5xx sport - to - ad5452w interface 80c51/80l51 - to - ad5452w interface a serial interface between the dac and the 80c51/80l51 is shown in figure 44 . txd of the 80c51/80l51 drives sclk of the da c serial interface, and rxd drives the serial data line, s din. p1.1 is a bit - programmable pin on the serial port and is used to drive sync . as data is transmitted to the switch, p1.1 is taken low. the 80c51/80l51 transmit data only in 8 - bit bytes; there - fore, only eight falling clock edges occur in the transmit cycle. to load data correctly to the dac, p1.1 is left low after the first eight bits are transmitted, and a second write cycle is ini tiated to transmit the second byte of data. data on rxd is clocked out of the microcontroller upon the rising edge of txd and is valid upon the falling edge. as a result, no glue logic is required between the dac and microcontroller interface. p1.1 is take n high following the completion of this cycle. the 80c51/80l51 provide the lsb of its sbuf register as the first bit in the data stream. the dac input register acquires its data with the msb as the first bit received. the transmit routine should take this into account. figure 44 . 80c51/80l51 - to - ad5452w interface mc68hc11 - to - ad5452w interface figure 45 is an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr); see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the dac interface; the mosi output drives the serial data line (sdin) of the dac. th e sync signal is derived from a port line (pc7). when data is being transmitted to the ad5452w , the sync line is taken low (pc7). data appearing on the mosi output is valid upon the falling edge of sck. serial data from the 68hc11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, pc7 is left low after the first ei ght bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. figure 45 . mc68hc11 - to - ad5452w interface if the user wants to verify the data previously written to the input shift register, the sdo line can be connected to miso of the mc68hc11. in this configuration with sync low, the shift register clocks data out upon the rising edges of sclk. sclk sck sync spixsel sdin mosi adsp-bf5xx* *additional pins omitted for clarity ad5452w* 10657-102 sclk sclk sync tfs sdin dt adsp-bf5xx* *additional pins omitted for clarity ad5452w* 10657-103 sclk txd 8051* sync p1.1 sdin rxd *additional pins omitted for clarity ad5452w* 10657-104 sclk sck ad5452w* sync pc7 sdin mosi mc68hc11* *additional pins omitted for clarity 10657-105
data sheet ad5452w rev. 0 | page 21 of 24 microwire - to - ad5452w interface figure 46 shows an interface between the dac and any microwire - compatible device. serial data is shifted out upon the falling edge of the serial clock, sk, and is clocked into the dac input shift register upon the rising edge of sk, which corresponds to the falling edge of the dacs sclk. figure 46 . microwire - to - ad5452w interface pic16c6x/pic16c7x - to - ad5452w interface the pic16c6x/pic16c7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon); see the pic16/pic17 microcontroller user manual . in this example, i/o port ra1 is u sed to provide a sync signal and enable the serial port of the dac. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. figure 47 shows the connection diagram. figure 47 . pic16c6x/7x - to - ad5452w interface pcb laout and power suppl decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which a n ad545 2w dac is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due t o internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast switching sig nals should be shielded with a digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at r ight angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is the best solution, but its use is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to the ground plane and signal traces are placed on the solder side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal t races between v ref and r fb should also be matched to minimize gain error. to optimize high frequency performance, the i - to - v amplifier should be located as close to the device as possible. sclk sk microwire* sync cs sdin so ad5452w* *additional pins omitted for clarity 10657-106 sclk sck/rc3 pic16c6x/pic16c7x* sync ra1 sdin sdi/rc4 ad5452w* *additional pins omitted for clarity 10657-107
ad5452w data sheet rev. 0 | page 22 of 24 table 12. overview of ad54xx and ad55xx current output devices part no. resolution no. dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru - 16, cp - 20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm - 10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru - 20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru - 10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial uj - 8 12 mhz bw, 50 mhz serial interface ad5432 10 1 0.5 serial rm - 10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru - 20, cp - 20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru - 16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru - 24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial uj - 8 12 mhz bw, 50 mhz serial interface ad5443 12 1 1 serial rm - 10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm - 10 12 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru - 24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp - 40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru - 20, cp - 20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru - 24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru - 16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial uj - 8, rm - 8 12 mhz bw, 50 mhz serial interface ad5446 14 1 1 serial rm - 10 12 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj - 8, rm - 8 12 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru - 28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru - 38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru - 28 4 mhz bw, 20 n wr pulse width ad5545 16 2 2 serial ru - 16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru - 38 4 mhz bw, 20 ns wr pulse width 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
data sheet ad5452w rev. 0 | page 23 of 24 outline dimensions figure 48 . 8- lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters ordering guide model 1 , 2 resolution inl temperature range package description package option branding ad w50007z - 0reel7 12 0.5 ?40c to +125c 8 - lead msop rm -8 d70 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the adw50007z model is available with controlled manufacturing to support the quality and reliability requirements of automot ive applications. note that this automotive model may have specifications that differ from the commercial models; therefore, desi gn ers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information a nd to obtain the specific automoti ve reliability reports for this model. compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanar ity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 ident ifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07- 2009-b
ad5452w data sheet rev. 0 | page 24 of 24 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10657 - 0 - 4/12(0)

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