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m95640, m95320 m95160, m95080 64k/32k/16k/8k serial spi eeprom with positive clock strobe preliminary data march 1998 1/21 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. ai01789c s v cc m95xxx hold v ss w q c d figure 1. logic diagram c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground table 1. signal names 8 1 so8 (mn) 150 mil width 8 1 psdip8 (bn) 0.25mm frame 100,000 erase/write cycles 40 years data retention single supply voltage C 4.5v to 5.5v for m95xxx C 2.5v to 5.5v for m95xxx-w C 1.8v to 3.6v for m95xxx-r spi bus compatible serial interface 5 mhz clock rate max status register hardware protection of the status register 32 byte page mode sizeable read only eeprom area self-timed programming cycle e.s.d.protection greater than 4000v supports positive clock spi modes description the m95xxx is a family of electrically erasable programmable memories (eeprom) fabricated with sgs-thomsons high endurance double polysilicon cmos technology. each memory is accessed by a simple spi bus compatible serial interface. the bus signals are a serial clock input (c), a serial data input (d) and a serial data output (q).
symbol parameter value unit t a ambient operating temperature (2) C40 to 125 c t stg storage temperature C65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v o output voltage C0.3 to v cc +0.6 v v i input voltage with respect to ground C0.3 to 6.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (3) 4000 v electrostatic discharge voltage (machine model) (4) 400 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the sgs-thomson sure program and other relevant quality documents. 2. depends on range 3. dmil-std-883c, 3015.7 (100pf, 1500 w ) 4. eiaj ic-121 (condition c) (200pf, 0 w ) table 2. absolute maximum ratings (1) the device connected to the bus is selected when the chip select input ( s) goes low. communications with the chip can be interrupted with a hold input ( hold). data is clocked in during the low to high transition of clock c, data is clocked out during the high to low transition of clock c. signals description serial output (q). the output pin is used to trans- fer data serially out of the memory. data is shifted out on the falling edge of the serial clock. serial input (d). the input pin is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. input is latched on the rising edge of the serial clock. d v ss c hold q sv cc w ai01790c m95xxx 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 ai01791c 2 3 4 8 7 6 5 d v ss c hold q sv cc w m95xxx figure 2b. so pin connections description (contd) 2/21 m95640, m95320, m95160, m95080
ai01438 c c msb lsb cpha d or q 0 1 cpol 0 1 figure 3. data and clock timing ai01957b spi interface with (cpol, cpha) = ('0', '0') or ('1', '1') microcontroller (st6,st7,st9,st10, others) m95xxx sck sdi sdo c q d figure 4. microcontroller and spi interface set-up serial clock (c). the serial clock provides the timing of the serial interface. instructions, ad- dresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the q pin changes after the falling edge of the clock input. chip select ( s). when s is high, the memory is deselected and the q output pin is at high imped- ance and, unless an internal write operation is underway the memory will be in the standby power mode. s low enables the memory, placing it in the active power mode. it should be noted that after power-on, a high to low transition on s is required prior to the start of any operation. write protect ( w). this pin is for hardware write protection of the status register (sr); except wip and wel bits. when bit 7 (srwd) of the status register is 0 (the initial delivery state); it is possible to write the sr once the wel (write enable latch) has been set and whatever is the status of pin w (high or low). note: srwd stands for; status register write disable. 3/21 m95640, m95320, m95160, m95080
w srwd status register (sr) data bytes (protected area) mode data bytes (unprotected area) x0 writable after setting wel software write protected by the bpn bits of the status register spm writable after setting wel 11 writable after setting wel software write protected by the bpn bits of the status register spm writable after setting wel 01 hardware write protected hardware write protected hpm writable after setting wel notes: 1. spm stands for software protected mode. 2. bpn are bp0 to bp1 bits of the status register. 3. spm and hpm are also described in the write status register (wrsr) section. table 3. protection feature once bit 7 (srwd) of the status register has been set to 1; the possibility to rewrite the sr depends on the logical level present at pin w: Cif w pin is high; it will be possible to rewrite the status register after having set the wel (write enable latch). Cif w pin is low; any attempt to modify the status register will be ignored by the device even if the wel was set. as a consequence: all the data bytes in the eeprom area protected by the bpn bits of the status register are also hardware protected against data corruption and can be seen as a read only eeprom area from the microcontroller. this mode is called the hard- ware protected mode (hpm). it is possible to enter the hardware protected mode (hpm) by setting srwd bit after pulling down the w pin or by pulling down the w pin after setting srwd bit. the only way to abort the hardware protected mode once entered is to pull high the w pin. if w pin is permanently tied to high level; the hardware protected mode will never be activated and the memory will only allow the user to software protect a part of the memory with the bpn bits of the status register. all protection features of the device are summarized in table 3. hold ( hold). the hold pin is used to pause serial communications with an spi memory without resetting the serial sequence. to take the hold condition into account, the product must be se- lected ( s = 0). then the hold state is validated by a high to low transition on hold when c is low. to resume the communications, hold is brought high while c is low. during the hold condition d, q, and c are at a high impedance state. when the memory is under the hold condition, it is possible to deselect the device. however, the serial communications will remain paused after a rese- lect, and the chip will be reset. the memory can be driven by a microcontroller with its spi peripheral running in either of the two fol- lowing modes: (cpol, cpha) = (0, 0) or (cpol, cpha) = (1, 1). for these two modes, input data is latched in by the low to high transition of clock c, and output data is available from the high to low transition of clock (c). the difference between (cpol, cpha) = (0, 0) and (cpol, cpha) = (1, 1) is the stand-by polarity: c remains at 0 for (cpol, cpha) = (0, 0) and c remains at 1 for (cpol, cpha) = (1, 1) when there is no data transfer. signals description (contd) 4/21 m95640, m95320, m95160, m95080
operations all instructions, addresses and data are shifted in and out of the chip msb first. data input (d) is sampled on the first rising edge of clock (c) after the chip select ( s) goes low. prior to any operation, a one-byte instruction code must be entered in the chip. this code is entered via the data input (d), and latched on the rising edge of the clock input (c). to enter an instruction code, the product must have been previously selected ( s = low). table 4 shows the instruction set and format for device operation. if an invalid instruction is sent (one not contained in table 4), the chip is automatically deselected. write enable (wren) and write disable (wrdi) the memory contains a write enable latch. this latch must be set prior to every write, wrsr operation. the wren instruction will set the latch and the wrdi instruction will reset the latch. the latch is reset under the following conditions: C power on, C wrdi instruction completion, C wrsr instruction completion, C write instruction completion. as soon as the wren or wrdi instruction is received, the circuit executes the instruction and enters a wait mode until it is deselected. read status register (rdsr) the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write to the memory operation. as soon as the 8th bit of the status register is read out, the memory enters a wait mode (data on d is not decoded, q is in hi-z) until it is deselected. the status register format is as follows: b7 b0 srwd x x x bp1 bp0 wel wip bp0, bp1: read and write bits wel, wip: read only bits. srwd: read and write bit. during a write to the memory operation: all bits bp0, bp1, wel, wip are valid and can be read. during a write to the status register, only the bits wel and wip are valid and can be read. the values of bp1 and bp0 read at that time corre- spond to the previous contents of the status regis- ter. the write-in-process (wip) read-only bit indicates whether the memory is busy with a write operation. when set to a 1 a write is in progress, when set to a 0 no write is in progress. the write enable latch (wel) read-only bit indi- cates the status of the write enable latch. when set to a 1 the latch is set, when set to a 0 the latch is reset. the block protect (bp0 and bp1) bits indi- cate the extent of the protection employed. these bits are set by the user issuing the wrsr instruc- tion. these bits are non-volatile. instruction description instruction format wren set write enable latch 0000 0110 wrdi reset write enable latch 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read data from memory array 0000 0011 write write data to memory array 0000 0010 table 4. instruction set device m95080 m95160 m95320 m95640 address bit a0-a9 a0-a10 a0-a11 a0-a12 note: address bits up to a15 not specified are dont care. table 5. address range bits 5/21 m95640, m95320, m95160, m95080
ai01792b hold s w control logic high voltage generator i/o shift register address register and counter data register 32 bytes x decoder y decoder sizeable read only eeprom area c d q status an an - 31 001fh 0000h figure 5. block diagram note: an is the top address of the memory. 6/21 m95640, m95320, m95160, m95080
write status register (wrsr) when the wrsr instruction and the 8 bits of the status register are latched-in, the internal write cycle is then triggered by the rising edge of s. this rising edge of s must appear just before the rising edge of the 17 th clock pulse (see serial input timing figure 14), otherwise the internal write sequence is not performed. the wrsr instruction allows the user: 1. to select the size of the memory to be protected, 2. to choose the protection level between the spm (software protected mode) and the hpm (hardware protected mode). size selection. the way to select the size of the eeprom area to be protected is common to both spm and hpm. bp1 and bp0 bits (initial delivery states = 00; that is size = 0) of the status register have to be written once the data to be protected are stored in the eeprom. the table 6 summa- rizes the size selection functions of the memory. c d ai01793 s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 765432 0 1 high impedance data out instruction 16 bit address 0 msb figure 6. read eeprom array operation sequence note: depending on the memory size, most significant address bits are dont care. status register bits protected block array addresses protected bp1 bp0 m95080 m95160 m95320 m95640 0 0 none none none none none 0 1 upper quarter 0300h - 03ffh 0600h - 07ffh 0c00h - 0fffh 1800h - 1fffh 1 0 upper half 0200h - 03ffh 0400h - 07ffh 0800h - 0fffh 1000h - 1fffh 1 1 whole memory 0000h - 03ffh 0000h - 07ffh 0000h - 0fffh 0000h - 1fffh table 6. write protected block size 7/21 m95640, m95320, m95160, m95080
c d ai01795 s q 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 high impedance instruction 16 bit address 0 765432 0 1 data byte 31 figure 8. byte write operation sequence c d ai02281 s q 2 1 34567 high impedance 0 figure 7. write enable latch sequence note: depending on the memory size, most significant address bits are dont care. 8/21 m95640, m95320, m95160, m95080
c d ai01796 s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 c d s 15 2 1 345678910 2021222324252627 1413 3210 28 29 30 instruction 16 bit address 0 765432 0 1 data byte 1 31 43 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n figure 9. page write operation sequence c d s 2 1 3456789101112131415 instruction 0 ai01444 q 7 6543210 status reg. out high impedance msb figure 10. rdsr: read status register sequence note: depending on the memory size, most significant address bits are dont care. 9/21 m95640, m95320, m95160, m95080
selection of the protection level C once bp0 and bp1 bits are written; the soft- ware protected mode (spm) is entered. this means that any attempt to write a byte or a page in the protected area will be ignored even if the write enable latch was set before the write instruction. in this software protected mode; bp0 and bp1 bits can be rewritten with the wsr instruction after having set the wel. C if a higher level of protection is needed; the hardware protected mode (hpm) can be se- lected. it is possible to enter the hpm by setting srwd bit after pulling down the w pin or by pulling down the w pin after setting srwd. in both cases, the srwd is set by using the wsr instruction after having set the wel bit. it should also be noted that the srwd can be set after writing bp0 and bp1 or at the same time. C once the hpm is entered, the content of the status register and all data bytes in the pro- tected area are hardware protected against write attempts. the only way to write again the status register is to abort the hpm by pulling high the w pin. aborting the hpm will put the device in the spm with bp0 and bp1 bits unchanged. note: see also the write protect pin ( w) descrip- tion on page 3). typical applications C the w pin can be dynamically driven by an output port of a microcontroller but can also be connected directly or through a pull-down resis- tor to v ss . C with such a pcb (printed circuit board): a) the memory in the initial delivery state can be soldered directly. after power on, the microcon- troller can write data to be protected in the mem- ory. then write bp0, bp1 and set the srwd to enter the hpm. b) data to be protected, bp0, bp1 can be written and srwd can be set before soldering the memory. as a consequence, once soldered, the memory is immediately placed in the hpm. in these two cases, the only way to abort the hpm will be to remove the memory from the pcb or to apply v cc on the w pin through an external equipment when a pull-down resistor is inserted between the pin and v ss . read operation the chip is first selected by putting s low. the serial one byte read instruction is followed by a two bytes address (a15-a0), each bit being latched-in during the rising edge of the clock (c). c d ai02282 s q 2 1 3456789101112131415 high impedance instruction status reg. 0 765432 0 1 msb figure 11. wrsr: write status register sequence 10/21 m95640, m95320, m95160, m95080
then the data stored in the memory at the selected address is shifted out on the q output pin; each bit being shifted out during the falling edge of the clock (c). the data stored in the memory at the next address can be read in sequence by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest ad- dress is reached, the address counter rolls over to "0h" allowing the read cycle to be continued indefi- nitely. the read operation is terminated by dese- lecting the chip. the chip can be deselected at any time during data output. any read attempt during a write cycle will be rejected and will deselect the chip. byte write operation prior to any write attempt, the write enable latch must be set by issuing the wren instruction. first the device is selected ( s = low) and a serial wren instruction byte is issued. then the product is de- selected by taking s high. after the wren instruc- tion byte is sent, the memory will set the write enable latch and then remain in standby until it is deselected. then the write state is entered by selecting the chip, issuing three bytes of instruction and address, and one byte of data. chip select ( s) must remain low for the entire duration of the operation. the product must be deselected just after the eighth bit of data has been latched in. if not, the write process is cancelled. as soon as the product is deselected, the self-timed write cycle is initiated. while the write is in progress, the status register may be read to check bp1, bp0, wel and wip. wip is high during the self-timed write cycle. when the cycle is completed, the write enable latch is reset. page write operation a maximum of 32 bytes of data may be written during one non-volatile write cycle. all 32 bytes must reside on the same page. the page write mode is the same as the byte write mode except that instead of deselecting the device after the first byte of data, up to 31 additional bytes can be shifted in prior to deselecting the chip. any address of the memory can be chosen as the first address to be written. if the address counter reaches the end of the page (xxxx xxx1 1111) and the clock continues, the counter will roll over to the first address of the page (xxxx xxx0 0000) and overwrite any pre- viously written data. the programming cycle will only start if the s transition occurs just after the eighth bit of data of a word is received. ai01958 master m95xxx d q c cqd s m95xxx cqd s m95xxx cqd s cs3 cs2 cs1 figure 12. eeprom and spi bus 11/21 m95640, m95320, m95160, m95080
ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc figure 13. ac testing input output input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc output load c l = 100pf note that output hi-z is defined as the point where data is no longer driven. table 8. ac measurement conditions symbol parameter min max unit c out output capacitance (q) 8 pf c in input capacitance (other pins) 6 pf note: 1. sampled only, not 100% tested. table 7. input parameters (1) (t a = 25 c, f = 5 mhz ) power on state after a power up the memory is in the following state: C the device is in the low power standby state. C the chip is deselected. C the chip is not in hold condition. C the write enable latch is reset. C b7 to b2 bits of the status register are un- changed (non-volatile bits). data protection and protocol safety C non valid s and hold transitions are not taken into account. C s must come high at the proper clock count in order to start a non-volatile write cycle (in the memory array or in the status register), that is the chip select s must rise during the clock pulse following the introduction of a multiple of 8 bits. C access to the memory array during non-volatile programming cycle is ignored; however, the pro- gramming cycle continues. C after any of the operations wren, wrdi, rdsr is completed, the chip enters a wait state and waits for a deselect. C the write enable latch is reset upon power-up. initial delivery state the device is delivered with the memory array in a fully erased state (all data set at all "1s" or ffh). the status register bits are initialized to 00. status register: b7 b0 00000000 12/21 m95640, m95320, m95160, m95080
symbol parameter test condition min max unit i li input leakage current 2 m a i lo output leakage current 2 m a i cc supply current c = 0.1 v cc /0.9 v cc , at 5 mhz, v cc = 5v, q = open 4ma c = 0.1 v cc /0.9 v cc , at 2 mhz, v cc = 5v, q = open, note 2 4ma supply current (w series) c = 0.1 v cc /0.9 v cc , at 2 mhz, v cc = 2.5v, q = open 2ma supply current (r series) c = 0.1 v cc /0.9 v cc , at 1 mhz, v cc = 1.8v, q = open 2ma i cc1 standby current s = v cc , v in = v ss or v cc , v cc = 5v 10 m a s = v cc , v in = v ss or v cc , v cc = 5v, note 2 10 m a standby current (w series) s = v cc , v in = v ss or v cc , v cc = 2.5v 2 m a standby current (r series) s = v cc , v in = v ss or v cc , v cc = 1.8v 1 m a v il input low voltage C0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 1 v v ol (1) output low voltage i ol = 2ma, v cc = 5v 0.4 v i ol = 2ma, v cc = 5v, note 2 0.4 v output low voltage (w series) i ol = 1.5ma, v cc = 2.5v 0.4 v output low voltage (r series) i ol = 0.15ma, v cc = 1.8v 0.3 v v oh (1) output high voltage i oh = C2ma, v cc = 5v 0.8 v cc v i oh = C2ma, v cc = 5v, note 2 0.8 v cc v output high voltage (w series) i oh = C0.4ma, v cc = 2.5v 0.8 v cc v output high voltage (r series) i oh = C0.1ma, v cc = 1.8v 0.8 v cc v notes: 1. the device meets output requirements for both ttl and cmos standards. 2. test performed at C40 to 125 c temperature range, grade 3. table 9. dc characteristics (t a = 0 to 70 c; C40 to 85 c or C40 to125 c; v cc = 4.5v to 5.5v) (t a = 0 to 70 c; C40 to 85 c; v cc = 2.5v to 5.5v) (t a = 0 to 70 c; C20 to 85 c; v cc = 1.8v to 3.6v) 13/21 m95640, m95320, m95160, m95080
symbol alt parameter m95640 / 320 / 160 / 080 unit v cc = 4.5v to 5.5v, t a = 0 to 70 c, t a = C40 to 85 c v cc = 4.5v to 5.5v, t a = C40 to 125 c min max min max f c f c clock frequency d.c. 5 d.c. 2 mhz t slch t css s active setup time 90 200 ns t chsl s not active hold time 90 200 ns t ch (1) t clh clock high time 90 200 ns t cl (1) t cll clock low time 90 200 ns t clch (2) t rc clock rise time 1 1 m s t chcl (2) t fc clock fall time 1 1 m s t dvch t dsu data in setup time 20 40 ns t chdx t dh data in hold time 30 50 ns t dldh (2) t ri data in rise time 1 1 m s t dhdl (2) t fi data in fall time 1 1 m s t hhch t cd hold setup time 70 140 ns t hlch t cd clock low hold time 40 90 ns t clhl t hd hold hold time 0 0 ns t clhh t hd clock low setup time 0 0 ns t chsh t csh s active hold time 90 200 ns t shch s not active setup time 90 200 ns t shsl t cs s deselect time 100 200 ns t shqz (2) t dis output disable time 100 250 ns t clqv t v clock low to output valid 60 150 ns t clqx t ho output hold time 0 0 ns t qlqh (2) t ro output rise time 50 100 ns t qhql (2) t fo output fall time 50 100 ns t hhqx (2) t lz hold high to output low-z 50 100 ns t hlqz (2) t hz hold low to output high-z 100 250 ns t w t wp write cycle time 10 10 ms notes: 1. t ch + t cl 3 1/fc 2. value guaranteed by characterization, not 100% tested in production. table 10a. ac characteristics 14/21 m95640, m95320, m95160, m95080
symbol alt parameter m95640 / 320 / 160 / 080 unit v cc = 2.5v to 5.5v, t a = 0 to 70 c, t a = C40 to 85 c v cc = 1.8v to 3.6v, t a = 0 to 70 c, t a = C20 to 85 c min max min max f c f c clock frequency d.c. 2 d.c. 1 mhz t slch t css s active setup time 200 400 ns t chsl s not active hold time 200 400 ns t ch (1) t clh clock high time 200 400 ns t cl (1) t cll clock low time 200 400 ns t clch (2) t rc clock rise time 1 1 m s t chcl (2) t fc clock fall time 1 1 m s t dvch t dsu data in setup time 40 60 ns t chdx t dh data in hold time 50 100 ns t dldh (2) t ri data in rise time 1 1 m s t dhdl (2) t fi data in fall time 1 1 m s t hhch t cd hold setup time 140 350 ns t hlch t cd clock low hold time 90 200 ns t clhl t hd hold hold time 0 0 ns t clhh t hd clock low setup time 0 0 ns t chsh t csh s active hold time 200 400 ns t shch s not active setup time 200 400 ns t shsl t cs s deselect time 200 300 ns t shqz (2) t dis output disable time 250 500 ns t clqv t v clock low to output valid 150 380 ns t clqx t ho output hold time 0 0 ns t qlqh (2) t ro output rise time 100 200 ns t qhql (2) t fo output fall time 100 200 ns t hhqx (2) t lz hold high to output low-z 100 250 ns t hlqz (2) t hz hold low to output high-z 250 500 ns t w t wp write cycle time 10 10 ms notes: 1. t ch + t cl 3 1/fc 2. value guaranteed by characterization, not 100% tested in production. table 10b. ac characteristics 15/21 m95640, m95320, m95160, m95080
c d ai01447 s msb in q tdvch high impedance lsb in tslch tchdx tdldh tdhdl tchcl tclch tshch tshsl tchsh tchsl figure 14. serial input timing c q ai01448 s d hold tclhl thlch thhch tclhh thhqx thlqz figure 15. hold timing 16/21 m95640, m95320, m95160, m95080
c q ai01449b s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv figure 16. output timing 17/21 m95640, m95320, m95160, m95080
ordering information scheme notes: 1. data in is strobed on rising edge of the clock (c) and data out is synchronized from the falling edge of the clock. 2. temperature range on request only, 3. produced with high reliability certified flow (hrcf), in v cc range 4.5v to 5.5v only. 4. -r version (1.8v to 3.6v) are only available in temperature ranges 5 or 1. devices are shipped from the factory with the memory content set at all "1s" (ffh). for a list of available options (operating voltage, package, etc...) or for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. density 64 64k (8k x8) 32 32k (4k x8) 16 16k (2k x8) 08 8k (1k x8) data strobe 0 note 1 operating voltage blank 4.5v to 5.5v w 2.5v to 5.5v r (4) 1.8v to 3.6v package bn psdip8 0.25 mm frame mn so8 150mils width option t tape & reel packing temperature range 1 (2) 0 to 70 c 5 C20 to 85 c 6 C40 to 85 c 3 (3) C40 to 125 c example: m95xx0 C r mn 5 t 18/21 m95640, m95320, m95160, m95080
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb 10.00 0.394 l 3.00 3.80 0.118 0.150 n8 8 cp 0.10 0.004 drawing is not to scale. psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame 19/21 m95640, m95320, m95160, m95080
so-a e n cp b e a d c l a1 a 1 h h x 45? symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27C C0.050C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 drawing is not to scale. so8 - 8 lead plastic small outline, 150 mils body width 20/21 m95640, m95320, m95160, m95080
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification s mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously s upplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of sgs-thomson microelectronics. ? 1998 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 21/21 m95640, m95320, m95160, m95080

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