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1 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter features ? converts low-swing ac coupled differential input to hdmi rev 1.3 compliant open-drain current steering rx terminated dif- ferential output ? hdmi level shifting operation up to 2.5gbps per lane (250mhz pixel clock) ? integrated 50-ohm termination resistors for ac-coupled dif- ferential inputs. ? enable/disable feature to turn off tmds outputs to enter low- power state. ? output slew rate control on tmds outputs to minimize emi. ? transparent operation: no re-timing or con guration required. ? 3.3 power supply required. ? integrated esd protection to 8kv contact on all high speed i/o pins (in_x and out_x) per iec61000-4-2 test spec, level 4 ? ddc level shifters from 5v from sink side down to 3.3v on source side ? level shifter for hpd signal from hdmi/dvi connector ? integrated pull-down on hpd_sink input guarantees "input low" when no display is plugged in ? packaging (pb-free & green available) ? 48 tqfn, 7mm 7mm (zde) ? 48 tqfn, 7mm x 7mm (zbe) ? 42 tqfn, 9mm 3.5mm (zhe) description pericom semiconductor?s pi3vdp411ls provides the ability to use a dual-mode dp transmitter in hdmi mode. this exibility provides the user a choice of how to connect to their favorite display. all signal paths accept ac coupled video signals. the pi3vdp411ls converts this ac coupled signal into an hdmi rev 1.3 compliant signal with proper signal swing. this conver- sion is automatic and transparent to the user. the pi3vdp411ls supports up to 2.5gbps, which provides 12- bits of color depth per channel, as indicated in hdmi rev 1.3. pin con guration 1 2 3 4 5 67 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 gnd vdd in_d1- in_d1+ in_d2- in_d2+ gnd in_d3- in_d3+ in_d4- in_d4+ vdd gnd vdd out_d1- out_d1 + out_d2- out_d2+ gnd out_d3- out_d3+ out_d4- out_d4+ vdd gnd vdd eq_1 eq_0 ddc_en gnd hpd_sink sda_sink scl_sink vdd oe# gnd gnd oc_1 vdd oc_0 gnd oc_2(rext ) hpd_source sda_source scl_source vdd gnd oc_3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 eq_0 ddc_en hpd_sink sda_sink hpd_source sda_source scl_source vdd gnd in_d1- in_d1+ vdd in_d2- in_d2+ gnd in_d3- in_d3+ vdd in_d4- in_d4+ gnd vdd oc_0 oc_1 oc_2 scl_sink gnd vdd oe# gnd out_d1- out_d1+ vdd out_d2- out_d2+ gnd out_d3- out_d3+ vdd out_d4- out_d4+ gnd gnd 48-pin tqfn (zde/zbe) 42-pin tqfn (zhe) 08-0294
2 ps8913d 11/05/08 pi3vdp411ls display port redriver w/ level conversion feature for dvi/hdmi interoperability block diagram inx_d4+ inx_d4- oe# rx outx_d4+ outx_d4- 0v inx_d3+ inx_d3- rx outx_d3+ outx_d3- inx_d2+ inx_d2- rx outx_d2+ outx_d2- inx_d1+ inx_d1- rx outx_d1+ outx_d1- hpd hpd_source hpd_sink hpd (times 2) 0v 0v 0v ddc_en (0v to 3.3v) scl_source sda_source scl_sink sda_sink x = 1 or 2 08-0294
3 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter storage temperature.....................................?65c to +150c supply voltage to ground potential.............?0.5v to +5v dc input voltage..........................................?0.5v to v dd dc output current .......................................120ma power dissipation .........................................1.0w note: stresses greater than those listed under max i mum rat ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to absolute max i mum rating con di tions for extended periods may affect re li abil i ty. maximum ratings (above which useful life may be im- paired. for user guide lines, not tested.) table 2: signal descriptions pin name type description oe# 5.5v tolerant low-voltage single-ended input enable for level shifter path oe# in_d termination out_d outputs 1 >100k high-z 050 active in_d4+ differential input low-swing diff input from gmch pcie outputs. in_d4+ makes a differential pair with in_d4?. in_d4? differential input low-swing diff input from gmch pcie outputs. in_d4? makes a differential pair with in_d4+. in_d3+ differential input low-swing diff input from gmch pcie outputs. in_d3+ makes a differential pair with in_d3?. in_d3? differential input low-swing diff input from gmch pcie outputs. in_d3? makes a differential pair with in_d3+. in_d2+ differential input low-swing diff input from gmch pcie outputs. in_d2+ makes a differential pair with in_d2?. in_d2? differential input low-swing diff input from gmch pcie outputs. in_d2? makes a differential pair with in_d2+. in_d1+ differential input low-swing diff input from gmch pcie outputs. in_d1+ makes a differential pair with in_d1?. in_d1? differential input low-swing diff input from gmch pcie outputs. in_d1? makes a differential pair with in_d1+. out_d4+ tmds differential output hdmi 1.3 compliant tmds output. out_d4+ makes a differential output signal with out_d4?. out_d4? tmds differential output hdmi 1.3 compliant tmds output. out_d4? makes a differential output signal with out_d4+. out_d3+ tmds differential output hdmi 1.3 compliant tmds output. out_d3+ makes a differential output signal with out_d3?. out_d3? tmds differential output hdmi 1.3 compliant tmds output. out_d3? makes a differential output signal with out_d3+. (continued) 08-0294
4 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter pin name type description out_d2+ tmds differential output hdmi 1.3 compliant tmds output. out_d2+ makes a differential output signal with out_d2?. out_d2? tmds differential output hdmi 1.3 compliant tmds output. out_d2? makes a differential output signal with out_d2+. out_d1+ tmds differential output hdmi 1.3 compliant tmds output. out_d1+ makes a differential output signal with out_d1?. out_d1? tmds differential output hdmi 1.3 compliant tmds output. out_d1? makes a differential output signal with out_d1+. hpd_sink 5v tolerance single-ended input low frequency, 0v to 5v (nominal) input signal. this signal comes from the hdmi connector. voltage high indicates "plugged" state; voltage low indicated "unplugged". hpd_sink is pulled down by an integrated 100k ohm put-down resistor. hpd_source 3.3v single-ended output hpd_source: 0v to 3.3v (nominal) output signal. this is level-shifted version of the hpd_sink signal. scl_source single-ended 3.3v open-drain ddc i/o 3.3v ddc data i/o. pulled up by external termina- tion to 3.3v. connected to scl_sink through volt- age-limiting integrated nmos passgate. sda_source single-ended 3.3v open-drain ddc i/o 3.3v ddc data i/o. pulled up by external termination to 3.3v. connected to sda_sink through voltage- limiting integrated nmos passgate. scl_sink single-ended 5v open-drain ddc i/o 5v ddc clock i/o. pulled up by external termination to 5v. connected to scl_source through voltage- limiting integrated nmos passgate. sda_sink single-ended 5v open-drain ddc i/o 5v ddc data i/o. pulled up by external termination to 5v. connected to sda_source through voltage- limiting integrated nmos passgate. ddc_en 5.0v tolerant single-ended input enables bias voltage to the ddc passgate level shifter gates. (may be implemented as a bias voltage connec- tion to the ddc pass gates themselves.) ddc_en passgate 0v disabled 3.3v enabled vdd 3.3v dc supply 3.3v 10% oc_2 (rext) 3.3v single-ended control input acceptable connections to oc_1 (rext) pin are: re- sistor to gnd; resistor to 3.3v; nc. (resistor should be 0-ohm). 08-0294
5 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter pin name type description oc_3 analog connection to external component or supply acceptable connections to oc_3 pin are: short to 3.3v or to gnd; nc. oc_0 oc_1 eq_0 eq_1 output and input jitter elimina- tion control control pins are to enable jitter elimination features. for normal operation these pins are tied gnd or to vdd. please see the truth tables for more information. truth table 1 oc_3 (2) oc_2 (1) oc_1 (1) oc_0 (1) vswing (mv) pre/de- emphasis 0 0 0 0 500 0 0 0 0 1 600 0 0 0 1 0 750 0 0 0 1 1 1000 0 0 1 0 0 500 0 0 1 0 1 500 1.5db 0 1 1 0 500 3.5db 0 1 1 1 500 6db 1 0 0 0 400 0 1 0 0 1 400 3.5db 1 0 1 0 400 6db 1 0 1 1 400 9db 1 1 0 0 1000 0 1 1 0 1 1000 -3.5db 1 1 1 0 1000 -6db 1 1 1 1 1000 -9db truth table 2 eq_1 (2) eq_0 (1) equalization @ 1.25ghz (db) 003 016 109 111 2 notes: 1) these signals have internal 100k pull-ups. 2) for 42-tqfn package, these signals are internally connected to gnd directly. for 48-tqfn package, these signals have internal 100k pull-ups, with external connection. 08-0294
6 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter electrical characteristics table 3: power supplies and temperature range symbol parameter min nom max units comments vdd 3.3v power supply 3.0 3.3 3.6 v icc max current 100 ma total current from vdd 3.3v supply when de-emphasis/ pre-emphasis is set to 0db. iccq standby cur- rent consump- tion 2ma oe# = high tcase case tempera- ture range for operation with spec. -40 85 celcius table 4: oe# description oe# device state comments asserted (low voltage) differential input buffers and output buffers enabled. input impedance = 50 normal functioning state for in_d to out_d level shifting function. unasserted (high voltage) low-power state. differential input buffers and termina- tion are disabled. differential inputs are in a high-impedance state. out_d level-shifting outputs are disabled. out_d level-shifting outputs are in high-impedence state. internal bias currents are turned off. intended for lowest power condi- tion when: ? no display is plugged in or ? the level shifted data path is disabled hpd_sink input and hpd_source output are not affected by oe# scl_ source, scl_sink, sda_source and sda_sink signals and functions are not affected by oe# 08-0294
7 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter table 5: differential input characteristics for in_d and rx_in signals symbol parameter min nom max units comments tbit unit interval 360 ps tbit is determined by the display mode. nom- inal bit rate ranges from 250mbps to 2.5gbps per lane. nominal tbit at 2.5 gbps=400ps. 360ps=400ps-10% v rx-diffp-p differential input peak to peak voltage 0.175 1.200 v vrx-diffp-p=2'|vrx-d+ x vrx-d-| applies to in_d and rx_in signals t rx-eye minimum eye width at in_d input pair 0.8 tbit the level shifter may add a maximum of 0.02ui jitter v cm-ac-pp ac peak common mode input voltage 100 mv vcm-ac-pp = |vrx-d+ + vrx-d-|/2 - vrx-cm-dc. vrx-cm-dc = dc(avg) of|vrx-d+ + vrx-d-|/2 vcm-ac-pp includes all frequencies above 30 khz. z rx-dc 40 50 60 required in_d+ as well as in_d- dc impedance (50 20% tolerance). v rx-bias 0 2.0 v intended to limit power-up stress on chipset's pcie output buffers. z rx-high-z 100 k differential inputs must be in a high im- pedance state when oe# is high. 08-0294
8 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter symbol parameter min nom max units comments v h single-ended high level output voltage vdd-10mv vdd vdd+10mv v vdd is the dc termination voltage in the hdmi or dvi sink. vdd is nominally 3.3v v l single-ended low level output voltage vdd-600mv vdd-500mv vdd-400mv v the open-drain output pulls down from vdd. v swing single-ended output swing voltage 450mv 500mv 600mv v swing down from tmds termination voltage (3.3v 10%) i off single-ended current in high-z state 50 a measured with tmds out- puts pulled up to vdd max _(3.6v) through 50: resistors. t r rise time 125ps 0.4tbit ps max rise/fall time @2.7gbps = 148ps. 125ps = 148-15% t f fall time 125ps 0.4tbit ps max rise/fall time @2.7gbps = 148ps. 125ps = 148-15% t skew-intra intra-pair differential skew 30 ps this differential skew bud- get is in addition to the skew presented between d+ and d- paired input pins. hdmi revision 1.3 source allowable intra-pair skew is 0.15tbit. t skew-inter inter-pair lane- to-lane output skew 100 ps this lane-to-lane skew budget is in addition to skew between differential input pairs t jit jitter added to tmds signals 25 ps jitter budget for tmds signals as they pass through the level shifter. 25ps = 0.056 tbit at 2.25 gb/s tmds outputs the level shifter's tmds outputs are required to meet hdmi 1.3 speci cations. the hdmi 1.3 speci cation is assumed to be the correct reference in instances where this document con icts with the hdmi 1.3 speci cation. table 6: differential output characteristics for tmds_out signals 08-0294
9 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter tmds output oscillation elimination the inputs do not incorporate a squelch circuit. therefore, we reccomend the input to be externally biased to prevent output oscillation. pericom reccomends to add a 1.5kohm pull-up to the clk- input. tmds input fail-safe recommendation 1.5kohm r int vbias r int dmdp receiver tmds driver s s s s r t r t av dd 3.3v 08-0294
10 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter table 8: hpd input characteristics symbol parameter min nom max units comments v ih-hpd input high level 2.0 5.0 5.3 v low-speed input changes state on cable plug/unplug v il-hpd hpd_sink input low level 0 0.8 v i in-hpd hpd_sink input leakage current 70 a measured with hpd_sink at v ih-hpd max and v il-hpd min v oh-hpdb hpd_sink output high-level 2.5 v dd vv dd = 3.3v 10% v ol-hpdb hpd_sink output low-level 0 0.02 v t hpd hpd_sink to hpd_source propagation delay 200 ns time from hpd_sink changing state to hpd_source changing state. in- cludes hpd_source rise/fall time t rf-hpdb hpd_source rise/ fall time 1 20 ns time required to transition from v oh- hpdb to v ol-hpdb or from v ol-hpdb to v oh-hpdb table 9: oe# input and ddc_en symbol parameter min nom max units comments v ih input high level 2.0 vdd v tmds enable input changes state on cable plug/unplug v il input low level 0 0.8 v i in input leakage current 10 a measured with input at v ih-en max and v il-en min table 10: termination resistors symbol parameter min nom max units comments r hpd hpd_sink input pull- down resistor. 80k 100k 120k : guarantees hpd_sink is low when no display is plugged in. 08-0294
11 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter packaging mechanical: 48-pin, tqfn (zd) description: 48-contact, thin fine pitch quad flat no-lead (tqfn) package code: zd (zd48) document control #: pd-2045 revision: c date: 09/11/08 08-0294
12 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter : 48-pin, thin fine pitch quad flat no-lead (tqfn) noitpircsed :edoc egakcap 2080 -dp :# lortnoc tnemucod -- :noisiver 80/31/80 :etad zb48 packaging mechanical: 48-pin, tqfn (zb) 08-0294
13 ps8913d 11/05/08 pi3vdp411ls digital video level shifter from ac coupled digital video input to a dvi/hdmi transmitter ordering information ordering code package code package description pi3vdp411lszbe zbe 48-pin pb-free & green, tqfn pi3vdp411lszde zde 48-pin pb-free & green, tqfn PI3VDP411LSZHE zhe 42--pin pb-free & green, tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? adding an x suf x = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com description: 42-contact thin fine pitch quad flat no-lead (tqfn) package code: zh (zh42) document control #: pd-2035 revision: b date: 03/03/08 08-0098 packaging mechanical: 42 pin, tqfn (zh) 08-0294

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