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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. zvs full-bridge pwm controller with adjustable synchronous rectifier control ISL78223 the ISL78223 is a high-perform ance zero-voltage switching (zvs) full-bridge pwm controller. it achieves zvs operation by driving the upper bridge fets at a fixed 50% duty cycle while the lower bridge fets are trailing-edge modulated with adjustable resonant switching delays. adding to the ISL78223?s feature set are average current monitoring and soft-start. the average current signal may be used for average current limiting, current sharing circuits and average current mode control. additionally, the ISL78223 supports both voltage- and current-mode control. the ISL78223 features complemented pwm outputs for synchronous rectifier (sr) control. the complemented outputs may be dynamically advanced or delayed relative to the pwm outputs using an external control voltage. this advanced bicmos design features precision deadtime and resonant delay control, and an oscillator adjustable to 2mhz operating frequency. additionally, multi-pulse suppression ensures alternating output pulses at low duty cycles where pulse skipping may occur. the ISL78223 is both aec - q100 rated and fully ts16949 compliant. the ISL78223 is rated for the automotive temperature range (-40c to +105c). features ? adjustable resonant delay for zvs operation ? synchronous rectifier control outputs with adjustable delay/advance ? voltage- or current-mode control ? 3% current limit threshold ? adjustable average current limit ? adjustable deadtime control ? 175a start-up current ? supply uvlo ? adjustable oscillator frequency up to 2mhz ? internal over-temperature protection ? buffered oscillator sawtooth output ? fast current sense to output delay ? adjustable cycle-by-cycle peak current limit ? 70ns leading edge blanking ? multi-pulse suppression ? aec - q100 qualified ? pb-free (rohs compliant) applications ? zvs full-bridge converters ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems figure 1. board layout figure 2. efficiency vs load 0.65 0.70 0.75 0.80 0.85 0.90 0.95 10.0 020406080100 efficiency load (0-125a) (%) v o = 13.1v v in = 250v v in = 350v v in = 450v january 2, 2013 fn7936.1
ISL78223 2 fn7936.1 january 2, 2013 functional block diagram pwm steering logic iout uvlo over- temperature protection vref oscillator ct rtd vdd gnd vref + - + - 0.6v 0.33 80mv vref soft-start control vref verr fb 1ma ss cs pwm comparator + - 1.00v overcurrent comparator +70ns leading edge blanking sample and hold 4x ramp ctbuf resdel 50% pwm outll outlr outul outur vdd outlln outlrn delay/ advance timing control vadj
ISL78223 3 fn7936.1 january 2, 2013 typical application - high voltage input prim ary side control zvs full-bridge converter vin+ vin- return t2 r4 c15 400 vdc u1 l1 t1 r2 r6 + vout c16 c1 q2 q3 r16 r15 r18 r17 c11 c5 c4 c3 c2 c14 c13 t3 q5a q5b q8a q8b cr3 cr2 + + q6a q6b q7a q7b vdd r25 r24 c18 c17 u3 tl431 r23 r19 r20 q9a q9b q10a q10b u2 cr1 q1 q4 r1 r3 c7 u5 t4 c12 r7 r8 r9 r10 r21 r22 cr4 q12 q13 el7212 el7212 c6 u4 rtd ss ct outur outul ctbuf outlr resdel ramp outll vdd verr vref cs gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb outlln outlrn 9 10 17 18 vadj bias r5 r11 r12 r13 r14 c8 c9 c10 u1 ISL78223
ISL78223 4 fn7936.1 january 2, 2013 typical application - high voltage input seco ndary side control zvs full-bridge converter vin+ vin- return t2 r4 c2 400 vdc u1 l1 t1 np:ns:ns=9:2:2 r2 r12 + vout c15 c1 q2 q3 r18 r17 r20 r19 c5 c3 c12 c14 c13 t3 1:1:1 q5 cr3 cr2 + + secondary bias supply r25 r24 c17 c16 u3 r23 q9a q9b q10a q10b cr1 q1 q4 r1 r3 c4 r10 r6 q16 q15 c9 q12a q12b q11a q11b r16 cr5 r15 cr4 q13a q13b q14a q14b q7a q7b c10 q8a q8b q6 t4 1:1:1 c11 np ns ns c8 + - vref r22 r21 c18 vref rtd ss ct outur outul ctbuf outlr resdel ramp outll vdd verr vref cs gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb outlln outlrn 9 10 17 18 vadj r5 r7 r8 r9 r11 r13 r14 cr6 c6 c7 ISL78223
ISL78223 5 fn7936.1 january 2, 2013 pin configuration ISL78223 (20 ld qsop) top view rtd ss ct outur outul ctbuf outlr resdel ramp outll vdd verr vref cs gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 iout fb outlln outlrn 9 10 17 18 vadj pin descriptions pin number symbol description 1 vref the 5.00v reference voltage output having 3% tolerance over line, load and operating temperature. bypass to gnd with a 0.1f to 2.2f low esr capacitor. 2 verr the control voltage input to the inverting input of the pwm comparator. the output of an external error amplifier (ea) is applied to this input, either directly or through an opto-coupler, for closed loop regulation. verr has a nominal 1ma pull-up current source. when verr is driven by an opto-coupler or other current source device, a pull-up resistor from vref is required to linearize the gain. generally, a pull-up resistor on the order of 5k ? is acceptable. 3 ctbuf ctbuf is the buffered output of the sawtooth oscillator waveform present on ct and is capable of sourcing 2ma. it is offset from ground by 0.40v and has a nominal valley-to-peak gain of 2. it may be used for slope compensation. 4 rtd this is the oscillator timing capacitor discharge current control pin. the current flowing in a resistor connected between this pin and gnd determines the magnitude of the current that discharges ct. the ct discharge current is nominally 20x the resistor current. the pwm deadtime is determined by the timing capacitor discharge duration. the voltage at rtd is nominally 2.00v. 5 resdel sets the resonant delay period between the toggle of the upper fets and the turn on of either of the lower fets. the voltage applied to resdel determines when the upper fets switch relative to a lower fet turning on. varying the control voltage from 0 to 2.00v increases the resonant delay duration from 0 to 100% of the deadtime. the control voltage divided by 2 represents the percent of the deadtime equal to the resonant delay. in practice the maximum resonant delay must be set lower than 2.00v to ensure that the lower fets, at maximum duty cycle, are off prior to the switching of the upper fets. 6 ct the oscillator timing capacitor is connected between this pin and gnd. it is charged through an internal 200 a current source and discharged with a user adjustable current source controlled by rtd 7 fb fb is the inverting inputs to the error amplifier (ea). the amplifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (iea). if the amplifier is not used, fb should be grounded. 8 ramp this is the input for the sawtooth waveform for th e pwm comparator. the ramp pin is shorted to gnd at the termination of the pwm signal. a sawtooth volt age waveform is required at this input. for current-mode control this pin is connected to cs and th e current loop feedback signal is applied to both inputs. for voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, ramp may be connected to the input voltage through a rc network for voltage feed forward control, or ramp may be connected to vref through a rc network to produce the desired sawtooth waveform. 9 cs this is the input to the overcurrent comparator. th e overcurrent comparator threshold is set at 1.00v nominal. the cs pin is shorted to gnd at the termination of either pwm output. depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. this delay may result in cs being discharged prior to the power switching device being turned off.
ISL78223 6 fn7936.1 january 2, 2013 10 iout output of the 4x buffer amplifier of the sample and hold circuitry that captures and averages the cs signal. 11 gnd signal and power ground connections for this devi ce. due to high peak currents and high frequency operation, a low impedance layout is necessary. ground planes and short traces are highly recommended. 13, 12 outlln, outlrn these outputs are the complements of the pwm (lower) bridge fe ts. outlln is the complement of outll and outlrn is the complement of outlr. these outputs are suitable for control of synchronous rectifiers. the phase relationship between each output and its complement is controlled by the voltage applied to vadj. 15, 14 outul, outur these outputs control the upper bridge fets and operate at a fixed 50% duty cycle in alternate sequence. outul controls the upper left fet and outur controls the upper right fet. the left and right designation may be switched as long as they are switched in conjunction with the lower fet outputs, outll and outlr. 17, 16 outll, outlr these outputs control the lower bridge fets, are pulse width modulated, and operate in alternate sequence. outll controls the lower left fet and outlr controls the lower right fet. the left and right designation may be switched as long as they are sw itched in conjunction with the upper fet outputs, outul and outur. 18 vdd v dd is the power connection for the ic. to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the v dd and gnd pins as possible. vdd is monitored for supply voltage undervoltage lock -out (uvlo). the start and stop thresholds track each other resulting in relatively constant hysteresis. 19 vadj a 0v to 5v control voltage applied to this input sets the relative delay or advance between outll/outlr and outlln/outlrn. the phase relationship betw een outul/outur and outll/outlr is maintained regardless of the phase adjustment be tween outll/outlr and outlln/outlrn. the range of phase delay/advance is either zero or 40 to 300ns with the phase differential increasing as the voltage deviation from 2.5v increases. the re lationship between the control voltage and phase differential is non-linear. the gain ( t/ v) is low for control voltages ne ar 2.5v and rapidly increases as the voltage approaches the extremes of the control range. this behavior prov ides the user increased accuracy when selecting a shorter delay/advance duration. when the pwm outputs are delayed relative to the sr outputs (vadj < 2.425v), the delay time should not exceed 90% of the deadtime as determined by rtd and ct. 20 ss connect the soft-start timing capacitor between this pin and gnd to control the duration of soft-start. the value of the capacitor and the internal current source determine the rate of increase of the duty cycle during start-up. ss may also be used to inhibit the outputs by gr ounding through a small transistor in an open collector/drain configuration. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL78223aaz 78223 aaz -40 to +105 20 ld qsop m20.15 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs comp liant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed th e pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78223 . for more information on msl, please see tech brief tb363 .
ISL78223 7 fn7936.1 january 2, 2013 absolute maximum rating s thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +22.0v outxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref + 0.3v v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1a esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101e). . . . . . . . . . . . . . 1kv latchup rating (tested per jesd78b; class ii, level a) . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 20 lead qsop (notes 4, 5) . . . . . . . . . . . . . 88 48 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . 9vdc to 16vdc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. 6. all voltages are with respect to gnd. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and ?typical application? schematics beginning on page 3. 9v < v dd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions min (note 11) typ max (note 11) units supply voltage supply voltage -- 20 v start-up current, i dd v dd = 5.0v - 175 400 a operating current, vdd 12v, i dd v dd = 12v, load = 0, c out = 0 - 12 17 ma uvlo start threshold 8.00 8.75 9.00 v uvlo stop threshold 6.50 7.00 7.50 v hysteresis -1.75-v reference voltage overall accuracy i vref = 0ma to 10ma 4.78 5.00 5.19 v long term stability t a = +125c, 1000 hours (note 7) - 3 - mv load current (sourcing) (note 7) 10 --ma load current (sinking) 3.70 --ma current limit (sourcing) v ref = 4.85v 12 - 120 ma current sense current limit threshold verr = v ref 0.90 1.00 1.14 v cs to out delay excluding leb - 35 - ns leading edge blanking (leb) duration - 70 - ns cs to out delay + leb t a = +25c - - 150 ns cs sink current device impedance v cs = 1.1v - - 20 ? input bias current v cs = 0.3v -1.0 - 1.0 a i out sample and hold buffer amplifier gain t a = +25c 3.85 4.00 4.15 v/v i out sample and hold voh v cs = max, i source = 300a 3.9 --v i out sample and hold vol v cs = 0.00v, i sink = 10a - - 0.3 v
ISL78223 8 fn7936.1 january 2, 2013 ramp ramp sink current device impedance v ramp = 1.1v - - 20 ? ramp to pwm comparator offset t a = +25c (note 7) 65 80 95 mv bias current (sinking) v ramp = 0.3v 2 - 5 a pulse width modulator minimum duty cycle verr < 0.6v (note 7) - - 0 % maximum duty cycle (per half-cycle) verr = 4.20v, v cs = 0v (note 8) - 94 - % rtd = 2.00k ? , ct = 220pf - 97 - % rtd = 2.00k ? , ct = 470pf - 99 - % zero duty cycle verr voltage 0.85 - 1.20 v verr to pwm comparator input offset t a = +25c 0.7 0.8 0.9 v verr to pwm comparator input gain 0.31 0.33 0.35 v/v common mode (cm) input range (note 7) 0 - 4.45 v error amplifier input common mode (cm) range (note 7) 0 -v ref v gbwp (note 7) 5 --mhz verr vol i load_sink = 2ma 0.2 0.4 v verr voh i load = 0ma 3.8 4.5 - v verr pull-up current source (sinking) verr = 2.5v 0.8 1.0 1.3 ma ea reference t a = +25c (note 7) 0.594 0.600 0.606 v ea reference + ea input offset voltage 0.590 0.600 0.612 v oscillator frequency accuracy, overall (note 7) 165 183 201 khz -10 - 10 % frequency variation with v dd t a = +25c, (f20v- - f10v)/f10v - 0.3 1.7 % temperature stability v dd = 10v, |f-40c - f0c|/f0c - 4.5 - % |f0c - f105c|/f25c (note 7) - 1.5 - % charge current (sourcing) t a = +25c 184 200 215 a discharge current gain 17 21 24 a/a ct valley voltage static threshold 0.75 0.80 0.88 v ct peak voltage static threshold 2.73 2.80 2.88 v ct pk-pk voltage static value 1.92 2.00 2.05 v rtd voltage 1.94 2.00 2.07 v resdel voltage range 0 - 2.00 v ctbuf gain (v ctbufp-p /v ctp-p )v ct = 0.8v, 2.6v 1.95 2.0 2.05 v/v ctbuf offset from gnd v ct = 0.8v 0.34 0.40 0.45 v ctbuf voh v(i load = 0ma, i load = 2ma), v ct = 2.6v - - 0.10 v ctbuf vol v(i load = 2ma, i load = 0ma), v ct = 0.8v - - 0.10 v electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and ?typical application? schematics beginning on page 3. 9v < v dd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 11) typ max (note 11) units
ISL78223 9 fn7936.1 january 2, 2013 soft-start charging current (sourcing) ss = 3v 55 70 81 a ss clamp voltage 4.4 4.500 4.65 v ss discharge current ss = 2v 10 30 - ma reset threshold voltage t a = +25c 0.23 0.27 0.33 v output high level output voltage (voh) i out = 10ma, v dd - voh - 0.5 1.0 v low level output voltage (vol) i out = -10ma, vol - gnd - 0.3 1.0 v rise time c out = 220pf, v dd = 15v (note 7) - 110 200 ns fall time c out = 220pf, v dd = 15v (note 7) - 90 150 ns uvlo output voltage clamp v dd = 7v, i load = 1ma (note 9) - - 1.25 v output delay/advance range outlln/outlrn relative to outll/outlr v adj = 2.50v (note 7) - 2 - ns v adj < 2.425v (note 7) -40 - -300 ns v adj > 2.575v (note 7) 40 - 300 ns delay/advance control voltage range outlln/outlrn relative to outll/outlr outlxn delayed (note 7) 2.575 - 5.000 v outlxn advanced (note 7) 0 - 2.425 v v adj delay time t a = +25c (outlx delayed) (note 10) v adj = 0 - 300 - ns v adj = 0.5v - 105 - ns v adj = 1.0v - 70 - ns v adj = 1.5v - 55 - ns v adj = 2.0v - 50 - ns t a = +25c (outlxn delayed) v adj = v ref - 300 - ns v adj = v ref - 0.5v - 100 - ns v adj = v ref - 1.0v - 68 - ns v adj = v ref - 1.5v - 55 - ns v adj = v ref - 2.0v - 48 - ns thermal protection thermal shutdown (note 7) - 140 - c thermal shutdown clear (note 7) - 125 - c hysteresis, internal protection (note 7) - 15 - c notes: 7. limits established by characteriza tion and are not production tested. 8. this is the maximum duty cycle achievable using the specified va lues of rtd and ct. larger or smaller maximum duty cycles may be obtained using other values for these componen ts. see equations 1 through 3. 9. adjust v dd below the uvlo stop threshold prior to setting at 7v. 10. when outlx is delayed relative to outlxn (v adj < 2.425v), the delay duration as set by v adj should not exceed 90% of the ct discharge time (deadtime) as determ ined by ct and rtd. 11. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and ?typical application? schematics beginning on page 3. 9v < v dd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 11) typ max (note 11) units
ISL78223 10 fn7936.1 january 2, 2013 typical performance curves figure 3. reference voltage vs temperature figur e 4. ct discharge curren t gain vs rtd current figure 5. deadtime (dt) vs capacita nce figure 6. capacitance vs frequency -40 -25 -10 5 20 35 50 65 80 95 110 0.98 0.99 1 1.01 1.02 temperature (c) normalized v ref 0 200 400 600 800 1000 18 19 20 21 22 23 24 25 rtd current (a) ct discharge current gain 0 102030405060708090100 10 100 rtd (k ) deadtime td (ns) 1-10 4 1-10 3 ct = 1000pf ct = 680pf ct = 470pf ct = 100pf ct = 220pf ct = 330pf ct = 1000pf ct = 680pf ct = 470pf ct = 100pf ct = 220pf ct = 330pf 0.1 1 10 10 100 ct (nf) frequency (khz) 1-10 3 rtd = 100k ? rtd = 50k ? rtd = 10k ?
ISL78223 11 fn7936.1 january 2, 2013 functional description features the ISL78223 pwm is an excellent choice for low cost zvs full-bridge applications requiring adjustable synchronous rectifier drive. with its many protection and control features, a highly flexible design with minimal external components is possible. among its many features are a ve ry accurate overcurrent limit threshold, thermal protection, a buffered sawtooth oscillator output suitable for slope comp ensation, synchronous rectifier outputs with variable delay/ad vance timing, and adjustable frequency. oscillator the ISL78223 has an oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor and capacitor. the switching period is the sum of the timing capacitor charge and discharge durations. the charge duration is determined by ct and a fixed 200a internal current source. the discharge duration is determined by rtd and ct. where t c and t d are the charge and discharge times, respectively, ct is the timing capacitor in farads, rtd is the discharge programming resistance in ohms, t sw is the oscillator period, and f sw is the oscillator frequency. one output switching cycle requires two oscillator cycles. the actual times will be slightly longer than calculated du e to internal propagation delays of approximately 10ns/transition. this delay adds directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley volt age thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. additionally, if very small discharge currents are used, there will be increased error due to the input impedance at the ct pin. the maximum recommended current through rtd is 1ma, which produces a ct discharge current of 20ma. the maximum duty cycle, d, and percent deadtime, dt, can be calculated from: overcurrent operation two overcurrent protection mechanisms are available to the power supply designer. the first method is cycle-by-cycle peak overcurrent protection which provides fast response. the cycle-by- cycle peak current limit results in pulse-by-pulse duty cycle reduction when the cu rrent feedback signal exceeds 1.0v. when the peak current exceeds the thresh old, the active output pulse is immediately terminated. this results in a decrease in output voltage as the load current increases beyond the current limit threshold. the ISL78223 operates continuously in an overcurrent condition without shutdown. the second method is a slower, averaging method which produces constant or ?brick-wa ll? current limit behavior. if voltage-mode control is used, the average overcurrent protection also maintains flux balance in the transformer by maintaining duty cycle symmetry between half-cycles. if voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstab le operation. the dc blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. average current limit will prevent the instability and allow continuous operation in current limit provided the control loop is designed with adequate bandwidth. the propagation delay from cs exceeding the current limit threshold to the termination of th e output pulse is increased by the leading edge blanking (leb) interval. the effective delay is the sum of the two delays and is nominally 105ns. the current sense signal applied to the cs pin connects to the peak current comparator and a sample and hold averaging circuit. after a 70ns leading edge blanking (leb) delay, the current sense signal is actively sampled during the on time, the average current for the cycle is determined, and the result is amplified by 4x and output on the i out pin. if an rc filter is placed on the cs input, its ti me constant should not exceed ~50ns or significant error may be introduced on i out . figure 7 shows the relationship between the cs signal and i out under steady state conditions. i out is 4x the average of cs. figure 8 shows the dynamic behavior of the current averaging circuitry when cs is modulated by an external sine wave. notice i out is updated by the sample and hold circuitry at the termination of the active output pulse. t c 11.5 10 ? 3 ct ? s (eq. 1) t d 0.06 rtd ct ?? () 50 10 9 ? ? + s (eq. 2) t sw t c t d + 1 f sw ------------ == s (eq. 3) d t c t sw ------------ = (eq. 4) dt 1 d ? = (eq. 5) figure 7. cs input vs i out channel 1 (yellow): outll channel 3 (blue): cs channel 2 (red): outlr channel 4 (green): iout
ISL78223 12 fn7936.1 january 2, 2013 the average current signal on i out remains accurate provided the output inductor current rema ins continuous (ccm operation). once the inductor current becomes discontinuous (dcm operation), i out represents 1/2 the peak inductor current rather than the average current. this occurs because the sample and hold circuitry is active only duri ng the on time of the switching cycle. it is unable to detect when the inductor current reaches zero during the off time. if average overcurrent limit is desired, i out may be used with the error amplifier of the ISL78223. typically i out is divided down and filtered as required to achieve the desired amplitude. the resulting signal is input to the current error amplifier (iea). the iea is similar to the voltage ea found in most pwm controllers, except it cannot source current. instead, verr has a separate internal 1ma pull-up current source. configure the iea as an integrat ing (type i) amplifier using the internal 0.6v reference. the volt age applied at fb is integrated against the 0.6v reference. the re sulting signal, verr, is applied to the pwm comparator where it is compared to the sawtooth voltage on ramp. if fb is less than 0.6v, the iea will be open loop (can?t source current), verr will be at a level determined by the voltage loop, and the duty cycle is unaffected. as the output load increases, i out will increase, and the voltage applied to fb will increase until it reaches 0.6v. at this point the iea will reduce verr as required to maintain the output current at the level that corresponds to the 0.6v reference. when the output current again drops below the average current limit threshold, the iea returns to an open loop condition, and the duty cycle is again controlled by the voltage loop. the average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. the ea available on the isl78 223 may also be used as the voltage ea for the voltage feedback control loop rather than the current ea as described above. an external op-amp may be used as either the current or voltage ea providing the circuit is not allowed to source current into ve rr. the external ea must only sink current, which may be accomplished by adding a diode in series with its output. the 4x gain of the sample and ho ld buffer allows a range of 150 - 1000mv peak on the cs signal, de pending on the resistor divider placed on i out . the overall bandwidth of the average current loop is determined by the integratin g current ea compensation and the divider on i out . the current ea cross-over frequency, assuming r6 >> (r4||r5), is: where f co is the cross-over frequency. a capacitor in parallel with r4 may be used to provide a double-pole roll-off. the average current loop bandwidth is normally set to be much less than the switching frequency, typically less than 5khz and often as slow as a few hundred he rtz or less. this is especially useful if the application experiences large surges. the average current loop can be set to the steady state overcurrent threshold and have a time response that is longer than the required transient. the peak current limi t can be set higher than the expected transient so that it does not interfere with the transient, but still protects for short-term la rger faults. in essence a 2-stage overcurrent response is possible. the peak overcurrent behavior is similar to most other pwm controllers. if the peak current exceeds 1.0v, the active output pulse is terminated immediately. if voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstable operation. dc blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. the average over current circuitry prevents this behavior by maintaining symmetric duty cycles for each half- cycle. if the average current limit circuitry is not used, a latching overcurrent shutdown method using external components is recommended. the cs to output propagation delay is increased by the leading edge blanking (leb) interval. the effective delay is the sum of the two delays and is 130ns maximum. figure 8. dynamic behavior of cs vs i out channel 1 (yellow): outll channel 3 (blue): cs channel 2 (red): outlr channel 4 (green): iout figure 9. average overcurrent implementation ss outur outul outlr outll vdd vref gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 n/c gnd 9 10 17 18 150 - 1000mv + - 0.6v s&h 4x r6 r5 r4 c10 cs fb iout verr ISL78223 f co 1 2 r6 c10 ?? ----------------------------------- = hz (eq. 6)
ISL78223 13 fn7936.1 january 2, 2013 voltage feed forward operation voltage feed forward is a technique used to regulate the output voltage for changes in input volt age without the intervention of the control loop. voltage feed forward is implemented in voltage- mode control loops, but is redundant and unnecessary in peak current-mode control loops. voltage feed forward operates by modulating the sawtooth ramp in direct proportion to the input voltage. figure 10 demonstrates the concept. input voltage feed forward may be implemented using the ramp input. an rc network connected between the input voltage and ground, as shown in figure 11, generates a voltage ramp whose charging rate varies with the amp litude of the source voltage. at the termination of the active output pulse, ramp is discharged to ground so that a repetitive sawtooth waveform is created. the ramp waveform is compared to the verr voltage to determine duty cycle. the selection of the rc components depends upon the desired input voltage operating range and the frequency of the oscillator. in typical applic ations, the rc components are selected so that the ramp ampl itude reaches 1.0v at minimum input voltage within the du ration of one half-cycle. the charging time of the ramp capacitor is: for optimum performance, the maximum value of the capacitor should be limited to 10nf. the maximum dc current through the resistor should be limited to 2m a maximum. for example, if the oscillator frequency is 400khz, the minimum input voltage is 300v, and a 4.7nf ramp capacitor is selected, the value of the resistor can be determined by rearranging equation 7. where t is equal to the oscillator period minus the deadtime. if the deadtime is short relative to the oscillator period, it can be ignored for this calculation. if feed forward operation is not desired, the rc network may be connected to v ref rather than the input voltage. alternatively, a resistor divider from ctbuf may be used as the sawtooth signal. regardless, a sawtooth waveform must be generated on ramp as it is required for proper pwm operation. gate drive the ISL78223 outputs are capable of sourcing and sinking 10ma (at rated voh, vol) and are intended to be used in conjunction with integrated fet drivers or discrete bipolar totem pole drivers. the typical on resistance of the outputs is 50 ? . slope compensation peak current-mode control requires slope compensation to improve noise immunity, particularly at lighter loads, and to prevent current loop instability, particularly for duty cycles greater than 50%. slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. adding the external ramp to the current feedback signal is the more popular method. from the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, fm, without slope compensation, is: where sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes: where se is slope of the external ramp and figure 10. voltage feed forward behavior vin error voltage ramp ct outll, lr r3 c7 ramp gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 ISL78223 9 10 17 18 vin figure 11. voltage feed forward control tr3c71 v ramp peak () v in min () --------------------------------------- - ? ?? ?? ?? ln ?? ? = s (eq. 7) r3 t ? c7 1 v ramp peak () v in min ) () --------------------------------------- - ? ?? ?? ?? ln ? ------------------------------------------------------------------------- 2.5 ? 10 6 ? ? 4.7 10 9 ? 1 1 300 --------- - ? ?? ?? ln ?? ------------------------------------------------------------ == 159 = k (eq. 8) fm 1 sntsw ------------------- - = (eq. 9) fm 1 sn se + () tsw -------------------------------------- - 1 m c sntsw ---------------------------- == (eq. 10) m c 1 se sn ------- + = (eq. 11)
ISL78223 14 fn7936.1 january 2, 2013 the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at half the oscillator frequency. the double-pole will be critically damped if the q-factor is set to 1, and over-damped for q > 1, and under-damped for q < 1. an under-damped condition can result in current loop instability. where d is the percent of on time during a half cycle. setting q = 1 and solving for s e yields: since s n and s e are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal during the on time and v e is the voltage that must be added by the external ramp. v n can be solved for in terms of input voltage, current transducer components, and output inductance yielding: where r cs is the current sense burden resistor, n ct is the current transformer turns ratio, l o is the output inductance, v o is the output voltage, and n s and n p are the secondary and primary turns, respectively. the inductor current, when reflected through the isolation transformer and the current sens e transformer to obtain the current feedback signal at the sense resistor yields: where v cs is the voltage across the current sense resistor and i o is the output current at current limit. since the peak current limit thresh old is 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value. substituting equations 15 and 16 into equation 17 and solving for r cs yields: for simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. magnetizing inductance provides a degree of slope compensation to the current feedback signal and reduces the amount of external ramp requir ed. the magnetizing inductance adds primary current in excess of what is reflected from the inductor current in the secondary. where v in is the input voltage that corresponds to the duty cycle d and l m is the primary magnetizing inductance. the effect of the magnetizing current at the current sense resistor, r cs , is: if v cs is greater than or equal to v e , then no additional slope compensation is needed and r cs becomes: if v cs is less than ve, then equation 16 is still valid for the value of r cs , but the amount of slope compensation added by the external ramp must be reduced by v cs . adding slope compensation may be accomplished in the ISL78223 using the ctbuf sign al. ctbuf is an amplified representation of the sawtooth sign al that appears on the ct pin. it is offset from ground by 0. 4v and is 2x the peak-to-peak amplitude of ct (0.4v to 4.4v). a typical application sums this signal with the current sense fee dback and applies the result to the cs pin as shown in figure 12. assuming the designer has selected values for the rc filter placed on the cs pin, the value of r9 required to add the appropriate external ramp can be found by superposition. q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 12) s e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 13) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 14) v e t sw v ? o r cs ? n ct l o ? ----------------------------------------- - n s n p ------- - ? 1 -- - d0.5 ? + ?? ?? = v (eq. 15) v cs n s r cs ? n p n ct ? ------------------------ i o dt ? sw 2l o --------------------- v in n s n p ------- - ? v o ? ?? ?? ?? + ?? ?? ?? = v (eq. 16) v e v cs + 1 = (eq. 17) r cs n p n ct ? n s ------------------------ 1 i o v o l o ------- - t sw 1 -- - d 2 --- - + ?? ?? + ------------------------------------------------------ ? = (eq. 18) i p v in dt sw ? l m ------------------------------- = a (eq. 19) v cs i p r cs ? n ct ------------------------- - = v (eq. 20) r cs n ct n s n p ------- - i o dt sw 2l o ----------------- v in n s n p ------- - ? v o ? ?? ?? ?? ? + ?? ?? ?? ? v in dt sw ? l m ------------------------------- + ------------------------------------------------------------------------------------------------------------------------------- ------ - = (eq. 21) figure 12. adding slope compensation r6 c4 r9 r cs ctbuf ramp cs gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 ISL78223 9 10 17 18 v e v cs ? dv ctbuf 0.4 ? () 0.4 + () r6 ? r6 r9 + ------------------------------------------------------------------------------- = v (eq. 22)
ISL78223 15 fn7936.1 january 2, 2013 rearranging to solve for r9 yields: the value of r cs determined in equation 18 or 21 must be rescaled so that the current sens e signal presented at the cs pin is that predicted by equation 16. the divider created by r6 and r9 makes this necessary. example: v in = 280v v o = 12v l o = 2.0h np/ns = 20 lm = 2mh i o = 55a oscillator frequency, fsw = 400khz duty cycle, d = 85.7% n ct = 50 r6 = 499 ? solve for the current sense resistor, r cs , using equation 18. r cs = 15.1 ? . determine the amount of voltage, v e , that must be added to the current feedback signal using equation 15. ve = 153mv next, determine the effect of the magnetizing current from equation 20. v cs = 91mv using equation 23, solve for the summing resistor, r9, from ctbuf to cs. r9 = 30.1k ? determine the new value of r cs , r? cs , using equation 24. r? cs = 15.4 ? the above discussion determines the minimum external ramp that is required. additional slope compensation may be considered for design margin. if the application requires dead time less than about 500ns, the ctbuf signal may not perform adequately for slope compensation. ctbuf lags the ct sawtooth waveform by 300ns to 400ns. this behavior results in a non-zero value of ctbuf when the next half-cycle begins when the deadtime is short. under these situations, slope compensation may be added by externally buffering the ct signal as shown in figure 13. using ct to provide slope co mpensation instead of ctbuf requires the same calculations, except that equations 22 and 23 require modification. equation 22 becomes: and equation 23 becomes: the buffer transistor used to create the external ramp from ct should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base current is required reduces the charging current into ct an d will reduce the oscillator frequency. zvs full-bridge operation the ISL78223 is a full-bridge zero-voltage switching (zvs) pwm controller that behaves much li ke a traditional hard-switched topology controller. rather than drive the diagonal bridge switches simultaneously, the uppe r switches (outul, outur) are driven at a fixed 50% duty cycle and the lower switches (outll, outlr) are pulse width modulated on the trailing edge. r9 dv ctbuf 0.4 ? () v e v cs 0.4 ++ ? () r6 ? v e v cs ? ------------------------------------------------------------------------------------------------------------------ - = (eq. 23) r cs r6 r9 + r9 ---------------------- r cs ? = (eq. 24) figure 13. adding slope compensation using ct r6 c4 r9 r cs ct ct ramp vref cs gnd 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 ISL78223 9 10 17 18 v e v cs ? 2d r6 ? r6 r9 + ---------------------- = v (eq. 25) r9 2d v e v cs + ? () r6 ? v e v cs ? ------------------------------------------------------------ - = (eq. 26)
ISL78223 16 fn7936.1 january 2, 2013 to understand how the zvs method operates, one must include the parasitic elements of the circuit and examine a full switching cycle. in figure 15, the power semiconductor switches have been replaced by ideal switch elements with parallel diodes and capacitance, the output rectifiers are ideal, and the transformer leakage inductance has been incl uded as a discrete element. the parasitic capacitance has been lumped together as switch capacitance, but represents all parasitic capacitance in the circuit including winding capacitanc e. each switch is designated by its position, upper left (ul), upper right (ur), lower left (ll), and lower right (lr). the beginning of the cycle, shown in figure 16, is arbitrarily set as ha ving switches ul and lr on and ur and ll off. the direction of the primary and secondary currents are indicated by i p and i s , respectively. the ul - lr power transfer period terminates when switch lr turns off as determined by the pwm. the current flowing in the primary cannot be interrupted instantaneously, so it must find an alternate path. the current flows into the parasitic switch capacitance of lr and ur which charges the node to vin and then forward biases the body diode of upper switch ur. the primary leakage inductance, l l , maintains the current which now circulates around the path of switch ul, the transformer primary, and switch ur. when switch lr opens, the output inductor current free-wheels thro ugh both output diodes, d1 and d2. during the switch transition , the output inductor current assists the leakage inductance in charging the upper and lower bridge fet capacitance. the current flow from the previous power transfer cycle tends to be maintained during the free -wheeling period because the transformer primary winding is essentially shorted. diode d1 may conduct very little or none of the free-wheeling current, depending on circuit parasitics. this behavior is quite different than what occurs in a conventional hard-switched full-bridge topology where the free-wheeling current splits nearly evenly between the output diodes, and flows not at all in the primary. this condition persists through the remainder of the half-cycle. during the period when ct discharges, also referred to as the deadtime, the upper switches toggle. switch ul turns off and switch ur turns on. the actual timing of the upper switch toggle is dependent on resdel which sets the resonant delay. the voltage applied to resdel determines how far in advance the toggle occurs prior to a lower switch turning on. the zvs transition occurs after the upper switches toggle and before the diagonal lower switch turns on. the required resonant delay is 1/4 of the period of the lc re sonant frequency of the circuit formed by the leakage inductance and the parasitic capacitance. the resonant transition may be estimated from equation 27. where is the resonant transition time, l l is the leakage inductance, c p is the parasitic capacitance, and r is the equivalent resistance in series with l l and c p . the resonant delay is always less than or equal to the deadtime and may be calculated using equation 28. where resdel is the desired resonant delay, v resdel is a voltage between 0v and 2v applied to the resdel pin, and dt is the deadtime (see equations 1 through 5). figure 14. bridge drive signal timing ct deadtime outll outlr outur outul resdel window resonant delay pwm pwm pwm pwm figure 15. idealized full-bridge vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 figure 16. ul - lr power transfer cycle vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 17. ul - ur free-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 2 -- - 1 1 l l c p -------------- - r 2 4l l 2 --------- - ? ----------------------------------- = (eq. 27) resdel v resdel 2 -------------------- dt ? = s (eq. 28)
ISL78223 17 fn7936.1 january 2, 2013 when the upper switches toggle, the primary current that was flowing through ul must find an alternate path. it charges/discharges the parasitic capacitance of switches ul and ll until the body diode of ll is forward biased. if resdel is set properly, switch ll will be turned on at this time. the output inductor does not assist this transition. it is purely a resonant transition driven by the leakage inductance. the second power transfer peri od commences when switch ll closes. with switches ur and ll on, the primary and secondary currents flow as indicated in figure 19. the ur - ll power transfer period terminates when switch ll turns off as determined by the pwm. the current flowing in the primary must find an alternate path. the current flows into the parasitic switch capacitance which charges the node to v in and then forward biases the body diode of upper switch ul. as before, the output inductor current assists in this transition. the primary leakage inductance, l l , maintains the current, which now circulates around the path of switch ur, the transformer primary, and switch ul. when switch l l opens, the output inductor current free-wheels predominantly through diode d1. diode d2 may actually conduct very little or no ne of the free-wheeling current, depending on circuit parasitics. this condition persists through the remainder of the half-cycle. when the upper switches toggle, the primary current that was flowing through ur must find an alternate path. it charges/discharges the parasiti c capacitance of switches ur and lr until the body diode of lr is forward biased. if resdel is set properly, switch lr will be turned on at this time. the first power transfer period commences when switch lr closes and the cycle repeats. the zvs transition requires that the leakage inductance has sufficient energy stored to fully charge the parasitic capacitances. since the energy stored is proportional to the square of the current (1/2 l l i p 2 ), the zvs resonant transition is load depe ndent. if the leakage inductance is not able to store sufficient energy for zvs, a discrete inductor may be added in series with the transformer primary. synchronous rectifier outputs and control the ISL78223 provides double-ended pwm outputs, outll and outlr, and synchronous rectifier (sr) outputs, outlln and outlrn. the sr outputs are the complements of the pwm outputs. it should be noted th at the complemented outputs are used in conjunction with the opposite pwm output, i.e., outll and outlrn are paired togeth er and outlr and outlln are paired together. vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 i s i p figure 18. upper switch togg le and resonant transition vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 figure 19. ur - ll power transfer cycle figure 20. ur - ul free-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 21. upper switch toggle and resonant transition
ISL78223 18 fn7936.1 january 2, 2013 referring to figure 22, the srs alternate between being both on during the free-wheeling portion of the cycle (outll/lr off), and one or the other being off when outll or outlr is on. if outll is on, its corresponding sr must also be on, indicating that outlrn is the correct sr control signal. likewise, if outlr is on, its corresponding sr must also be on , indicating that outlln is the correct sr control signal. a useful feature of the ISL78223 is the ability to vary the phase relationship between the pwm outputs (outll, out lr) and the their complements (outlln, outlrn) by 300ns. this feature allows the designer to compensate for differences in the propagation times between the pwm fets and the sr fets. a voltage applied to v adj controls the phase relationship. setting v adj to v ref /2 results in no delay on any output. the no delay voltage has a 75mv tolerance window. control voltages below the v ref /2 zero delay threshold cause the pwm outputs, outll/lr, to be delayed. control voltages greater than the v ref /2 zero delay threshold cause the sr outputs, outlln/lrn, to be delayed. it should be noted that when the pwm outputs, outll/lr, are delayed, the cs to output propagation delay is increased by the amount of the added delay. the delay feature is provided to compensate for mismatched propagation delays between the pwm and sr outputs as may be experienced when one set of signals crosses the primary-secondary isolation boundary. if required, individual output pulses may be stretched or compressed as required using external resistors, capacitors, and diodes. when the pwm outputs are delayed, the 50% upper outputs are equally delayed, so the resonant delay setting is unaffected. on/off control the ISL78223 does not have a separate enable/disable control pin. the pwm outputs, outll/outlr, may be disabled by pulling verr to ground. doing so reduces the duty cycle to zero, but the upper 50% duty cycle outputs, outul/outur, will continue operation. likewise, the sr outputs outlln/outlrn will be active high. pulling soft-start to ground will disable all outputs and set them to a low condition. fault conditions a fault condition occurs if v ref or v dd fall below their undervoltage lockout (uvlo) thresholds or if the thermal protection is triggered. when a fault is detected the outputs are disabled low. when the fault condition clears the outputs are re-enabled. an overcurrent condition is not considered a fault and does not result in a shutdown. figure 22. basic waveform timing ct outll outlr outlln (sr1) outlrn (sr2) figure 23. waveform timing with pwm outputs delayed, 0v < v adj < 2.425v ct outll outlr outlln (sr1) outlrn (sr2) figure 24. waveform timing with sr outputs delayed, 2.575v < v adj < 5.00v ct outll outlr outlln (sr1) outlrn (sr2)
ISL78223 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7936.1 january 2, 2013 for additional products, see www.intersil.com/en/products.html thermal protection internal die over temperature protection is provided. an integrated temperature sensor protects the device should the junction temperature exceed +140c. there is approximately +15c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. v dd and v ref should be bypassed directly to gnd with good high frequency capacitance. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee transactions on power electronics, vol. 6, no. 2, april 1991. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL78223 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 2, 2013 fn7936.1 initial release.
ISL78223 20 fn7936.1 january 2, 2013 package outline drawing m20.15 20 lead quarter size outline plastic package (qsop) rev 2, 1/11 detail "x" side view typical recommended land pattern top view 0.010 (0.25) 0.007 (0.18) 8 0.050 (1.27) 0.016 (0.41) 20 123 index area (0.635 bsc) 0.025 1 2 0.025 (0.64) x 18 0.220(5.59) seating plane 0.015 (0.38) x 20 0.060 (1.52) x 20 3 20 3 4 5 0.244 (6.19) 0.228 (5.80) 0.157 (3.98) 0.150 (3.81) 0.344 (8.74) 0.337 (8.56) 0.069 (1.75) 0.053 (1.35) 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0 0.0196 (0.49) 0.0099 (0.26) 0.061 max (1.54 mil) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing conform to amse y14.5m-1994. 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. length of terminal for soldering to a substrate. 7. terminal numbers are shown for reference only. 8. dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of dimension at maximum material condition. 9. controlling dimens ion: inches. converted millimeter di mensions are not necessarily exact. 6 0.25 0.010 gauge plane 8

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