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64-position up/down control digital potentiometer ad5227 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703? 2004C2009 analog devices, inc. all rights reserved. features 64-position digital potentiometer 10 k, 50 k, 100 k end-to-end terminal resistance simple up/down digital or ma nual configurable control midscale preset low potentiometer mode tempco = 10 ppm/c low rheostat mode tempco = 35 ppm/c ultralow power, i dd = 0.4 a typ and 3 a max fast adjustment time, ts = 1 s chip select enable multiple device operation low operating voltage, 2.7 v to 5.5 v automotive temperature range, ?40c to +105c compact thin sot-23-8 (2.9 mm 3 mm) pb-free package applications mechanical potentiometer and trimmer replacements lcd backlight, contrast, and brightness controls portable electronics level adjustment programmable power supply digital trimmer replacements automatic closed-loop control functional block diagram 04419-0-001 cs u/d clk gnd v dd 6-bit up/down control logic por midscale wiper register a w b ad5227 figure 1. general description the ad5227 is analog devices latest 64-step up/down control digital potentiometer 1 . this device performs the same electronic adjustment function as a 5 v potentiometer or variable resistor. its simple 3-wire up/down interface allows manual switching or high speed digital control. the ad5227 presets to midscale at power-up. when cs is enabled, the devices changes step at every clock pulse. the direction is determined by the state of the u/ d pin (see ). the interface is simple to activate by any host controller, discrete logic, or manually with a rotary encoder or pushbuttons. the ad5227s 64-step resolution, small footprint, and simple interface enable it to replace mechanical potentiometers and trimmers with typically 6 improved resolution, solid-state reliability, and design layout flexibility, resulting in a considerable cost savings in end users systems. table 1 1 the terms digital potentiometer and rdac are used interchangeably. the ad5227 is available in a compact thin sot-23-8 (tsot-8) pb-free package. the part is guaranteed to operate over the automotive temperature range of ?40c to +105c. users who consider eemem potentiometers should refer to some recommendations in the applications section. table 1. truth table cs clk u/ d operation 1 0 0 r wb decrement 0 1 r wb increment 1 x x no operation 1 r wa increments if r wb decrements and vice versa.
ad5227 rev. b | page 2 of 16 table of contents electrical characteristics ................................................................. 3 ? interface timing diagrams ......................................................... 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 10 ? programming the digital potentiometers ............................... 10 ? digital interface .......................................................................... 11 ? terminal voltage operation range ......................................... 11 ? power-up and power-down sequences .................................. 11 ? layout and power supply biasing ............................................ 11 ? applications ..................................................................................... 12 ? manual control with toggle and pushbutton switches ........ 12 ? manual control with rotary encoder ..................................... 12 ? adjustable led driver .............................................................. 12 ? adjustable current source for led driver ............................ 12 ? adjustable high power led driver ........................................ 13 ? automatic lcd panel backlight control ................................ 13 ? 6-bit controller .......................................................................... 13 ? constant bias with supply to retain resistance setting ....... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 5/09rev. a to rev. b changes to table 23 4/09rev. 0 to rev. a changes to table 23 changes to ordering guide 15 3/04revision 0: initial version
ad5227 rev. b | page 3 of 16 electrical characteristics 10 k, 50 k, 100 k versions: v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?40c < t a < +105c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb , a = no connect ?0.5 0.15 +0.5 lsb resistor integral nonlinearity 2 r-inl r wb , a = no connect ?1 0.3 +1 lsb nominal resistor tolerance 3 ?r ab /r ab ?20 +20 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 35 ppm/c wiper resistance r w v dd = 2.7 v 100 250 v dd = 2.8 v to 5.5 v 50 200 dc characteristics potentiometer divider mode resolution n 6 bits integral nonlinearity 3 inl ?1 0.1 +1 lsb differential nonlinearity 3 , 4 dnl ?0.5 0.1 +0.5 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 midscale 5 ppm/c full-scale error v wfse +31 steps from midscale ?1.2 ?0.5 0 lsb ?40c < t a < +60c, v dd = 2.8 v to 5.5 v ?1 ?0.5 0 lsb zero-scale error v wzse ?32 steps from midscale 0 0.5 1.2 lsb ?40c < t a < +60c, v dd = 2.8 v to 5.5 v 0 0.5 1 lsb resistor terminals voltage range 5 v a, b, w with respect to gnd 0 v dd v capacitance a, b 6 c a, b f = 1 mhz, measured to gnd 140 pf capacitance w 6 c w f = 1 mhz, measured to gnd 150 pf common-mode leakage i cm v a = v b = v w 1 na digital inputs ( cs , clk, u/ d ) input logic high v ih 2.4 5.5 v input logic low v il 0 0.8 v input current i i v in = 0 v or 5 v 1 a input capacitance 6 c i 5 pf power supplies power supply range v dd 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v, v dd = 5 v 0.4 3 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 17 w power supply sensitivity pssr v dd = 5 v 10% 0.01 0.05 %/% dynamic characteristics 6 , 8 , 9 bandwidth ?3 db bw_10 k r ab = 10 k, midscale 460 khz bw_50 k r ab = 50 k, midscale 100 khz bw_100 k r ab = 100 k, midscale 50 khz total harmonic distortion thd v a = 1 v rms, r ab = 10 k, v b = 0 v dc, f = 1 khz 0.05 % adjustment settling time t s v a = 5 v 1 lsb error band, v b = 0, measured at v w 1 s resistor noise voltage e n_wb r wb = 5 k, f = 1 khz 14 nv/hz footnotes on the next page.
ad5227 rev. b | page 4 of 16 parameter symbol conditions min typ 1 max unit interface timing characteristics (applies to all parts 6 , 10 ) clock frequency f clk 50 mhz input clock pulse width t ch , t cl clock level high or low 10 ns cs to clk setup time t css 10 ns cs rise to clk hold time t csh 10 ns u/ d to clock fall setup time t uds 10 ns 1 typicals represent average readings at 25c, v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 nl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. 4 dnl specification limits of 1 lsb maximum ar e guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the f astest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 all dynamic characteristics use v dd = v. 10 all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characteristics are measured using v dd = 5 v. interface timing diagrams 04419-0-004 cs = low u/d = high clk r wb figure 2. increment r wb 04419-0-005 cs = low u/d = 0 clk r wb figure 3. decrement r wb 04419-0-006 1 0 1 0 1 0 cs clk u/d r wb t s t uds t cl t ch t css t csh figure 4. detailed timing diagram (only r wb decrement shown)
ad5227 rev. b | page 5 of 16 absolute maximum ratings table 3. parameter rating v dd to gnd ?0.3 v, +7 v v a , v b , v w to gnd 0 v, v dd digital input voltage to gnd ( cs , clk, u/ d ) 0 v, v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 5 k, a open) 1 1 ma i wa continuous (r wa 5 k, b open) 1 1 ma i ab continuous (r ab = 10 k/50 k/100 k) 1 500 a/ 100 a/50 a operating temperature range ?40c to +105c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c lead temperature (soldering, 10 s C 30 s) 245c thermal resistance 2 ja 230c/w 1 maximum terminal current is boun ded by the maximum applied voltage across any two of the a, b, and w terminals at a given resistance, the maximum current handling of the sw itches, and the maximum power dissipation of the package. v dd = 5 v. 2 package power dissipation = (t j max C t a ) / ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5227 rev. b | page 6 of 1 6 pin configuration and fu nction descriptions 04419-0-003 ad5227 top view (not to scale) clk 1 u/d 2 a 3 gnd 4 v dd cs b w 8 7 6 5 figure 5. pin configuration table 4. pin function descriptions pin o. neonic description 1 clk clock input. each clock pulse executes the step-up or st ep-down of the resistance. the direction is determined by the state of the u/ d pin. clk is a negative-edge trigger. lo gic high signal can be higher than v dd , but lower than 5.5 v. 2 u/ d up/down selections. logic 1 selects up and logic 0 selects down. u can be higher than v dd , but lower th an 5.5 v. 3 a resistor terminal a. gnd v a v dd . 4 gnd common ground. 5 w wiper terminal w. gnd v w v dd . 6 b resistor terminal b. gnd v b v dd . 7 cs chip select. active low. logic high signal can be higher than v dd , but lower than 5.5 v. 8 v dd positive power supply, 2.7 v to 5.5 v.
ad5227 rev. b | page 7 of 16 typical performance characteristics 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 06 4 5648403224168 04419-0-007 code (decimal) rheostat mode inl (lsb) v dd = 5.5v ?40 c +25 c +85 c +105 c figure 6. r-inl vs. code vs. temperature, v dd = 5 v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 06 4 5648403224168 04419-0-008 code (decimal) rheostat mode dnl (lsb) v dd = 5.5v ?40 c +25 c +85 c +105 c figure 7. r-dnl vs. code vs. temperature, v dd = 5 v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 06 4 5648403224168 04419-0-010 code (decimal) potentiometer mode inl (lsb) v dd = 5.5v ?40 c +25 c +85 c +105 c figure 8. inl vs. code, v dd = 5 v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 06 5648403224168 04419-0-012 code (decimal) potentiometer mode dnl (lsb) 4 v dd = 5.5v ?40 c +25 c +85 c +105 c figure 9. dnl vs. code vs. temperature, v dd = 5 v 0 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 ?40 ?20 0 20 40 60 100 80 04419-0-013 temperature ( c) fse (lsb) v dd = 5.5v v dd = 2.7v figure 10. full-scale error vs. temperature 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?40 ?20 0 20 40 60 100 80 04419-0-014 temperature ( c) zse (lsb) v dd = 5.5v v dd = 2.7v figure 11. zero-scale error vs. temperature
ad5227 rev. b | page 8 of 16 1 0.1 ?40 ?20 0 20 40 60 100 80 04419-0-015 temperature ( c) supply current ( a) v dd = 5.5v figure 12. supply current vs. temperature 1 0.1 ?40 ?20 0 20 40 60 100 80 04419-0-016 temperature ( c) nominal resistance, r ab (k ) v dd = 5.5v r ab = 50k r ab = 100k r ab = 10k figure 13. nominal resistance vs. temperature 120 0 20 40 60 80 100 ?40 ?20 0 20 40 60 100 80 04419-0-017 temperature ( c) wiper resistance, r w ( ) v dd = 5.5v v dd = 2.7v figure 14. wiper resistance vs. temperature 20 ?20 ?15 ?10 ?5 0 5 10 15 0 8 16 24 32 40 48 56 64 04419-0-018 code (decimal) rheostat mode tempco (ppm/ c) 10k 50k 100k v dd = 5.5v figure 15. rheostat mode tempco r wb /t vs. code 20 ?20 ?15 ?10 ?5 0 5 10 15 0 8 16 24 32 40 48 56 64 04419-0-019 code (decimal) potentiometer mode tempco (ppm/ c) 10k 50k 100k v dd = 5.5v figure 16. potentiometer mode tempco r wb /t vs. code 6 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 1m start 1 000.000hz stop 1 000 000.000hz ref level 0db /div 6.0db marker mag (a/r) 461 441.868h z ?8.957db 100k 04419-0-042 db t a = 25 c v dd = 5.5v v a = 50mv rms 32 steps 16 steps 8 steps 4 steps 2 steps 1 step figure 17. gain vs. frequency vs. code, r ab = 10 k
ad5227 rev. b | page 9 of 16 6 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 1m start 1 000.000hz stop 1 000 000.000hz ref level 0db /div 6.0db marker mag (a/r) 100 885.289h z ?9.060db 100k 04419-0-043 db t a = 25 c v dd = 5.5v v a = 50mv rms 32 steps 16 steps 8 steps 4 steps 2 steps 1 step figure 18. gain vs. frequency vs. code, r ab = 50 k 6 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 1m start 1 000.000hz stop 1 000 000.000hz ref level 0db /div 6.0db marker mag (a/r) 52 246.435h z ?9.139db 100k 04419-0-044 db t a = 25 c v dd = 5.5v v a = 50mv rms 32 steps 16 steps 8 steps 4 steps 2 steps 1 step figure 19. gain vs. frequency vs. code, r ab = 100 k 0 ?60 ?40 ?20 100 1k 10k 100k 1m 04419-0-023 frequency (hz) psrr (db) v dd = 5v dc 10% p-p ac v dd = 3v dc 10% p-p ac step = midscale, v a = v dd , v b = 0v figure 20. psrr 200 0 100 150 50 10k 100k 10m 1m 04419-0-024 frequency (hz) i dd ( a) v dd = 5v v dd = 3v figure 21. i dd vs. clk frequency 1.2 0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40 48 56 64 04419-0-025 code (decimal) theoretical i wb_max (ma) r ab = 10k r ab = 50k r ab = 100k a = open t a = 25 c figure 22. maximum i wb vs. code 04419-0-022 ch1 2.00v ch2 50.0mv m 400ns a ch2 60.0mv v w 1 2 va t 0.00000s v dd = 5v v a = 5v v b = 0v vb = 0v step n+1 step n figure 23. step change settling time
ad5227 rev. b | page 10 of 1 6 theory of operation the ad5227 is a 64-position 3-terminal digitally controlled potentiometer device. it presets to a midscale at system power- on. when cs is enabled, changing the resistance settings is achieved by clocking the clk pin. it is negative-edge triggered, and the direction of stepping is determined by the state of the u/ d input. when the wiper reaches the maximum or the minimum setting, additional clk pulses do not change the wiper setting. 04419-0-026 cs u/d clk gnd v dd 6-bit up/down control logic por midscale wiper register a w b ad5227 figure 24. functional block diagram 04419-0-027 b w a d0 d2 d1 d4 d5 d3 r s r s = r ab /64 r w r s r s r s rdac up/down ctrl and decode figure 25. ad5227 equivalent rdac circuit programming the digital potentiometers rheostat operation if only the w-to-b or w-to-a terminals are used as variable resistors, the unused terminal can be opened or shorted with w. this operation is called rheostat mode and is shown in figure 26 . 04419-0-028 a w b a w b a w b figure 26. rheostat mode configuration the end-to-end resistance, r ab , has 64 contact points accessed by the wiper terminal, plus the b terminal contact, assuming that r wb is used (see figure 25 ). clocking the clk input steps, r wb by one step. the direction is determined by the state of u/ d pin. the change of r wb can be determined by the number of clock pulses, provided that the ad5227 has not reached its maximum or minimum scale. r wb can, therefore, be approximated as ? ? ? ? ? ? += w ab wb r r cp r 64 (1) where: cp is the number of clock pulses. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on-resistance of the internal switch. since in the lowest end of the resistor string a finite wiper resistance is present, care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switches can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened or shorted to w. s i m i l a r l y, r wa can be approximated as () ? ? ? ? ? ? +?= w ab wa r r cp r 64 64 (2) equations 1 and 2 do not apply when cp = 0. the typical distribution of the resistance tolerance from device to device is process lot dependent. it is possible to have 20% tolerance. potentiometer mode operation if all three terminals are used, the operation is called potentiometer mode. the most common configuration is the voltage divider operation as shown in figure 27 . 04419-0-029 a w b v i v c figure 27. potentiometer mode configuration
ad5227 rev. b | page 11 of 1 6 the change of v wb is known provided that the ad5227 has not reached the maximum or minimum scale. if one ignores the effect of the wiper resistance, the transfer functions can be simplified as a wb v cp v 64 += u/ d = 1 (3) a wb v cp v 64 ?= u/ d = 0 (4) unlike rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratiometric function of cp/64 with a relatively small error contributed by the r w term. the tolerance effect is, therefore, almost canceled. although the thin film step resistor, r s , and cmos switches resistance, r w , have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient to 5 ppm/c except at low value codes where r w dominates. potentiometer mode operation includes an op amp gain configuration among others. the a, w, and b terminals can be input or output terminals and have no polarity constraint provided that |v ab |, |v wa |, and |v wb | do not exceed v dd -to-gnd. digital interface the ad5227 contains a 3-wire serial input interface. the three inputs are clock (clk), chip select ( cs ), and up/down control (u/ d ). these inputs can be controlled digitally for optimum speed and flexibility when cs is pulled low, a clock pulse increments or decrements the up/down counter. the direction is determined by the state of the u/ d pin. when a specific state of the u/ d remains, the device continues to change in the same direction under con- secutive clocks until it comes to the end of the resistance setting. all digital inputs, cs , clk, and u/ d pins, are protected with a series input resistor and a parallel zener esd structure as shown in . figure 28 04419-0-030 1k logic figure 28. equivalent esd protection digital pins terminal voltage operation range the ad5227 is designed with inte rnal esd protection diodes ( figure 29 ), but the diodes also set the boundary of the terminal operating voltages. voltage present on terminal a, b, or w that exceeds v dd by more than 0.5 v is clamped by the diode and, therefore, elevates v dd . there is no polarity constraint between v ab , v wa , and v wb , but they cannot be higher than v dd -to- gnd. power-up and power-down sequences because of the esd protection diodes, it is important to power on v dd before applying any voltage to terminals a, b, and w. otherwise, the diodes are forward-biased such that v dd can be powered unintentionally and can affect the rest of the system circuit. similarly, v dd should be powered down last. the ideal power-on sequence is in the following order: gnd, v dd , v a/b/w , and digital inputs. 04419-0-031 v dd gnd a w b figure 29. maximum terminal voltages set by v dd and gnd layout and power supply biasing it is a good practice to use compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. low esr (equivalent series resistance) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. figure 30 illustrates the basic supply bypassing configuration for the ad5227. the ground pin of the ad5227 is a digital ground reference that should be joined to the common ground at a single point to minimize the digital ground bounce. 04419-0-032 v dd v dd + gnd ad5227 c2 10 f c1 0.1 f figure 30. power supply bypassing
ad5227 rev. b | page 12 of 1 6 applications manual control with toggle and pushbutton switches the ad5227s simple interface allows it to be used with mechanical switches for simple manual operation. the states of the cs and u/ d can be selected by toggle switches and the clk input can be controlled by a pushbutton switch. because of the numerous bounces due to contact closure, the pushbutton switch should be debounced by flip-flops or by the adm812 as shown in . figure 31 04419-0-033 up/down mr reset v cc gnd adm812 clk ad5227 cs u/d 5v increment figure 31. manual push button up/down control manual control with rotary encoder figure 32 shows another way of using ad5227 to emulate mechanical potentiometer in a rotary knob operation. the rotary encoder u1 has a c ground terminal and two out-of- phase signals, a and b. when u1 is turned clockwise, a pulse generated from the b terminal leads a pulse generated from the a terminal and vice versa. signals a and b of u1 pass through a quadrature decoder u2 that translates the phase difference between a and b of u1 into compatible inputs for u3 ad5227. therefore, when b leads a (clockwise), u2 provides the ad5227 with a logic high u/ d signal, and vice versa. u2 also filters noise, jitter, and other transients as well as debouncing the contact bounces generated by u1. 04419-0-034 u3 ad5227 digital potentiometer clk 1 v dd 8 u/d 2 cs 7 a13 b1 6 gnd 4 w1 5 b1 a1 w1 u2 ls7084 quadrature decoder rbias 1 clk 8 v dd 2 u/d 7 vss 3 x4/x1 6 a 4 b 5 b c a u1 rotary encoder re11ct-v1y12-ef2cs r3 10k r1 10k r2 10k 5v figure 32. manual rotary control adjustable led driver the ad5227 can be used in many electronics-level adjustments such as led drivers for lcd panel backlight control. figure 33 shows an adjustable led driver. the ad5227 sets the voltage across the white led d1 for the brightness control. since u2 handles up to 250 ma, a typical white led with v f of 3.5 v requires a resistor, r1, to limit the u2 current. this circuit is simple but not power-efficient, therefore the u2 shutdown pin can be toggled with a pwm signal to conserve power. 04419-0-035 a w b 10k v dd gnd cs clk u/d u1 ad5227 c1 1 f c2 0.1 f 5v u2 ad8591 + ? v+ v? sd 5v c3 0.1 f r1 6 white led d1 pwm figure 33. low cost adjustable led driver adjustable current source for led driver since led brightness is a function of current rather than forward voltage, an adjustable current source is preferred over a voltage source as shown in figure 34 . 04419-0-036 a w b 10k r1 418k gnd u2 ad5227 v dd 5v cs clk u/d 5v u3 ad8591 + ? v+ v? 5v pwm v in v out gnd u1 adp3333 arm-1.5 sd r set 0.1 vl id d1 figure 34. adjustable current source for led driver the load current can be found as the v wb of the ad5227 divided by r set . set wb d r v i = (5)
ad5227 rev. b | page 13 of 1 6 the u1 adp3333arm-1.5 is a 1.5 v ldo that is lifted above or lowered below 0 v. when v wb of the ad5227 is at minimum, there is no current through d1, so the gnd pin of u1 would be at ?1.5 v if u3 were biased with the dual supplies. as a result, some of the u2 low resistance steps have no effect on the output until the u1 gnd pin is lifted above 0 v. when v wb of the ad5227 is at its maximum, v out becomes v l + v ab , so the u1 supply voltage must be biased with adequate headroom. similarly, a pwm signal can be applied at the u1 shutdown pin for power efficiency. this circuit works well for a single led. adjustable high power led driver figure 35 shows a circuit that can drive three to four high power leds. adp1610 is an adjustable boost regulator that provides the voltage headroom and current for the leds. the ad5227 and the op amp form an average gain of 12 feedback network that servos the r set voltage and adp1610s fb pin 1.2 v band gap reference voltage. as the loop is set, the voltage across r set is regulated around 0.1 v and adjusted by the digital potentiometer. set r led r v i set = (6) r set should be small enough to conserve power but large enough to limit maximum led current. r3 should also be used in parallel with ad5227 to limit the led current within an achievable range. a wider current adjustment range is possible by lowering the r2 to r1 ratio, as well as changing r3 accordingly. 04419-0-037 ss rt gnd in u2 adp1610 sw fb pwm 1.2v sd comp c ss 10nf c c 390pf r c 100k l1 10 f d1 c3 10 f r4 13.5k d2 d3 d4 v out c2 10 f 5v + ? ad8541 u1 l1?slf6025-100m1r0 d1?mbr0520lt1 u3 v+ v? 5v c8 0.1 f u1 ad5227 ba 10k r3 200 w r1 100 r2 1.1k r set 0.25 figure 35. adjustable current source for leds in series automatic lcd panel backlight control with the addition of a photocell sensor, an automatic brightness control can be achieved. as shown in figure 36 , the resistance of the photocell changes linearly but inversely with the light output. the brighter the light output, the lower the photocell resistance and vice versa. the ad5227 sets the voltage level that is gained up by u2 to drive n1 to a desirable brightness. with the photocell acting as the variable feedback resistor, the change in the light output changes the r2 resistance, therefore causing u2 to drive n1 accordingly to regulate the output. this simple low cost implementation of the led controller can compensate for the temperature and aging effects typically found in high power leds. similarly, for power efficiency, a pwm signal can be applied at the gate of n2 to switch the led on and off without any noticeable effect. 04419-0-038 cs clk u/d a w b 10k v dd gnd u1 ad5227 c1 1 f c2 0.1 f 5v u2 ad8591 + ? v+ v? 5v c3 0.1 f r1 1k r2 5v pwm n1 2n7002 white led d1 5v photocell sd figure 36. automatic lcd panel backlight control 6-bit controller the ad5227 can form a simple 6-bit controller with a clock generator, a comparator, and some output components. figure 37 shows a generic 6-bit controller with a comparator that first compares the sampling output with the reference level and outputs either a high or low level to the ad5227 u/ d pin. the ad5227 then changes step at every clock cycle in the direction indicated by the u/ d state. although this circuit is not as elegant as the one shown in , it is self-contained, very easy to design, and can adapt to various applications. figure 36 04419-0-039 clk u/d b 5v v dd gnd cs u1 ad5227 + ? u2 comparator sampling_output ref u3 ad8531 + ? output op amp figure 37. 6-bit controller
ad5227 rev. b | page 14 of 1 6 3.50 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3.49 02468101 04419-0-041 days battery voltage (v) constant bias with supply to retain resistance setting 2 t a = 25 c users who consider eemem potentiometers but cannot justify the additional cost and programming for their designs can con- sider constantly biasing the ad5227 with the supply to retain the resistance setting as shown in figure 38 . the ad5227 is designed specifically with low power to allow power conservation even in battery-operated systems. as shown in figure 39 , a similar low power digital potentiometer is biased with a 3.4 v 450 ma/hour li-ion cell phone ba ttery. the measurement shows that the device drains negligible power. constantly biasing the potentiometer is a practical approach because most portable devices do not require detachable batteries for charging. although the resistance setting of the ad5227 is lost when the battery needs to be replaced, this event occurs so infrequently that the inconvenience is minimal for most applications. figure 39. battery consumption measurement 04419-0-040 v dd ad5227 u1 gnd v dd u2 gnd component x v dd u3 gnd component y gnd v dd battery or system power sw1 + ? figure 38. constant bias ad5 227 for resistance retention
ad5227 rev. b | page 15 of 1 6 outline dimensions 2.90 bsc 13 56 2 8 4 7 pin 1 indicator 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.10 max * 0.90 0.87 0.84 seating plane * 1.00 max 0.20 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc * compliant to jedec standards mo-193-ba with the exception of package height and thickness. figure 40. 8-lead thin small outline transistor package [tsot] (uj-8) dimensions shown in millimeters ordering guide model r ab 1 (k) temperature range package description pa ckage option ordering quantity branding ad5227bujz10-rl7 2 10 ?40c to +105c 8-lead tsot uj-8 3000 d3g ad5227bujz10-r2 2 10 ?40c to +105c 8-lead tsot uj-8 250 d3g AD5227BUJZ50-RL7 2 50 ?40c to +105c 8-lead tsot uj-8 3000 d3h ad5227bujz50-r2 2 50 ?40c to +105c 8-lead tsot uj-8 250 d3h ad5227bujz100-rl7 2 100 ?40c to +105c 8-lead tsot uj-8 3000 d3j ad5227bujz100-r2 2 100 ?40c to +105c 8-lead tsot uj-8 250 d3j ad5227eval 10 evaluation board 1 1 the end-to-end resistance r ab is available in 10 k, 50 k, and 100 k ve rsions. the final three charac ters of the part number de termine the nominal resista nce value, for example, 10 k = 10. 2 z = rohs compliant part.
ad5227 rev. b | page 16 of 16 notes ? 2004C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04419C0C5/09(b)

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