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1 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory k9f1g08x0a * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
2 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory document title 128m x 8 bit / 256m x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.0 remark advance preliminary preliminary preliminary preliminary preliminary history 1. initial issue 1. the tadl(address to data loading time) is added. - tadl minimum 100ns (page 11, 23~26) - tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle at program operation. 2. added addressing method for program operation 1. add the protrusion/burr value in wsop1 pkg diagram . 1. pkg(tsop1, wsop1) dimension change 1. technical note is changed 2. notes of ac timing characteristics are added 3. the description of c opy-back program is changed 4. voltage range is changed -1.7v~1.95v -> 1.65v~1.95v 5. note2 of command sets is added 1. ce access time : 23ns->35ns (p.11) 1. the value of trea for 3. 3v device is changed.(18ns->20ns) 2. edo mode is added. 1. the flow chart to creat the initial invalid block table is cahnged. 1. 1.8v fbga package is added 1. 3.3v fbga package is added draft date aug. 24. 2003 jan. 27. 2004 apr. 23. 2004 may. 19. 2004 jan. 21. 2005 feb. 14. 2005 may. 4. 2005 may 6. 2005 aug. 5. 2005 jan. 27. 2006
3 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory general description features ? voltage supply -1.8v device(k9f1g08r0a): 1.65v~1.95v -3.3v device(k9f1g08u0a): 2.7 v ~3.6 v ? organization - memory cell array : (128m + 4,096k)bit x 8bit - data register : (2k + 64)bit x8bit - cache register : (2k + 64)bit x8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : 2k-byte - random read : 25 s(max.) - serial access : 30ns(min.) - 3.3v device 50ns(min.) -1.8v device 128m x 8 bit /256m x 8 bit nand flash memory ? fast write cycle time - program time : 200 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? command register operation ? cache program operation for high performance program ? intelligent copy-back operation ? unique id for copyright protection ? package : - k9f1g08x0a-jcb0/jib0 63- ball fbga (9.5 x 12) - pb-free package - k9f1g08u0a-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - k9f1g08u0a-fib0 48 - pin wsop i (12x17x0.7mm)- pb-free package * k9f1g08u0a-f(wsopi ) is the same device as k9f1g08u0a-p(tsop1) except package type. - k9k2g08u1a-icb0/iib0 52-ulga (12x17x0.65mm) offered in 128mx8bit the k9f1g08x0a is 1g bi t with spare 32m bit capacity. its nand ce ll provides the most cost-effective solu tion for the solid state mass storage market. a pr ogram operation can be performed in typical 200 s on the 2112-byte page and an erase operation can be performed in typical 2ms on a 128k-byte block. data in the data page can be read out at 30ns(50ns with 1.8v device) cycle time per byte. th e i/o pins serve as the ports for address and dat a input/output as well as command input. the on -chip write controller automates all program and er ase functions including pulse repetition, where required, and internal verificatio n and margining of data. even the write-intensive systems can take advantage of the k9f1g08x0a s extended reliability of 100k program/ erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the k9f1g08x0a is an optimum solu- tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non- v ol atil i ty. product list part number vcc range organization pkg type k9f1g08r0a-j 1.65 ~ 1.95v x8 fbga k9f1g08u0a-p 2.7 ~ 3.6v tsop1 k9f1g08u0a-f wsop1 k9f1g08u0a-j fbga k9k2g08u1a-i 52-ulga
4 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory pin configuration (tsop1) k9f1g08u0a-pcb0/pib0 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c 0.20 +0.07 -0.03
5 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory pin configuration (wsop1) k9f1g08u0a-fib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0.20 +0.07 -0.03 0.16 +0.07 -0.03 0.50typ (0.50 0.06) #48 #25 0.10 +0.075 -0.035 17.00 0.20 0 ~ 8 0.45~0.75 12.00 0.10 0.58 0.04 0.70 max (0.01min) 12.40max
6 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory k9f1g08x0a-jcb0/jib0 pin configuration (fbga) r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vcc i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c 3456 1 2 a b c d g e f h top view
7 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory 9.50 0.10 #a1 side view top view 1.20 (max) 0.45 0.05 bottom view 12.00 0.10 63- ? 0.45 0.05 0.25 (min.) 0.10max 0.20 m a b ? 12.00 0.10 4321 a b c d g 0.80 x 7= 5.60 12.00 0.10 0.80 x 5= 4.00 0.80 b a 2.80 2.00 9.50 0.10 (datum b) (datum a) 0.80 0.80 x 11= 8.80 0.80 x 9= 7.20 65 e f h #a1 index mark(optional) package demensions(fbga)
8 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory pin configuration (ulga) 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.65 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 k9k2g08u1a-icb0/iib0 52-ulga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 /rb1 /rb2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 ? ab c m 0.1 ? ab c m 0.1 package dimensions
9 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode. re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection du ring power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
10 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory 2k bytes 64 bytes figure 1-1. k9f1g08x0a functional block diagram figure 2-1. k9f1g08x0a array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 27 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 64k pages (=1,024 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 1024 blocks = 1056 mbits row address page register ale pre 1024m + 32m bit nand flash array (2048 + 64)byte x 65536 y-gating cache register row address column address column address data register & s/a
11 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory product introduction the k9f1g08x0a is a 1056mbit(1,107,296,256 bit) memory organi zed as 65,536 rows(pages) by 2112x8 columns. spare 64 col- umns are located from column address of 2048~2111. a 2112-byte dat a register and a 2112-byte cache register are serially con- nected to each other. those serially connected registers are c onnected to memory cell arrays for accommodating data transfer between the i/o buffers and memory cells during page read and page program operations. the memory array is made up of 32 cells that are serially connected to form a nand structure. each of t he 32 cells resides in a different page. a block consists of two nand structured strings. a nand structure consists of 32 cells. total 1081344 nand cells reside in a block. the program and read ope ra- tions are executed on a page basis, while the erase operation is executed on a block bas is. the memory array consists of 1024 s ep- arately erasable 128k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9f1g08x0a. the k9f1g08x0a has addresses multiplexed into 8 i/os. this sc heme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system boar d design. command, address and dat a are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively , via the i/o pins. some comm ands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for ex ecution. the 132m byte physical space requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in t hat order. page read and page program need the same four address cycles following the required command input. in block erase oper- ation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the com- mand register. table 1 defines the s pecific commands of the k9f1g08x0a. the device provides cache program in a block. it is possible to write data into the cache registers while data stored in data r egisters are being programmed into memory cells in cache program mode. the program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the exter nal buffer memory. since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk a pplication is signi ficantly increased. table 1. command sets note : 1. random data input/output can be executed in a page. 2. cache program and copy-back program are supported only with 3.3v device. function 1st. cycle 2nd. cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h cache program *2 80h 15h copy-back program 85h 10h block erase 60h d0h random data input *1 85h - random data output *1 05h e0h read status 70h o caution : any undefined command inputs are prohibited except for above command set of table 1.
12 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory recommended operating conditions (voltage reference to gnd, k9f1g08x0a-xcb0 : t a =0 to 70 c, k9f1g08x0a-xib0 : t a =-40 to 85 c) parameter symbol k9f1g08r0a(1.8v) k9f1g08u0a(3.3v) unit min typ. max min typ. max supply voltage v cc 1.65 1.8 1.95 2.7 3.3 3.6 v supply voltage v ss 000000 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit 1.8v device 3.3v device voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9f1g08x0a-xcb0 t bias -10 to +125 c k9f1g08x0a-xib0 -40 to +125 storage temperature k9f1g08x0a-xcb0 t stg -65 to +150 c k9f1g08x0a-xib0 short circuit current ios 5 ma dc and operating characteristics (recommended operating conditions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9f1g08r0a k9f1g08u0a unit 1.8v 3.3v min typ max min typ max operating current page read with serial access i cc 1 trc=30ns(50ns with 1.8v device), ce =v il i out =0ma - 10 20 - 15 30 ma program i cc 2 - - 10 20 - 15 30 erase i cc 3 - - 10 20 - 15 30 stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 --1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 input high voltage v ih* -0.8xv cc - v cc +0.3 0.8xvcc - v cc +0.3 v input low voltage, all inputs v il* - -0.3 - 0.2xvcc -0.3 - 0.2xvcc output high voltage level v oh k9f1g08r0a :i oh =-100 a k9f1g08u0a :i oh =-400 a vcc -0.1 --2.4-- output low voltage level v ol k9f1g08r0a :i ol =100ua k9f1g08u0a :i ol =2.1ma --0.1--0.4 output low current(r/b )i ol (r/b ) k9f1g08r0a :v ol =0.1v k9f1g08u0a :v ol =0.4v 34- 810-ma
13 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory capacitance ( t a =25 c, v cc =1.8v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f1g08x0a may include invalid blocks when first shipped. additional in valid blocks may develop while being used. the number of valid blocks is presented with both cases of inva lid blocks considered. invalid blocks are def ined as blocks that contain one or more bad bits. do not erase or program factory-marked bad blocks . refer to the attached technical notes for appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guar anteed to be a valid block, does not require error correction u p to 1k program/erase cycles. * : each k9f1g08u0a chip in the k9k2g08u1a has maximum 20 invalid blocks. parameter symbol min typ. max unit k9f1g08x0a n vb 1004 - 1024 blocks k9k2g08u1a n vb 2008 - 2048 blocks ac test condition (k9f1g08x0a-xcb0 :ta=0 to 70 c, k9f1g08x0a-xib0:ta=-40 to 85 c k9f1g08r0a : vcc=1.65v~1.95v, k9f1g08u0a : vcc=2.7v~3.6v unless otherwise noted) parameter k9f1g08r0a k9f1g08u0a input pulse levels 0v to vcc 0v to vcc input rise and fall times 5ns 5ns input and output timing levels vcc/2 vcc/2 output load 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(4clock) hll hh write mode command input l h l h h address input(4clock) l l l h h data input l l l h x data output xxxxhx during r ead(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x *1 x x x l write protect xxhxx 0v/v cc (2) stand-by program / erase characteristics note : 1. typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at vcc of 3.3v a ns 25?c. 2. max. time of tcbsy depends on timing between internal program completion and data in. parameter symbol min typ max unit program time t prog *1 - 200 700 s dummy busy time for cache program t cbsy *2 3 700 s number of partial program cycles in the same page main array nop - - 4 cycles spare array - - 4 cycles block erase time t bers -23ms
14 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory ac timing characteristics for command / address / data input note : 1. the transition of the corresponding control pins must occur only once while we is held low. 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 3. for cache program operation, the whole ac charcateristics must be same as that of k9f1g08r0a. parameter symbol min max unit k9f1g08r0a k9f1g08u0a k9f1g08r0a k9f1g08u0a cle setup time t cls *1 25 15 - - ns cle hold time t clh 10 5 - - ns ce setup time t cs *1 35 20 - - ns ce hold time t ch 10 5 - - ns we pulse width t wp 25 15 - - ns ale setup time t als *1 25 15 - - ns ale hold time t alh 10 5 - - ns data setup time t ds *1 20 15 - - ns data hold time t dh 10 5 - - ns write cycle time t wc 45 30 - - ns we high hold time t wh 15 10 - - ns ale to data loading time t adl *2 100 *2 100 *2 --ns ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. for cache program operation, the whole ac charcateristics must be same as that of k9f1g08r0a. parameter symbol min max unit k9f1g08r0a k9f1g08u0a k9f1g08r0a k9f1g08u0a data transfer from cell to register t r - - 25 25 s ale to re delay t ar 10 10 - - ns cle to re delay t clr 10 10 - - ns ready to re low t rr 20 20 - - ns re pulse width t rp 25 15 - - ns we high to busy t wb - - 100 100 ns read cycle time t rc 50 30 - - ns re access time t rea - - 30 20 ns ce access time t cea - - 45 35 ns re high to output hi-z t rhz - - 30 30 ns ce high to output hi-z t chz - - 20 20 ns re or ce high to output hold t oh 15 15 - - ns re high hold time t reh 15 10 - - ns output hi-z to re low t ir 00 - -ns we high to re low t whr 60 60 - - ns device resetting time (read/program/erase) t rst -- 5/10/500 *1 5/10/500 *1 s
15 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invali d block(s) is so called as the initial in valid block information. devices with init ial invalid block(s) have the same quality level as dev ices with all valid blocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) bec ause it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, d oes not require error correcti on up to 1k program/erase cycle s. all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung makes sure that either the 1st or 2nd pag e of every initial invalid block has non-ffh data at the column address of 2048. since the initial invalid block information is also era sable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recogniz e the initial invalid block(s) based on the initial invalid block info rmation and create the initial invalid block table via the foll owing suggested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh increment block address last block ? end no yes yes create (or update) no initial invalid block(s) table of the 1st and 2nd page in the block 2048
16 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register or r/b = 1 ? program error yes no yes error in write or read operation within its life time, addi tional invalid blocks ma y develop with nand flash memory. refer to the qualification report for the b lock failure rate.the following possible failur e modes should be considered to implement a highly reliable system. in the case of st atus read failure after erase or program, bloc k replacement should be done. because program status fail during a page program does n ot affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copy ing the rest of the replaced block.in case of read, ecc mu st be employed. to improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ecc without any block replac ement. the block failure rate in the qualification report does not include those recla imed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure ve rify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection program completed : if program operation results in an error, map out the block including the page in error and copy the * target data to another block.
17 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme.
18 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. ran dom page address programming is prohibited. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 nand flash technical notes (continued) addressing for program operation : : : :
19 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or seri al access as shown below . the internal 2112byte data registers are utilized as separate buffers for this operat ion and the system design gets more flexible. in addition, for v oice or audio applications which use sl ow cycle time on the order of u-seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch address(4cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(4cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox t rea t cs
20 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale col. add1 t cls t cs t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 k9f1g08x0a i/o 0 ~ i/o 7 ~2112byte a0~a7 a8~a11 a12~a19 a20~a27 i/ox i/ox col. add2 row add1 row add2 t wc
21 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory input data latch cycle ce cle we din 0 din 1 din final* ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox notes : din final means 2112 re ce r/b i/ox t rr t cea t rea t rp t reh t rea t rc t rhz* t rea dout t oh dout dout t oh t rhz* t chz* serial access cycle after read (cle=l, we =h, ale=l) notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
22 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory status read cycle ce we cle re 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir* t oh t oh t whr t cea t cls i/ox t chz* t rhz*
23 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 t oh t oh
24 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory t clr random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t wb t ar t r t rr t rc 30h 05h column address dout m dout m+1 e0h i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 t whr t rea
25 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory m = 2112byte page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 t adl notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle.
26 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 t adl t adl
27 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory copy-back program operation with random data input ce cle r/b we ale re 00h 70h i/o 0 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl
28 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory cache program operation (available only within a block) ce cle r/b we ale re 80h din n din 15h m serial data input command column address serial input program max. 63 times repeatable tcbsy twb twc command last page input & program t cbsy : max. 700us (dummy) din n din 10h tprog twb i/o 80h col add1,2 & row add1,2 r/b data address & data input 15h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h ex.) cache program t cbsy t cbsy t cbsy t prog program confirm command (true) 80h 70h 70h m row address i/ox i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. tadl tadl
29 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2
30 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory read id operation ce cle we ale re 90h read id command maker code device code 00h ech device t rea address. 1cycle xxh 4th cyc.* i/ox t ar device device code*(2nd cycle) 4th cycle* k9f1g08r0a a1h 15h k9f1g08u0a f1h 15h k9k2g08u1a same as each k9f1g08u0a in it code* id defintition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte maker code device code don?t care page size, block size, spare size, organization,serial access minimum
31 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory 4th id data item description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb reserved reserved 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb reserved 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1
32 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. therefore only five address cycles and 30h command initiates that operation after initial power up. the 2,112 bytes of data within the selected page are transferred to the data registers in less than 25 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time(50ns with 1. 8v device) by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the c onsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(4cycle) 00h col add1,2 & row add1,2 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox
33 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory figure 7. random data output in a page address 00h data output r/b re t r 30h address 05h e0h 4cycles 2cycles data output data field spare field data field spare field page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(1time/16byte). the addressing should be done in sequential order in a block. a page program cycle consists of a serial da ta loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming pe riod where the loaded data is programmed into the appropriate cell. the serial data loading period begins by i nputting the serial data input command(80h), followed by the four cycle address input s and then serial data loading. the words other than those to be pr ogrammed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random dat a input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programmi ng process. writing 10h alone without previously entering the serial data will not initiate the programming process. the intern al write state controller automa tically executes the algorithm s and tim- ings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of a pro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o 0 pass data 10h 70h fail t prog i/ox i/ox col add1,2 & row add1,2 "0" "1" col add1,2 & row add1,2
34 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory cache program figure 9. random data input in a page 80h r/b address & data input i/o 0 pass 10h 70h fail t prog 85h address & data input cache program is an extension of page progr am, which is executed with 2112byte data r egisters, and is available only within a b lock. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programme d into memory cell. after writing the first set of data up to 2112byte into the sele cted cache registers, cache program command (15h) instead of ac tual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cach e reg- isters to data registers, the device rema ins in busy state for a short period of ti me(tcbsy) and has its cache regist ers ready for the next data-input while the internal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache registers bec ome ready by polling the cache-busy status bit(i/o 6). pass/fail status of only t he pre- viouse page is available upon the return to ready state. when t he next set of data is inputted with the cache program command, tcbsy is affected by the progress of pending in ternal programming. the programming of t he cache registers is initiated only whe n the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the statu s bit(i/ o5) for internal ready/busy may be polled to identify the completi on of internal programming. if the system monitors the progre ss of programming only with r/b , the last page of the target programming sequence must be progammed with actual page program com- mand (10h). figure 10. cache program (available only within a block) 80h r/b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog 70h address & data input* 15h i/ox col add1,2 & row add1,2 col add1,2 data data col add1,2 & row add1,2 col add1,2 & row add1,2 col add1,2 & row add1,2 data data data col add1,2 & row add1,2 data "0" "1"
35 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory copy-back program figure 11. page copy-back program operation 00h r/b add.(4cycles) i/o 0 pass 85h 70h fail t prog add.(4cycles) t r source address destination address the copy-back program is configured to qui ckly and efficiently rewrite data stored in one page without utilizing an external me mory. since the time-consuming cycles of serial access and re-loading cy cles are removed, the system performance is improved. the ben - efit is especially obvious when a portion of a block is updated and the rest of the bl ock also need to be copied to the newly a ssigned free block. the operation for performing a copy-back program is a sequential execution of page-read without serial access and c opy- ing-program with the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. as soon as the device returns to ready state, page-copy data-input comma nd (85h) with the address cycles of destination page followed may be written. the program confirm co mmand (10h) is required to act u- ally begin the programming operation. data i nput cycle for modifying a portion or multip le distant portions of the source page is allowed as shown in figure 12. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has an error bit by charge loss, accumulated copy-back operations could also accumulate bit errors. in this case, verifying the source page for a bit error is recommended before copy-back program" 35h note : since programming the last page does not employ caching, the pr ogram time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycl e of the last page is initiated only after comple- tion of the previous cycl e, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) 10h figure 12. page copy-back program operation with random data input 00h r/b add.(4cycles) 85h 70h t prog add.(4cycles) t r source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox i/ox col. add1,2 & row add1,2 col. add1,2 & row add1,2 col. add1,2 & row add1,2 col. add1,2 & row add1,2 col add1,2 note: it?s prohibited to operate copy-back program from an odd addres s page(source page) to an even address page(target page) or fro m an even address page(source page) to an odd address page(target page). therefore, the copy-back program is permitted just between odd a ddress pages or even address pages .
36 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory figure 13. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accomplished in two cycles initiated by an erase setup c om- mand(60h). only address a 18 to a 27 is valid while a 12 to a 17 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasi ng process. this two-step sequence of set up followed by execution command ensures t hat memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bi t(i/o 0) may be checked. figure 13 details the sequence. 60h block add. : a 12 ~ a 27 r/b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. afte r writing 70h command to the command register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. table2. read staus register definition note : 1. true ready/busy represents internal program operation status which is being executed in cache program mode. 2. i/os defined ?not use? are reco mmended to be masked out when read status is being executed. i/o no. page program block erase cache prorgam read definition i/o 0 pass/fail pass/fail pass/fail(n) not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) n ot use pass : "0" fail : "1" i/o 2 not use not use not use not use "0" i/o 3 not use not use not use not use "0" i/o 4 not use not use not use not use "0" i/o 5 ready/busy ready/busy true ready/b usy ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy ready/busy r eady/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect protected:"0" not protected:"1" i/ox "0" "1"
37 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory figure 14. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product ident ification mode, initiated by writing 90h to t he command register, followed by an address inp ut of 00h. four read cycles sequentially output t he manufacturer code(ech), and the device code and xxh, 4th cycle id, respectively. the command register remains in read id mode until further comm ands are issued to it. figure 14 shows the operation sequence. device xxh 4th cyc.* ech figure 15. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort t hese operations. the contents of me mory cells being altered are no longer valid, as the data will be partia lly programmed or erased. the command regist er is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device st atus after reset operation.if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 15 below. ffh i/o x r/b t rst t whr t clr code* device device code*(2nd cycle) 4th cycle* k9f1g08r0a a1h 15h k9f1g08u0a f1h 15h k9k2g08u1a same as each k9f1g08u0a in it table3. device status after power-up after reset operation mode 00h command is latched waiting for next command
38 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropr iate value can be obtained with the follow ing reference chart(fig 17). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 17. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : v cc -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v c l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.70 1.70 1.70 1.70 1.70 0.85 0.57 0.43 tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 50 tf 100 150 200 1.8 1.8 1.8 1.8 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l
39 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase duri ng power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v(1.8v device), 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 s is required before internal circuit gets ready for any command sequences as shown in figure 17. the two step command sequence for program/erase provides addi- tional software protection. figure 17. ac waveforms for power transition v cc wp high we 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 s
40 k9f1g08u0a k9f1g08r0a k9k2g08u1a flash memory c l (f) figure 19. rp vs trhoh vs c l rp = 10k @ vcc = 3.3v, ta = 25 c 30p 50p 70p 100p 50n 100n 36 60 85 120 trloh / trhoh value guidance figure 18. serial access cycle after read (edo type, cle=l, we =h, ale=l) 300n 500n 180 300 425 600 rp = 100k 200n 400n 600n 360 600 v cc device gnd rp c l i/o drive trhoh rp = 50k 30 42 60 18 rp = 5k re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhoh t rloh dout dout t rea notes : transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t rhoh trhoh = c l * v ol * rp / vcc trloh(min, 3.3v part) = trhoh - treh extended data out mode for the edo mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that cont roller could fetch the data at the falling edge. however nand flash dosen?t support the edo mode exactly. the device stops the data input into the i/o bus after re rising edge. but since the previous dat a remains in the i/o bus, the flow of i/ o data seems like figure 18 and the system can access serially t he data with edo mode. trloh which is the parameter for fetchin g data at re falling time is necessary. its appropriate value can be obtained with the reference chart as shown in figure 19. the trhoh value depands on output load(c l ) and i/o bus pull-up resistor (rp).

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