View UPD4811650GF-A10-9BT_7120888.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. ? 1998 mos integrated circuit m pd4811650 for rev.e 16 m-bit synchronous gram 256k-word by 32-bit by 2-bank preliminary data sheet document no. m13616ej2v0ds00 (1st edition) date published august 1998 ns cp (k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd4811650 is a synchronous graphics memory (sgram) organized as 262,144 words 32 bits 2 banks random access port. this device can operate up to 143 mhz by using synchronous interface. also, it has 8-column block write function to improve capability in graphics system. this product is packaged in 100-pin plastic tqfp (14 20 mm). features 262,144 words 32 bits 2 banks memory synchronous interface (fully synchronous dram with all input signals are latched at rising edge of clock) : pulsed interface : automatic precharge and controlled precharge commands : ping-pong operation between the two internal memory banks : up to 143 mhz operation frequency possible to assert random column address in every cycle dual internal banks controlled by a10 (bank address: ba) byte control using dqm0 to dqm3 signals both in read and write cycle 8-column block write (bw) function persistent write per bit (wpb) function wrap sequence : sequential / interleave programmable burst length (1, 2, 4, 8 and full page) programmable /cas latency (-a70r: 3, -a80, -a10, -a12: 2 and 3) power down operation and clock suspend operation auto refresh (cbr refresh) or self refresh capability single 3.3 v 0.3 v power supply lvttl compatible inputs and outputs 100-pin plastic tqfp (14 20 mm) 2,048 refresh cycles/32 ms burst termination by precharge command burst termination by burst stop command ordering information part number cycle time clock frequency package ns (min.) mhz (max.) m pd4811650gf-a70r-9bt 7 143 100-pin plastic tqfp (14 20 mm) m pd4811650gf-a80-9bt 8 125 m pd4811650gf-a10-9bt 10 100 m pd4811650gf-a12-9bt 12 83 h
2 preliminary data sheet m m m m pd4811650 for rev. e part number m pd48 nec cmos application specific memory device code 1: graphics ram capacity 16: 16m bits words organization 5: x32 function package gf: tqfp v cc a: 3.3 v 0.3 v cycle time 70r: 7 ns 80: 8 ns 10: 10 ns 12: 12 ns 1165 0 gf a80 -
3 m m m m pd4811650 for rev. e preliminary data sheet pin configuration (marking side) 100-pin plastic tqfp (14 20 mm) m m m m pd4811650gf-axx-9bt 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dq28 v cc q dq27 dq26 v ss q dq25 dq24 v cc q dq15 dq14 v ss q dq13 dq12 v cc q v ss v cc dq11 dq10 v ss q dq9 dq8 v cc q nc dqm3 dqm1 clk cke dsf nc a9 dq3 v cc q dq4 dq5 v ss q dq6 dq7 v cc q dq16 dq17 v ss q dq18 dq19 v cc q v cc v ss dq20 dq21 v ss q dq22 dq23 v cc q dqm0 dqm2 /we /cas /ras /cs a10 a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dq29 v ss q dq30 dq31 v ss nc nc nc nc nc nc nc nc nc nc v cc dq0 dq1 v ss q dq2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 a7 a6 a5 a4 v ss nc nc nc nc nc nc nc nc nc nc v cc a3 a2 a1 a0 a0 - a10 a0 - a9 a0 - a7 a10 dq0 - dq31 /cs /ras /cas /we dqm0 - dqm3 dsf cke clk v cc v ss v cc q v ss q nc : : : : : : : : : : : : : : : : : : address inputs row address inputs column address inputs bank address data inputs/outputs chip select row address strobe column address strobe write enable dq mask enable special function enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection
4 preliminary data sheet m m m m pd4811650 for rev. e block diagram refresh counter row decoder row decoder address buffer a0 a1 a2 a10 random i/o buffer dq0 to 31 v cc q v ss q dqm0 to 3 color register (32 bits) mask register (32 bits) 256 col. x 32 i/o 1,024 rows 32 32 256 col. x 32 i/o 1,024 rows 32 timing generator clk cke /cs /ras /cas /we dsf v cc v ss memory cell array bank b sense amp. column decoder memory cell array bank a sense amp. column decoder
5 m m m m pd4811650 for rev. e preliminary data sheet contents 1. input/output pin function ..... 7 2. commands ..... 8 3. simplified state diagram ..... 12 4. truth table ..... 13 4.1 command truth table ..... 13 4.2 dqm truth table ..... 13 4.3 cke truth table ..... 14 4.4 operative command table ..... 15 4.5 command truth table for cke ..... 22 4.6 command truth table for two banks operation ..... 23 5. initialization ..... 24 6. programming the mode register ..... 25 7. mode register ..... 26 7.1 burst length and sequence ..... 27 8. programming the special register ..... 28 8.1 color register ..... 28 8.2 mask register ..... 28 8.3 special register ..... 28 9. address bits of bank address and precharge ..... 29 10. precharge ..... 30 11. auto precharge ..... 31 11.1 read with auto precharge ..... 31 11.2 write with auto precharge ..... 32 11.3 block write with auto precharge ..... 33 12. write/block write with write per bit ..... 34 12.1 write per bit ..... 34 13. block write ..... 34 13.1 block write ..... 34 13.2 column mask ..... 35
6 preliminary data sheet m m m m pd4811650 for rev. e 13.3 block write function ..... 36 14. read/write command interval ..... 37 14.1 read to read command interval ..... 37 14.2 write to write command interval ..... 37 14.3 write to read command interval ..... 38 14.4 block write to write or write/block write command interval ..... 39 14.5 block write to read command interval ..... 39 14.6 read to write/block write command interval ..... 40 15. burst termination ..... 41 15.1 burst stop command in full page ..... 41 15.2 precharge termination ..... 42 15.2.1 precharge termination in read cycle ..... 42 15.2.2 precharge termination in write cycle ..... 43 16. electrical specifications ..... 44 16.1 ac parameters for read/write cycles ..... 49 16.2 relationship between frequency and latency ..... 51 16.3 /cs function ..... 52 16.4 basic cycles ..... 53 16.4.1 initialization ..... 53 16.4.2 mode register set ..... 54 16.4.3 refresh cycle ..... 55 16.4.4 cycle with auto precharge ..... 57 16.4.5 full page mode cycle ..... 61 16.4.6 precharge termination cycle ..... 65 16.4.7 clock suspension ..... 67 16.4.8 power down mode ..... 71 16.4.9 other cycles ..... 72 16.5 graphics cycles ..... 74 16.6 application cycles ..... 79 16.6.1 page cycles with same bank ..... 79 16.6.2 cycles with ping-pong banks ..... 83 16.6.3 read and write cycles ..... 87 16.6.4 full page random cycles ..... 89 17. package drawing ..... 91 18. recommended soldering conditions ..... 92
7 m m m m pd4811650 for rev. e preliminary data sheet 1. input/output pin function pin name input/output function clk input clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not asserted and the m pd4811650 suspends operation. when the m pd4811650 is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. in self refresh mode, low level on this pin is also used as part of the input command to specify self refresh. /cs input /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, /we input /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. dsf input dsf is part of the inputs of graphics command of the m pd4811650. if dsf is inactive (low level), m pd4811650 operates as same as sdram. a0 - a9 input row address is determined by a0 - a9 at the clk (clock) rising edge in the activate command cycle. column address is determined by a0 - a7 at the clk rising edge in the read or write command cycle. a9 defines the precharge mode. when a9 is high in the precharge command cycle, both banks are precharged; when a9 is low, only the bank selected by a10 is precharged. when a9 is high in read or write command cycle, the precharge starts automatically after the burst access. a10 a10 is the bank address signal (ba). in command cycle, a10 low selects bank a and a10 high selects bank b. dqm0 - dqm3 input dqm controls i/o buffers. dqm0 corresponds to the lowest byte (dq0 to dq7), dqm1 corresponds to dq8 to dq15, dqm2 corresponds to dq16 to dq23. dqm3 corresponds to dq24 to dq31. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clo cks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq31 input/output dq pins have the same function as i/o pins on a conventional dram. these are normally 32-bit data bus and are used for inputting and outputting data. function as the mask data input pins in the special register set command. write operations can be performed after active command with wpb (old mask data). functions as the column selection data input pin in the block write cycle. v cc , v ss , v cc q,v ss q (power supply) v cc and v ss are power supply pins for internal circuits. v cc q and v ss q are power supply pins for the output buffers.
8 preliminary data sheet m m m m pd4811650 for rev. e 2. commands mode register set command (/cs, /ras, /cas, /we, dsf = low) the m pd4811650 has a mode register that defines how the device operates. in this command, a0 through a10 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when both banks are in idle state. during 2 clk (t rsc ) following this command, the m pd4811650 cannot accept any other commands. refer to 6. programming the mode register . fig.1 mode register set command add a9 a10 /we /cas /ras /cs cke clk h dsf bank activate command (/cs, /ras, /dsf = low, /cas, /we = high) the m pd4811650 has two banks, each with 1,024 rows. this command activates the bank selected by a10 (ba) and a row address selected by a0 through a9. this command corresponds to a conventional drams /ras falling. fig.2 row address strobe and bank activate command add a9 a10 /we /cas /ras /cs cke clk h row row (bank address) dsf bank activate command with wpb enable (/cs, /ras = low, /cas, /we, /dsf = high) this command is same as bank activate command. after this command, write per bit function is available. mask registers data is used as write mask data. refer to 12. write/block write with write per bit . fig.3 row address strobe and bank activate command with wpb enable add a9 a10 /we /cas /ras /cs cke clk h row row (bank address) dsf
9 m m m m pd4811650 for rev. e preliminary data sheet precharge command (/cs, /ras, /we, dsf = low, /cas = high) this command begins precharge operation of the bank selected by a10 (ba) and a9. when a9 is high, both banks are precharged, regardless of a10. when a9 is low, only the bank selected by a10 is precharged. a10 low selects bank a and a10 high selects bank b. after this command, the m pd4811650 cant accept the activate command to the precharging bank during t rp (precharge to activate command period). this command can terminate the current burst operation (2, 4, 8, full page burst length). this command corresponds to a conventional drams /ras rising. refer to 10. precharge and 11. auto precharge . fig.4 precharge command add a9 a10 /we /cas /ras /cs cke clk h (bank address) (precharge select) dsf write command (/cs, /cas, /we, dsf = low, /ras = high) if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data must be input with this write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. fig.5 column address and write command add a9 a10 /we /cas /ras /cs cke clk h (bank address) col. dsf read command (/cs, /cas, dsf = low, /ras, /we = high) this command sets the burst start address given by the column address. read data is available after /cas latency requirements have been met. fig.6 column address and read command add a9 a10 /we /cas /ras /cs cke clk h (bank address) col. dsf
10 preliminary data sheet m m m m pd4811650 for rev. e cbr (auto) refresh command (/cs, /ras, /cas, dsf = low, /we, cke = high) this command is a request to begin the cbr refresh operation. the refresh address is generated internally. before executing cbr refresh, both banks must be precharged. after this cycle, both banks will be in the idle (precharged) state and ready for a bank activate command. during t rc period (from refresh command to refresh or activate command), the m pd4811650 cannot accept any other command. fig.7 cbr (auto) refresh command add a9 a10 /we /cas /ras /cs cke clk h (bank address) dsf self refresh entry command (/cs, /ras, /cas, dsf, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the m pd4811650 exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, both banks must be precharged. fig.8 self refresh entry command add a9 a10 /we /cas /ras /cs cke clk (bank address) dsf burst stop command in full page (/cs, /we, dsf = low, /ras, /cas = high) this command can stop the current burst operation. refer to 14. read/write command interval and 15. burst termination . fig.9 burst stop command in full page mode add a9 a10 /we /cas /ras /cs cke clk (bank address) h dsf h
11 m m m m pd4811650 for rev. e preliminary data sheet no operation (/cs, dsf = low, /ras, /cas, /we = high) this command is not a execution command. no operations begin or terminate by this command. fig.10 no operation add a9 a10 /we /cas /ras /cs cke clk h (bank address) dsf special register set command (/cs, /ras, /cas, /we = low, dsf = high) the m pd4811650 has two special registers for graphics commands. one is color register and the other is mask register. in this command, a0 through a10 are the data input pins for the register select (color or mask register). dq0 through dq31 are the data input pins for the color data or the wpb data. during 2 clk (t rsc ) following this command, the m pd4811650 can not accept any other commands. refer to 8. programming the special register . fig.11 special register set command /we /cas /ras /cs cke clk h dsf add a9 a10 dqi color/mask masked block write command (/cs, /cas, /we = low, /ras, dsf = high) this command activates 8-column block write function. in this command, the burst length = 1. write data comes from color register, column address mask data is input from dqi in this command. refer to 13. block write . fig.12 masked block write command /we /cas /ras /cs cke clk h dsf add a9 a10 dqi column mask
12 preliminary data sheet m m m m pd4811650 for rev. e 3. simplified state diagram cke cke cke cke cke cke cke cke precharge auto precharge pre read with auto precharge read bst bst pre (precharge termination) pre (precharge termination) act mrs ref cke cke self self exit idle mode register set cbr refresh row active self refresh power down active power down precharge read reada read suspend reada suspend writ/bw writa/bwa writ/bw suspend writa/bwa suspend power on write/block write read automatic sequence manual input cke cke read special register set srs actwpb srs write/block write write/block write with write/block write
13 m m m m pd4811650 for rev. e preliminary data sheet 4. truth table 4.1 command truth table function symbol cke /cs /ras /cas /we dsf address n - 1 n a10 a9 a8 a7-a0 device deselect desl h x h x x x x x x x x no operation nop h x l h h h l x x x x burst stop in full page bst h x l h h l l x x x x read read h x lhlhlbal xca read with auto precharge reada h x l h l h l ba h x ca write writ h x l h l l l ba l x ca write with auto precharge writa h x l h l l l ba h x ca masked block write bw h x l h l l h ba l x ca masked block write with auto precharge bwa h x l h l l h ba h x ca bank activate act h x l l h h l ba ra bank activate with wpb enable actwpb h x l l h h h ba ra precharge select bank pre h x l l h l l ba l x x precharge all banks pall h x l l h l l x h x x mode register set mrs h x l l l l l op.code special register set srs h x l l l l h op.code remark h = high level, l = low level, x = high or low level (don t care), ba = bank address (a10), ra = row address, ca = column address 4.2 dqm truth table function symbol cke dqmi n - 1 n data write/output enable enbi h x l data mask/output disable maski h x h remark h = high level, l = low level, x = high or low level (don t care), i = 0, 1, 2, 3
14 preliminary data sheet m m m m pd4811650 for rev. e 4.3 cke truth table current state function symbol cke /cs /ras /cas /we dsf address n C 1 n activating clock suspend mode entry h l x xxxx x any clock suspend l l x xxxx x clock suspend clock suspend mode exit l h x xxxx x idle cbr refresh command ref h h l l l h l x idle self refresh entry self h l l l l h l x self refresh self refresh exit l h l h h h x x l hhxxxx x idle power down entry h l xxxxx x power downpower down exit l h xxxxx x remark h = high level, l = low level, x = high or low level (don t care)
15 m m m m pd4811650 for rev. e preliminary data sheet 4.4 operative command table note 1 (1/7) current state /cs /ras /cas /we dsf address command action notes idle h x x x x x desl nop or power down 2 l h h h x x nop nop or power down 2 l h h l h x undefined illegal l h h l l x bst illegal 3 l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal 3 l h l l h ba, ca, a9 bw/bwa illegal 3 l h l l l ba, ca, a9 writ/writa illegal 3 l l h h h ba, ra actwpb bank active with wpb: latch ra l l h h l ba, ra act bank active: latch ra l l h l h x undefined illegal l l h l l ba, a9 pre/pall nop 11 l l l h h x undefined illegal l l l h l x ref/self cbr refresh/self refresh 4,12 llllhop-codesrs special register access lllllop-codemrs m ode register access 12 bank active h x x x x x desl nop lhhh xx nop nop l h h l h x undefined illegal l h h l l x bst illegal 3 l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada begin read; latch ca: determine ap 5 l h l l h ba, ca, a9 bw/bwa begin block write; latch ca: determine ap 5 l h l l l ba, ca, a9 writ/writa begin write; latch ca: determine ap 5 l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall precharge 6 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs special register access lllllop-codemrs illegal
16 preliminary data sheet m m m m pd4811650 for rev. e (2/7) current state /cs /ras /cas /we dsf address command action notes read h x x x x x desl continue burst to end ? bank active l h h h x x nop continue burst to end ? bank active l h h l h x undefined illegal l h h l l x bst burst stop ? bank active l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada term burst, new read: determine ap 7 l h l l h ba, ca, a9 bw/bwa term burst, start block write: determine ap 7, 8 l h l l l ba, ca, a9 writ/writa term burst, start write: determine ap 7, 8 l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall term burst, precharge timing for reads l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal write/block write h x x x x x desl continue burst to end ? write recovering lhhh xx nop continue burst to end ? write recovering l h h l h x undefined illegal l h h l l x bst burst stop ? bank active l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada term burst, start read: determine ap 7, 8 l h l l h ba, ca, a9 bw/bwa term burst, new block write: determine ap 7 l h l l l ba, ca, a9 writ/writa term burst, new write: determine ap 7 l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall term burst, precharge timing for writes 3, 9 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal h h
17 m m m m pd4811650 for rev. e preliminary data sheet (3/7) current state /cs /ras /cas /we dsf address command action notes read with auto h x x x x x desl continue burst to end ? precharging precharge l h h h x x nop continue burst to end ? precharging l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal l h l l h ba, ca, a9 bw/bwa illegal l h l l l ba, ca, a9 writ/writa illegal l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal 3 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal write/block write with auto h x x x x x desl continue burst to end ? write recovering with auto precharge precharge l h h h x x nop continue burst to end ? write recovering with auto precharge l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal l h l l h ba, ca, a9 bw/bwa illegal l h l l l ba, ca, a9 writ/writa illegal l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal 3 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal
18 preliminary data sheet m m m m pd4811650 for rev. e (4/7) current state /cs /ras /cas /we dsf address command action notes precharging h x x x x x desl nop ? enter idle after t rp lhhh xx nop nop ? enter idle after t rp l h h l h x undefined illegal l h h l l x bst illegal 3 l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal 3 l h l l h ba, ca, a9 bw/bwa illegal 3 l h l l l ba, ca, a9 writ/writa illegal 3 l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall nop ? enter idle after t rp 11 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs special register access lllllop-codemrs illegal bank activating h x x x x x desl nop ? enter bank active after t rcd (t rcd ) lhhh xx nop nop ? enter bank active after t rcd l h h l h x undefined illegal l h h l l x bst illegal 3 l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal 3 l h l l h ba, ca, a9 bw/bwa illegal 3 l h l l l ba, ca, a9 writ/writa illegal 3 l l h h h ba, ra actwpb illegal 3, 10 l l h h l ba, ra act illegal 3, 10 l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal 3 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs special register access lllllop-codemrs illegal
19 m m m m pd4811650 for rev. e preliminary data sheet (5/7) current state /cs /ras /cas /we dsf address command action notes write recovering h x x x x x desl nop ? enter bank active after t dpl (t dpl ) lhhh xx nop nop ? enter bank active after t dpl l h h l h x undefined illegal l h h l l x bst illegal 3 l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada begin read; latch ca: determine ap 8 l h l l h ba, ca, a9 bw/bwa begin block write; latch ca: determine ap l h l l l ba, ca, a9 writ/writa begin write; latch ca: determine ap l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal 3 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs special register access lllllop-codemrs illegal write recovering h x x x x x desl nop ? enter precharge after t dpl with auto l h h h x x nop nop ? enter precharge after t dpl precharge l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal 3, 8 l h l l h ba, ca, a9 bw/bwa illegal 3 l h l l l ba, ca, a9 writ/writa illegal 3 l l h h h ba, ra actwpb illegal 3 l l h h l ba, ra act illegal 3 l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal 3 l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs special register access lllllop-codemrs illegal
20 preliminary data sheet m m m m pd4811650 for rev. e (6/7) current state /cs /ras /cas /we dsf address command action notes refreshing h x x x x x desl nop ? enter idle after t rc lhhh xx nop nop ? enter idle after t rc l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal l h l l h ba, ca, a9 bw/bwa illegal l h l l l ba, ca, a9 writ/writa illegal l l h h h ba, ra actwpb illegal l l h h l ba, ra act illegal l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal mode register h x x x x x desl nop ? enter idle after t rsc accessing l h h h x x nop nop ? enter idle after t rsc l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal l h l l h ba, ca, a9 bw/bwa illegal l h l l l ba, ca, a9 writ/writa illegal l l h h h ba, ra actwpb illegal l l h h l ba, ra act illegal l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal
21 m m m m pd4811650 for rev. e preliminary data sheet (7/7) current state /cs /ras /cas /we dsf address command action notes special mode h x x x x x desl nop ? enter previous state after t rsc register l h h h x x nop nop ? enter previous state after t rsc accessing l h h l h x undefined illegal l h h l l x bst illegal l h l h h x undefined illegal l h l h l ba, ca, a9 read/reada illegal l h l l h ba, ca, a9 bw/bwa illegal l h l l l ba, ca, a9 writ/writa illegal l l h h h ba, ra actwpb illegal l l h h l ba, ra act illegal l l h l h x undefined illegal l l h l l ba, a9 pre/pall illegal l l l h h x undefined illegal l l l h l x ref/self illegal llllhop-codesrs illegal lllllop-codemrs illegal notes 1. all entries assume that cke was active (high level) during the preceding clock cycle. 2. if both banks are idle, and cke is inactive (low level), m pd4811650 will enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive (low level), m pd4811650 will enter self refresh. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which dont satisfy t dpl . 10. illegal if t rrd is not satisfied. 11. nop to bank precharging or in idle state. may precharge bank(s) indicated by ba (and a9). 12. illegal if any bank is not idle. remark h = high level, l = low level, x = high or low level (dont care), v = valid data input, ba = bank address (a10), a9 = precharge select, ra = row address, ca = column address, term = terminate, ap = auto precharge, nop = no operation, illegal = device operation and/or data-integrity are not guaranteed
22 preliminary data sheet m m m m pd4811650 for rev. e 4.5 command truth table for cke current state cke /cs /ras /cas /we dsf address action notes n- 1 n self refresh hxxxxxxx invalid, clk(n C1 ) would exit s.r. (s.r.) l h h x x x x x s.r. recovery lhlhhx xx s.r. recovery lhlhl x xx illegal l h l l x x x x illegal llxxxxxx maintain s.r. self refresh h h h x x x x x idle after t rc recovery h h l h h x x x idle after t rc h h l h l x x x illegal h h l l x x x x illegal hlhxxxxx illegal h l l h h x x x illegal h l l h l x x x illegal hlllxxxx illegal power downhxxxxxxx invalid, clk(n C1 ) would exit p.d. (p.d.) lhxxxxxx exit p.d. ? idle llxxxxxx maintain power down mode both banks h h h x x x x x refer to operations in operative command table idle h h l h x x x x refer to operations in operative command table h h l l h x x x refer to operations in operative command table hhlllhlx refresh hhllllxop-coderefer to operations in operative command table h l h x x x x x refer to operations in operative command table h l l h x x x x refer to operations in operative command table h l l l h x x x refer to operations in operative command table hllllhlx self refresh 1 hlllllxop-coderefer to operations in operative command table lxxxxxxx power down 1 row active hxxxxxxx refer to operations in operative command table lxxxxxxx power down 2 any state otherhhxxxxxx refer to operations in operative command table than listed h l xxxxxx begin clock sus pend next cycle 2 above l h xxxxxx exit clock sus pend next cycle llxxxxxx maintain clock sus pend notes 1. self refresh can be entered only from the both banks idle state. power down can be entered from the both banks idle state or row active state. 2. must be legal command as defined in operative command table. remark h = high level, l = low level, x = high or low level (dont care)
23 m m m m pd4811650 for rev. e preliminary data sheet 4.6 command truth table for two banks operation /cs /ras /cas /we dsf a10(ba) a9 a8 - a0 action fromstate note1 tostate note2 hxxxxxxxnop any any lhhhl x x xnop any any l h h l l x x x bst (r/w/a)0(i/a)1 a0(i/a)1 i0(i/a)1 i0(i/a)1 (r/w/a)1(i/a)0 a1(i/a)0 i1(i/a)0 i1(i/a)0 l h l h l h h ca read (r/w/a)1(i/a)0 rp1(i/a)0 h h ca a1(r/w)0 rp1a0 h l ca (r/w/a)1(i/a)0 r1(i/a)0 h l ca a1(r/w)0 r1a0 l h ca (r/w/a)0(i/a)1 rp0(i/a)1 l h ca a0(r/w)1 rp0a1 l l ca (r/w/a)0(i/a)1 r0(i/a)1 l l ca a0(r/w)1 r0a1 l h l l l/h h h ca write/block write (r/w/a)1(i/a)0 wp1(i/a)0 h h ca a1(r/w)0 wp1a0 h l ca (r/w/a)1(i/a)0 w1(i/a)0 h l ca a1(r/w)0 w1a0 l h ca (r/w/a)0(i/a)1 wp0(i/a)1 l h ca a0(r/w)1 wp0a1 l l ca (r/w/a)0(i/a)1 w0(i/a)1 l l ca a0(r/w)1 w0a1 l l h h l/h h ra active row i1any0 a1any0 l ra i0any1 a0any1 l l h l l x h x precharge (r/w/a/i)0(i/a)1 i0i1 x h x (r/w/a/i)1(i/a)0 i1i0 h l x (r/w/a/i)1(i/a)0 i1(i/a)0 h l x (i/a)(r/w/a/i)0 i1(r/w/a/i)0 l l x (r/w/a/i)0(i/a)1 i0(i/a)1 l l x (i/a)0(r/w/a/i)1 i0(r/w/a/i)1 l l l h l x x x refresh i0i1 i0i1 l l l l l op-code mode register access i0i1 i0i1 l l l l h op-code special register access (i/a)0(i/a)1 (i/a)0(i/a)1 notes 1. if the m pd4811650 is in a state other than above listed in the from state column, the command is illegal. 2. the states listed under to might not be entered on the next clock cycle. timing restrictions apply.
24 preliminary data sheet m m m m pd4811650 for rev. e remark h = high level, l = low level, x = high or low level (dont care), ba = bank address (a10) state abbreviations i = idle a = bank active r = read with no precharge (no precharge is posted) w = write with no precharge (no precharge is posted) rp = read with auto precharge (precharge is posted) wp = write with auto precharge (precharge is posted) any = any state x0y1 = bank0 is in state x, bank1 = in state y (x/y)0z1 = z1(x/y)0 = bank0 is in state x or y, bank1 is in state z 5. initialization the synchronous gram is initialized in the power-on sequence according to the following. (1) apply power and start clock. attempt to maintain cke = h, dqm = h, and nop or desl condition at the inputs. (2) maintain stable power, stable clock, cke = h, dqm = h, and nop or desl condition for a minimum of 100 m s. (3) issue precharge commands for all banks of the device. (4) issue a mode register set command to initialize the mode register. (5) issue two or more auto refresh commands. the device is now in the idle state and is ready for normal operation. remarks 1. the sequence of mode register programming and refresh above may be transposed. 2. the data bus is guaranteed to be high impedance after waiting a minimum of 100 m s (refer to step (2) above). it is recommended to maintain cke and dqm high until the precharge command is issued.
25 m m m m pd4811650 for rev. e preliminary data sheet 6. programming the mode register the mode register is programmed by the mode register set command using address bits a10 through a0 as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has four fields; options : a10 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be asserted before at least 2 clk (t rsc ) have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. the table in 16.2 relationship between frequency and latency shows the relationship of /cas latency to the clock period and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 1, 2, 4, 8 or full page (256 columns). wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. the m pd4811650 supports sequential mode and interleave mode. the table in 7.1 burst length and sequence shows the addressing sequence for each burst length.
26 preliminary data sheet m m m m pd4811650 for rev. e 7. mode register 1 0 0 0 1 2 3 4 5 76 8 9 jedec standard test set (refresh counter test) bl wt ltmode 0 0 1 0 1 2 3 4 5 76 8 9 burst read and single write (for write through cache) 0 1 0 1 2 3 4 5 76 8 9 use in future v v v v v v 1v 1 x 0 1 2 3 4 5 76 8 9 vender specific bl wt ltmode 0 0 0 0 1 2 3 4 5 76 8 9 mode register set v = valid x = don't care wt = 0 1 2 4 8 r r r full page a2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type /cas latency r r 2 3 r r r r a6-4 000 001 010 011 100 101 110 111 latency mode 0 10 10 10 x 10 0 10 wt = 1 1 2 4 8 r r r r 0 clk cke /cs /ras /cas /we a0 - a10 mode register write dsf remark r : reserved mode register write timing
27 m m m m pd4811650 for rev. e preliminary data sheet 7.1 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing with the length being 256.
28 preliminary data sheet m m m m pd4811650 for rev. e 8. programming the special register the special register is programming by the special register set command using address bits a10 through a0 and data bits dq0 through dq31. the color and mask register retain data until it is reprogrammed or the device losed power. the special register has four fields; reserved : a10 through a7 color register : a6 mask register : a5 reserved : a4 through a0 following special register programming, no command can be asserted before at least 2 clk (t rsc ) have elapsed. 8.1 color register color register is used as write data in block write cycle. in special register set command, if a5 is 0 and a6 is 1, the color register is selected. and the data of dq0 through dq31 is stored to color register as color data (write data). 8.2 mask register mask register is used as write mask data in write and block write cycle. in special register set command, if a5 is 1 and a6 is 0, the mask register is selected. and the data of dq0 through dq31 is stored to mask register as write mask data. 8.3 special register 0 0 0 0 0 0 1 2 3 4 5 76 8 9 function not load load bits 5 0 1 mask register lc lm 0 0 0 function not load load bits 6 0 1 color register 10 0 remark if lc and lm are both high (1), data of mask and color register will be unknown.
29 m m m m pd4811650 for rev. e preliminary data sheet 9. address bits of bank address and precharge a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 row (activate command) select bank a "activate" command 0 result precharge bank a precharge bank b precharge all banks a9 0 0 1 select bank b "activate" command 1 a10 0 1 x a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 (precharge command) disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 enables read/write commands for bank a 0 enables read/write commands for bank b 1 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) x : don't care a10 a10 a10 clk cke /cs /ras /cas /we h a9 a10 clk cke /cs /ras /cas /we h a9 a10 clk cke /cs /ras /cas /we h a9 a10 dsf dsf dsf precharge for bank a precharge for bank b precharge for all banks
30 preliminary data sheet m m m m pd4811650 for rev. e 10. precharge the precharge command can be asserted anytime after t ras(min.) is satisfied. soon after the precharge command is asserted, precharge operation performed and the synchronous gram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows. /cas latency = 2 : one clock earlier than the last read data. /cas latency = 3 : two clocks earlier than the last read data. t0 t1 t2 t3 t4 t5 t6 t7 burst length=4 read read q1 q2 q3 q4 pre hi-z q1 q2 q3 q4 pre hi-z (t ras is satisfied) clk command /cas latency = 2 dq command /cas latency = 3 dq in order to write all data to the memory cell correctly, the asynchronous parameter t dpl , t bpl must be satisfied. the t dpl(min.) , t bpl(min.) specification define the earliest time that a precharge command can be asserted. minimum number of clocks are calculated by dividing t dpl (min.) , t bpl(min.) with clock cycle time. in summary, the precharge command can be asserted relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. /cas latency read write block write 2C1+t dpl(min.) +t bpl(min.) 3C2+t dpl(min.) +t bpl(min.)
31 m m m m pd4811650 for rev. e preliminary data sheet 11. auto precharge during a read or write/block write command cycle, a9 controls whether auto precharge is selected. a9 high in the read or write/block write command (read with auto precharge command or write with auto precharge command/block write with auto precharge command), auto precharge is selected and begins after the burst access automatically. the t ras must be satisfied with a read with auto precharge or a write/ block write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after t rp has been satisfied. in write cycle, the t dal , t bal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on both the /cas latency programmed into the mode register and whether read or write/block write cycle. 11.1 read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras is satisfied)
32 preliminary data sheet m m m m pd4811650 for rev. e 11.2 write with auto precharge during a write cycle, the auto precharge begins one clock after the last data word input to the device (/cas latency of 2 or 3). db1 db2 db3 db4 auto precharge starts writa b hi-z db1 db2 db3 db4 auto precharge starts writa b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras is satisfied)
33 m m m m pd4811650 for rev. e preliminary data sheet 11.3 block write with auto precharge during a block write cycle, the auto precharge begins after t bwc of the last data word input to the device (/cas latency of 2 or 3). clk t0 t2 t1 t3 t4 t5 dq /cas latency = 2 command cm hi-z bwa dq /cas latency = 3 command cm hi-z bwa auto precharge starts auto precharge starts (t ras is satisfied) t bwc(min.) t bwc(min.) remark cm : column mask in summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means clocks after the reference. /cas latency read write block write 2C1+1+t bwc(min.) 3C2+1+t bwc(min.)
34 preliminary data sheet m m m m pd4811650 for rev. e 12. write/block write with write per bit 12.1 write per bit the write per bit function writes data using the write mask data only in the required dqi pins. it writes when the write mask data is 1 and prohibits writing when the data is 0 (refer to 8.2 mask register ). to use wpb operation (1) execute special register set command and set wpb data (32 bits) to mask register. (2) execute bank activate with wpb enable command (actwpb) after t rsc (2 clk) period from special register set command (srs). (3) execute write/block write command after t rcd period from actwpb. in case srs command is executed in activate state to set new wpb data, it is necessary to take t rsc (2 clk) interval between srs and write/block write command. remark mask data = mask registers data (wpb) + dqmi dqmi is prior to mask registers data (wpb) 13. block write 13.1 block write this cycle writes the color register data in 256 bits (8 columns x 32 i/os) memory cell in one cycle. the memory cell range in which data can be written in one block write cycle is eight continuous columns on one row address. this cycle controls writing in 8 columns x 8 dq = 64 bits by dqm0 to dqm3 input. color register data is written to the memory cell if dqm is low but not if dqm is high. dqm0 corresponds to the lowest byte (dq0 to dq7), dqm1 corresponds to dq8 to dq15, dqm2 corresponds to dq16 to dq23, dqm3 corresponds to dq24 to dq31. any column of the eight columns can be selected and writing prohibited. determine whether to write or prohibit writing according to the data selected for column (refer to 13.2 column mask ). to use block write operation (1) execute special register set command and set color data (32 bits) to color register. (2) execute bank activate (act) or bank activate with wpb enable command (actwpb) after t rsc (2 clk) period from srs. (3) execute block write command after t rcd period from act or actwpb. in case new write/block write is executed or, it is necessary to take t bwc interval from block write command to new write/block write command.
35 m m m m pd4811650 for rev. e preliminary data sheet 13.2 column mask in block write cycle any column of the eight columns can be selected and writing prohibited. determine which column to select according to the dqi pin to which the data selected for the column is to be input. refer to the table below. column address note column address and corresponding dq pin column select data writing a2 a1 a0 dqi (dqi) i 0 0 0 dq0/dq8/ 1 yes (1st column) dq16/dq24 0 no i+1 0 0 1 dq1/dq9/ 1 yes (2nd column) dq17/dq25 0 no i+2 0 1 0 dq2/dq10/ 1 yes (3rd column) dq18/dq26 0 no i+3 0 1 1 dq3/dq11/ 1 yes (4th column) dq19/dq27 0 no i+4 1 0 0 dq4/dq12/ 1 yes (5th column) dq20/dq28 0 no i+5 1 0 1 dq5/dq13/ 1 yes (6th column) dq21/dq29 0 no i+6 1 1 0 dq6/dq14/ 1 yes (7th column) dq22/dq30 0 no i+7 1 1 1 dq7/dq15/ 1 yes (8th column) dq23/dq31 0 no note refer to 13.3 block write function . remark i is times of 8 numeric.
36 preliminary data sheet m m m m pd4811650 for rev. e 13.3 block write function color register color data dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 = 1 dq1 = 1 dq2 = 1 dq3 = 0 dq4 = 0 dq5 = 1 dq6 = 1 dq7 = 0 column address mask mask register dq7 to dq0 01001011 dqm0 = 0 i i + 1 i + 2 i + 3 i + 4 i + 5 i + 6 i + 7 column address write data mask write, keep original data remarks 1. i is times of 8 numeric. 2. this diagram shows only for dq0 - dq7. the other dq is similar as this.
37 m m m m pd4811650 for rev. e preliminary data sheet 14. read/write command interval 14.1 read to read command interval during a read cycle, when new read command is asserted, it will be effective after /cas latency, even if the previous read operation does not completed. read command will be interrupted by another read command. the interval between the commands is minimum 1 cycle. each read command can be asserted in every clock without any restriction. qb1 qb2 qb3 qb4 hi-z read a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 read b qa1 1cycle 14.2 write to write command interval during a write cycle, when new write command is asserted, the previous burst will terminate and the new burst will begin with a new write command. write command will be interrupted by another write command. the interval between the commands is minimum 1 cycle. each write command can be asserted in every clock without any restriction. db1 db2 db3 db4 hi-z writ a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 writ b da1 1cycle
38 preliminary data sheet m m m m pd4811650 for rev. e 14.3 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . qb1 qb2 qb3 qb4 writ a hi-z qb1 qb2 qb3 qb4 writ a hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 da1 da1 read b read b
39 m m m m pd4811650 for rev. e preliminary data sheet 14.4 block write to write or write/block write command interval the interval between block write command and new block write command or write command is t bwc or minimum 1 cycle. if t ck is less than t bwc , nop command should be issued for the cycle between block write command and the following write command or new block write command. d1 d2 d3 bw dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 bw dq cm1 cm2 bw writ cm d4 burst length = 4, /cas latency = 2 hi-z command /cas latency = 2 t bwc t bwc 14.5 block write to read command interval block write command and read command is also t bwc or minimum 1 cycle. the data bus must be hi-z at least one cycle prior to the first d out . clk t0 t2 t1 t3 t4 t5 t6 t7 t8 bw /cas latency = 2 command dq cm q1 q2 q3 q4 hi-z bw /cas latency = 3 command dq cm q1 q2 q3 hi-z read read q4 t bwc t bwc
40 preliminary data sheet m m m m pd4811650 for rev. e 14.6 read to write/block write command interval during a read cycle, read command can be interrupted by write/block write command. the read and write/block write command interval is minimum 1 cycle. there is a restriction to avoid data conflict. the data bus must be hi-z using dqm before write/block write command. d1 d2 d3 d4 read dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 writ dqm hi-z 1cycle read command can be interrupted by write/block write command. dqm must be high at least 3 clocks prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command d1 d2 d3 writ dqm hi-z is necessary q1 q2 read dq command d1 d2 d3 writ dqm hi-z is necessary /cas latency = 2 /cas latency = 3
41 m m m m pd4811650 for rev. e preliminary data sheet 15. burst termination burst termination is to terminate a burst operation other than using a read or write command. 15.1 burst stop command during a read cycle, when the burst stop command is asserted, the burst read data are terminated and the data bus goes to high-impedance after the /cas latency from the burst stop command. read command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2, 3 q1 q2 q3 dq /cas latency = 2 hi-z q1 q2 q3 dq /cas latency = 3 hi-z bst during a write cycle, when the burst stop command is asserted, the burst read data are terminated and data bus goes to high-impedance at the same clock with the burst stop command. d2 d3 d4 writ dq command /cas latency = 2, 3 clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2, 3 bst hi-z d1 h
42 preliminary data sheet m m m m pd4811650 for rev. e 15.2 precharge termination 15.2.1 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is asserted, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 q1 dq command q2 q3 q4 act t rp pre hi-z (t ras is satisfied) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command q1 q2 q3 act t rp pre hi-z t8 q4 (t ras is satisfied)
43 m m m m pd4811650 for rev. e preliminary data sheet 15.2.2 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is asserted, the burst write operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the write data written prior to the precharge command will be correctly stored. however, the data written at the same clock as the precharge command will not be stored. writ clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 dq command d1 d2 d3 act t rp pre hi-z d4 d5 invalid (t ras is satisfied) when /cas latency is 3, the write data written prior to the precharge command will be correctly stored. however, the data written at the same clock as the precharge command will not be stored. writ clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command d1 d2 d3 act t rp pre hi-z d5 t8 invalid d4 (t ras is satisfied)
44 preliminary data sheet m m m m pd4811650 for rev. e 16. electrical specifications all voltages are referenced to v ss (gnd). after power up, wait more than 100 m s and then, execute power on sequence and auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q C1.0 to +4.6 v voltage on input pin relative to gnd v t C1.0 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to +70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage (-a70r) v cc , v cc q 3.4 3.5 3.6 v supply voltage (-a80, -a10, -a12) v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 + 0.8 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a10 2 6 pf c i2 clk, cke, /cs, /ras, /cas, /we, dsf, dqm0 - dqm3 26 data input/output capacitance c i/o dq0 - dq31 2 7 pf
45 m m m m pd4811650 for rev. e preliminary data sheet dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1 -a70r 230 ma 1 t ras 3 t ras(min.) , t rp 3 t rp(min.) , i o = 0 ma -a80 220 -a10 205 -a12 180 precharge standby current i cc2 p cke v il(max.) , t ck = 15 ns 4 ma in power down mode i cc2 ps cke v il(max.) , t ck = 3 precharge standby current i cc2 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) ,36ma in non power down mode input signals are changed one time during 30 ns. i cc2 ns cke 3 v ih(min.) , t ck = 22 input signals are stable. active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 5 ma power down mode i cc3 ps cke v il(max.) , t ck = 4 active standby current in i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) ,50ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke 3 v ih(min.) , t ck = 25 input signals are stable. operating current i cc4 t ck 3 t ck(min.), /cas latency = 2 -a80 220 ma 2 (burst mode) i o = 0 ma -a10 200 -a12 170 /cas latency = 3 -a70r 345 -a80 300 -a10 250 -a12 210 refresh current i cc5 t rc 3 t rc(min.) -a70r 190 ma 3 -a80 180 -a10 170 -a12 150 self refresh current i cc6 cke 0.2 v2ma operating current i cc7 t ck 3 t ck(min.) , i o = 0 ma, -a70r 290 ma (block write mode) t bwc 3 t bwc(min.) -a80 250 -a10 210 -a12 180 input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C5.0 +5.0 m a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 v C5.0 +5.0 m a high level output voltage v oh i o = C 2.0 ma 2.4 v low level output voltage v ol i o = + 2.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) .
46 preliminary data sheet m m m m pd4811650 for rev. e ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih(min.) and v il(max.) . an access time is measured at 1.4 v. t ck t ch t cl 2.0 v 1.4 v 0.8 v clk 2.0 v 1.4 v 0.8 v input t setup t hold output t ac t oh 1.4 v 1.4 v
47 m m m m pd4811650 for rev. e preliminary data sheet synchronous characteristics parameter symbol -a70r -a 80 -a10 -a 12 unit note min. max. min. max. min. max. min. max. clock cycle time /cas latency = 3 t ck3 7 (143 mhz) 8 (125 mhz) 10 (100 mhz) 12 (83 mhz) ns /cas latency = 2 t ck2 12 (83 mhz) 13 (77 mhz) 15 (67 mhz) ns access time from clk /cas latency = 3 t ac3 6.0 6.5 7.5 8 ns 1 /cas latency = 2 t ac2 9 10 11ns1 clk high level width t ch 3 3 3.5 4 ns clk low level width t cl 3 3 3.5 4 ns data-out hold time t oh 2.5 2.5 3 3 ns 1 data-out low-impedance time t lz 0000ns data-out high-impedance time /cas latency = 3 t hz3 2.5 6.0 2.5 6.5 3 7.5 3 8 ns /cas latency = 2 t hz2 2.5 9 3 10 3 11 ns data-in setup time t ds 2.5 2.5 2.5 3 ns data-in hold time t dh 1111.5ns address setup time t as 2.5 2.5 2.5 3 ns address hold time t ah 1111.5ns cke setup time t cks 2.5 2.5 2.5 3 ns cke hold time t ckh 1111.5ns cke setup time (power down exit) t cksp 2.5 2.5 2.5 3 ns command (/cs, /ras, /cas, /we, dsf, dqm) setup time t cms 2.5 2.5 2.5 3 ns command (/cs, /ras, /cas, /we, dsf, dqm) hold time t cmh 1111.5ns note 1. loading capacitance is 30 pf.
48 preliminary data sheet m m m m pd4811650 for rev. e asynchronous characteristics parameter symbol -a70r -a 80 -a10 -a 12 unit note min. max. min. max. min. max. min. max. ref to ref/act command period t rc 70 72 78 90 ns act to pre command period t ras 48 120,000 48 120,000 50 120,000 60 120,000 ns pre to act command period t rp 21 24 26 30 ns delay time act to read/write command t rcd 21 24 24 30 ns act(0) to act(1) command period t rrd 21 24 30 36 ns data-in to pre command period /cas latency = 3 t dpl3 7 8 10 12 ns /cas latency = 2 t dpl2 12 13 15 ns data-in to act(ref) command /cas latency = 3 t dal3 1clk+21 1clk+24 1clk+26 1clk+30 ns period (auto precharge) /cas latency = 2 t dal2 1clk+24 1clk+26 1clk+30 ns block write cycle time t bwc 14 16 20 24 ns block write data-in to pre command period t bpl 14 16 20 24 ns block write data-in active (ref) command period (auto precharge) t bal 35 40 46 54 ns mode register set cycle time t rsc 2222clk transition time t t 0.5 30 0.5 30 1 30 1 30 ns refresh time (2,048 refresh cycles) t ref 32 32 32 32 ms
49 m m m m pd4811650 for rev.e preliminary data sheet 16.1 ac parameters for read/write cycles ac parameters for read timing (burst length = 2, /cas latency = 2) clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t ac t lz t ac t oh t hz t oh t cks t ch t cl t ck t cms t cmh t as t ah t rcd t rrd t ras t rc t rp hi-z t ckh bank a activate command bank a precharge command bank b read command with auto precharge bank b activate command bank a read command bank a activate command dsf t cmh t cms auto precharge start for bank b
preliminary data sheet 50 m m m m pd4811650 for rev.e ac parameters for write timing (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq t cks t cms t ckh t as t ah hi-z t ds t dh t rcd t rrd t dal t rc t dpl t rp bank a activate command bank a precharge command bank a write command without auto precharge bank a activate command bank b write command with auto precharge bank b activate command bank a write command with auto precharge bank a activate command t cmh dsf t cms auto precharge start for bank a auto precharge start for bank b t cmh
51 m m m m pd4811650 for rev. e preliminary data sheet 16.2 relationship between frequency and latency speed version -a 70r -a 80 -a10 -a12 clock cycle time [ns] 7 8 12 10 13 12 15 frequency [mhz] 143 125 83 100 77 83 67 /cas latency 3323232 [t rcd ] 3323232 /ras latency (/cas latency + [t rcd ])6646464 [t rc ] 10968686 [t ras ] 7645454 [t rrd ] 3323333 [t rp ] 3323232 [t dpl ] 1111111 [t dal ] 4434343
preliminary data sheet 52 m m m m pd4811650 for rev.e 16.3 /cs function /cs function (only /cs signal needs to be asserted at minimum rate) (at 100 mhz burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h dab1 dab2 dab3 dab4 qaa1 qaa2 qaa3 qaa4 raa raa caa cab l activate command for bank a read command for bank a write command for bank a precharge command for bank a l dsf l
53 m m m m pd4811650 for rev.e preliminary data sheet 16.4 basic cycles 16.4.1 initialization power on sequence and auto refresh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq cke all banks precharge command is necessary t rp t rc t rc mode register set command is necessary refresh command is necessary refresh command is necessary activate command high level is necessary high level is necessary address key t rsc (2 clk) 2 refresh cycles are necessary dsf clk signal is necessary hi-z
preliminary data sheet 54 m m m m pd4811650 for rev.e 16.4.2 mode register set mode register (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq all banks precharge command if necessary t rp mode register set command activate command is valid hi-z h address key t rsc (2 clk) dsf
55 m m m m pd4811650 for rev.e preliminary data sheet 16.4.3 refresh cycle cbr refresh (/cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk /cs /ras /cas /we a10 (ba) a9 add cke h dq dqm 0 - 3 precharge command if necessary cbr refresh cbr refresh activate command read command q1 t rp t rc t rc dsf
preliminary data sheet 56 m m m m pd4811650 for rev.e self refresh (entry and exit) precharge command if necessary self refresh entry t rp self refresh exit self refresh entry or (activate command) next clock enable self refresh exit next clock enable activate command t rc t rc t0 t1 t2 t3 t4 t7 t8 t9 t10 t11 t12 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dom dq dqm 0 - 3 dsf
57 m m m m pd4811650 for rev.e preliminary data sheet 16.4.4 cycle with auto precharge auto precharge after read burst (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h l raa caa cab cbb rac cac raa rba rbb rac rba cba rbb hi-z activate command for bank a activate command for bank b bank a read command without auto precharge bank b read command with auto precharge bank a read command with auto precharge activate command for bank b auto precharge start for bank b auto precharge start for bank a bank b read command with auto precharge activate command for bank a auto precharge start for bank b bank a read command with auto precharge l qaa1 qaa2 qaa3 qaa4 qba1 qba2 qba3 qba4 qab1 qab2 qab3 qab4 qbb1 qbb2 qbb3 qbb4 qac1 qac2 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq dsf
preliminary data sheet 58 m m m m pd4811650 for rev.e auto precharge after read burst (2/2) (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h l hi-z activate command for bank a auto precharge start for bank b activate command for bank b bank a read command without auto precharge bank b read command with auto precharge bank a read command with auto precharge activate command for bank b auto precharge start for bank a bank b read command with auto precharge raa rba raa caa rba cba cab rbb cbb rbb dsf qaa1 qaa2 qaa3 qaa4 qba1 qba2 qba3 qba4 qab1 qab2 qab3 qab4 qbb1 qbb2
59 m m m m pd4811650 for rev.e preliminary data sheet auto precharge after write burst (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa caa cab cbb rac cac raa rba rbb rac rba cba rbb hi-z activate command for bank a activate command for bank b bank a write command without auto precharge bank b write command with auto precharge bank a write command with auto precharge activate command for bank b auto precharge start for bank b activate command for bank a l h bank b write command with auto precharge auto precharge start for bank a bank a write command with auto precharge auto precharge start for bank b dsf daa1 daa2 daa3 daa4 dba1 dba2 dba3 dba4 dab1 dab2 dab3 dab4 dbb1 dbb2 dbb3 dbb4 dac1 dac2 dac3 dac4
preliminary data sheet 60 m m m m pd4811650 for rev.e auto precharge after write burst (2/2) (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h l hi-z raa rba raa caa rba cba cab rbb cbb rbb activate command for bank a activate command for bank b bank a write command without auto precharge bank b write command with auto precharge bank a write command with auto precharge auto precharge start for bank b activate command for bank b auto precharge start for bank a bank b write command with auto precharge dsf daa1 daa2 daa3 daa4 dba1 dba2 dba3 dba4 dab1 dab2 dab3 dab4 dbb1 dbb2 dbb3 dbb4
61 m m m m pd4811650 for rev.e preliminary data sheet 16.4.5 full page mode cycle full page read cycle (1/2) (/cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h raa rba raa caa rba cba rbb rbb l hi-z read command for bank a burst cannot end in full page mode read command for bank a precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b qaa qaa+1 qaa+2 qaa _ 2 qaa _ 1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+6 qba+5 qba+4 dsf t rp
preliminary data sheet 62 m m m m pd4811650 for rev.e full page read cycle (2/2) (/cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h raa rba raa caa rba cba rbb rbb l hi-z read command for bank a burst cannot end in full page mode read command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b qaa qaa+1 qaa _ 3 qaa _ 2 qaa _ 1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+5 qba+4 precharge command for bank b dsf t rp
63 m m m m pd4811650 for rev.e preliminary data sheet full page write cycle (1/2) (/cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h daa daa+1 daa+2 daa _ 2 daa _ 1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 dba+5 raa rba raa caa rba cba rbb rbb l hi-z write command for bank a burst cannot end in full page mode write command for bank b precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b dsf t rp
preliminary data sheet 64 m m m m pd4811650 for rev.e full page write cycle (2/2) (/cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h daa daa+1 daa+2 daa+3 daa _ 1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 raa rba raa caa rba cba rbb rbb l hi-z write command for bank a burst cannot end in full page mode write command for bank b precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b dsf t rp
65 m m m m pd4811650 for rev.e preliminary data sheet 16.4.6 precharge termination cycle pre (precharge) termination of burst (1/2) (burst length = 2, 4, 8, full, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dq h daa1 daa2 daa3 daa4 qab1 qab2 qab3 qac1 qac2 qac3 raa caa rab cab rac cac raa rab rac hi-z dqm 0 - 3 l activate command for bank a bank a precharge command read command for bank a bank a activate command pre command termination bank a precharge command pre command termination read command for bank a bank a activate command t rp t rp t dpl t rcd write command for bank a t ras t ras hi-z dsf invalid
preliminary data sheet 66 m m m m pd4811650 for rev.e pre (precharge) termination of burst (2/2) (burst length = 2, 4, 8, full, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h daa1 qab1 qab2 qab3 raa caa rab cab rac raa rab rac hi-z l activate command for bank a bank a precharge command read command for bank a bank a activate command pre command termination bank a precharge command pre command termination bank a activate command t rp t rcd write command for bank a t ras t dpl t rp invalid dsf daa2 qab4
67 m m m m pd4811650 for rev.e preliminary data sheet 16.4.7 clock suspension clock suspension during burst read (using cke function) (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa raa caa qaa1 qaa2 qaa3 qaa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at end of burst read command for bank a dsf
preliminary data sheet 68 m m m m pd4811650 for rev.e clock suspension during burst read (using cke function) (2/2) (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa raa caa qaa1 qaa2 qaa3 qaa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at end of burst read command for bank a dsf
69 m m m m pd4811650 for rev.e preliminary data sheet clock suspension during burst write (using cke function) (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa raa caa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended write command for bank a 3-clock suspended dsf
preliminary data sheet 70 m m m m pd4811650 for rev.e clock suspension during burst write (using cke function) (2/2) (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa raa caa activate command for bank a write command for bank a daa1 daa2 daa3 daa4 1-clock suspended 2-clock suspended 3-clock suspended dsf
71 m m m m pd4811650 for rev.e preliminary data sheet 16.4.8 power down mode power down mode and clock suspension (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l raa caa activate command for bank a precharge command qaa1 qaa2 qaa4 clock mask start clock mask end qaa3 power down mode entry power down mode exit precharge standby read command for bank a power down mode exit power down mode entry active standby t cksp t cksp valid dsf
preliminary data sheet 72 m m m m pd4811650 for rev.e 16.4.9 other cycles byte read/write operation (by dqm) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm0 dqm1 dq 0 - 7 dq 8 - 15 h activate command for bank b read command for bank b byte of dq 8 - 15 not read byte of dq 0 - 7 not write write command for bank b byte of dq 8 - 15 not write byte of dq 0 - 7 not write dsf rba rba cba cbb cbc qba1 qba2 qba3 dbb2 dbb3 dbb1 dbb2 dbb4 qbc1 qbc2 qbc3 qbc4 qbc2 qbc3 qba2 qba3 qba4 byte of dq 0 - 7 not read byte of dq 0 - 7 not read byte of dq 0 - 7 not read read command for bank b remark the timings of dqm2, dqm3, and the corresponding dq16 - 23, dq24 - 31 are omitted.
73 m m m m pd4811650 for rev.e preliminary data sheet burst read and single write (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm0 dqm1 dq 0 - 7 dq 8 - 15 h activate command for bank b read command for bank b single write command single write command read command single write command dsf rba rba cba cbb qba1 qba2 qba3 qba4 dbc qbd1 dbe cbc cbd cbe dbb write masking remark the timings of dqm2, dqm3, and the corresponding dq16 - 23, dq24 - 31 are omitted.
preliminary data sheet 74 m m m m pd4811650 for rev.e 16.5 graphics cycles special register set (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk all banks precharge command if necessary t rp special register set command activate command is valid cke /cs /ras /cas /we dsf a10 (ba) a9 add dqm 0 - 3 dq t rsc (2 clk) h color or mask data address key hi-z remark special register set command is able to input at idle state or row active state.
75 m m m m pd4811650 for rev.e preliminary data sheet random row write with wpb (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 raa caa raa rba cba rab cab rba rab l activate command with wpb for bank a t rcd write command for bank a wpb is enable. activate command for bank b write command for bank b wpb is disable. precharge command for bank a activate command for bank a precharge command for bank b t rp dba8 dab2 dab3 dab4 write command for bank a wpb is disable. t dpl t dpl dsf
preliminary data sheet 76 m m m m pd4811650 for rev.e random row write with wpb (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h l daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 dba8 dab1 dab2 dab3 raa caa rba cba rab cab raa rba rab activate command with wpb for bank a write command for bank a wpb is enable. activate command for bank b write command for bank b wpb is disable. precharge command for bank a activate command for bank a write command for bank a wpb is disable. precharge command for bank b t rcd t dpl t rp t dpl dsf
77 m m m m pd4811650 for rev.e preliminary data sheet block write (page at same bank) (/cas latency = 3) t0 activate command for bank b t rcd h t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 block write for bank b cm cm cm cm block write for bank b block write for bank b block write for bank b precharge command for bank b activate command with wpb for bank b block write for bank b wpb is enable. cm i/o mask i/o mask i/o mask i/o mask i/o mask t bwc t bwc t bwc t bpl t rp t rcd clk cke /cs /ras /cas /we dsf a10 (ba) a9 add dqm 0 - 3 dq cbc rbb rbb cbd cbc cbb cba rba rba l = no i/o mask column mask
preliminary data sheet 78 m m m m pd4811650 for rev.e block write (page at same bank) changing color and mask data (/cas latency = 3) t0 activate command for bank b with wpb t rcd h t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 block write for bank b cm mask cm color special register write command (mask data) block write for bank b special register write command (color data) block write for bank b precharge command for bank b activate command for bank b i/o mask i/o mask i/o mask i/o mask t bwc t rsc (2 clk) t bwc t rsc (2 clk) t bpl t rp clk cke /cs /ras /cas /we dsf a10 (ba) a9 add dqm 0 - 3 dq rbb rbb 40h cbb 20h cba rba rba cbc cbd cm cm block write for bank b t bwc
79 m m m m pd4811650 for rev.e preliminary data sheet 16.6 application cycles 16.6.1 page cycles with same bank random column read (page with same bank) (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h l raa caa cac rad cad raa rad cab l qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 activate command for bank a read command for bank a read command for bank a precharge command for bank a activate command for bank a read command for bank a qad1 qad2 qad3 read command for bank a dsf t rp
preliminary data sheet 80 m m m m pd4811650 for rev.e random column read (page with same bank) (2/2) (burst length = 4, /cas latency = 3) raa t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 raa caa cab cac raa caa raa h activate command for bank a read command for bank a read command for bank a read command for bank a precharge command for bank a activate command for bank a read command for bank a dsf t rp
81 m m m m pd4811650 for rev.e preliminary data sheet random column write (page with same bank) (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h dba1 dba2 dba3 dba4 dbb1 dbb2 dbc1 dbc2 dbc3 dbc4 activate command for bank b dbd1 dbd2 dbd3 dbd4 l rba cba rba cbb cbc rbd cbd write command for bank b write command for bank b precharge command for bank b write command for bank b rbd activate command for bank b write command for bank b dsf t rp
preliminary data sheet 82 m m m m pd4811650 for rev.e random column write (page with same bank) (2/2) (burst length = 4, /cas latency = 3) rba t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l dba1 dba2 dba3 dba4 dbb1 dbb2 dbc1 dbc2 dbc3 dbc4 rba cba cbb cbc rbd cbd rbd h activate command for bank b write command for bank b write command for bank b write command for bank b precharge command for bank b activate command for bank b write command for bankb dbd1 dsf t rp
83 m m m m pd4811650 for rev.e preliminary data sheet 16.6.2 cycles with ping-pong banks random row read (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 qab1 rba cba rba raa caa rbb cbb raa rbb l activate command for bank b t rcd /cas latency read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b t rp dsf
preliminary data sheet 84 m m m m pd4811650 for rev.e random row read (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dq h dqm 0 - 3 l dq qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 rba cba raa caa rbb cbb rba raa rbb activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a t rcd /cas latency t rp dsf
85 m m m m pd4811650 for rev.e preliminary data sheet random row write (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 raa caa raa rba cba rab cab rba rab l activate command for bank a t rcd write command for bank a activate command for bank b write command for bank b precharge command for bank a activate command for bank a precharge command for bank b t rp dba8 dab1 dab2 dab3 dab4 write command for bank a t dpl t dpl dsf
preliminary data sheet 86 m m m m pd4811650 for rev.e random row write (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h l daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 dba8 dab1 dab2 dab3 raa caa rba cba rab cab raa rba rab activate command for bank a write command for bank a activate command for bank b write command for bank b precharge command for bank a activate command for bank a write command for bank a precharge command for bank b t rcd t dpl t rp t dpl dsf
87 m m m m pd4811650 for rev.e preliminary data sheet 16.6.3 read and write cycles read and write (1/2) (burst length = 4, /cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h raa caa cab cac raa activate command for bank a read command for bank a hi-z at the end of wrap function write command for bank a qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab4 qac1 qac2 qac4 0-clock latency read command for bank a 2-clock latency hi-z write latency = 0 write masking dsf
preliminary data sheet 88 m m m m pd4811650 for rev.e read and write (2/2) (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h raa caa cab cac raa activate command for bank a read command for bank a hi-z at the end of wrap function write command for bank a qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab4 qac1 qac2 0-clock latency read command for bank a 2-clock latency hi-z dsf write latency = 0 write masking
89 m m m m pd4811650 for rev.e preliminary data sheet 16.6.4 full page random cycles full page random column read (burst length = full page, /cas latency = 2) t0 t1 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq h qaa1 qba1 qab1 qab2 qbb1 qbb2 qac1 qac2 qac3 qbc1 qbc2 qbc3 raa rba raa rba caa cba cab cbb cac cbc activate command for bank a activate command for bank b read command for bank a read command for bank b read command for bank a read command for bank b read command for bank a read command for bank b precharge command for bank b (pre termination) t rrd t rcd hi-z l dsf t2 t rcd
preliminary data sheet 90 m m m m pd4811650 for rev.e full page random column write (burst length = full page, /cas latency = 2) t0 t1 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a10 (ba) a9 add dqm 0 - 3 dq l daa1 dba1 dab1 dab2 dbb1 dbb2 dac1 dac2 dac3 dbc1 dbc2 dbc3 write command for bank a activate command for bank a activate command for bank b write command for bank b write command for bank a write command for bank b write command for bank a write command for bank b precharge command for bank b (pre termination) raa rba raa rba caa cba cab cbb cac cbc t rrd t rcd h dsf invalid t2 t rcd
91 m m m m pd4811650 for rev. e preliminary data sheet 17. package drawing n ms s j h i m f g k u detail of lead end 100 pin plastic tqfp (14 20) notes 2. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters inches a b c d f g h i j 14.00.2 0.825 0.575 0.320.06 20.00.2 k l 0.8 0.65(t.p.) 0.10 1.60.15 m 0.10 17.20.2 n 0.787 0.6770.008 0.032 0.023 0.013 0.004 0.026 0.0630.006 0.031 0.004 0.5510.008 p 1.0 0.039 +0.002 C0.003 23.20.2 0.913 +0.009 C0.008 1. controlling dimension millimeter. b a r s p q l t +0.009 C0.008 0.170.05 0.007 +0.002 C0.003 s100gf-65-9bt 0.10.05 q 0.0040.002 r3 3 +5 C3 +5 C3 s 0.25 t 0.010 u 0.880.15 0.035 +0.007 C0.006 80 81 51 50 30 31 100 1 c d 1.10 0.043 +0.30 C0.05 +0.013 C0.002
92 m m m m pd4811650 for rev. e preliminary data sheet 18. recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd4811650. type of surface mount device m m m m pd4811650gf-9bt : 100-pin plastic tqfp (14 x 20 mm)
93 m m m m pd4811650 for rev. e preliminary data sheet [memo]
94 m m m m pd4811650 for rev. e preliminary data sheet [memo]
95 m m m m pd4811650 for rev. e preliminary data sheet notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd4811650 for rev. e [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

▲Up To Search▲

Price & Availability of UPD4811650GF-A10-9BT

	To Download UPD4811650GF-A10-9BT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .